arch/x86/kvm/lapic.c

   1
   2 /*
   3  * Local APIC virtualization
   4  *
   5  * Copyright (C) 2006 Qumranet, Inc.
   6  * Copyright (C) 2007 Novell
   7  * Copyright (C) 2007 Intel
   8  * Copyright 2009 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Dor Laor <dor.laor@qumranet.com>
  12  *   Gregory Haskins <ghaskins@novell.com>
  13  *   Yaozu (Eddie) Dong <eddie.dong@intel.com>
  14  *
  15  * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
  16  *
  17  * This work is licensed under the terms of the GNU GPL, version 2.  See
  18  * the COPYING file in the top-level directory.
  19  */
  20
  21 #include <linux/kvm_host.h>
  22 #include <linux/kvm.h>
  23 #include <linux/mm.h>
  24 #include <linux/highmem.h>
  25 #include <linux/smp.h>
  26 #include <linux/hrtimer.h>
  27 #include <linux/io.h>
  28 #include <linux/export.h>
  29 #include <linux/math64.h>
  30 #include <linux/slab.h>
  31 #include <asm/processor.h>
  32 #include <asm/msr.h>
  33 #include <asm/page.h>
  34 #include <asm/current.h>
  35 #include <asm/apicdef.h>
  36 #include <asm/delay.h>
  37 #include <linux/atomic.h>
  38 #include <linux/jump_label.h>
  39 #include "kvm_cache_regs.h"
  40 #include "irq.h"
  41 #include "trace.h"
  42 #include "x86.h"
  43 #include "cpuid.h"
  44 #include "hyperv.h"
  45
  46 #ifndef CONFIG_X86_64
  47 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
  48 #else
  49 #define mod_64(x, y) ((x) % (y))
  50 #endif
  51
  52 #define PRId64 "d"
  53 #define PRIx64 "llx"
  54 #define PRIu64 "u"
  55 #define PRIo64 "o"
  56
  57 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
  58 #define apic_debug(fmt, arg...) do {} while (0)
  59
  60 /* 14 is the version for Xeon and Pentium 8.4.8*/
  61 #define APIC_VERSION                    (0x14UL | ((KVM_APIC_LVT_NUM - 1) << 16))
  62 #define LAPIC_MMIO_LENGTH               (1 << 12)
  63 /* followed define is not in apicdef.h */
  64 #define APIC_SHORT_MASK                 0xc0000
  65 #define APIC_DEST_NOSHORT               0x0
  66 #define APIC_DEST_MASK                  0x800
  67 #define MAX_APIC_VECTOR                 256
  68 #define APIC_VECTORS_PER_REG            32
  69
  70 #define APIC_BROADCAST                  0xFF
  71 #define X2APIC_BROADCAST                0xFFFFFFFFul
  72
  73 static bool lapic_timer_advance_adjust_done = false;
  74 #define LAPIC_TIMER_ADVANCE_ADJUST_DONE 100
  75 /* step-by-step approximation to mitigate fluctuation */
  76 #define LAPIC_TIMER_ADVANCE_ADJUST_STEP 8
  77
  78 static inline int apic_test_vector(int vec, void *bitmap)
  79 {
  80         return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  81 }
  82
  83 bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
  84 {
  85         struct kvm_lapic *apic = vcpu->arch.apic;
  86
  87         return apic_test_vector(vector, apic->regs + APIC_ISR) ||
  88                 apic_test_vector(vector, apic->regs + APIC_IRR);
  89 }
  90
  91 static inline void apic_clear_vector(int vec, void *bitmap)
  92 {
  93         clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  94 }
  95
  96 static inline int __apic_test_and_set_vector(int vec, void *bitmap)
  97 {
  98         return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  99 }
 100
 101 static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
 102 {
 103         return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 104 }
 105
 106 struct static_key_deferred apic_hw_disabled __read_mostly;
 107 struct static_key_deferred apic_sw_disabled __read_mostly;
 108
 109 static inline int apic_enabled(struct kvm_lapic *apic)
 110 {
 111         return kvm_apic_sw_enabled(apic) &&     kvm_apic_hw_enabled(apic);
 112 }
 113
 114 #define LVT_MASK        \
 115         (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
 116
 117 #define LINT_MASK       \
 118         (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
 119          APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
 120
 121 static inline u8 kvm_xapic_id(struct kvm_lapic *apic)
 122 {
 123         return kvm_lapic_get_reg(apic, APIC_ID) >> 24;
 124 }
 125
 126 static inline u32 kvm_x2apic_id(struct kvm_lapic *apic)
 127 {
 128         return apic->vcpu->vcpu_id;
 129 }
 130
 131 static inline bool kvm_apic_map_get_logical_dest(struct kvm_apic_map *map,
 132                 u32 dest_id, struct kvm_lapic ***cluster, u16 *mask) {
 133         switch (map->mode) {
 134         case KVM_APIC_MODE_X2APIC: {
 135                 u32 offset = (dest_id >> 16) * 16;
 136                 u32 max_apic_id = map->max_apic_id;
 137
 138                 if (offset <= max_apic_id) {
 139                         u8 cluster_size = min(max_apic_id - offset + 1, 16U);
 140
 141                         *cluster = &map->phys_map[offset];
 142                         *mask = dest_id & (0xffff >> (16 - cluster_size));
 143                 } else {
 144                         *mask = 0;
 145                 }
 146
 147                 return true;
 148                 }
 149         case KVM_APIC_MODE_XAPIC_FLAT:
 150                 *cluster = map->xapic_flat_map;
 151                 *mask = dest_id & 0xff;
 152                 return true;
 153         case KVM_APIC_MODE_XAPIC_CLUSTER:
 154                 *cluster = map->xapic_cluster_map[(dest_id >> 4) & 0xf];
 155                 *mask = dest_id & 0xf;
 156                 return true;
 157         default:
 158                 /* Not optimized. */
 159                 return false;
 160         }
 161 }
 162
 163 static void kvm_apic_map_free(struct rcu_head *rcu)
 164 {
 165         struct kvm_apic_map *map = container_of(rcu, struct kvm_apic_map, rcu);
 166
 167         kvfree(map);
 168 }
 169
 170 static void recalculate_apic_map(struct kvm *kvm)
 171 {
 172         struct kvm_apic_map *new, *old = NULL;
 173         struct kvm_vcpu *vcpu;
 174         int i;
 175         u32 max_id = 255; /* enough space for any xAPIC ID */
 176
 177         mutex_lock(&kvm->arch.apic_map_lock);
 178
 179         kvm_for_each_vcpu(i, vcpu, kvm)
 180                 if (kvm_apic_present(vcpu))
 181                         max_id = max(max_id, kvm_x2apic_id(vcpu->arch.apic));
 182
 183         new = kvzalloc(sizeof(struct kvm_apic_map) +
 184                            sizeof(struct kvm_lapic *) * ((u64)max_id + 1), GFP_KERNEL);
 185
 186         if (!new)
 187                 goto out;
 188
 189         new->max_apic_id = max_id;
 190
 191         kvm_for_each_vcpu(i, vcpu, kvm) {
 192                 struct kvm_lapic *apic = vcpu->arch.apic;
 193                 struct kvm_lapic **cluster;
 194                 u16 mask;
 195                 u32 ldr;
 196                 u8 xapic_id;
 197                 u32 x2apic_id;
 198
 199                 if (!kvm_apic_present(vcpu))
 200                         continue;
 201
 202                 xapic_id = kvm_xapic_id(apic);
 203                 x2apic_id = kvm_x2apic_id(apic);
 204
 205                 /* Hotplug hack: see kvm_apic_match_physical_addr(), ... */
 206                 if ((apic_x2apic_mode(apic) || x2apic_id > 0xff) &&
 207                                 x2apic_id <= new->max_apic_id)
 208                         new->phys_map[x2apic_id] = apic;
 209                 /*
 210                  * ... xAPIC ID of VCPUs with APIC ID > 0xff will wrap-around,
 211                  * prevent them from masking VCPUs with APIC ID <= 0xff.
 212                  */
 213                 if (!apic_x2apic_mode(apic) && !new->phys_map[xapic_id])
 214                         new->phys_map[xapic_id] = apic;
 215
 216                 ldr = kvm_lapic_get_reg(apic, APIC_LDR);
 217
 218                 if (apic_x2apic_mode(apic)) {
 219                         new->mode |= KVM_APIC_MODE_X2APIC;
 220                 } else if (ldr) {
 221                         ldr = GET_APIC_LOGICAL_ID(ldr);
 222                         if (kvm_lapic_get_reg(apic, APIC_DFR) == APIC_DFR_FLAT)
 223                                 new->mode |= KVM_APIC_MODE_XAPIC_FLAT;
 224                         else
 225                                 new->mode |= KVM_APIC_MODE_XAPIC_CLUSTER;
 226                 }
 227
 228                 if (!kvm_apic_map_get_logical_dest(new, ldr, &cluster, &mask))
 229                         continue;
 230
 231                 if (mask)
 232                         cluster[ffs(mask) - 1] = apic;
 233         }
 234 out:
 235         old = rcu_dereference_protected(kvm->arch.apic_map,
 236                         lockdep_is_held(&kvm->arch.apic_map_lock));
 237         rcu_assign_pointer(kvm->arch.apic_map, new);
 238         mutex_unlock(&kvm->arch.apic_map_lock);
 239
 240         if (old)
 241                 call_rcu(&old->rcu, kvm_apic_map_free);
 242
 243         kvm_make_scan_ioapic_request(kvm);
 244 }
 245
 246 static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
 247 {
 248         bool enabled = val & APIC_SPIV_APIC_ENABLED;
 249
 250         kvm_lapic_set_reg(apic, APIC_SPIV, val);
 251
 252         if (enabled != apic->sw_enabled) {
 253                 apic->sw_enabled = enabled;
 254                 if (enabled)
 255                         static_key_slow_dec_deferred(&apic_sw_disabled);
 256                 else
 257                         static_key_slow_inc(&apic_sw_disabled.key);
 258         }
 259 }
 260
 261 static inline void kvm_apic_set_xapic_id(struct kvm_lapic *apic, u8 id)
 262 {
 263         kvm_lapic_set_reg(apic, APIC_ID, id << 24);
 264         recalculate_apic_map(apic->vcpu->kvm);
 265 }
 266
 267 static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
 268 {
 269         kvm_lapic_set_reg(apic, APIC_LDR, id);
 270         recalculate_apic_map(apic->vcpu->kvm);
 271 }
 272
 273 static inline u32 kvm_apic_calc_x2apic_ldr(u32 id)
 274 {
 275         return ((id >> 4) << 16) | (1 << (id & 0xf));
 276 }
 277
 278 static inline void kvm_apic_set_x2apic_id(struct kvm_lapic *apic, u32 id)
 279 {
 280         u32 ldr = kvm_apic_calc_x2apic_ldr(id);
 281
 282         WARN_ON_ONCE(id != apic->vcpu->vcpu_id);
 283
 284         kvm_lapic_set_reg(apic, APIC_ID, id);
 285         kvm_lapic_set_reg(apic, APIC_LDR, ldr);
 286         recalculate_apic_map(apic->vcpu->kvm);
 287 }
 288
 289 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
 290 {
 291         return !(kvm_lapic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
 292 }
 293
 294 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
 295 {
 296         return kvm_lapic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
 297 }
 298
 299 static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
 300 {
 301         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT;
 302 }
 303
 304 static inline int apic_lvtt_period(struct kvm_lapic *apic)
 305 {
 306         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC;
 307 }
 308
 309 static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
 310 {
 311         return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE;
 312 }
 313
 314 static inline int apic_lvt_nmi_mode(u32 lvt_val)
 315 {
 316         return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
 317 }
 318
 319 void kvm_apic_set_version(struct kvm_vcpu *vcpu)
 320 {
 321         struct kvm_lapic *apic = vcpu->arch.apic;
 322         struct kvm_cpuid_entry2 *feat;
 323         u32 v = APIC_VERSION;
 324
 325         if (!lapic_in_kernel(vcpu))
 326                 return;
 327
 328         /*
 329          * KVM emulates 82093AA datasheet (with in-kernel IOAPIC implementation)
 330          * which doesn't have EOI register; Some buggy OSes (e.g. Windows with
 331          * Hyper-V role) disable EOI broadcast in lapic not checking for IOAPIC
 332          * version first and level-triggered interrupts never get EOIed in
 333          * IOAPIC.
 334          */
 335         feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
 336         if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))) &&
 337             !ioapic_in_kernel(vcpu->kvm))
 338                 v |= APIC_LVR_DIRECTED_EOI;
 339         kvm_lapic_set_reg(apic, APIC_LVR, v);
 340 }
 341
 342 static const unsigned int apic_lvt_mask[KVM_APIC_LVT_NUM] = {
 343         LVT_MASK ,      /* part LVTT mask, timer mode mask added at runtime */
 344         LVT_MASK | APIC_MODE_MASK,      /* LVTTHMR */
 345         LVT_MASK | APIC_MODE_MASK,      /* LVTPC */
 346         LINT_MASK, LINT_MASK,   /* LVT0-1 */
 347         LVT_MASK                /* LVTERR */
 348 };
 349
 350 static int find_highest_vector(void *bitmap)
 351 {
 352         int vec;
 353         u32 *reg;
 354
 355         for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
 356              vec >= 0; vec -= APIC_VECTORS_PER_REG) {
 357                 reg = bitmap + REG_POS(vec);
 358                 if (*reg)
 359                         return __fls(*reg) + vec;
 360         }
 361
 362         return -1;
 363 }
 364
 365 static u8 count_vectors(void *bitmap)
 366 {
 367         int vec;
 368         u32 *reg;
 369         u8 count = 0;
 370
 371         for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
 372                 reg = bitmap + REG_POS(vec);
 373                 count += hweight32(*reg);
 374         }
 375
 376         return count;
 377 }
 378
 379 bool __kvm_apic_update_irr(u32 *pir, void *regs, int *max_irr)
 380 {
 381         u32 i, vec;
 382         u32 pir_val, irr_val, prev_irr_val;
 383         int max_updated_irr;
 384
 385         max_updated_irr = -1;
 386         *max_irr = -1;
 387
 388         for (i = vec = 0; i <= 7; i++, vec += 32) {
 389                 pir_val = READ_ONCE(pir[i]);
 390                 irr_val = *((u32 *)(regs + APIC_IRR + i * 0x10));
 391                 if (pir_val) {
 392                         prev_irr_val = irr_val;
 393                         irr_val |= xchg(&pir[i], 0);
 394                         *((u32 *)(regs + APIC_IRR + i * 0x10)) = irr_val;
 395                         if (prev_irr_val != irr_val) {
 396                                 max_updated_irr =
 397                                         __fls(irr_val ^ prev_irr_val) + vec;
 398                         }
 399                 }
 400                 if (irr_val)
 401                         *max_irr = __fls(irr_val) + vec;
 402         }
 403
 404         return ((max_updated_irr != -1) &&
 405                 (max_updated_irr == *max_irr));
 406 }
 407 EXPORT_SYMBOL_GPL(__kvm_apic_update_irr);
 408
 409 bool kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir, int *max_irr)
 410 {
 411         struct kvm_lapic *apic = vcpu->arch.apic;
 412
 413         return __kvm_apic_update_irr(pir, apic->regs, max_irr);
 414 }
 415 EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
 416
 417 static inline int apic_search_irr(struct kvm_lapic *apic)
 418 {
 419         return find_highest_vector(apic->regs + APIC_IRR);
 420 }
 421
 422 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
 423 {
 424         int result;
 425
 426         /*
 427          * Note that irr_pending is just a hint. It will be always
 428          * true with virtual interrupt delivery enabled.
 429          */
 430         if (!apic->irr_pending)
 431                 return -1;
 432
 433         result = apic_search_irr(apic);
 434         ASSERT(result == -1 || result >= 16);
 435
 436         return result;
 437 }
 438
 439 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
 440 {
 441         struct kvm_vcpu *vcpu;
 442
 443         vcpu = apic->vcpu;
 444
 445         if (unlikely(vcpu->arch.apicv_active)) {
 446                 /* need to update RVI */
 447                 apic_clear_vector(vec, apic->regs + APIC_IRR);
 448                 kvm_x86_ops->hwapic_irr_update(vcpu,
 449                                 apic_find_highest_irr(apic));
 450         } else {
 451                 apic->irr_pending = false;
 452                 apic_clear_vector(vec, apic->regs + APIC_IRR);
 453                 if (apic_search_irr(apic) != -1)
 454                         apic->irr_pending = true;
 455         }
 456 }
 457
 458 static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
 459 {
 460         struct kvm_vcpu *vcpu;
 461
 462         if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
 463                 return;
 464
 465         vcpu = apic->vcpu;
 466
 467         /*
 468          * With APIC virtualization enabled, all caching is disabled
 469          * because the processor can modify ISR under the hood.  Instead
 470          * just set SVI.
 471          */
 472         if (unlikely(vcpu->arch.apicv_active))
 473                 kvm_x86_ops->hwapic_isr_update(vcpu, vec);
 474         else {
 475                 ++apic->isr_count;
 476                 BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
 477                 /*
 478                  * ISR (in service register) bit is set when injecting an interrupt.
 479                  * The highest vector is injected. Thus the latest bit set matches
 480                  * the highest bit in ISR.
 481                  */
 482                 apic->highest_isr_cache = vec;
 483         }
 484 }
 485
 486 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
 487 {
 488         int result;
 489
 490         /*
 491          * Note that isr_count is always 1, and highest_isr_cache
 492          * is always -1, with APIC virtualization enabled.
 493          */
 494         if (!apic->isr_count)
 495                 return -1;
 496         if (likely(apic->highest_isr_cache != -1))
 497                 return apic->highest_isr_cache;
 498
 499         result = find_highest_vector(apic->regs + APIC_ISR);
 500         ASSERT(result == -1 || result >= 16);
 501
 502         return result;
 503 }
 504
 505 static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
 506 {
 507         struct kvm_vcpu *vcpu;
 508         if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
 509                 return;
 510
 511         vcpu = apic->vcpu;
 512
 513         /*
 514          * We do get here for APIC virtualization enabled if the guest
 515          * uses the Hyper-V APIC enlightenment.  In this case we may need
 516          * to trigger a new interrupt delivery by writing the SVI field;
 517          * on the other hand isr_count and highest_isr_cache are unused
 518          * and must be left alone.
 519          */
 520         if (unlikely(vcpu->arch.apicv_active))
 521                 kvm_x86_ops->hwapic_isr_update(vcpu,
 522                                                apic_find_highest_isr(apic));
 523         else {
 524                 --apic->isr_count;
 525                 BUG_ON(apic->isr_count < 0);
 526                 apic->highest_isr_cache = -1;
 527         }
 528 }
 529
 530 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
 531 {
 532         /* This may race with setting of irr in __apic_accept_irq() and
 533          * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
 534          * will cause vmexit immediately and the value will be recalculated
 535          * on the next vmentry.
 536          */
 537         return apic_find_highest_irr(vcpu->arch.apic);
 538 }
 539 EXPORT_SYMBOL_GPL(kvm_lapic_find_highest_irr);
 540
 541 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 542                              int vector, int level, int trig_mode,
 543                              struct dest_map *dest_map);
 544
 545 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
 546                      struct dest_map *dest_map)
 547 {
 548         struct kvm_lapic *apic = vcpu->arch.apic;
 549
 550         return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
 551                         irq->level, irq->trig_mode, dest_map);
 552 }
 553
 554 int kvm_pv_send_ipi(struct kvm *kvm, unsigned long ipi_bitmap_low,
 555                     unsigned long ipi_bitmap_high, u32 min,
 556                     unsigned long icr, int op_64_bit)
 557 {
 558         int i;
 559         struct kvm_apic_map *map;
 560         struct kvm_vcpu *vcpu;
 561         struct kvm_lapic_irq irq = {0};
 562         int cluster_size = op_64_bit ? 64 : 32;
 563         int count = 0;
 564
 565         irq.vector = icr & APIC_VECTOR_MASK;
 566         irq.delivery_mode = icr & APIC_MODE_MASK;
 567         irq.level = (icr & APIC_INT_ASSERT) != 0;
 568         irq.trig_mode = icr & APIC_INT_LEVELTRIG;
 569
 570         if (icr & APIC_DEST_MASK)
 571                 return -KVM_EINVAL;
 572         if (icr & APIC_SHORT_MASK)
 573                 return -KVM_EINVAL;
 574
 575         rcu_read_lock();
 576         map = rcu_dereference(kvm->arch.apic_map);
 577
 578         if (unlikely(!map)) {
 579                 count = -EOPNOTSUPP;
 580                 goto out;
 581         }
 582
 583         if (min > map->max_apic_id)
 584                 goto out;
 585         /* Bits above cluster_size are masked in the caller.  */
 586         for_each_set_bit(i, &ipi_bitmap_low,
 587                 min((u32)BITS_PER_LONG, (map->max_apic_id - min + 1))) {
 588                 if (map->phys_map[min + i]) {
 589                         vcpu = map->phys_map[min + i]->vcpu;
 590                         count += kvm_apic_set_irq(vcpu, &irq, NULL);
 591                 }
 592         }
 593
 594         min += cluster_size;
 595
 596         if (min > map->max_apic_id)
 597                 goto out;
 598
 599         for_each_set_bit(i, &ipi_bitmap_high,
 600                 min((u32)BITS_PER_LONG, (map->max_apic_id - min + 1))) {
 601                 if (map->phys_map[min + i]) {
 602                         vcpu = map->phys_map[min + i]->vcpu;
 603                         count += kvm_apic_set_irq(vcpu, &irq, NULL);
 604                 }
 605         }
 606
 607 out:
 608         rcu_read_unlock();
 609         return count;
 610 }
 611
 612 static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
 613 {
 614
 615         return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
 616                                       sizeof(val));
 617 }
 618
 619 static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
 620 {
 621
 622         return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
 623                                       sizeof(*val));
 624 }
 625
 626 static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
 627 {
 628         return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
 629 }
 630
 631 static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
 632 {
 633         u8 val;
 634         if (pv_eoi_get_user(vcpu, &val) < 0)
 635                 apic_debug("Can't read EOI MSR value: 0x%llx\n",
 636                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 637         return val & 0x1;
 638 }
 639
 640 static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
 641 {
 642         if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
 643                 apic_debug("Can't set EOI MSR value: 0x%llx\n",
 644                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 645                 return;
 646         }
 647         __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
 648 }
 649
 650 static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
 651 {
 652         if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
 653                 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
 654                            (unsigned long long)vcpu->arch.pv_eoi.msr_val);
 655                 return;
 656         }
 657         __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
 658 }
 659
 660 static int apic_has_interrupt_for_ppr(struct kvm_lapic *apic, u32 ppr)
 661 {
 662         int highest_irr;
 663         if (apic->vcpu->arch.apicv_active)
 664                 highest_irr = kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
 665         else
 666                 highest_irr = apic_find_highest_irr(apic);
 667         if (highest_irr == -1 || (highest_irr & 0xF0) <= ppr)
 668                 return -1;
 669         return highest_irr;
 670 }
 671
 672 static bool __apic_update_ppr(struct kvm_lapic *apic, u32 *new_ppr)
 673 {
 674         u32 tpr, isrv, ppr, old_ppr;
 675         int isr;
 676
 677         old_ppr = kvm_lapic_get_reg(apic, APIC_PROCPRI);
 678         tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI);
 679         isr = apic_find_highest_isr(apic);
 680         isrv = (isr != -1) ? isr : 0;
 681
 682         if ((tpr & 0xf0) >= (isrv & 0xf0))
 683                 ppr = tpr & 0xff;
 684         else
 685                 ppr = isrv & 0xf0;
 686
 687         apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
 688                    apic, ppr, isr, isrv);
 689
 690         *new_ppr = ppr;
 691         if (old_ppr != ppr)
 692                 kvm_lapic_set_reg(apic, APIC_PROCPRI, ppr);
 693
 694         return ppr < old_ppr;
 695 }
 696
 697 static void apic_update_ppr(struct kvm_lapic *apic)
 698 {
 699         u32 ppr;
 700
 701         if (__apic_update_ppr(apic, &ppr) &&
 702             apic_has_interrupt_for_ppr(apic, ppr) != -1)
 703                 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
 704 }
 705
 706 void kvm_apic_update_ppr(struct kvm_vcpu *vcpu)
 707 {
 708         apic_update_ppr(vcpu->arch.apic);
 709 }
 710 EXPORT_SYMBOL_GPL(kvm_apic_update_ppr);
 711
 712 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
 713 {
 714         kvm_lapic_set_reg(apic, APIC_TASKPRI, tpr);
 715         apic_update_ppr(apic);
 716 }
 717
 718 static bool kvm_apic_broadcast(struct kvm_lapic *apic, u32 mda)
 719 {
 720         return mda == (apic_x2apic_mode(apic) ?
 721                         X2APIC_BROADCAST : APIC_BROADCAST);
 722 }
 723
 724 static bool kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 mda)
 725 {
 726         if (kvm_apic_broadcast(apic, mda))
 727                 return true;
 728
 729         if (apic_x2apic_mode(apic))
 730                 return mda == kvm_x2apic_id(apic);
 731
 732         /*
 733          * Hotplug hack: Make LAPIC in xAPIC mode also accept interrupts as if
 734          * it were in x2APIC mode.  Hotplugged VCPUs start in xAPIC mode and
 735          * this allows unique addressing of VCPUs with APIC ID over 0xff.
 736          * The 0xff condition is needed because writeable xAPIC ID.
 737          */
 738         if (kvm_x2apic_id(apic) > 0xff && mda == kvm_x2apic_id(apic))
 739                 return true;
 740
 741         return mda == kvm_xapic_id(apic);
 742 }
 743
 744 static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda)
 745 {
 746         u32 logical_id;
 747
 748         if (kvm_apic_broadcast(apic, mda))
 749                 return true;
 750
 751         logical_id = kvm_lapic_get_reg(apic, APIC_LDR);
 752
 753         if (apic_x2apic_mode(apic))
 754                 return ((logical_id >> 16) == (mda >> 16))
 755                        && (logical_id & mda & 0xffff) != 0;
 756
 757         logical_id = GET_APIC_LOGICAL_ID(logical_id);
 758
 759         switch (kvm_lapic_get_reg(apic, APIC_DFR)) {
 760         case APIC_DFR_FLAT:
 761                 return (logical_id & mda) != 0;
 762         case APIC_DFR_CLUSTER:
 763                 return ((logical_id >> 4) == (mda >> 4))
 764                        && (logical_id & mda & 0xf) != 0;
 765         default:
 766                 apic_debug("Bad DFR vcpu %d: %08x\n",
 767                            apic->vcpu->vcpu_id, kvm_lapic_get_reg(apic, APIC_DFR));
 768                 return false;
 769         }
 770 }
 771
 772 /* The KVM local APIC implementation has two quirks:
 773  *
 774  *  - Real hardware delivers interrupts destined to x2APIC ID > 0xff to LAPICs
 775  *    in xAPIC mode if the "destination & 0xff" matches its xAPIC ID.
 776  *    KVM doesn't do that aliasing.
 777  *
 778  *  - in-kernel IOAPIC messages have to be delivered directly to
 779  *    x2APIC, because the kernel does not support interrupt remapping.
 780  *    In order to support broadcast without interrupt remapping, x2APIC
 781  *    rewrites the destination of non-IPI messages from APIC_BROADCAST
 782  *    to X2APIC_BROADCAST.
 783  *
 784  * The broadcast quirk can be disabled with KVM_CAP_X2APIC_API.  This is
 785  * important when userspace wants to use x2APIC-format MSIs, because
 786  * APIC_BROADCAST (0xff) is a legal route for "cluster 0, CPUs 0-7".
 787  */
 788 static u32 kvm_apic_mda(struct kvm_vcpu *vcpu, unsigned int dest_id,
 789                 struct kvm_lapic *source, struct kvm_lapic *target)
 790 {
 791         bool ipi = source != NULL;
 792
 793         if (!vcpu->kvm->arch.x2apic_broadcast_quirk_disabled &&
 794             !ipi && dest_id == APIC_BROADCAST && apic_x2apic_mode(target))
 795                 return X2APIC_BROADCAST;
 796
 797         return dest_id;
 798 }
 799
 800 bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
 801                            int short_hand, unsigned int dest, int dest_mode)
 802 {
 803         struct kvm_lapic *target = vcpu->arch.apic;
 804         u32 mda = kvm_apic_mda(vcpu, dest, source, target);
 805
 806         apic_debug("target %p, source %p, dest 0x%x, "
 807                    "dest_mode 0x%x, short_hand 0x%x\n",
 808                    target, source, dest, dest_mode, short_hand);
 809
 810         ASSERT(target);
 811         switch (short_hand) {
 812         case APIC_DEST_NOSHORT:
 813                 if (dest_mode == APIC_DEST_PHYSICAL)
 814                         return kvm_apic_match_physical_addr(target, mda);
 815                 else
 816                         return kvm_apic_match_logical_addr(target, mda);
 817         case APIC_DEST_SELF:
 818                 return target == source;
 819         case APIC_DEST_ALLINC:
 820                 return true;
 821         case APIC_DEST_ALLBUT:
 822                 return target != source;
 823         default:
 824                 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
 825                            short_hand);
 826                 return false;
 827         }
 828 }
 829 EXPORT_SYMBOL_GPL(kvm_apic_match_dest);
 830
 831 int kvm_vector_to_index(u32 vector, u32 dest_vcpus,
 832                        const unsigned long *bitmap, u32 bitmap_size)
 833 {
 834         u32 mod;
 835         int i, idx = -1;
 836
 837         mod = vector % dest_vcpus;
 838
 839         for (i = 0; i <= mod; i++) {
 840                 idx = find_next_bit(bitmap, bitmap_size, idx + 1);
 841                 BUG_ON(idx == bitmap_size);
 842         }
 843
 844         return idx;
 845 }
 846
 847 static void kvm_apic_disabled_lapic_found(struct kvm *kvm)
 848 {
 849         if (!kvm->arch.disabled_lapic_found) {
 850                 kvm->arch.disabled_lapic_found = true;
 851                 printk(KERN_INFO
 852                        "Disabled LAPIC found during irq injection\n");
 853         }
 854 }
 855
 856 static bool kvm_apic_is_broadcast_dest(struct kvm *kvm, struct kvm_lapic **src,
 857                 struct kvm_lapic_irq *irq, struct kvm_apic_map *map)
 858 {
 859         if (kvm->arch.x2apic_broadcast_quirk_disabled) {
 860                 if ((irq->dest_id == APIC_BROADCAST &&
 861                                 map->mode != KVM_APIC_MODE_X2APIC))
 862                         return true;
 863                 if (irq->dest_id == X2APIC_BROADCAST)
 864                         return true;
 865         } else {
 866                 bool x2apic_ipi = src && *src && apic_x2apic_mode(*src);
 867                 if (irq->dest_id == (x2apic_ipi ?
 868                                      X2APIC_BROADCAST : APIC_BROADCAST))
 869                         return true;
 870         }
 871
 872         return false;
 873 }
 874
 875 /* Return true if the interrupt can be handled by using *bitmap as index mask
 876  * for valid destinations in *dst array.
 877  * Return false if kvm_apic_map_get_dest_lapic did nothing useful.
 878  * Note: we may have zero kvm_lapic destinations when we return true, which
 879  * means that the interrupt should be dropped.  In this case, *bitmap would be
 880  * zero and *dst undefined.
 881  */
 882 static inline bool kvm_apic_map_get_dest_lapic(struct kvm *kvm,
 883                 struct kvm_lapic **src, struct kvm_lapic_irq *irq,
 884                 struct kvm_apic_map *map, struct kvm_lapic ***dst,
 885                 unsigned long *bitmap)
 886 {
 887         int i, lowest;
 888
 889         if (irq->shorthand == APIC_DEST_SELF && src) {
 890                 *dst = src;
 891                 *bitmap = 1;
 892                 return true;
 893         } else if (irq->shorthand)
 894                 return false;
 895
 896         if (!map || kvm_apic_is_broadcast_dest(kvm, src, irq, map))
 897                 return false;
 898
 899         if (irq->dest_mode == APIC_DEST_PHYSICAL) {
 900                 if (irq->dest_id > map->max_apic_id) {
 901                         *bitmap = 0;
 902                 } else {
 903                         *dst = &map->phys_map[irq->dest_id];
 904                         *bitmap = 1;
 905                 }
 906                 return true;
 907         }
 908
 909         *bitmap = 0;
 910         if (!kvm_apic_map_get_logical_dest(map, irq->dest_id, dst,
 911                                 (u16 *)bitmap))
 912                 return false;
 913
 914         if (!kvm_lowest_prio_delivery(irq))
 915                 return true;
 916
 917         if (!kvm_vector_hashing_enabled()) {
 918                 lowest = -1;
 919                 for_each_set_bit(i, bitmap, 16) {
 920                         if (!(*dst)[i])
 921                                 continue;
 922                         if (lowest < 0)
 923                                 lowest = i;
 924                         else if (kvm_apic_compare_prio((*dst)[i]->vcpu,
 925                                                 (*dst)[lowest]->vcpu) < 0)
 926                                 lowest = i;
 927                 }
 928         } else {
 929                 if (!*bitmap)
 930                         return true;
 931
 932                 lowest = kvm_vector_to_index(irq->vector, hweight16(*bitmap),
 933                                 bitmap, 16);
 934
 935                 if (!(*dst)[lowest]) {
 936                         kvm_apic_disabled_lapic_found(kvm);
 937                         *bitmap = 0;
 938                         return true;
 939                 }
 940         }
 941
 942         *bitmap = (lowest >= 0) ? 1 << lowest : 0;
 943
 944         return true;
 945 }
 946
 947 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
 948                 struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map)
 949 {
 950         struct kvm_apic_map *map;
 951         unsigned long bitmap;
 952         struct kvm_lapic **dst = NULL;
 953         int i;
 954         bool ret;
 955
 956         *r = -1;
 957
 958         if (irq->shorthand == APIC_DEST_SELF) {
 959                 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
 960                 return true;
 961         }
 962
 963         rcu_read_lock();
 964         map = rcu_dereference(kvm->arch.apic_map);
 965
 966         ret = kvm_apic_map_get_dest_lapic(kvm, &src, irq, map, &dst, &bitmap);
 967         if (ret) {
 968                 *r = 0;
 969                 for_each_set_bit(i, &bitmap, 16) {
 970                         if (!dst[i])
 971                                 continue;
 972                         *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
 973                 }
 974         }
 975
 976         rcu_read_unlock();
 977         return ret;
 978 }
 979
 980 /*
 981  * This routine tries to handler interrupts in posted mode, here is how
 982  * it deals with different cases:
 983  * - For single-destination interrupts, handle it in posted mode
 984  * - Else if vector hashing is enabled and it is a lowest-priority
 985  *   interrupt, handle it in posted mode and use the following mechanism
 986  *   to find the destinaiton vCPU.
 987  *      1. For lowest-priority interrupts, store all the possible
 988  *         destination vCPUs in an array.
 989  *      2. Use "guest vector % max number of destination vCPUs" to find
 990  *         the right destination vCPU in the array for the lowest-priority
 991  *         interrupt.
 992  * - Otherwise, use remapped mode to inject the interrupt.
 993  */
 994 bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq,
 995                         struct kvm_vcpu **dest_vcpu)
 996 {
 997         struct kvm_apic_map *map;
 998         unsigned long bitmap;
 999         struct kvm_lapic **dst = NULL;
1000         bool ret = false;
1001
1002         if (irq->shorthand)
1003                 return false;
1004
1005         rcu_read_lock();
1006         map = rcu_dereference(kvm->arch.apic_map);
1007
1008         if (kvm_apic_map_get_dest_lapic(kvm, NULL, irq, map, &dst, &bitmap) &&
1009                         hweight16(bitmap) == 1) {
1010                 unsigned long i = find_first_bit(&bitmap, 16);
1011
1012                 if (dst[i]) {
1013                         *dest_vcpu = dst[i]->vcpu;
1014                         ret = true;
1015                 }
1016         }
1017
1018         rcu_read_unlock();
1019         return ret;
1020 }
1021
1022 /*
1023  * Add a pending IRQ into lapic.
1024  * Return 1 if successfully added and 0 if discarded.
1025  */
1026 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
1027                              int vector, int level, int trig_mode,
1028                              struct dest_map *dest_map)
1029 {
1030         int result = 0;
1031         struct kvm_vcpu *vcpu = apic->vcpu;
1032
1033         trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
1034                                   trig_mode, vector);
1035         switch (delivery_mode) {
1036         case APIC_DM_LOWEST:
1037                 vcpu->arch.apic_arb_prio++;
1038         case APIC_DM_FIXED:
1039                 if (unlikely(trig_mode && !level))
1040                         break;
1041
1042                 /* FIXME add logic for vcpu on reset */
1043                 if (unlikely(!apic_enabled(apic)))
1044                         break;
1045
1046                 result = 1;
1047
1048                 if (dest_map) {
1049                         __set_bit(vcpu->vcpu_id, dest_map->map);
1050                         dest_map->vectors[vcpu->vcpu_id] = vector;
1051                 }
1052
1053                 if (apic_test_vector(vector, apic->regs + APIC_TMR) != !!trig_mode) {
1054                         if (trig_mode)
1055                                 kvm_lapic_set_vector(vector, apic->regs + APIC_TMR);
1056                         else
1057                                 apic_clear_vector(vector, apic->regs + APIC_TMR);
1058                 }
1059
1060                 if (vcpu->arch.apicv_active)
1061                         kvm_x86_ops->deliver_posted_interrupt(vcpu, vector);
1062                 else {
1063                         kvm_lapic_set_irr(vector, apic);
1064
1065                         kvm_make_request(KVM_REQ_EVENT, vcpu);
1066                         kvm_vcpu_kick(vcpu);
1067                 }
1068                 break;
1069
1070         case APIC_DM_REMRD:
1071                 result = 1;
1072                 vcpu->arch.pv.pv_unhalted = 1;
1073                 kvm_make_request(KVM_REQ_EVENT, vcpu);
1074                 kvm_vcpu_kick(vcpu);
1075                 break;
1076
1077         case APIC_DM_SMI:
1078                 result = 1;
1079                 kvm_make_request(KVM_REQ_SMI, vcpu);
1080                 kvm_vcpu_kick(vcpu);
1081                 break;
1082
1083         case APIC_DM_NMI:
1084                 result = 1;
1085                 kvm_inject_nmi(vcpu);
1086                 kvm_vcpu_kick(vcpu);
1087                 break;
1088
1089         case APIC_DM_INIT:
1090                 if (!trig_mode || level) {
1091                         result = 1;
1092                         /* assumes that there are only KVM_APIC_INIT/SIPI */
1093                         apic->pending_events = (1UL << KVM_APIC_INIT);
1094                         /* make sure pending_events is visible before sending
1095                          * the request */
1096                         smp_wmb();
1097                         kvm_make_request(KVM_REQ_EVENT, vcpu);
1098                         kvm_vcpu_kick(vcpu);
1099                 } else {
1100                         apic_debug("Ignoring de-assert INIT to vcpu %d\n",
1101                                    vcpu->vcpu_id);
1102                 }
1103                 break;
1104
1105         case APIC_DM_STARTUP:
1106                 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
1107                            vcpu->vcpu_id, vector);
1108                 result = 1;
1109                 apic->sipi_vector = vector;
1110                 /* make sure sipi_vector is visible for the receiver */
1111                 smp_wmb();
1112                 set_bit(KVM_APIC_SIPI, &apic->pending_events);
1113                 kvm_make_request(KVM_REQ_EVENT, vcpu);
1114                 kvm_vcpu_kick(vcpu);
1115                 break;
1116
1117         case APIC_DM_EXTINT:
1118                 /*
1119                  * Should only be called by kvm_apic_local_deliver() with LVT0,
1120                  * before NMI watchdog was enabled. Already handled by
1121                  * kvm_apic_accept_pic_intr().
1122                  */
1123                 break;
1124
1125         default:
1126                 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
1127                        delivery_mode);
1128                 break;
1129         }
1130         return result;
1131 }
1132
1133 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
1134 {
1135         return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
1136 }
1137
1138 static bool kvm_ioapic_handles_vector(struct kvm_lapic *apic, int vector)
1139 {
1140         return test_bit(vector, apic->vcpu->arch.ioapic_handled_vectors);
1141 }
1142
1143 static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
1144 {
1145         int trigger_mode;
1146
1147         /* Eoi the ioapic only if the ioapic doesn't own the vector. */
1148         if (!kvm_ioapic_handles_vector(apic, vector))
1149                 return;
1150
1151         /* Request a KVM exit to inform the userspace IOAPIC. */
1152         if (irqchip_split(apic->vcpu->kvm)) {
1153                 apic->vcpu->arch.pending_ioapic_eoi = vector;
1154                 kvm_make_request(KVM_REQ_IOAPIC_EOI_EXIT, apic->vcpu);
1155                 return;
1156         }
1157
1158         if (apic_test_vector(vector, apic->regs + APIC_TMR))
1159                 trigger_mode = IOAPIC_LEVEL_TRIG;
1160         else
1161                 trigger_mode = IOAPIC_EDGE_TRIG;
1162
1163         kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
1164 }
1165
1166 static int apic_set_eoi(struct kvm_lapic *apic)
1167 {
1168         int vector = apic_find_highest_isr(apic);
1169
1170         trace_kvm_eoi(apic, vector);
1171
1172         /*
1173          * Not every write EOI will has corresponding ISR,
1174          * one example is when Kernel check timer on setup_IO_APIC
1175          */
1176         if (vector == -1)
1177                 return vector;
1178
1179         apic_clear_isr(vector, apic);
1180         apic_update_ppr(apic);
1181
1182         if (test_bit(vector, vcpu_to_synic(apic->vcpu)->vec_bitmap))
1183                 kvm_hv_synic_send_eoi(apic->vcpu, vector);
1184
1185         kvm_ioapic_send_eoi(apic, vector);
1186         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
1187         return vector;
1188 }
1189
1190 /*
1191  * this interface assumes a trap-like exit, which has already finished
1192  * desired side effect including vISR and vPPR update.
1193  */
1194 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
1195 {
1196         struct kvm_lapic *apic = vcpu->arch.apic;
1197
1198         trace_kvm_eoi(apic, vector);
1199
1200         kvm_ioapic_send_eoi(apic, vector);
1201         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
1202 }
1203 EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
1204
1205 static void apic_send_ipi(struct kvm_lapic *apic)
1206 {
1207         u32 icr_low = kvm_lapic_get_reg(apic, APIC_ICR);
1208         u32 icr_high = kvm_lapic_get_reg(apic, APIC_ICR2);
1209         struct kvm_lapic_irq irq;
1210
1211         irq.vector = icr_low & APIC_VECTOR_MASK;
1212         irq.delivery_mode = icr_low & APIC_MODE_MASK;
1213         irq.dest_mode = icr_low & APIC_DEST_MASK;
1214         irq.level = (icr_low & APIC_INT_ASSERT) != 0;
1215         irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
1216         irq.shorthand = icr_low & APIC_SHORT_MASK;
1217         irq.msi_redir_hint = false;
1218         if (apic_x2apic_mode(apic))
1219                 irq.dest_id = icr_high;
1220         else
1221                 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
1222
1223         trace_kvm_apic_ipi(icr_low, irq.dest_id);
1224
1225         apic_debug("icr_high 0x%x, icr_low 0x%x, "
1226                    "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
1227                    "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x, "
1228                    "msi_redir_hint 0x%x\n",
1229                    icr_high, icr_low, irq.shorthand, irq.dest_id,
1230                    irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
1231                    irq.vector, irq.msi_redir_hint);
1232
1233         kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
1234 }
1235
1236 static u32 apic_get_tmcct(struct kvm_lapic *apic)
1237 {
1238         ktime_t remaining, now;
1239         s64 ns;
1240         u32 tmcct;
1241
1242         ASSERT(apic != NULL);
1243
1244         /* if initial count is 0, current count should also be 0 */
1245         if (kvm_lapic_get_reg(apic, APIC_TMICT) == 0 ||
1246                 apic->lapic_timer.period == 0)
1247                 return 0;
1248
1249         now = ktime_get();
1250         remaining = ktime_sub(apic->lapic_timer.target_expiration, now);
1251         if (ktime_to_ns(remaining) < 0)
1252                 remaining = 0;
1253
1254         ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
1255         tmcct = div64_u64(ns,
1256                          (APIC_BUS_CYCLE_NS * apic->divide_count));
1257
1258         return tmcct;
1259 }
1260
1261 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
1262 {
1263         struct kvm_vcpu *vcpu = apic->vcpu;
1264         struct kvm_run *run = vcpu->run;
1265
1266         kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
1267         run->tpr_access.rip = kvm_rip_read(vcpu);
1268         run->tpr_access.is_write = write;
1269 }
1270
1271 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
1272 {
1273         if (apic->vcpu->arch.tpr_access_reporting)
1274                 __report_tpr_access(apic, write);
1275 }
1276
1277 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
1278 {
1279         u32 val = 0;
1280
1281         if (offset >= LAPIC_MMIO_LENGTH)
1282                 return 0;
1283
1284         switch (offset) {
1285         case APIC_ARBPRI:
1286                 apic_debug("Access APIC ARBPRI register which is for P6\n");
1287                 break;
1288
1289         case APIC_TMCCT:        /* Timer CCR */
1290                 if (apic_lvtt_tscdeadline(apic))
1291                         return 0;
1292
1293                 val = apic_get_tmcct(apic);
1294                 break;
1295         case APIC_PROCPRI:
1296                 apic_update_ppr(apic);
1297                 val = kvm_lapic_get_reg(apic, offset);
1298                 break;
1299         case APIC_TASKPRI:
1300                 report_tpr_access(apic, false);
1301                 /* fall thru */
1302         default:
1303                 val = kvm_lapic_get_reg(apic, offset);
1304                 break;
1305         }
1306
1307         return val;
1308 }
1309
1310 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
1311 {
1312         return container_of(dev, struct kvm_lapic, dev);
1313 }
1314
1315 int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
1316                 void *data)
1317 {
1318         unsigned char alignment = offset & 0xf;
1319         u32 result;
1320         /* this bitmask has a bit cleared for each reserved register */
1321         static const u64 rmask = 0x43ff01ffffffe70cULL;
1322
1323         if ((alignment + len) > 4) {
1324                 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
1325                            offset, len);
1326                 return 1;
1327         }
1328
1329         if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
1330                 apic_debug("KVM_APIC_READ: read reserved register %x\n",
1331                            offset);
1332                 return 1;
1333         }
1334
1335         result = __apic_read(apic, offset & ~0xf);
1336
1337         trace_kvm_apic_read(offset, result);
1338
1339         switch (len) {
1340         case 1:
1341         case 2:
1342         case 4:
1343                 memcpy(data, (char *)&result + alignment, len);
1344                 break;
1345         default:
1346                 printk(KERN_ERR "Local APIC read with len = %x, "
1347                        "should be 1,2, or 4 instead\n", len);
1348                 break;
1349         }
1350         return 0;
1351 }
1352 EXPORT_SYMBOL_GPL(kvm_lapic_reg_read);
1353
1354 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
1355 {
1356         return addr >= apic->base_address &&
1357                 addr < apic->base_address + LAPIC_MMIO_LENGTH;
1358 }
1359
1360 static int apic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
1361                            gpa_t address, int len, void *data)
1362 {
1363         struct kvm_lapic *apic = to_lapic(this);
1364         u32 offset = address - apic->base_address;
1365
1366         if (!apic_mmio_in_range(apic, address))
1367                 return -EOPNOTSUPP;
1368
1369         if (!kvm_apic_hw_enabled(apic) || apic_x2apic_mode(apic)) {
1370                 if (!kvm_check_has_quirk(vcpu->kvm,
1371                                          KVM_X86_QUIRK_LAPIC_MMIO_HOLE))
1372                         return -EOPNOTSUPP;
1373
1374                 memset(data, 0xff, len);
1375                 return 0;
1376         }
1377
1378         kvm_lapic_reg_read(apic, offset, len, data);
1379
1380         return 0;
1381 }
1382
1383 static void update_divide_count(struct kvm_lapic *apic)
1384 {
1385         u32 tmp1, tmp2, tdcr;
1386
1387         tdcr = kvm_lapic_get_reg(apic, APIC_TDCR);
1388         tmp1 = tdcr & 0xf;
1389         tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
1390         apic->divide_count = 0x1 << (tmp2 & 0x7);
1391
1392         apic_debug("timer divide count is 0x%x\n",
1393                                    apic->divide_count);
1394 }
1395
1396 static void limit_periodic_timer_frequency(struct kvm_lapic *apic)
1397 {
1398         /*
1399          * Do not allow the guest to program periodic timers with small
1400          * interval, since the hrtimers are not throttled by the host
1401          * scheduler.
1402          */
1403         if (apic_lvtt_period(apic) && apic->lapic_timer.period) {
1404                 s64 min_period = min_timer_period_us * 1000LL;
1405
1406                 if (apic->lapic_timer.period < min_period) {
1407                         pr_info_ratelimited(
1408                             "kvm: vcpu %i: requested %lld ns "
1409                             "lapic timer period limited to %lld ns\n",
1410                             apic->vcpu->vcpu_id,
1411                             apic->lapic_timer.period, min_period);
1412                         apic->lapic_timer.period = min_period;
1413                 }
1414         }
1415 }
1416
1417 static void apic_update_lvtt(struct kvm_lapic *apic)
1418 {
1419         u32 timer_mode = kvm_lapic_get_reg(apic, APIC_LVTT) &
1420                         apic->lapic_timer.timer_mode_mask;
1421
1422         if (apic->lapic_timer.timer_mode != timer_mode) {
1423                 if (apic_lvtt_tscdeadline(apic) != (timer_mode ==
1424                                 APIC_LVT_TIMER_TSCDEADLINE)) {
1425                         hrtimer_cancel(&apic->lapic_timer.timer);
1426                         kvm_lapic_set_reg(apic, APIC_TMICT, 0);
1427                         apic->lapic_timer.period = 0;
1428                         apic->lapic_timer.tscdeadline = 0;
1429                 }
1430                 apic->lapic_timer.timer_mode = timer_mode;
1431                 limit_periodic_timer_frequency(apic);
1432         }
1433 }
1434
1435 static void apic_timer_expired(struct kvm_lapic *apic)
1436 {
1437         struct kvm_vcpu *vcpu = apic->vcpu;
1438         struct swait_queue_head *q = &vcpu->wq;
1439         struct kvm_timer *ktimer = &apic->lapic_timer;
1440
1441         if (atomic_read(&apic->lapic_timer.pending))
1442                 return;
1443
1444         atomic_inc(&apic->lapic_timer.pending);
1445         kvm_set_pending_timer(vcpu);
1446
1447         /*
1448          * For x86, the atomic_inc() is serialized, thus
1449          * using swait_active() is safe.
1450          */
1451         if (swait_active(q))
1452                 swake_up_one(q);
1453
1454         if (apic_lvtt_tscdeadline(apic))
1455                 ktimer->expired_tscdeadline = ktimer->tscdeadline;
1456 }
1457
1458 /*
1459  * On APICv, this test will cause a busy wait
1460  * during a higher-priority task.
1461  */
1462
1463 static bool lapic_timer_int_injected(struct kvm_vcpu *vcpu)
1464 {
1465         struct kvm_lapic *apic = vcpu->arch.apic;
1466         u32 reg = kvm_lapic_get_reg(apic, APIC_LVTT);
1467
1468         if (kvm_apic_hw_enabled(apic)) {
1469                 int vec = reg & APIC_VECTOR_MASK;
1470                 void *bitmap = apic->regs + APIC_ISR;
1471
1472                 if (vcpu->arch.apicv_active)
1473                         bitmap = apic->regs + APIC_IRR;
1474
1475                 if (apic_test_vector(vec, bitmap))
1476                         return true;
1477         }
1478         return false;
1479 }
1480
1481 void wait_lapic_expire(struct kvm_vcpu *vcpu)
1482 {
1483         struct kvm_lapic *apic = vcpu->arch.apic;
1484         u64 guest_tsc, tsc_deadline, ns;
1485
1486         if (!lapic_in_kernel(vcpu))
1487                 return;
1488
1489         if (apic->lapic_timer.expired_tscdeadline == 0)
1490                 return;
1491
1492         if (!lapic_timer_int_injected(vcpu))
1493                 return;
1494
1495         tsc_deadline = apic->lapic_timer.expired_tscdeadline;
1496         apic->lapic_timer.expired_tscdeadline = 0;
1497         guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1498         trace_kvm_wait_lapic_expire(vcpu->vcpu_id, guest_tsc - tsc_deadline);
1499
1500         /* __delay is delay_tsc whenever the hardware has TSC, thus always.  */
1501         if (guest_tsc < tsc_deadline)
1502                 __delay(min(tsc_deadline - guest_tsc,
1503                         nsec_to_cycles(vcpu, lapic_timer_advance_ns)));
1504
1505         if (!lapic_timer_advance_adjust_done) {
1506                 /* too early */
1507                 if (guest_tsc < tsc_deadline) {
1508                         ns = (tsc_deadline - guest_tsc) * 1000000ULL;
1509                         do_div(ns, vcpu->arch.virtual_tsc_khz);
1510                         lapic_timer_advance_ns -= min((unsigned int)ns,
1511                                 lapic_timer_advance_ns / LAPIC_TIMER_ADVANCE_ADJUST_STEP);
1512                 } else {
1513                 /* too late */
1514                         ns = (guest_tsc - tsc_deadline) * 1000000ULL;
1515                         do_div(ns, vcpu->arch.virtual_tsc_khz);
1516                         lapic_timer_advance_ns += min((unsigned int)ns,
1517                                 lapic_timer_advance_ns / LAPIC_TIMER_ADVANCE_ADJUST_STEP);
1518                 }
1519                 if (abs(guest_tsc - tsc_deadline) < LAPIC_TIMER_ADVANCE_ADJUST_DONE)
1520                         lapic_timer_advance_adjust_done = true;
1521         }
1522 }
1523
1524 static void start_sw_tscdeadline(struct kvm_lapic *apic)
1525 {
1526         u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
1527         u64 ns = 0;
1528         ktime_t expire;
1529         struct kvm_vcpu *vcpu = apic->vcpu;
1530         unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
1531         unsigned long flags;
1532         ktime_t now;
1533
1534         if (unlikely(!tscdeadline || !this_tsc_khz))
1535                 return;
1536
1537         local_irq_save(flags);
1538
1539         now = ktime_get();
1540         guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1541         if (likely(tscdeadline > guest_tsc)) {
1542                 ns = (tscdeadline - guest_tsc) * 1000000ULL;
1543                 do_div(ns, this_tsc_khz);
1544                 expire = ktime_add_ns(now, ns);
1545                 expire = ktime_sub_ns(expire, lapic_timer_advance_ns);
1546                 hrtimer_start(&apic->lapic_timer.timer,
1547                                 expire, HRTIMER_MODE_ABS_PINNED);
1548         } else
1549                 apic_timer_expired(apic);
1550
1551         local_irq_restore(flags);
1552 }
1553
1554 static void update_target_expiration(struct kvm_lapic *apic, uint32_t old_divisor)
1555 {
1556         ktime_t now, remaining;
1557         u64 ns_remaining_old, ns_remaining_new;
1558
1559         apic->lapic_timer.period = (u64)kvm_lapic_get_reg(apic, APIC_TMICT)
1560                 * APIC_BUS_CYCLE_NS * apic->divide_count;
1561         limit_periodic_timer_frequency(apic);
1562
1563         now = ktime_get();
1564         remaining = ktime_sub(apic->lapic_timer.target_expiration, now);
1565         if (ktime_to_ns(remaining) < 0)
1566                 remaining = 0;
1567
1568         ns_remaining_old = ktime_to_ns(remaining);
1569         ns_remaining_new = mul_u64_u32_div(ns_remaining_old,
1570                                            apic->divide_count, old_divisor);
1571
1572         apic->lapic_timer.tscdeadline +=
1573                 nsec_to_cycles(apic->vcpu, ns_remaining_new) -
1574                 nsec_to_cycles(apic->vcpu, ns_remaining_old);
1575         apic->lapic_timer.target_expiration = ktime_add_ns(now, ns_remaining_new);
1576 }
1577
1578 static bool set_target_expiration(struct kvm_lapic *apic)
1579 {
1580         ktime_t now;
1581         u64 tscl = rdtsc();
1582
1583         now = ktime_get();
1584         apic->lapic_timer.period = (u64)kvm_lapic_get_reg(apic, APIC_TMICT)
1585                 * APIC_BUS_CYCLE_NS * apic->divide_count;
1586
1587         if (!apic->lapic_timer.period) {
1588                 apic->lapic_timer.tscdeadline = 0;
1589                 return false;
1590         }
1591
1592         limit_periodic_timer_frequency(apic);
1593
1594         apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
1595                    PRIx64 ", "
1596                    "timer initial count 0x%x, period %lldns, "
1597                    "expire @ 0x%016" PRIx64 ".\n", __func__,
1598                    APIC_BUS_CYCLE_NS, ktime_to_ns(now),
1599                    kvm_lapic_get_reg(apic, APIC_TMICT),
1600                    apic->lapic_timer.period,
1601                    ktime_to_ns(ktime_add_ns(now,
1602                                 apic->lapic_timer.period)));
1603
1604         apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) +
1605                 nsec_to_cycles(apic->vcpu, apic->lapic_timer.period);
1606         apic->lapic_timer.target_expiration = ktime_add_ns(now, apic->lapic_timer.period);
1607
1608         return true;
1609 }
1610
1611 static void advance_periodic_target_expiration(struct kvm_lapic *apic)
1612 {
1613         ktime_t now = ktime_get();
1614         u64 tscl = rdtsc();
1615         ktime_t delta;
1616
1617         /*
1618          * Synchronize both deadlines to the same time source or
1619          * differences in the periods (caused by differences in the
1620          * underlying clocks or numerical approximation errors) will
1621          * cause the two to drift apart over time as the errors
1622          * accumulate.
1623          */
1624         apic->lapic_timer.target_expiration =
1625                 ktime_add_ns(apic->lapic_timer.target_expiration,
1626                                 apic->lapic_timer.period);
1627         delta = ktime_sub(apic->lapic_timer.target_expiration, now);
1628         apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) +
1629                 nsec_to_cycles(apic->vcpu, delta);
1630 }
1631
1632 static void start_sw_period(struct kvm_lapic *apic)
1633 {
1634         if (!apic->lapic_timer.period)
1635                 return;
1636
1637         if (ktime_after(ktime_get(),
1638                         apic->lapic_timer.target_expiration)) {
1639                 apic_timer_expired(apic);
1640
1641                 if (apic_lvtt_oneshot(apic))
1642                         return;
1643
1644                 advance_periodic_target_expiration(apic);
1645         }
1646
1647         hrtimer_start(&apic->lapic_timer.timer,
1648                 apic->lapic_timer.target_expiration,
1649                 HRTIMER_MODE_ABS_PINNED);
1650 }
1651
1652 bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu)
1653 {
1654         if (!lapic_in_kernel(vcpu))
1655                 return false;
1656
1657         return vcpu->arch.apic->lapic_timer.hv_timer_in_use;
1658 }
1659 EXPORT_SYMBOL_GPL(kvm_lapic_hv_timer_in_use);
1660
1661 static void cancel_hv_timer(struct kvm_lapic *apic)
1662 {
1663         WARN_ON(preemptible());
1664         WARN_ON(!apic->lapic_timer.hv_timer_in_use);
1665         kvm_x86_ops->cancel_hv_timer(apic->vcpu);
1666         apic->lapic_timer.hv_timer_in_use = false;
1667 }
1668
1669 static bool start_hv_timer(struct kvm_lapic *apic)
1670 {
1671         struct kvm_timer *ktimer = &apic->lapic_timer;
1672         int r;
1673
1674         WARN_ON(preemptible());
1675         if (!kvm_x86_ops->set_hv_timer)
1676                 return false;
1677
1678         if (!apic_lvtt_period(apic) && atomic_read(&ktimer->pending))
1679                 return false;
1680
1681         if (!ktimer->tscdeadline)
1682                 return false;
1683
1684         r = kvm_x86_ops->set_hv_timer(apic->vcpu, ktimer->tscdeadline);
1685         if (r < 0)
1686                 return false;
1687
1688         ktimer->hv_timer_in_use = true;
1689         hrtimer_cancel(&ktimer->timer);
1690
1691         /*
1692          * Also recheck ktimer->pending, in case the sw timer triggered in
1693          * the window.  For periodic timer, leave the hv timer running for
1694          * simplicity, and the deadline will be recomputed on the next vmexit.
1695          */
1696         if (!apic_lvtt_period(apic) && (r || atomic_read(&ktimer->pending))) {
1697                 if (r)
1698                         apic_timer_expired(apic);
1699                 return false;
1700         }
1701
1702         trace_kvm_hv_timer_state(apic->vcpu->vcpu_id, true);
1703         return true;
1704 }
1705
1706 static void start_sw_timer(struct kvm_lapic *apic)
1707 {
1708         struct kvm_timer *ktimer = &apic->lapic_timer;
1709
1710         WARN_ON(preemptible());
1711         if (apic->lapic_timer.hv_timer_in_use)
1712                 cancel_hv_timer(apic);
1713         if (!apic_lvtt_period(apic) && atomic_read(&ktimer->pending))
1714                 return;
1715
1716         if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic))
1717                 start_sw_period(apic);
1718         else if (apic_lvtt_tscdeadline(apic))
1719                 start_sw_tscdeadline(apic);
1720         trace_kvm_hv_timer_state(apic->vcpu->vcpu_id, false);
1721 }
1722
1723 static void restart_apic_timer(struct kvm_lapic *apic)
1724 {
1725         preempt_disable();
1726         if (!start_hv_timer(apic))
1727                 start_sw_timer(apic);
1728         preempt_enable();
1729 }
1730
1731 void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu)
1732 {
1733         struct kvm_lapic *apic = vcpu->arch.apic;
1734
1735         preempt_disable();
1736         /* If the preempt notifier has already run, it also called apic_timer_expired */
1737         if (!apic->lapic_timer.hv_timer_in_use)
1738                 goto out;
1739         WARN_ON(swait_active(&vcpu->wq));
1740         cancel_hv_timer(apic);
1741         apic_timer_expired(apic);
1742
1743         if (apic_lvtt_period(apic) && apic->lapic_timer.period) {
1744                 advance_periodic_target_expiration(apic);
1745                 restart_apic_timer(apic);
1746         }
1747 out:
1748         preempt_enable();
1749 }
1750 EXPORT_SYMBOL_GPL(kvm_lapic_expired_hv_timer);
1751
1752 void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu)
1753 {
1754         restart_apic_timer(vcpu->arch.apic);
1755 }
1756 EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_hv_timer);
1757
1758 void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu)
1759 {
1760         struct kvm_lapic *apic = vcpu->arch.apic;
1761
1762         preempt_disable();
1763         /* Possibly the TSC deadline timer is not enabled yet */
1764         if (apic->lapic_timer.hv_timer_in_use)
1765                 start_sw_timer(apic);
1766         preempt_enable();
1767 }
1768 EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_sw_timer);
1769
1770 void kvm_lapic_restart_hv_timer(struct kvm_vcpu *vcpu)
1771 {
1772         struct kvm_lapic *apic = vcpu->arch.apic;
1773
1774         WARN_ON(!apic->lapic_timer.hv_timer_in_use);
1775         restart_apic_timer(apic);
1776 }
1777
1778 static void start_apic_timer(struct kvm_lapic *apic)
1779 {
1780         atomic_set(&apic->lapic_timer.pending, 0);
1781
1782         if ((apic_lvtt_period(apic) || apic_lvtt_oneshot(apic))
1783             && !set_target_expiration(apic))
1784                 return;
1785
1786         restart_apic_timer(apic);
1787 }
1788
1789 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1790 {
1791         bool lvt0_in_nmi_mode = apic_lvt_nmi_mode(lvt0_val);
1792
1793         if (apic->lvt0_in_nmi_mode != lvt0_in_nmi_mode) {
1794                 apic->lvt0_in_nmi_mode = lvt0_in_nmi_mode;
1795                 if (lvt0_in_nmi_mode) {
1796                         apic_debug("Receive NMI setting on APIC_LVT0 "
1797                                    "for cpu %d\n", apic->vcpu->vcpu_id);
1798                         atomic_inc(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1799                 } else
1800                         atomic_dec(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1801         }
1802 }
1803
1804 int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
1805 {
1806         int ret = 0;
1807
1808         trace_kvm_apic_write(reg, val);
1809
1810         switch (reg) {
1811         case APIC_ID:           /* Local APIC ID */
1812                 if (!apic_x2apic_mode(apic))
1813                         kvm_apic_set_xapic_id(apic, val >> 24);
1814                 else
1815                         ret = 1;
1816                 break;
1817
1818         case APIC_TASKPRI:
1819                 report_tpr_access(apic, true);
1820                 apic_set_tpr(apic, val & 0xff);
1821                 break;
1822
1823         case APIC_EOI:
1824                 apic_set_eoi(apic);
1825                 break;
1826
1827         case APIC_LDR:
1828                 if (!apic_x2apic_mode(apic))
1829                         kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
1830                 else
1831                         ret = 1;
1832                 break;
1833
1834         case APIC_DFR:
1835                 if (!apic_x2apic_mode(apic)) {
1836                         kvm_lapic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
1837                         recalculate_apic_map(apic->vcpu->kvm);
1838                 } else
1839                         ret = 1;
1840                 break;
1841
1842         case APIC_SPIV: {
1843                 u32 mask = 0x3ff;
1844                 if (kvm_lapic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
1845                         mask |= APIC_SPIV_DIRECTED_EOI;
1846                 apic_set_spiv(apic, val & mask);
1847                 if (!(val & APIC_SPIV_APIC_ENABLED)) {
1848                         int i;
1849                         u32 lvt_val;
1850
1851                         for (i = 0; i < KVM_APIC_LVT_NUM; i++) {
1852                                 lvt_val = kvm_lapic_get_reg(apic,
1853                                                        APIC_LVTT + 0x10 * i);
1854                                 kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i,
1855                                              lvt_val | APIC_LVT_MASKED);
1856                         }
1857                         apic_update_lvtt(apic);
1858                         atomic_set(&apic->lapic_timer.pending, 0);
1859
1860                 }
1861                 break;
1862         }
1863         case APIC_ICR:
1864                 /* No delay here, so we always clear the pending bit */
1865                 kvm_lapic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
1866                 apic_send_ipi(apic);
1867                 break;
1868
1869         case APIC_ICR2:
1870                 if (!apic_x2apic_mode(apic))
1871                         val &= 0xff000000;
1872                 kvm_lapic_set_reg(apic, APIC_ICR2, val);
1873                 break;
1874
1875         case APIC_LVT0:
1876                 apic_manage_nmi_watchdog(apic, val);
1877         case APIC_LVTTHMR:
1878         case APIC_LVTPC:
1879         case APIC_LVT1:
1880         case APIC_LVTERR:
1881                 /* TODO: Check vector */
1882                 if (!kvm_apic_sw_enabled(apic))
1883                         val |= APIC_LVT_MASKED;
1884
1885                 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
1886                 kvm_lapic_set_reg(apic, reg, val);
1887
1888                 break;
1889
1890         case APIC_LVTT:
1891                 if (!kvm_apic_sw_enabled(apic))
1892                         val |= APIC_LVT_MASKED;
1893                 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
1894                 kvm_lapic_set_reg(apic, APIC_LVTT, val);
1895                 apic_update_lvtt(apic);
1896                 break;
1897
1898         case APIC_TMICT:
1899                 if (apic_lvtt_tscdeadline(apic))
1900                         break;
1901
1902                 hrtimer_cancel(&apic->lapic_timer.timer);
1903                 kvm_lapic_set_reg(apic, APIC_TMICT, val);
1904                 start_apic_timer(apic);
1905                 break;
1906
1907         case APIC_TDCR: {
1908                 uint32_t old_divisor = apic->divide_count;
1909
1910                 if (val & 4)
1911                         apic_debug("KVM_WRITE:TDCR %x\n", val);
1912                 kvm_lapic_set_reg(apic, APIC_TDCR, val);
1913                 update_divide_count(apic);
1914                 if (apic->divide_count != old_divisor &&
1915                                 apic->lapic_timer.period) {
1916                         hrtimer_cancel(&apic->lapic_timer.timer);
1917                         update_target_expiration(apic, old_divisor);
1918                         restart_apic_timer(apic);
1919                 }
1920                 break;
1921         }
1922         case APIC_ESR:
1923                 if (apic_x2apic_mode(apic) && val != 0) {
1924                         apic_debug("KVM_WRITE:ESR not zero %x\n", val);
1925                         ret = 1;
1926                 }
1927                 break;
1928
1929         case APIC_SELF_IPI:
1930                 if (apic_x2apic_mode(apic)) {
1931                         kvm_lapic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
1932                 } else
1933                         ret = 1;
1934                 break;
1935         default:
1936                 ret = 1;
1937                 break;
1938         }
1939         if (ret)
1940                 apic_debug("Local APIC Write to read-only register %x\n", reg);
1941         return ret;
1942 }
1943 EXPORT_SYMBOL_GPL(kvm_lapic_reg_write);
1944
1945 static int apic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
1946                             gpa_t address, int len, const void *data)
1947 {
1948         struct kvm_lapic *apic = to_lapic(this);
1949         unsigned int offset = address - apic->base_address;
1950         u32 val;
1951
1952         if (!apic_mmio_in_range(apic, address))
1953                 return -EOPNOTSUPP;
1954
1955         if (!kvm_apic_hw_enabled(apic) || apic_x2apic_mode(apic)) {
1956                 if (!kvm_check_has_quirk(vcpu->kvm,
1957                                          KVM_X86_QUIRK_LAPIC_MMIO_HOLE))
1958                         return -EOPNOTSUPP;
1959
1960                 return 0;
1961         }
1962
1963         /*
1964          * APIC register must be aligned on 128-bits boundary.
1965          * 32/64/128 bits registers must be accessed thru 32 bits.
1966          * Refer SDM 8.4.1
1967          */
1968         if (len != 4 || (offset & 0xf)) {
1969                 /* Don't shout loud, $infamous_os would cause only noise. */
1970                 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
1971                 return 0;
1972         }
1973
1974         val = *(u32*)data;
1975
1976         /* too common printing */
1977         if (offset != APIC_EOI)
1978                 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1979                            "0x%x\n", __func__, offset, len, val);
1980
1981         kvm_lapic_reg_write(apic, offset & 0xff0, val);
1982
1983         return 0;
1984 }
1985
1986 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
1987 {
1988         kvm_lapic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
1989 }
1990 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
1991
1992 /* emulate APIC access in a trap manner */
1993 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
1994 {
1995         u32 val = 0;
1996
1997         /* hw has done the conditional check and inst decode */
1998         offset &= 0xff0;
1999
2000         kvm_lapic_reg_read(vcpu->arch.apic, offset, 4, &val);
2001
2002         /* TODO: optimize to just emulate side effect w/o one more write */
2003         kvm_lapic_reg_write(vcpu->arch.apic, offset, val);
2004 }
2005 EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
2006
2007 void kvm_free_lapic(struct kvm_vcpu *vcpu)
2008 {
2009         struct kvm_lapic *apic = vcpu->arch.apic;
2010
2011         if (!vcpu->arch.apic)
2012                 return;
2013
2014         hrtimer_cancel(&apic->lapic_timer.timer);
2015
2016         if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
2017                 static_key_slow_dec_deferred(&apic_hw_disabled);
2018
2019         if (!apic->sw_enabled)
2020                 static_key_slow_dec_deferred(&apic_sw_disabled);
2021
2022         if (apic->regs)
2023                 free_page((unsigned long)apic->regs);
2024
2025         kfree(apic);
2026 }
2027
2028 /*
2029  *----------------------------------------------------------------------
2030  * LAPIC interface
2031  *----------------------------------------------------------------------
2032  */
2033 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
2034 {
2035         struct kvm_lapic *apic = vcpu->arch.apic;
2036
2037         if (!lapic_in_kernel(vcpu) ||
2038                 !apic_lvtt_tscdeadline(apic))
2039                 return 0;
2040
2041         return apic->lapic_timer.tscdeadline;
2042 }
2043
2044 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
2045 {
2046         struct kvm_lapic *apic = vcpu->arch.apic;
2047
2048         if (!lapic_in_kernel(vcpu) || apic_lvtt_oneshot(apic) ||
2049                         apic_lvtt_period(apic))
2050                 return;
2051
2052         hrtimer_cancel(&apic->lapic_timer.timer);
2053         apic->lapic_timer.tscdeadline = data;
2054         start_apic_timer(apic);
2055 }
2056
2057 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
2058 {
2059         struct kvm_lapic *apic = vcpu->arch.apic;
2060
2061         apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
2062                      | (kvm_lapic_get_reg(apic, APIC_TASKPRI) & 4));
2063 }
2064
2065 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
2066 {
2067         u64 tpr;
2068
2069         tpr = (u64) kvm_lapic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
2070
2071         return (tpr & 0xf0) >> 4;
2072 }
2073
2074 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
2075 {
2076         u64 old_value = vcpu->arch.apic_base;
2077         struct kvm_lapic *apic = vcpu->arch.apic;
2078
2079         if (!apic)
2080                 value |= MSR_IA32_APICBASE_BSP;
2081
2082         vcpu->arch.apic_base = value;
2083
2084         if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE)
2085                 kvm_update_cpuid(vcpu);
2086
2087         if (!apic)
2088                 return;
2089
2090         /* update jump label if enable bit changes */
2091         if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
2092                 if (value & MSR_IA32_APICBASE_ENABLE) {
2093                         kvm_apic_set_xapic_id(apic, vcpu->vcpu_id);
2094                         static_key_slow_dec_deferred(&apic_hw_disabled);
2095                 } else {
2096                         static_key_slow_inc(&apic_hw_disabled.key);
2097                         recalculate_apic_map(vcpu->kvm);
2098                 }
2099         }
2100
2101         if (((old_value ^ value) & X2APIC_ENABLE) && (value & X2APIC_ENABLE))
2102                 kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id);
2103
2104         if ((old_value ^ value) & (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE))
2105                 kvm_x86_ops->set_virtual_apic_mode(vcpu);
2106
2107         apic->base_address = apic->vcpu->arch.apic_base &
2108                              MSR_IA32_APICBASE_BASE;
2109
2110         if ((value & MSR_IA32_APICBASE_ENABLE) &&
2111              apic->base_address != APIC_DEFAULT_PHYS_BASE)
2112                 pr_warn_once("APIC base relocation is unsupported by KVM");
2113
2114         /* with FSB delivery interrupt, we can restart APIC functionality */
2115         apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
2116                    "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
2117
2118 }
2119
2120 void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event)
2121 {
2122         struct kvm_lapic *apic = vcpu->arch.apic;
2123         int i;
2124
2125         if (!apic)
2126                 return;
2127
2128         apic_debug("%s\n", __func__);
2129
2130         /* Stop the timer in case it's a reset to an active apic */
2131         hrtimer_cancel(&apic->lapic_timer.timer);
2132
2133         if (!init_event) {
2134                 kvm_lapic_set_base(vcpu, APIC_DEFAULT_PHYS_BASE |
2135                                          MSR_IA32_APICBASE_ENABLE);
2136                 kvm_apic_set_xapic_id(apic, vcpu->vcpu_id);
2137         }
2138         kvm_apic_set_version(apic->vcpu);
2139
2140         for (i = 0; i < KVM_APIC_LVT_NUM; i++)
2141                 kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
2142         apic_update_lvtt(apic);
2143         if (kvm_vcpu_is_reset_bsp(vcpu) &&
2144             kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_LINT0_REENABLED))
2145                 kvm_lapic_set_reg(apic, APIC_LVT0,
2146                              SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
2147         apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0));
2148
2149         kvm_lapic_set_reg(apic, APIC_DFR, 0xffffffffU);
2150         apic_set_spiv(apic, 0xff);
2151         kvm_lapic_set_reg(apic, APIC_TASKPRI, 0);
2152         if (!apic_x2apic_mode(apic))
2153                 kvm_apic_set_ldr(apic, 0);
2154         kvm_lapic_set_reg(apic, APIC_ESR, 0);
2155         kvm_lapic_set_reg(apic, APIC_ICR, 0);
2156         kvm_lapic_set_reg(apic, APIC_ICR2, 0);
2157         kvm_lapic_set_reg(apic, APIC_TDCR, 0);
2158         kvm_lapic_set_reg(apic, APIC_TMICT, 0);
2159         for (i = 0; i < 8; i++) {
2160                 kvm_lapic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
2161                 kvm_lapic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
2162                 kvm_lapic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
2163         }
2164         apic->irr_pending = vcpu->arch.apicv_active;
2165         apic->isr_count = vcpu->arch.apicv_active ? 1 : 0;
2166         apic->highest_isr_cache = -1;
2167         update_divide_count(apic);
2168         atomic_set(&apic->lapic_timer.pending, 0);
2169         if (kvm_vcpu_is_bsp(vcpu))
2170                 kvm_lapic_set_base(vcpu,
2171                                 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
2172         vcpu->arch.pv_eoi.msr_val = 0;
2173         apic_update_ppr(apic);
2174         if (vcpu->arch.apicv_active) {
2175                 kvm_x86_ops->apicv_post_state_restore(vcpu);
2176                 kvm_x86_ops->hwapic_irr_update(vcpu, -1);
2177                 kvm_x86_ops->hwapic_isr_update(vcpu, -1);
2178         }
2179
2180         vcpu->arch.apic_arb_prio = 0;
2181         vcpu->arch.apic_attention = 0;
2182
2183         apic_debug("%s: vcpu=%p, id=0x%x, base_msr="
2184                    "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
2185                    vcpu, kvm_lapic_get_reg(apic, APIC_ID),
2186                    vcpu->arch.apic_base, apic->base_address);
2187 }
2188
2189 /*
2190  *----------------------------------------------------------------------
2191  * timer interface
2192  *----------------------------------------------------------------------
2193  */
2194
2195 static bool lapic_is_periodic(struct kvm_lapic *apic)
2196 {
2197         return apic_lvtt_period(apic);
2198 }
2199
2200 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
2201 {
2202         struct kvm_lapic *apic = vcpu->arch.apic;
2203
2204         if (apic_enabled(apic) && apic_lvt_enabled(apic, APIC_LVTT))
2205                 return atomic_read(&apic->lapic_timer.pending);
2206
2207         return 0;
2208 }
2209
2210 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
2211 {
2212         u32 reg = kvm_lapic_get_reg(apic, lvt_type);
2213         int vector, mode, trig_mode;
2214
2215         if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
2216                 vector = reg & APIC_VECTOR_MASK;
2217                 mode = reg & APIC_MODE_MASK;
2218                 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
2219                 return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
2220                                         NULL);
2221         }
2222         return 0;
2223 }
2224
2225 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
2226 {
2227         struct kvm_lapic *apic = vcpu->arch.apic;
2228
2229         if (apic)
2230                 kvm_apic_local_deliver(apic, APIC_LVT0);
2231 }
2232
2233 static const struct kvm_io_device_ops apic_mmio_ops = {
2234         .read     = apic_mmio_read,
2235         .write    = apic_mmio_write,
2236 };
2237
2238 static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
2239 {
2240         struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
2241         struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
2242
2243         apic_timer_expired(apic);
2244
2245         if (lapic_is_periodic(apic)) {
2246                 advance_periodic_target_expiration(apic);
2247                 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
2248                 return HRTIMER_RESTART;
2249         } else
2250                 return HRTIMER_NORESTART;
2251 }
2252
2253 int kvm_create_lapic(struct kvm_vcpu *vcpu)
2254 {
2255         struct kvm_lapic *apic;
2256
2257         ASSERT(vcpu != NULL);
2258         apic_debug("apic_init %d\n", vcpu->vcpu_id);
2259
2260         apic = kzalloc(sizeof(*apic), GFP_KERNEL);
2261         if (!apic)
2262                 goto nomem;
2263
2264         vcpu->arch.apic = apic;
2265
2266         apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
2267         if (!apic->regs) {
2268                 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
2269                        vcpu->vcpu_id);
2270                 goto nomem_free_apic;
2271         }
2272         apic->vcpu = vcpu;
2273
2274         hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
2275                      HRTIMER_MODE_ABS_PINNED);
2276         apic->lapic_timer.timer.function = apic_timer_fn;
2277
2278         /*
2279          * APIC is created enabled. This will prevent kvm_lapic_set_base from
2280          * thinking that APIC satet has changed.
2281          */
2282         vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
2283         static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
2284         kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
2285
2286         return 0;
2287 nomem_free_apic:
2288         kfree(apic);
2289 nomem:
2290         return -ENOMEM;
2291 }
2292
2293 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
2294 {
2295         struct kvm_lapic *apic = vcpu->arch.apic;
2296         u32 ppr;
2297
2298         if (!apic_enabled(apic))
2299                 return -1;
2300
2301         __apic_update_ppr(apic, &ppr);
2302         return apic_has_interrupt_for_ppr(apic, ppr);
2303 }
2304
2305 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
2306 {
2307         u32 lvt0 = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LVT0);
2308         int r = 0;
2309
2310         if (!kvm_apic_hw_enabled(vcpu->arch.apic))
2311                 r = 1;
2312         if ((lvt0 & APIC_LVT_MASKED) == 0 &&
2313             GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
2314                 r = 1;
2315         return r;
2316 }
2317
2318 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
2319 {
2320         struct kvm_lapic *apic = vcpu->arch.apic;
2321
2322         if (atomic_read(&apic->lapic_timer.pending) > 0) {
2323                 kvm_apic_local_deliver(apic, APIC_LVTT);
2324                 if (apic_lvtt_tscdeadline(apic))
2325                         apic->lapic_timer.tscdeadline = 0;
2326                 if (apic_lvtt_oneshot(apic)) {
2327                         apic->lapic_timer.tscdeadline = 0;
2328                         apic->lapic_timer.target_expiration = 0;
2329                 }
2330                 atomic_set(&apic->lapic_timer.pending, 0);
2331         }
2332 }
2333
2334 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
2335 {
2336         int vector = kvm_apic_has_interrupt(vcpu);
2337         struct kvm_lapic *apic = vcpu->arch.apic;
2338         u32 ppr;
2339
2340         if (vector == -1)
2341                 return -1;
2342
2343         /*
2344          * We get here even with APIC virtualization enabled, if doing
2345          * nested virtualization and L1 runs with the "acknowledge interrupt
2346          * on exit" mode.  Then we cannot inject the interrupt via RVI,
2347          * because the process would deliver it through the IDT.
2348          */
2349
2350         apic_clear_irr(vector, apic);
2351         if (test_bit(vector, vcpu_to_synic(vcpu)->auto_eoi_bitmap)) {
2352                 /*
2353                  * For auto-EOI interrupts, there might be another pending
2354                  * interrupt above PPR, so check whether to raise another
2355                  * KVM_REQ_EVENT.
2356                  */
2357                 apic_update_ppr(apic);
2358         } else {
2359                 /*
2360                  * For normal interrupts, PPR has been raised and there cannot
2361                  * be a higher-priority pending interrupt---except if there was
2362                  * a concurrent interrupt injection, but that would have
2363                  * triggered KVM_REQ_EVENT already.
2364                  */
2365                 apic_set_isr(vector, apic);
2366                 __apic_update_ppr(apic, &ppr);
2367         }
2368
2369         return vector;
2370 }
2371
2372 static int kvm_apic_state_fixup(struct kvm_vcpu *vcpu,
2373                 struct kvm_lapic_state *s, bool set)
2374 {
2375         if (apic_x2apic_mode(vcpu->arch.apic)) {
2376                 u32 *id = (u32 *)(s->regs + APIC_ID);
2377                 u32 *ldr = (u32 *)(s->regs + APIC_LDR);
2378
2379                 if (vcpu->kvm->arch.x2apic_format) {
2380                         if (*id != vcpu->vcpu_id)
2381                                 return -EINVAL;
2382                 } else {
2383                         if (set)
2384                                 *id >>= 24;
2385                         else
2386                                 *id <<= 24;
2387                 }
2388
2389                 /* In x2APIC mode, the LDR is fixed and based on the id */
2390                 if (set)
2391                         *ldr = kvm_apic_calc_x2apic_ldr(*id);
2392         }
2393
2394         return 0;
2395 }
2396
2397 int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s)
2398 {
2399         memcpy(s->regs, vcpu->arch.apic->regs, sizeof(*s));
2400         return kvm_apic_state_fixup(vcpu, s, false);
2401 }
2402
2403 int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s)
2404 {
2405         struct kvm_lapic *apic = vcpu->arch.apic;
2406         int r;
2407
2408
2409         kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
2410         /* set SPIV separately to get count of SW disabled APICs right */
2411         apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
2412
2413         r = kvm_apic_state_fixup(vcpu, s, true);
2414         if (r)
2415                 return r;
2416         memcpy(vcpu->arch.apic->regs, s->regs, sizeof(*s));
2417
2418         recalculate_apic_map(vcpu->kvm);
2419         kvm_apic_set_version(vcpu);
2420
2421         apic_update_ppr(apic);
2422         hrtimer_cancel(&apic->lapic_timer.timer);
2423         apic_update_lvtt(apic);
2424         apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0));
2425         update_divide_count(apic);
2426         start_apic_timer(apic);
2427         apic->irr_pending = true;
2428         apic->isr_count = vcpu->arch.apicv_active ?
2429                                 1 : count_vectors(apic->regs + APIC_ISR);
2430         apic->highest_isr_cache = -1;
2431         if (vcpu->arch.apicv_active) {
2432                 kvm_x86_ops->apicv_post_state_restore(vcpu);
2433                 kvm_x86_ops->hwapic_irr_update(vcpu,
2434                                 apic_find_highest_irr(apic));
2435                 kvm_x86_ops->hwapic_isr_update(vcpu,
2436                                 apic_find_highest_isr(apic));
2437         }
2438         kvm_make_request(KVM_REQ_EVENT, vcpu);
2439         if (ioapic_in_kernel(vcpu->kvm))
2440                 kvm_rtc_eoi_tracking_restore_one(vcpu);
2441
2442         vcpu->arch.apic_arb_prio = 0;
2443
2444         return 0;
2445 }
2446
2447 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
2448 {
2449         struct hrtimer *timer;
2450
2451         if (!lapic_in_kernel(vcpu))
2452                 return;
2453
2454         timer = &vcpu->arch.apic->lapic_timer.timer;
2455         if (hrtimer_cancel(timer))
2456                 hrtimer_start_expires(timer, HRTIMER_MODE_ABS_PINNED);
2457 }
2458
2459 /*
2460  * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
2461  *
2462  * Detect whether guest triggered PV EOI since the
2463  * last entry. If yes, set EOI on guests's behalf.
2464  * Clear PV EOI in guest memory in any case.
2465  */
2466 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
2467                                         struct kvm_lapic *apic)
2468 {
2469         bool pending;
2470         int vector;
2471         /*
2472          * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
2473          * and KVM_PV_EOI_ENABLED in guest memory as follows:
2474          *
2475          * KVM_APIC_PV_EOI_PENDING is unset:
2476          *      -> host disabled PV EOI.
2477          * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
2478          *      -> host enabled PV EOI, guest did not execute EOI yet.
2479          * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
2480          *      -> host enabled PV EOI, guest executed EOI.
2481          */
2482         BUG_ON(!pv_eoi_enabled(vcpu));
2483         pending = pv_eoi_get_pending(vcpu);
2484         /*
2485          * Clear pending bit in any case: it will be set again on vmentry.
2486          * While this might not be ideal from performance point of view,
2487          * this makes sure pv eoi is only enabled when we know it's safe.
2488          */
2489         pv_eoi_clr_pending(vcpu);
2490         if (pending)
2491                 return;
2492         vector = apic_set_eoi(apic);
2493         trace_kvm_pv_eoi(apic, vector);
2494 }
2495
2496 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
2497 {
2498         u32 data;
2499
2500         if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
2501                 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
2502
2503         if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
2504                 return;
2505
2506         if (kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
2507                                   sizeof(u32)))
2508                 return;
2509
2510         apic_set_tpr(vcpu->arch.apic, data & 0xff);
2511 }
2512
2513 /*
2514  * apic_sync_pv_eoi_to_guest - called before vmentry
2515  *
2516  * Detect whether it's safe to enable PV EOI and
2517  * if yes do so.
2518  */
2519 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
2520                                         struct kvm_lapic *apic)
2521 {
2522         if (!pv_eoi_enabled(vcpu) ||
2523             /* IRR set or many bits in ISR: could be nested. */
2524             apic->irr_pending ||
2525             /* Cache not set: could be safe but we don't bother. */
2526             apic->highest_isr_cache == -1 ||
2527             /* Need EOI to update ioapic. */
2528             kvm_ioapic_handles_vector(apic, apic->highest_isr_cache)) {
2529                 /*
2530                  * PV EOI was disabled by apic_sync_pv_eoi_from_guest
2531                  * so we need not do anything here.
2532                  */
2533                 return;
2534         }
2535
2536         pv_eoi_set_pending(apic->vcpu);
2537 }
2538
2539 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
2540 {
2541         u32 data, tpr;
2542         int max_irr, max_isr;
2543         struct kvm_lapic *apic = vcpu->arch.apic;
2544
2545         apic_sync_pv_eoi_to_guest(vcpu, apic);
2546
2547         if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
2548                 return;
2549
2550         tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI) & 0xff;
2551         max_irr = apic_find_highest_irr(apic);
2552         if (max_irr < 0)
2553                 max_irr = 0;
2554         max_isr = apic_find_highest_isr(apic);
2555         if (max_isr < 0)
2556                 max_isr = 0;
2557         data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
2558
2559         kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
2560                                 sizeof(u32));
2561 }
2562
2563 int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
2564 {
2565         if (vapic_addr) {
2566                 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2567                                         &vcpu->arch.apic->vapic_cache,
2568                                         vapic_addr, sizeof(u32)))
2569                         return -EINVAL;
2570                 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
2571         } else {
2572                 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
2573         }
2574
2575         vcpu->arch.apic->vapic_addr = vapic_addr;
2576         return 0;
2577 }
2578
2579 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
2580 {
2581         struct kvm_lapic *apic = vcpu->arch.apic;
2582         u32 reg = (msr - APIC_BASE_MSR) << 4;
2583
2584         if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
2585                 return 1;
2586
2587         if (reg == APIC_ICR2)
2588                 return 1;
2589
2590         /* if this is ICR write vector before command */
2591         if (reg == APIC_ICR)
2592                 kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2593         return kvm_lapic_reg_write(apic, reg, (u32)data);
2594 }
2595
2596 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
2597 {
2598         struct kvm_lapic *apic = vcpu->arch.apic;
2599         u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
2600
2601         if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
2602                 return 1;
2603
2604         if (reg == APIC_DFR || reg == APIC_ICR2) {
2605                 apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n",
2606                            reg);
2607                 return 1;
2608         }
2609
2610         if (kvm_lapic_reg_read(apic, reg, 4, &low))
2611                 return 1;
2612         if (reg == APIC_ICR)
2613                 kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high);
2614
2615         *data = (((u64)high) << 32) | low;
2616
2617         return 0;
2618 }
2619
2620 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
2621 {
2622         struct kvm_lapic *apic = vcpu->arch.apic;
2623
2624         if (!lapic_in_kernel(vcpu))
2625                 return 1;
2626
2627         /* if this is ICR write vector before command */
2628         if (reg == APIC_ICR)
2629                 kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2630         return kvm_lapic_reg_write(apic, reg, (u32)data);
2631 }
2632
2633 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
2634 {
2635         struct kvm_lapic *apic = vcpu->arch.apic;
2636         u32 low, high = 0;
2637
2638         if (!lapic_in_kernel(vcpu))
2639                 return 1;
2640
2641         if (kvm_lapic_reg_read(apic, reg, 4, &low))
2642                 return 1;
2643         if (reg == APIC_ICR)
2644                 kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high);
2645
2646         *data = (((u64)high) << 32) | low;
2647
2648         return 0;
2649 }
2650
2651 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data, unsigned long len)
2652 {
2653         u64 addr = data & ~KVM_MSR_ENABLED;
2654         struct gfn_to_hva_cache *ghc = &vcpu->arch.pv_eoi.data;
2655         unsigned long new_len;
2656
2657         if (!IS_ALIGNED(addr, 4))
2658                 return 1;
2659
2660         vcpu->arch.pv_eoi.msr_val = data;
2661         if (!pv_eoi_enabled(vcpu))
2662                 return 0;
2663
2664         if (addr == ghc->gpa && len <= ghc->len)
2665                 new_len = ghc->len;
2666         else
2667                 new_len = len;
2668
2669         return kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc, addr, new_len);
2670 }
2671
2672 void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
2673 {
2674         struct kvm_lapic *apic = vcpu->arch.apic;
2675         u8 sipi_vector;
2676         unsigned long pe;
2677
2678         if (!lapic_in_kernel(vcpu) || !apic->pending_events)
2679                 return;
2680
2681         /*
2682          * INITs are latched while in SMM.  Because an SMM CPU cannot
2683          * be in KVM_MP_STATE_INIT_RECEIVED state, just eat SIPIs
2684          * and delay processing of INIT until the next RSM.
2685          */
2686         if (is_smm(vcpu)) {
2687                 WARN_ON_ONCE(vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED);
2688                 if (test_bit(KVM_APIC_SIPI, &apic->pending_events))
2689                         clear_bit(KVM_APIC_SIPI, &apic->pending_events);
2690                 return;
2691         }
2692
2693         pe = xchg(&apic->pending_events, 0);
2694         if (test_bit(KVM_APIC_INIT, &pe)) {
2695                 kvm_vcpu_reset(vcpu, true);
2696                 if (kvm_vcpu_is_bsp(apic->vcpu))
2697                         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2698                 else
2699                         vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
2700         }
2701         if (test_bit(KVM_APIC_SIPI, &pe) &&
2702             vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
2703                 /* evaluate pending_events before reading the vector */
2704                 smp_rmb();
2705                 sipi_vector = apic->sipi_vector;
2706                 apic_debug("vcpu %d received sipi with vector # %x\n",
2707                          vcpu->vcpu_id, sipi_vector);
2708                 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
2709                 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2710         }
2711 }
2712
2713 void kvm_lapic_init(void)
2714 {
2715         /* do not patch jump label more than once per second */
2716         jump_label_rate_limit(&apic_hw_disabled, HZ);
2717         jump_label_rate_limit(&apic_sw_disabled, HZ);
2718 }
2719
2720 void kvm_lapic_exit(void)
2721 {
2722         static_key_deferred_flush(&apic_hw_disabled);
2723         static_key_deferred_flush(&apic_sw_disabled);
2724 }