1 // SPDX-License-Identifier: GPL-2.0-only
2 #include <linux/clocksource.h>
3 #include <linux/clockchips.h>
4 #include <linux/interrupt.h>
6 #include <linux/export.h>
7 #include <linux/delay.h>
8 #include <linux/errno.h>
9 #include <linux/i8253.h>
10 #include <linux/slab.h>
11 #include <linux/hpet.h>
12 #include <linux/init.h>
13 #include <linux/cpu.h>
17 #include <asm/cpufeature.h>
18 #include <asm/irqdomain.h>
19 #include <asm/fixmap.h>
24 #define pr_fmt(fmt) "hpet: " fmt
26 #define HPET_MASK CLOCKSOURCE_MASK(32)
28 #define HPET_DEV_USED_BIT 2
29 #define HPET_DEV_USED (1 << HPET_DEV_USED_BIT)
30 #define HPET_DEV_VALID 0x8
31 #define HPET_DEV_FSB_CAP 0x1000
32 #define HPET_DEV_PERI_CAP 0x2000
34 #define HPET_MIN_CYCLES 128
35 #define HPET_MIN_PROG_DELTA (HPET_MIN_CYCLES + (HPET_MIN_CYCLES >> 1))
38 * HPET address is set in acpi/boot.c, when an ACPI entry exists
40 unsigned long hpet_address;
41 u8 hpet_blockid; /* OS timer block num */
42 bool hpet_msi_disable;
45 static unsigned int hpet_num_timers;
47 static void __iomem *hpet_virt_address;
50 struct clock_event_device evt;
58 static inline struct hpet_dev *EVT_TO_HPET_DEV(struct clock_event_device *evtdev)
60 return container_of(evtdev, struct hpet_dev, evt);
63 inline unsigned int hpet_readl(unsigned int a)
65 return readl(hpet_virt_address + a);
68 static inline void hpet_writel(unsigned int d, unsigned int a)
70 writel(d, hpet_virt_address + a);
74 #include <asm/pgtable.h>
77 static inline void hpet_set_mapping(void)
79 hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
82 static inline void hpet_clear_mapping(void)
84 iounmap(hpet_virt_address);
85 hpet_virt_address = NULL;
89 * HPET command line enable / disable
91 bool boot_hpet_disable;
93 static bool hpet_verbose;
95 static int __init hpet_setup(char *str)
98 char *next = strchr(str, ',');
102 if (!strncmp("disable", str, 7))
103 boot_hpet_disable = true;
104 if (!strncmp("force", str, 5))
105 hpet_force_user = true;
106 if (!strncmp("verbose", str, 7))
112 __setup("hpet=", hpet_setup);
114 static int __init disable_hpet(char *str)
116 boot_hpet_disable = true;
119 __setup("nohpet", disable_hpet);
121 static inline int is_hpet_capable(void)
123 return !boot_hpet_disable && hpet_address;
127 * HPET timer interrupt enable / disable
129 static bool hpet_legacy_int_enabled;
132 * is_hpet_enabled - check whether the hpet timer interrupt is enabled
134 int is_hpet_enabled(void)
136 return is_hpet_capable() && hpet_legacy_int_enabled;
138 EXPORT_SYMBOL_GPL(is_hpet_enabled);
140 static void _hpet_print_config(const char *function, int line)
143 pr_info("%s(%d):\n", function, line);
144 l = hpet_readl(HPET_ID);
145 h = hpet_readl(HPET_PERIOD);
146 timers = ((l & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
147 pr_info("ID: 0x%x, PERIOD: 0x%x\n", l, h);
148 l = hpet_readl(HPET_CFG);
149 h = hpet_readl(HPET_STATUS);
150 pr_info("CFG: 0x%x, STATUS: 0x%x\n", l, h);
151 l = hpet_readl(HPET_COUNTER);
152 h = hpet_readl(HPET_COUNTER+4);
153 pr_info("COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h);
155 for (i = 0; i < timers; i++) {
156 l = hpet_readl(HPET_Tn_CFG(i));
157 h = hpet_readl(HPET_Tn_CFG(i)+4);
158 pr_info("T%d: CFG_l: 0x%x, CFG_h: 0x%x\n", i, l, h);
159 l = hpet_readl(HPET_Tn_CMP(i));
160 h = hpet_readl(HPET_Tn_CMP(i)+4);
161 pr_info("T%d: CMP_l: 0x%x, CMP_h: 0x%x\n", i, l, h);
162 l = hpet_readl(HPET_Tn_ROUTE(i));
163 h = hpet_readl(HPET_Tn_ROUTE(i)+4);
164 pr_info("T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n", i, l, h);
168 #define hpet_print_config() \
171 _hpet_print_config(__func__, __LINE__); \
175 * When the hpet driver (/dev/hpet) is enabled, we need to reserve
176 * timer 0 and timer 1 in case of RTC emulation.
180 static void hpet_reserve_msi_timers(struct hpet_data *hd);
182 static void hpet_reserve_platform_timers(unsigned int id)
184 struct hpet __iomem *hpet = hpet_virt_address;
185 struct hpet_timer __iomem *timer = &hpet->hpet_timers[2];
186 unsigned int nrtimers, i;
189 nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
191 memset(&hd, 0, sizeof(hd));
192 hd.hd_phys_address = hpet_address;
193 hd.hd_address = hpet;
194 hd.hd_nirqs = nrtimers;
195 hpet_reserve_timer(&hd, 0);
197 #ifdef CONFIG_HPET_EMULATE_RTC
198 hpet_reserve_timer(&hd, 1);
202 * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254
203 * is wrong for i8259!) not the output IRQ. Many BIOS writers
204 * don't bother configuring *any* comparator interrupts.
206 hd.hd_irq[0] = HPET_LEGACY_8254;
207 hd.hd_irq[1] = HPET_LEGACY_RTC;
209 for (i = 2; i < nrtimers; timer++, i++) {
210 hd.hd_irq[i] = (readl(&timer->hpet_config) &
211 Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT;
214 hpet_reserve_msi_timers(&hd);
220 static void hpet_reserve_platform_timers(unsigned int id) { }
226 static unsigned long hpet_freq;
228 static struct clock_event_device hpet_clockevent;
230 static void hpet_stop_counter(void)
232 u32 cfg = hpet_readl(HPET_CFG);
233 cfg &= ~HPET_CFG_ENABLE;
234 hpet_writel(cfg, HPET_CFG);
237 static void hpet_reset_counter(void)
239 hpet_writel(0, HPET_COUNTER);
240 hpet_writel(0, HPET_COUNTER + 4);
243 static void hpet_start_counter(void)
245 unsigned int cfg = hpet_readl(HPET_CFG);
246 cfg |= HPET_CFG_ENABLE;
247 hpet_writel(cfg, HPET_CFG);
250 static void hpet_restart_counter(void)
253 hpet_reset_counter();
254 hpet_start_counter();
257 static void hpet_resume_device(void)
262 static void hpet_resume_counter(struct clocksource *cs)
264 hpet_resume_device();
265 hpet_restart_counter();
268 static void hpet_enable_legacy_int(void)
270 unsigned int cfg = hpet_readl(HPET_CFG);
272 cfg |= HPET_CFG_LEGACY;
273 hpet_writel(cfg, HPET_CFG);
274 hpet_legacy_int_enabled = true;
277 static void hpet_legacy_clockevent_register(void)
279 /* Start HPET legacy interrupts */
280 hpet_enable_legacy_int();
283 * Start hpet with the boot cpu mask and make it
284 * global after the IO_APIC has been initialized.
286 hpet_clockevent.cpumask = cpumask_of(boot_cpu_data.cpu_index);
287 clockevents_config_and_register(&hpet_clockevent, hpet_freq,
288 HPET_MIN_PROG_DELTA, 0x7FFFFFFF);
289 global_clock_event = &hpet_clockevent;
290 pr_debug("Clockevent registered\n");
293 static int hpet_set_periodic(struct clock_event_device *evt, int timer)
295 unsigned int cfg, cmp, now;
299 delta = ((uint64_t)(NSEC_PER_SEC / HZ)) * evt->mult;
300 delta >>= evt->shift;
301 now = hpet_readl(HPET_COUNTER);
302 cmp = now + (unsigned int)delta;
303 cfg = hpet_readl(HPET_Tn_CFG(timer));
304 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC | HPET_TN_SETVAL |
306 hpet_writel(cfg, HPET_Tn_CFG(timer));
307 hpet_writel(cmp, HPET_Tn_CMP(timer));
310 * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL
311 * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL
312 * bit is automatically cleared after the first write.
313 * (See AMD-8111 HyperTransport I/O Hub Data Sheet,
314 * Publication # 24674)
316 hpet_writel((unsigned int)delta, HPET_Tn_CMP(timer));
317 hpet_start_counter();
323 static int hpet_set_oneshot(struct clock_event_device *evt, int timer)
327 cfg = hpet_readl(HPET_Tn_CFG(timer));
328 cfg &= ~HPET_TN_PERIODIC;
329 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
330 hpet_writel(cfg, HPET_Tn_CFG(timer));
335 static int hpet_shutdown(struct clock_event_device *evt, int timer)
339 cfg = hpet_readl(HPET_Tn_CFG(timer));
340 cfg &= ~HPET_TN_ENABLE;
341 hpet_writel(cfg, HPET_Tn_CFG(timer));
346 static int hpet_resume(struct clock_event_device *evt)
348 hpet_enable_legacy_int();
353 static int hpet_next_event(unsigned long delta,
354 struct clock_event_device *evt, int timer)
359 cnt = hpet_readl(HPET_COUNTER);
361 hpet_writel(cnt, HPET_Tn_CMP(timer));
364 * HPETs are a complete disaster. The compare register is
365 * based on a equal comparison and neither provides a less
366 * than or equal functionality (which would require to take
367 * the wraparound into account) nor a simple count down event
368 * mode. Further the write to the comparator register is
369 * delayed internally up to two HPET clock cycles in certain
370 * chipsets (ATI, ICH9,10). Some newer AMD chipsets have even
371 * longer delays. We worked around that by reading back the
372 * compare register, but that required another workaround for
373 * ICH9,10 chips where the first readout after write can
374 * return the old stale value. We already had a minimum
375 * programming delta of 5us enforced, but a NMI or SMI hitting
376 * between the counter readout and the comparator write can
377 * move us behind that point easily. Now instead of reading
378 * the compare register back several times, we make the ETIME
379 * decision based on the following: Return ETIME if the
380 * counter value after the write is less than HPET_MIN_CYCLES
381 * away from the event or if the counter is already ahead of
382 * the event. The minimum programming delta for the generic
383 * clockevents code is set to 1.5 * HPET_MIN_CYCLES.
385 res = (s32)(cnt - hpet_readl(HPET_COUNTER));
387 return res < HPET_MIN_CYCLES ? -ETIME : 0;
390 static int hpet_legacy_shutdown(struct clock_event_device *evt)
392 return hpet_shutdown(evt, 0);
395 static int hpet_legacy_set_oneshot(struct clock_event_device *evt)
397 return hpet_set_oneshot(evt, 0);
400 static int hpet_legacy_set_periodic(struct clock_event_device *evt)
402 return hpet_set_periodic(evt, 0);
405 static int hpet_legacy_resume(struct clock_event_device *evt)
407 return hpet_resume(evt);
410 static int hpet_legacy_next_event(unsigned long delta,
411 struct clock_event_device *evt)
413 return hpet_next_event(delta, evt, 0);
417 * The hpet clock event device
419 static struct clock_event_device hpet_clockevent = {
421 .features = CLOCK_EVT_FEAT_PERIODIC |
422 CLOCK_EVT_FEAT_ONESHOT,
423 .set_state_periodic = hpet_legacy_set_periodic,
424 .set_state_oneshot = hpet_legacy_set_oneshot,
425 .set_state_shutdown = hpet_legacy_shutdown,
426 .tick_resume = hpet_legacy_resume,
427 .set_next_event = hpet_legacy_next_event,
435 #ifdef CONFIG_PCI_MSI
437 static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev);
438 static struct hpet_dev *hpet_devs;
439 static struct irq_domain *hpet_domain;
441 void hpet_msi_unmask(struct irq_data *data)
443 struct hpet_dev *hdev = irq_data_get_irq_handler_data(data);
447 cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
448 cfg |= HPET_TN_ENABLE | HPET_TN_FSB;
449 hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
452 void hpet_msi_mask(struct irq_data *data)
454 struct hpet_dev *hdev = irq_data_get_irq_handler_data(data);
458 cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
459 cfg &= ~(HPET_TN_ENABLE | HPET_TN_FSB);
460 hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
463 void hpet_msi_write(struct hpet_dev *hdev, struct msi_msg *msg)
465 hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num));
466 hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4);
469 void hpet_msi_read(struct hpet_dev *hdev, struct msi_msg *msg)
471 msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num));
472 msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4);
476 static int hpet_msi_shutdown(struct clock_event_device *evt)
478 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
480 return hpet_shutdown(evt, hdev->num);
483 static int hpet_msi_set_oneshot(struct clock_event_device *evt)
485 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
487 return hpet_set_oneshot(evt, hdev->num);
490 static int hpet_msi_set_periodic(struct clock_event_device *evt)
492 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
494 return hpet_set_periodic(evt, hdev->num);
497 static int hpet_msi_resume(struct clock_event_device *evt)
499 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
500 struct irq_data *data = irq_get_irq_data(hdev->irq);
503 /* Restore the MSI msg and unmask the interrupt */
504 irq_chip_compose_msi_msg(data, &msg);
505 hpet_msi_write(hdev, &msg);
506 hpet_msi_unmask(data);
510 static int hpet_msi_next_event(unsigned long delta,
511 struct clock_event_device *evt)
513 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
514 return hpet_next_event(delta, evt, hdev->num);
517 static irqreturn_t hpet_interrupt_handler(int irq, void *data)
519 struct hpet_dev *dev = (struct hpet_dev *)data;
520 struct clock_event_device *hevt = &dev->evt;
522 if (!hevt->event_handler) {
523 pr_info("Spurious interrupt HPET timer %d\n", dev->num);
527 hevt->event_handler(hevt);
531 static int hpet_setup_irq(struct hpet_dev *dev)
534 if (request_irq(dev->irq, hpet_interrupt_handler,
535 IRQF_TIMER | IRQF_NOBALANCING,
539 disable_irq(dev->irq);
540 irq_set_affinity(dev->irq, cpumask_of(dev->cpu));
541 enable_irq(dev->irq);
543 pr_debug("%s irq %d for MSI\n", dev->name, dev->irq);
548 static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu)
550 struct clock_event_device *evt = &hdev->evt;
552 if (!(hdev->flags & HPET_DEV_VALID))
556 per_cpu(cpu_hpet_dev, cpu) = hdev;
557 evt->name = hdev->name;
558 hpet_setup_irq(hdev);
559 evt->irq = hdev->irq;
562 evt->features = CLOCK_EVT_FEAT_ONESHOT;
563 if (hdev->flags & HPET_DEV_PERI_CAP) {
564 evt->features |= CLOCK_EVT_FEAT_PERIODIC;
565 evt->set_state_periodic = hpet_msi_set_periodic;
568 evt->set_state_shutdown = hpet_msi_shutdown;
569 evt->set_state_oneshot = hpet_msi_set_oneshot;
570 evt->tick_resume = hpet_msi_resume;
571 evt->set_next_event = hpet_msi_next_event;
572 evt->cpumask = cpumask_of(hdev->cpu);
574 clockevents_config_and_register(evt, hpet_freq, HPET_MIN_PROG_DELTA,
579 /* Reserve at least one timer for userspace (/dev/hpet) */
580 #define RESERVE_TIMERS 1
582 #define RESERVE_TIMERS 0
585 static void hpet_msi_capability_lookup(unsigned int start_timer)
588 unsigned int num_timers;
589 unsigned int num_timers_used = 0;
592 if (hpet_msi_disable)
595 if (boot_cpu_has(X86_FEATURE_ARAT))
597 id = hpet_readl(HPET_ID);
599 num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
600 num_timers++; /* Value read out starts from 0 */
603 hpet_domain = hpet_create_irq_domain(hpet_blockid);
607 hpet_devs = kcalloc(num_timers, sizeof(struct hpet_dev), GFP_KERNEL);
611 hpet_num_timers = num_timers;
613 for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) {
614 struct hpet_dev *hdev = &hpet_devs[num_timers_used];
615 unsigned int cfg = hpet_readl(HPET_Tn_CFG(i));
617 /* Only consider HPET timer with MSI support */
618 if (!(cfg & HPET_TN_FSB_CAP))
622 if (cfg & HPET_TN_PERIODIC_CAP)
623 hdev->flags |= HPET_DEV_PERI_CAP;
624 sprintf(hdev->name, "hpet%d", i);
627 irq = hpet_assign_irq(hpet_domain, hdev, hdev->num);
632 hdev->flags |= HPET_DEV_FSB_CAP;
633 hdev->flags |= HPET_DEV_VALID;
635 if (num_timers_used == num_possible_cpus())
639 pr_info("%d channels of %d reserved for per-cpu timers\n",
640 num_timers, num_timers_used);
644 static void hpet_reserve_msi_timers(struct hpet_data *hd)
651 for (i = 0; i < hpet_num_timers; i++) {
652 struct hpet_dev *hdev = &hpet_devs[i];
654 if (!(hdev->flags & HPET_DEV_VALID))
657 hd->hd_irq[hdev->num] = hdev->irq;
658 hpet_reserve_timer(hd, hdev->num);
663 static struct hpet_dev *hpet_get_unused_timer(void)
670 for (i = 0; i < hpet_num_timers; i++) {
671 struct hpet_dev *hdev = &hpet_devs[i];
673 if (!(hdev->flags & HPET_DEV_VALID))
675 if (test_and_set_bit(HPET_DEV_USED_BIT,
676 (unsigned long *)&hdev->flags))
683 static int hpet_cpuhp_online(unsigned int cpu)
685 struct hpet_dev *hdev = hpet_get_unused_timer();
688 init_one_hpet_msi_clockevent(hdev, cpu);
692 static int hpet_cpuhp_dead(unsigned int cpu)
694 struct hpet_dev *hdev = per_cpu(cpu_hpet_dev, cpu);
698 free_irq(hdev->irq, hdev);
699 hdev->flags &= ~HPET_DEV_USED;
700 per_cpu(cpu_hpet_dev, cpu) = NULL;
705 static void hpet_msi_capability_lookup(unsigned int start_timer)
711 static void hpet_reserve_msi_timers(struct hpet_data *hd)
717 #define hpet_cpuhp_online NULL
718 #define hpet_cpuhp_dead NULL
723 * Clock source related code
725 #if defined(CONFIG_SMP) && defined(CONFIG_64BIT)
727 * Reading the HPET counter is a very slow operation. If a large number of
728 * CPUs are trying to access the HPET counter simultaneously, it can cause
729 * massive delay and slow down system performance dramatically. This may
730 * happen when HPET is the default clock source instead of TSC. For a
731 * really large system with hundreds of CPUs, the slowdown may be so
732 * severe that it may actually crash the system because of a NMI watchdog
733 * soft lockup, for example.
735 * If multiple CPUs are trying to access the HPET counter at the same time,
736 * we don't actually need to read the counter multiple times. Instead, the
737 * other CPUs can use the counter value read by the first CPU in the group.
739 * This special feature is only enabled on x86-64 systems. It is unlikely
740 * that 32-bit x86 systems will have enough CPUs to require this feature
741 * with its associated locking overhead. And we also need 64-bit atomic
744 * The lock and the hpet value are stored together and can be read in a
745 * single atomic 64-bit read. It is explicitly assumed that arch_spinlock_t
746 * is 32 bits in size.
750 arch_spinlock_t lock;
756 static union hpet_lock hpet __cacheline_aligned = {
757 { .lock = __ARCH_SPIN_LOCK_UNLOCKED, },
760 static u64 read_hpet(struct clocksource *cs)
763 union hpet_lock old, new;
765 BUILD_BUG_ON(sizeof(union hpet_lock) != 8);
768 * Read HPET directly if in NMI.
771 return (u64)hpet_readl(HPET_COUNTER);
774 * Read the current state of the lock and HPET value atomically.
776 old.lockval = READ_ONCE(hpet.lockval);
778 if (arch_spin_is_locked(&old.lock))
781 local_irq_save(flags);
782 if (arch_spin_trylock(&hpet.lock)) {
783 new.value = hpet_readl(HPET_COUNTER);
785 * Use WRITE_ONCE() to prevent store tearing.
787 WRITE_ONCE(hpet.value, new.value);
788 arch_spin_unlock(&hpet.lock);
789 local_irq_restore(flags);
790 return (u64)new.value;
792 local_irq_restore(flags);
798 * Wait until the HPET value change or the lock is free to indicate
799 * its value is up-to-date.
801 * It is possible that old.value has already contained the latest
802 * HPET value while the lock holder was in the process of releasing
803 * the lock. Checking for lock state change will enable us to return
804 * the value immediately instead of waiting for the next HPET reader
809 new.lockval = READ_ONCE(hpet.lockval);
810 } while ((new.value == old.value) && arch_spin_is_locked(&new.lock));
812 return (u64)new.value;
818 static u64 read_hpet(struct clocksource *cs)
820 return (u64)hpet_readl(HPET_COUNTER);
824 static struct clocksource clocksource_hpet = {
829 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
830 .resume = hpet_resume_counter,
833 static int hpet_clocksource_register(void)
838 /* Start the counter */
839 hpet_restart_counter();
841 /* Verify whether hpet counter works */
842 t1 = hpet_readl(HPET_COUNTER);
846 * We don't know the TSC frequency yet, but waiting for
847 * 200000 TSC cycles is safe:
854 } while ((now - start) < 200000UL);
856 if (t1 == hpet_readl(HPET_COUNTER)) {
857 pr_warn("Counter not counting. HPET disabled\n");
861 clocksource_register_hz(&clocksource_hpet, (u32)hpet_freq);
865 static u32 *hpet_boot_cfg;
868 * hpet_enable - Try to setup the HPET timer. Returns 1 on success.
870 int __init hpet_enable(void)
872 u32 hpet_period, cfg, id;
874 unsigned int i, last;
876 if (!is_hpet_capable())
880 if (!hpet_virt_address)
884 * Read the period and check for a sane value:
886 hpet_period = hpet_readl(HPET_PERIOD);
889 * AMD SB700 based systems with spread spectrum enabled use a
890 * SMM based HPET emulation to provide proper frequency
891 * setting. The SMM code is initialized with the first HPET
892 * register access and takes some time to complete. During
893 * this time the config register reads 0xffffffff. We check
894 * for max. 1000 loops whether the config register reads a non
895 * 0xffffffff value to make sure that HPET is up and running
896 * before we go further. A counting loop is safe, as the HPET
897 * access takes thousands of CPU cycles. On non SB700 based
898 * machines this check is only done once and has no side
901 for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) {
903 pr_warn("Config register invalid. Disabling HPET\n");
908 if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD)
912 * The period is a femto seconds value. Convert it to a
916 do_div(freq, hpet_period);
920 * Read the HPET ID register to retrieve the IRQ routing
921 * information and the number of channels
923 id = hpet_readl(HPET_ID);
926 last = (id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT;
928 #ifdef CONFIG_HPET_EMULATE_RTC
930 * The legacy routing mode needs at least two channels, tick timer
931 * and the rtc emulation channel.
937 cfg = hpet_readl(HPET_CFG);
938 hpet_boot_cfg = kmalloc_array(last + 2, sizeof(*hpet_boot_cfg),
941 *hpet_boot_cfg = cfg;
943 pr_warn("HPET initial state will not be saved\n");
944 cfg &= ~(HPET_CFG_ENABLE | HPET_CFG_LEGACY);
945 hpet_writel(cfg, HPET_CFG);
947 pr_warn("Global config: Unknown bits %#x\n", cfg);
949 for (i = 0; i <= last; ++i) {
950 cfg = hpet_readl(HPET_Tn_CFG(i));
952 hpet_boot_cfg[i + 1] = cfg;
953 cfg &= ~(HPET_TN_ENABLE | HPET_TN_LEVEL | HPET_TN_FSB);
954 hpet_writel(cfg, HPET_Tn_CFG(i));
955 cfg &= ~(HPET_TN_PERIODIC | HPET_TN_PERIODIC_CAP
956 | HPET_TN_64BIT_CAP | HPET_TN_32BIT | HPET_TN_ROUTE
957 | HPET_TN_FSB | HPET_TN_FSB_CAP);
959 pr_warn("Channel #%u config: Unknown bits %#x\n", i, cfg);
963 if (hpet_clocksource_register())
966 if (id & HPET_ID_LEGSUP) {
967 hpet_legacy_clockevent_register();
973 hpet_clear_mapping();
979 * Needs to be late, as the reserve_timer code calls kalloc !
981 * Not a problem on i386 as hpet_enable is called from late_time_init,
982 * but on x86_64 it is necessary !
984 static __init int hpet_late_init(void)
988 if (boot_hpet_disable)
992 if (!force_hpet_address)
995 hpet_address = force_hpet_address;
999 if (!hpet_virt_address)
1002 if (hpet_readl(HPET_ID) & HPET_ID_LEGSUP)
1003 hpet_msi_capability_lookup(2);
1005 hpet_msi_capability_lookup(0);
1007 hpet_reserve_platform_timers(hpet_readl(HPET_ID));
1008 hpet_print_config();
1010 if (hpet_msi_disable)
1013 if (boot_cpu_has(X86_FEATURE_ARAT))
1016 ret = cpuhp_setup_state(CPUHP_AP_X86_HPET_ONLINE, "x86/hpet:online",
1017 hpet_cpuhp_online, NULL);
1020 ret = cpuhp_setup_state(CPUHP_X86_HPET_DEAD, "x86/hpet:dead", NULL,
1027 cpuhp_remove_state(CPUHP_AP_X86_HPET_ONLINE);
1030 fs_initcall(hpet_late_init);
1032 void hpet_disable(void)
1034 if (is_hpet_capable() && hpet_virt_address) {
1035 unsigned int cfg = hpet_readl(HPET_CFG), id, last;
1038 cfg = *hpet_boot_cfg;
1039 else if (hpet_legacy_int_enabled) {
1040 cfg &= ~HPET_CFG_LEGACY;
1041 hpet_legacy_int_enabled = false;
1043 cfg &= ~HPET_CFG_ENABLE;
1044 hpet_writel(cfg, HPET_CFG);
1049 id = hpet_readl(HPET_ID);
1050 last = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
1052 for (id = 0; id <= last; ++id)
1053 hpet_writel(hpet_boot_cfg[id + 1], HPET_Tn_CFG(id));
1055 if (*hpet_boot_cfg & HPET_CFG_ENABLE)
1056 hpet_writel(*hpet_boot_cfg, HPET_CFG);
1060 #ifdef CONFIG_HPET_EMULATE_RTC
1062 /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
1063 * is enabled, we support RTC interrupt functionality in software.
1064 * RTC has 3 kinds of interrupts:
1065 * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
1067 * 2) Alarm Interrupt - generate an interrupt at a specific time of day
1068 * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
1069 * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
1070 * (1) and (2) above are implemented using polling at a frequency of
1071 * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
1072 * overhead. (DEFAULT_RTC_INT_FREQ)
1073 * For (3), we use interrupts at 64Hz or user specified periodic
1074 * frequency, whichever is higher.
1076 #include <linux/mc146818rtc.h>
1077 #include <linux/rtc.h>
1079 #define DEFAULT_RTC_INT_FREQ 64
1080 #define DEFAULT_RTC_SHIFT 6
1081 #define RTC_NUM_INTS 1
1083 static unsigned long hpet_rtc_flags;
1084 static int hpet_prev_update_sec;
1085 static struct rtc_time hpet_alarm_time;
1086 static unsigned long hpet_pie_count;
1087 static u32 hpet_t1_cmp;
1088 static u32 hpet_default_delta;
1089 static u32 hpet_pie_delta;
1090 static unsigned long hpet_pie_limit;
1092 static rtc_irq_handler irq_handler;
1095 * Check that the hpet counter c1 is ahead of the c2
1097 static inline int hpet_cnt_ahead(u32 c1, u32 c2)
1099 return (s32)(c2 - c1) < 0;
1103 * Registers a IRQ handler.
1105 int hpet_register_irq_handler(rtc_irq_handler handler)
1107 if (!is_hpet_enabled())
1112 irq_handler = handler;
1116 EXPORT_SYMBOL_GPL(hpet_register_irq_handler);
1119 * Deregisters the IRQ handler registered with hpet_register_irq_handler()
1122 void hpet_unregister_irq_handler(rtc_irq_handler handler)
1124 if (!is_hpet_enabled())
1130 EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler);
1133 * Timer 1 for RTC emulation. We use one shot mode, as periodic mode
1134 * is not supported by all HPET implementations for timer 1.
1136 * hpet_rtc_timer_init() is called when the rtc is initialized.
1138 int hpet_rtc_timer_init(void)
1140 unsigned int cfg, cnt, delta;
1141 unsigned long flags;
1143 if (!is_hpet_enabled())
1146 if (!hpet_default_delta) {
1149 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1150 clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT;
1151 hpet_default_delta = clc;
1154 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1155 delta = hpet_default_delta;
1157 delta = hpet_pie_delta;
1159 local_irq_save(flags);
1161 cnt = delta + hpet_readl(HPET_COUNTER);
1162 hpet_writel(cnt, HPET_T1_CMP);
1165 cfg = hpet_readl(HPET_T1_CFG);
1166 cfg &= ~HPET_TN_PERIODIC;
1167 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
1168 hpet_writel(cfg, HPET_T1_CFG);
1170 local_irq_restore(flags);
1174 EXPORT_SYMBOL_GPL(hpet_rtc_timer_init);
1176 static void hpet_disable_rtc_channel(void)
1178 u32 cfg = hpet_readl(HPET_T1_CFG);
1179 cfg &= ~HPET_TN_ENABLE;
1180 hpet_writel(cfg, HPET_T1_CFG);
1184 * The functions below are called from rtc driver.
1185 * Return 0 if HPET is not being used.
1186 * Otherwise do the necessary changes and return 1.
1188 int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
1190 if (!is_hpet_enabled())
1193 hpet_rtc_flags &= ~bit_mask;
1194 if (unlikely(!hpet_rtc_flags))
1195 hpet_disable_rtc_channel();
1199 EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit);
1201 int hpet_set_rtc_irq_bit(unsigned long bit_mask)
1203 unsigned long oldbits = hpet_rtc_flags;
1205 if (!is_hpet_enabled())
1208 hpet_rtc_flags |= bit_mask;
1210 if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE))
1211 hpet_prev_update_sec = -1;
1214 hpet_rtc_timer_init();
1218 EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit);
1220 int hpet_set_alarm_time(unsigned char hrs, unsigned char min,
1223 if (!is_hpet_enabled())
1226 hpet_alarm_time.tm_hour = hrs;
1227 hpet_alarm_time.tm_min = min;
1228 hpet_alarm_time.tm_sec = sec;
1232 EXPORT_SYMBOL_GPL(hpet_set_alarm_time);
1234 int hpet_set_periodic_freq(unsigned long freq)
1238 if (!is_hpet_enabled())
1241 if (freq <= DEFAULT_RTC_INT_FREQ)
1242 hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
1244 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1246 clc >>= hpet_clockevent.shift;
1247 hpet_pie_delta = clc;
1252 EXPORT_SYMBOL_GPL(hpet_set_periodic_freq);
1254 int hpet_rtc_dropped_irq(void)
1256 return is_hpet_enabled();
1258 EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq);
1260 static void hpet_rtc_timer_reinit(void)
1265 if (unlikely(!hpet_rtc_flags))
1266 hpet_disable_rtc_channel();
1268 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1269 delta = hpet_default_delta;
1271 delta = hpet_pie_delta;
1274 * Increment the comparator value until we are ahead of the
1278 hpet_t1_cmp += delta;
1279 hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
1281 } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER)));
1284 if (hpet_rtc_flags & RTC_PIE)
1285 hpet_pie_count += lost_ints;
1286 if (printk_ratelimit())
1287 pr_warn("Lost %d RTC interrupts\n", lost_ints);
1291 irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
1293 struct rtc_time curr_time;
1294 unsigned long rtc_int_flag = 0;
1296 hpet_rtc_timer_reinit();
1297 memset(&curr_time, 0, sizeof(struct rtc_time));
1299 if (hpet_rtc_flags & (RTC_UIE | RTC_AIE))
1300 mc146818_get_time(&curr_time);
1302 if (hpet_rtc_flags & RTC_UIE &&
1303 curr_time.tm_sec != hpet_prev_update_sec) {
1304 if (hpet_prev_update_sec >= 0)
1305 rtc_int_flag = RTC_UF;
1306 hpet_prev_update_sec = curr_time.tm_sec;
1309 if (hpet_rtc_flags & RTC_PIE &&
1310 ++hpet_pie_count >= hpet_pie_limit) {
1311 rtc_int_flag |= RTC_PF;
1315 if (hpet_rtc_flags & RTC_AIE &&
1316 (curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
1317 (curr_time.tm_min == hpet_alarm_time.tm_min) &&
1318 (curr_time.tm_hour == hpet_alarm_time.tm_hour))
1319 rtc_int_flag |= RTC_AF;
1322 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
1324 irq_handler(rtc_int_flag, dev_id);
1328 EXPORT_SYMBOL_GPL(hpet_rtc_interrupt);