arch/x86/kernel/genx2apic_uv_x.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * SGI UV APIC functions (note: not an Intel compatible APIC)
   7  *
   8  * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/threads.h>
  13 #include <linux/cpumask.h>
  14 #include <linux/string.h>
  15 #include <linux/ctype.h>
  16 #include <linux/init.h>
  17 #include <linux/sched.h>
  18 #include <linux/bootmem.h>
  19 #include <linux/module.h>
  20 #include <linux/hardirq.h>
  21 #include <asm/smp.h>
  22 #include <asm/ipi.h>
  23 #include <asm/genapic.h>
  24 #include <asm/pgtable.h>
  25 #include <asm/uv/uv_mmrs.h>
  26 #include <asm/uv/uv_hub.h>
  27 #include <asm/uv/bios.h>
  28
  29 static enum uv_system_type uv_system_type;
  30
  31 static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
  32 {
  33         if (!strcmp(oem_id, "SGI")) {
  34                 if (!strcmp(oem_table_id, "UVL"))
  35                         uv_system_type = UV_LEGACY_APIC;
  36                 else if (!strcmp(oem_table_id, "UVX"))
  37                         uv_system_type = UV_X2APIC;
  38                 else if (!strcmp(oem_table_id, "UVH")) {
  39                         uv_system_type = UV_NON_UNIQUE_APIC;
  40                         return 1;
  41                 }
  42         }
  43         return 0;
  44 }
  45
  46 enum uv_system_type get_uv_system_type(void)
  47 {
  48         return uv_system_type;
  49 }
  50
  51 int is_uv_system(void)
  52 {
  53         return uv_system_type != UV_NONE;
  54 }
  55
  56 DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
  57 EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);
  58
  59 struct uv_blade_info *uv_blade_info;
  60 EXPORT_SYMBOL_GPL(uv_blade_info);
  61
  62 short *uv_node_to_blade;
  63 EXPORT_SYMBOL_GPL(uv_node_to_blade);
  64
  65 short *uv_cpu_to_blade;
  66 EXPORT_SYMBOL_GPL(uv_cpu_to_blade);
  67
  68 short uv_possible_blades;
  69 EXPORT_SYMBOL_GPL(uv_possible_blades);
  70
  71 unsigned long sn_rtc_cycles_per_second;
  72 EXPORT_SYMBOL(sn_rtc_cycles_per_second);
  73
  74 /* Start with all IRQs pointing to boot CPU.  IRQ balancing will shift them. */
  75
  76 static cpumask_t uv_target_cpus(void)
  77 {
  78         return cpumask_of_cpu(0);
  79 }
  80
  81 static cpumask_t uv_vector_allocation_domain(int cpu)
  82 {
  83         cpumask_t domain = CPU_MASK_NONE;
  84         cpu_set(cpu, domain);
  85         return domain;
  86 }
  87
  88 int uv_wakeup_secondary(int phys_apicid, unsigned int start_rip)
  89 {
  90         unsigned long val;
  91         int pnode;
  92
  93         pnode = uv_apicid_to_pnode(phys_apicid);
  94         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
  95             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
  96             (((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
  97             APIC_DM_INIT;
  98         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
  99         mdelay(10);
 100
 101         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
 102             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
 103             (((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
 104             APIC_DM_STARTUP;
 105         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 106         return 0;
 107 }
 108
 109 static void uv_send_IPI_one(int cpu, int vector)
 110 {
 111         unsigned long val, apicid, lapicid;
 112         int pnode;
 113
 114         apicid = per_cpu(x86_cpu_to_apicid, cpu); /* ZZZ - cache node-local ? */
 115         lapicid = apicid & 0x3f;                /* ZZZ macro needed */
 116         pnode = uv_apicid_to_pnode(apicid);
 117         val =
 118             (1UL << UVH_IPI_INT_SEND_SHFT) | (lapicid <<
 119                                               UVH_IPI_INT_APIC_ID_SHFT) |
 120             (vector << UVH_IPI_INT_VECTOR_SHFT);
 121         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 122 }
 123
 124 static void uv_send_IPI_mask(cpumask_t mask, int vector)
 125 {
 126         unsigned int cpu;
 127
 128         for (cpu = 0; cpu < NR_CPUS; ++cpu)
 129                 if (cpu_isset(cpu, mask))
 130                         uv_send_IPI_one(cpu, vector);
 131 }
 132
 133 static void uv_send_IPI_allbutself(int vector)
 134 {
 135         cpumask_t mask = cpu_online_map;
 136
 137         cpu_clear(smp_processor_id(), mask);
 138
 139         if (!cpus_empty(mask))
 140                 uv_send_IPI_mask(mask, vector);
 141 }
 142
 143 static void uv_send_IPI_all(int vector)
 144 {
 145         uv_send_IPI_mask(cpu_online_map, vector);
 146 }
 147
 148 static int uv_apic_id_registered(void)
 149 {
 150         return 1;
 151 }
 152
 153 static void uv_init_apic_ldr(void)
 154 {
 155 }
 156
 157 static unsigned int uv_cpu_mask_to_apicid(cpumask_t cpumask)
 158 {
 159         int cpu;
 160
 161         /*
 162          * We're using fixed IRQ delivery, can only return one phys APIC ID.
 163          * May as well be the first.
 164          */
 165         cpu = first_cpu(cpumask);
 166         if ((unsigned)cpu < NR_CPUS)
 167                 return per_cpu(x86_cpu_to_apicid, cpu);
 168         else
 169                 return BAD_APICID;
 170 }
 171
 172 static unsigned int get_apic_id(unsigned long x)
 173 {
 174         unsigned int id;
 175
 176         WARN_ON(preemptible() && num_online_cpus() > 1);
 177         id = x | __get_cpu_var(x2apic_extra_bits);
 178
 179         return id;
 180 }
 181
 182 static unsigned long set_apic_id(unsigned int id)
 183 {
 184         unsigned long x;
 185
 186         /* maskout x2apic_extra_bits ? */
 187         x = id;
 188         return x;
 189 }
 190
 191 static unsigned int uv_read_apic_id(void)
 192 {
 193
 194         return get_apic_id(apic_read(APIC_ID));
 195 }
 196
 197 static unsigned int phys_pkg_id(int index_msb)
 198 {
 199         return uv_read_apic_id() >> index_msb;
 200 }
 201
 202 #ifdef ZZZ              /* Needs x2apic patch */
 203 static void uv_send_IPI_self(int vector)
 204 {
 205         apic_write(APIC_SELF_IPI, vector);
 206 }
 207 #endif
 208
 209 struct genapic apic_x2apic_uv_x = {
 210         .name = "UV large system",
 211         .acpi_madt_oem_check = uv_acpi_madt_oem_check,
 212         .int_delivery_mode = dest_Fixed,
 213         .int_dest_mode = (APIC_DEST_PHYSICAL != 0),
 214         .target_cpus = uv_target_cpus,
 215         .vector_allocation_domain = uv_vector_allocation_domain,/* Fixme ZZZ */
 216         .apic_id_registered = uv_apic_id_registered,
 217         .init_apic_ldr = uv_init_apic_ldr,
 218         .send_IPI_all = uv_send_IPI_all,
 219         .send_IPI_allbutself = uv_send_IPI_allbutself,
 220         .send_IPI_mask = uv_send_IPI_mask,
 221         /* ZZZ.send_IPI_self = uv_send_IPI_self, */
 222         .cpu_mask_to_apicid = uv_cpu_mask_to_apicid,
 223         .phys_pkg_id = phys_pkg_id,     /* Fixme ZZZ */
 224         .get_apic_id = get_apic_id,
 225         .set_apic_id = set_apic_id,
 226         .apic_id_mask = (0xFFFFFFFFu),
 227 };
 228
 229 static __cpuinit void set_x2apic_extra_bits(int pnode)
 230 {
 231         __get_cpu_var(x2apic_extra_bits) = (pnode << 6);
 232 }
 233
 234 /*
 235  * Called on boot cpu.
 236  */
 237 static __init int boot_pnode_to_blade(int pnode)
 238 {
 239         int blade;
 240
 241         for (blade = 0; blade < uv_num_possible_blades(); blade++)
 242                 if (pnode == uv_blade_info[blade].pnode)
 243                         return blade;
 244         BUG();
 245 }
 246
 247 struct redir_addr {
 248         unsigned long redirect;
 249         unsigned long alias;
 250 };
 251
 252 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
 253
 254 static __initdata struct redir_addr redir_addrs[] = {
 255         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_SI_ALIAS0_OVERLAY_CONFIG},
 256         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_SI_ALIAS1_OVERLAY_CONFIG},
 257         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_SI_ALIAS2_OVERLAY_CONFIG},
 258 };
 259
 260 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
 261 {
 262         union uvh_si_alias0_overlay_config_u alias;
 263         union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
 264         int i;
 265
 266         for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
 267                 alias.v = uv_read_local_mmr(redir_addrs[i].alias);
 268                 if (alias.s.base == 0) {
 269                         *size = (1UL << alias.s.m_alias);
 270                         redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
 271                         *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
 272                         return;
 273                 }
 274         }
 275         BUG();
 276 }
 277
 278 static __init void map_low_mmrs(void)
 279 {
 280         init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
 281         init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
 282 }
 283
 284 enum map_type {map_wb, map_uc};
 285
 286 static void map_high(char *id, unsigned long base, int shift, enum map_type map_type)
 287 {
 288         unsigned long bytes, paddr;
 289
 290         paddr = base << shift;
 291         bytes = (1UL << shift);
 292         printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr,
 293                                                 paddr + bytes);
 294         if (map_type == map_uc)
 295                 init_extra_mapping_uc(paddr, bytes);
 296         else
 297                 init_extra_mapping_wb(paddr, bytes);
 298
 299 }
 300 static __init void map_gru_high(int max_pnode)
 301 {
 302         union uvh_rh_gam_gru_overlay_config_mmr_u gru;
 303         int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
 304
 305         gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
 306         if (gru.s.enable)
 307                 map_high("GRU", gru.s.base, shift, map_wb);
 308 }
 309
 310 static __init void map_config_high(int max_pnode)
 311 {
 312         union uvh_rh_gam_cfg_overlay_config_mmr_u cfg;
 313         int shift = UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_BASE_SHFT;
 314
 315         cfg.v = uv_read_local_mmr(UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR);
 316         if (cfg.s.enable)
 317                 map_high("CONFIG", cfg.s.base, shift, map_uc);
 318 }
 319
 320 static __init void map_mmr_high(int max_pnode)
 321 {
 322         union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
 323         int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
 324
 325         mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
 326         if (mmr.s.enable)
 327                 map_high("MMR", mmr.s.base, shift, map_uc);
 328 }
 329
 330 static __init void map_mmioh_high(int max_pnode)
 331 {
 332         union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
 333         int shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
 334
 335         mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
 336         if (mmioh.s.enable)
 337                 map_high("MMIOH", mmioh.s.base, shift, map_uc);
 338 }
 339
 340 static __init void uv_rtc_init(void)
 341 {
 342         long status, ticks_per_sec, drift;
 343
 344         status =
 345             x86_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK, &ticks_per_sec,
 346                                         &drift);
 347         if (status != 0 || ticks_per_sec < 100000) {
 348                 printk(KERN_WARNING
 349                         "unable to determine platform RTC clock frequency, "
 350                         "guessing.\n");
 351                 /* BIOS gives wrong value for clock freq. so guess */
 352                 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
 353         } else
 354                 sn_rtc_cycles_per_second = ticks_per_sec;
 355 }
 356
 357 static __init void uv_system_init(void)
 358 {
 359         union uvh_si_addr_map_config_u m_n_config;
 360         union uvh_node_id_u node_id;
 361         unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
 362         int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
 363         int max_pnode = 0;
 364         unsigned long mmr_base, present;
 365
 366         map_low_mmrs();
 367
 368         m_n_config.v = uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG);
 369         m_val = m_n_config.s.m_skt;
 370         n_val = m_n_config.s.n_skt;
 371         mmr_base =
 372             uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
 373             ~UV_MMR_ENABLE;
 374         printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);
 375
 376         for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
 377                 uv_possible_blades +=
 378                   hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
 379         printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades());
 380
 381         bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
 382         uv_blade_info = alloc_bootmem_pages(bytes);
 383
 384         get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
 385
 386         bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
 387         uv_node_to_blade = alloc_bootmem_pages(bytes);
 388         memset(uv_node_to_blade, 255, bytes);
 389
 390         bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
 391         uv_cpu_to_blade = alloc_bootmem_pages(bytes);
 392         memset(uv_cpu_to_blade, 255, bytes);
 393
 394         blade = 0;
 395         for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
 396                 present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
 397                 for (j = 0; j < 64; j++) {
 398                         if (!test_bit(j, &present))
 399                                 continue;
 400                         uv_blade_info[blade].pnode = (i * 64 + j);
 401                         uv_blade_info[blade].nr_possible_cpus = 0;
 402                         uv_blade_info[blade].nr_online_cpus = 0;
 403                         blade++;
 404                 }
 405         }
 406
 407         node_id.v = uv_read_local_mmr(UVH_NODE_ID);
 408         gnode_upper = (((unsigned long)node_id.s.node_id) &
 409                        ~((1 << n_val) - 1)) << m_val;
 410
 411         uv_rtc_init();
 412
 413         for_each_present_cpu(cpu) {
 414                 nid = cpu_to_node(cpu);
 415                 pnode = uv_apicid_to_pnode(per_cpu(x86_cpu_to_apicid, cpu));
 416                 blade = boot_pnode_to_blade(pnode);
 417                 lcpu = uv_blade_info[blade].nr_possible_cpus;
 418                 uv_blade_info[blade].nr_possible_cpus++;
 419
 420                 uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
 421                 uv_cpu_hub_info(cpu)->lowmem_remap_top =
 422                                         lowmem_redir_base + lowmem_redir_size;
 423                 uv_cpu_hub_info(cpu)->m_val = m_val;
 424                 uv_cpu_hub_info(cpu)->n_val = m_val;
 425                 uv_cpu_hub_info(cpu)->numa_blade_id = blade;
 426                 uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
 427                 uv_cpu_hub_info(cpu)->pnode = pnode;
 428                 uv_cpu_hub_info(cpu)->pnode_mask = (1 << n_val) - 1;
 429                 uv_cpu_hub_info(cpu)->gpa_mask = (1 << (m_val + n_val)) - 1;
 430                 uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
 431                 uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
 432                 uv_cpu_hub_info(cpu)->coherency_domain_number = 0;/* ZZZ */
 433                 uv_node_to_blade[nid] = blade;
 434                 uv_cpu_to_blade[cpu] = blade;
 435                 max_pnode = max(pnode, max_pnode);
 436
 437                 printk(KERN_DEBUG "UV: cpu %d, apicid 0x%x, pnode %d, nid %d, "
 438                         "lcpu %d, blade %d\n",
 439                         cpu, per_cpu(x86_cpu_to_apicid, cpu), pnode, nid,
 440                         lcpu, blade);
 441         }
 442
 443         map_gru_high(max_pnode);
 444         map_mmr_high(max_pnode);
 445         map_config_high(max_pnode);
 446         map_mmioh_high(max_pnode);
 447 }
 448
 449 /*
 450  * Called on each cpu to initialize the per_cpu UV data area.
 451  *      ZZZ hotplug not supported yet
 452  */
 453 void __cpuinit uv_cpu_init(void)
 454 {
 455         if (!uv_node_to_blade)
 456                 uv_system_init();
 457
 458         uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;
 459
 460         if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
 461                 set_x2apic_extra_bits(uv_hub_info->pnode);
 462 }
 463
 464