1 // SPDX-License-Identifier: GPL-2.0-only
3 * Machine check handler.
5 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
6 * Rest from unknown author(s).
7 * 2004 Andi Kleen. Rewrote most of it.
8 * Copyright 2008 Intel Corporation
12 #include <linux/thread_info.h>
13 #include <linux/capability.h>
14 #include <linux/miscdevice.h>
15 #include <linux/ratelimit.h>
16 #include <linux/rcupdate.h>
17 #include <linux/kobject.h>
18 #include <linux/uaccess.h>
19 #include <linux/kdebug.h>
20 #include <linux/kernel.h>
21 #include <linux/percpu.h>
22 #include <linux/string.h>
23 #include <linux/device.h>
24 #include <linux/syscore_ops.h>
25 #include <linux/delay.h>
26 #include <linux/ctype.h>
27 #include <linux/sched.h>
28 #include <linux/sysfs.h>
29 #include <linux/types.h>
30 #include <linux/slab.h>
31 #include <linux/init.h>
32 #include <linux/kmod.h>
33 #include <linux/poll.h>
34 #include <linux/nmi.h>
35 #include <linux/cpu.h>
36 #include <linux/ras.h>
37 #include <linux/smp.h>
40 #include <linux/debugfs.h>
41 #include <linux/irq_work.h>
42 #include <linux/export.h>
43 #include <linux/set_memory.h>
44 #include <linux/sync_core.h>
45 #include <linux/task_work.h>
46 #include <linux/hardirq.h>
47 #include <linux/kexec.h>
49 #include <asm/intel-family.h>
50 #include <asm/processor.h>
51 #include <asm/traps.h>
52 #include <asm/tlbflush.h>
55 #include <asm/reboot.h>
60 /* sysfs synchronization */
61 static DEFINE_MUTEX(mce_sysfs_mutex);
63 #define CREATE_TRACE_POINTS
64 #include <trace/events/mce.h>
66 #define SPINUNIT 100 /* 100ns */
68 DEFINE_PER_CPU(unsigned, mce_exception_count);
70 DEFINE_PER_CPU_READ_MOSTLY(unsigned int, mce_num_banks);
72 DEFINE_PER_CPU_READ_MOSTLY(struct mce_bank[MAX_NR_BANKS], mce_banks_array);
75 /* One object for each MCE bank, shared by all CPUs */
77 struct device_attribute attr; /* device attribute */
78 char attrname[ATTR_LEN]; /* attribute name */
79 u8 bank; /* bank number */
81 static struct mce_bank_dev mce_bank_devs[MAX_NR_BANKS];
83 struct mce_vendor_flags mce_flags __read_mostly;
85 struct mca_config mca_cfg __read_mostly = {
90 static DEFINE_PER_CPU(struct mce, mces_seen);
91 static unsigned long mce_need_notify;
94 * MCA banks polled by the period polling timer for corrected events.
95 * With Intel CMCI, this only has MCA banks which do not support CMCI (if any).
97 DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
98 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
102 * MCA banks controlled through firmware first for corrected errors.
103 * This is a global list of banks for which we won't enable CMCI and we
104 * won't poll. Firmware controls these banks and is responsible for
105 * reporting corrected errors through GHES. Uncorrected/recoverable
106 * errors are still notified through a machine check.
108 mce_banks_t mce_banks_ce_disabled;
110 static struct work_struct mce_work;
111 static struct irq_work mce_irq_work;
114 * CPU/chipset specific EDAC code can register a notifier call here to print
115 * MCE errors in a human-readable form.
117 BLOCKING_NOTIFIER_HEAD(x86_mce_decoder_chain);
119 /* Do initial initialization of a struct mce */
120 void mce_setup(struct mce *m)
122 memset(m, 0, sizeof(struct mce));
123 m->cpu = m->extcpu = smp_processor_id();
124 /* need the internal __ version to avoid deadlocks */
125 m->time = __ktime_get_real_seconds();
126 m->cpuvendor = boot_cpu_data.x86_vendor;
127 m->cpuid = cpuid_eax(1);
128 m->socketid = cpu_data(m->extcpu).topo.pkg_id;
129 m->apicid = cpu_data(m->extcpu).topo.initial_apicid;
130 m->mcgcap = __rdmsr(MSR_IA32_MCG_CAP);
131 m->ppin = cpu_data(m->extcpu).ppin;
132 m->microcode = boot_cpu_data.microcode;
135 DEFINE_PER_CPU(struct mce, injectm);
136 EXPORT_PER_CPU_SYMBOL_GPL(injectm);
138 void mce_log(struct mce *m)
140 if (!mce_gen_pool_add(m))
141 irq_work_queue(&mce_irq_work);
143 EXPORT_SYMBOL_GPL(mce_log);
145 void mce_register_decode_chain(struct notifier_block *nb)
147 if (WARN_ON(nb->priority < MCE_PRIO_LOWEST ||
148 nb->priority > MCE_PRIO_HIGHEST))
151 blocking_notifier_chain_register(&x86_mce_decoder_chain, nb);
153 EXPORT_SYMBOL_GPL(mce_register_decode_chain);
155 void mce_unregister_decode_chain(struct notifier_block *nb)
157 blocking_notifier_chain_unregister(&x86_mce_decoder_chain, nb);
159 EXPORT_SYMBOL_GPL(mce_unregister_decode_chain);
161 static void __print_mce(struct mce *m)
163 pr_emerg(HW_ERR "CPU %d: Machine Check%s: %Lx Bank %d: %016Lx\n",
165 (m->mcgstatus & MCG_STATUS_MCIP ? " Exception" : ""),
166 m->mcgstatus, m->bank, m->status);
169 pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ",
170 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
173 if (m->cs == __KERNEL_CS)
174 pr_cont("{%pS}", (void *)(unsigned long)m->ip);
178 pr_emerg(HW_ERR "TSC %llx ", m->tsc);
180 pr_cont("ADDR %llx ", m->addr);
182 pr_cont("MISC %llx ", m->misc);
184 pr_cont("PPIN %llx ", m->ppin);
186 if (mce_flags.smca) {
188 pr_cont("SYND %llx ", m->synd);
190 pr_cont("IPID %llx ", m->ipid);
196 * Note this output is parsed by external tools and old fields
197 * should not be changed.
199 pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n",
200 m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid,
204 static void print_mce(struct mce *m)
208 if (m->cpuvendor != X86_VENDOR_AMD && m->cpuvendor != X86_VENDOR_HYGON)
209 pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n");
212 #define PANIC_TIMEOUT 5 /* 5 seconds */
214 static atomic_t mce_panicked;
216 static int fake_panic;
217 static atomic_t mce_fake_panicked;
219 /* Panic in progress. Enable interrupts and wait for final IPI */
220 static void wait_for_panic(void)
222 long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
226 while (timeout-- > 0)
228 if (panic_timeout == 0)
229 panic_timeout = mca_cfg.panic_timeout;
230 panic("Panicing machine check CPU died");
233 static const char *mce_dump_aux_info(struct mce *m)
235 if (boot_cpu_has_bug(X86_BUG_TDX_PW_MCE))
236 return tdx_dump_mce_info(m);
241 static noinstr void mce_panic(const char *msg, struct mce *final, char *exp)
243 struct llist_node *pending;
244 struct mce_evt_llist *l;
249 * Allow instrumentation around external facilities usage. Not that it
250 * matters a whole lot since the machine is going to panic anyway.
252 instrumentation_begin();
256 * Make sure only one CPU runs in machine check panic
258 if (atomic_inc_return(&mce_panicked) > 1)
265 /* Don't log too much for fake panic */
266 if (atomic_inc_return(&mce_fake_panicked) > 1)
269 pending = mce_gen_pool_prepare_records();
270 /* First print corrected ones that are still unlogged */
271 llist_for_each_entry(l, pending, llnode) {
272 struct mce *m = &l->mce;
273 if (!(m->status & MCI_STATUS_UC)) {
276 apei_err = apei_write_mce(m);
279 /* Now print uncorrected but with the final one last */
280 llist_for_each_entry(l, pending, llnode) {
281 struct mce *m = &l->mce;
282 if (!(m->status & MCI_STATUS_UC))
284 if (!final || mce_cmp(m, final)) {
287 apei_err = apei_write_mce(m);
293 apei_err = apei_write_mce(final);
296 pr_emerg(HW_ERR "Machine check: %s\n", exp);
298 memmsg = mce_dump_aux_info(final);
300 pr_emerg(HW_ERR "Machine check: %s\n", memmsg);
303 if (panic_timeout == 0)
304 panic_timeout = mca_cfg.panic_timeout;
307 * Kdump skips the poisoned page in order to avoid
308 * touching the error bits again. Poison the page even
309 * if the error is fatal and the machine is about to
312 if (kexec_crash_loaded()) {
313 if (final && (final->status & MCI_STATUS_ADDRV)) {
315 p = pfn_to_online_page(final->addr >> PAGE_SHIFT);
322 pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg);
325 instrumentation_end();
328 /* Support code for software error injection */
330 static int msr_to_offset(u32 msr)
332 unsigned bank = __this_cpu_read(injectm.bank);
334 if (msr == mca_cfg.rip_msr)
335 return offsetof(struct mce, ip);
336 if (msr == mca_msr_reg(bank, MCA_STATUS))
337 return offsetof(struct mce, status);
338 if (msr == mca_msr_reg(bank, MCA_ADDR))
339 return offsetof(struct mce, addr);
340 if (msr == mca_msr_reg(bank, MCA_MISC))
341 return offsetof(struct mce, misc);
342 if (msr == MSR_IA32_MCG_STATUS)
343 return offsetof(struct mce, mcgstatus);
347 void ex_handler_msr_mce(struct pt_regs *regs, bool wrmsr)
350 pr_emerg("MSR access error: WRMSR to 0x%x (tried to write 0x%08x%08x) at rIP: 0x%lx (%pS)\n",
351 (unsigned int)regs->cx, (unsigned int)regs->dx, (unsigned int)regs->ax,
352 regs->ip, (void *)regs->ip);
354 pr_emerg("MSR access error: RDMSR from 0x%x at rIP: 0x%lx (%pS)\n",
355 (unsigned int)regs->cx, regs->ip, (void *)regs->ip);
358 show_stack_regs(regs);
360 panic("MCA architectural violation!\n");
366 /* MSR access wrappers used for error injection */
367 noinstr u64 mce_rdmsrl(u32 msr)
369 DECLARE_ARGS(val, low, high);
371 if (__this_cpu_read(injectm.finished)) {
375 instrumentation_begin();
377 offset = msr_to_offset(msr);
381 ret = *(u64 *)((char *)this_cpu_ptr(&injectm) + offset);
383 instrumentation_end();
389 * RDMSR on MCA MSRs should not fault. If they do, this is very much an
390 * architectural violation and needs to be reported to hw vendor. Panic
391 * the box to not allow any further progress.
393 asm volatile("1: rdmsr\n"
395 _ASM_EXTABLE_TYPE(1b, 2b, EX_TYPE_RDMSR_IN_MCE)
396 : EAX_EDX_RET(val, low, high) : "c" (msr));
399 return EAX_EDX_VAL(val, low, high);
402 static noinstr void mce_wrmsrl(u32 msr, u64 v)
406 if (__this_cpu_read(injectm.finished)) {
409 instrumentation_begin();
411 offset = msr_to_offset(msr);
413 *(u64 *)((char *)this_cpu_ptr(&injectm) + offset) = v;
415 instrumentation_end();
421 high = (u32)(v >> 32);
423 /* See comment in mce_rdmsrl() */
424 asm volatile("1: wrmsr\n"
426 _ASM_EXTABLE_TYPE(1b, 2b, EX_TYPE_WRMSR_IN_MCE)
427 : : "c" (msr), "a"(low), "d" (high) : "memory");
431 * Collect all global (w.r.t. this processor) status about this machine
432 * check into our "mce" struct so that we can use it later to assess
433 * the severity of the problem as we read per-bank specific details.
435 static noinstr void mce_gather_info(struct mce *m, struct pt_regs *regs)
438 * Enable instrumentation around mce_setup() which calls external
441 instrumentation_begin();
443 instrumentation_end();
445 m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
448 * Get the address of the instruction at the time of
449 * the machine check error.
451 if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) {
456 * When in VM86 mode make the cs look like ring 3
457 * always. This is a lie, but it's better than passing
458 * the additional vm86 bit around everywhere.
460 if (v8086_mode(regs))
463 /* Use accurate RIP reporting if available. */
465 m->ip = mce_rdmsrl(mca_cfg.rip_msr);
469 int mce_available(struct cpuinfo_x86 *c)
471 if (mca_cfg.disabled)
473 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
476 static void mce_schedule_work(void)
478 if (!mce_gen_pool_empty())
479 schedule_work(&mce_work);
482 static void mce_irq_work_cb(struct irq_work *entry)
487 bool mce_usable_address(struct mce *m)
489 if (!(m->status & MCI_STATUS_ADDRV))
492 switch (m->cpuvendor) {
494 return amd_mce_usable_address(m);
496 case X86_VENDOR_INTEL:
497 case X86_VENDOR_ZHAOXIN:
498 return intel_mce_usable_address(m);
504 EXPORT_SYMBOL_GPL(mce_usable_address);
506 bool mce_is_memory_error(struct mce *m)
508 switch (m->cpuvendor) {
510 case X86_VENDOR_HYGON:
511 return amd_mce_is_memory_error(m);
513 case X86_VENDOR_INTEL:
514 case X86_VENDOR_ZHAOXIN:
516 * Intel SDM Volume 3B - 15.9.2 Compound Error Codes
518 * Bit 7 of the MCACOD field of IA32_MCi_STATUS is used for
519 * indicating a memory error. Bit 8 is used for indicating a
520 * cache hierarchy error. The combination of bit 2 and bit 3
521 * is used for indicating a `generic' cache hierarchy error
522 * But we can't just blindly check the above bits, because if
523 * bit 11 is set, then it is a bus/interconnect error - and
524 * either way the above bits just gives more detail on what
525 * bus/interconnect error happened. Note that bit 12 can be
526 * ignored, as it's the "filter" bit.
528 return (m->status & 0xef80) == BIT(7) ||
529 (m->status & 0xef00) == BIT(8) ||
530 (m->status & 0xeffc) == 0xc;
536 EXPORT_SYMBOL_GPL(mce_is_memory_error);
538 static bool whole_page(struct mce *m)
540 if (!mca_cfg.ser || !(m->status & MCI_STATUS_MISCV))
543 return MCI_MISC_ADDR_LSB(m->misc) >= PAGE_SHIFT;
546 bool mce_is_correctable(struct mce *m)
548 if (m->cpuvendor == X86_VENDOR_AMD && m->status & MCI_STATUS_DEFERRED)
551 if (m->cpuvendor == X86_VENDOR_HYGON && m->status & MCI_STATUS_DEFERRED)
554 if (m->status & MCI_STATUS_UC)
559 EXPORT_SYMBOL_GPL(mce_is_correctable);
561 static int mce_early_notifier(struct notifier_block *nb, unsigned long val,
564 struct mce *m = (struct mce *)data;
569 /* Emit the trace record: */
572 set_bit(0, &mce_need_notify);
579 static struct notifier_block early_nb = {
580 .notifier_call = mce_early_notifier,
581 .priority = MCE_PRIO_EARLY,
584 static int uc_decode_notifier(struct notifier_block *nb, unsigned long val,
587 struct mce *mce = (struct mce *)data;
590 if (!mce || !mce_usable_address(mce))
593 if (mce->severity != MCE_AO_SEVERITY &&
594 mce->severity != MCE_DEFERRED_SEVERITY)
597 pfn = (mce->addr & MCI_ADDR_PHYSADDR) >> PAGE_SHIFT;
598 if (!memory_failure(pfn, 0)) {
600 mce->kflags |= MCE_HANDLED_UC;
606 static struct notifier_block mce_uc_nb = {
607 .notifier_call = uc_decode_notifier,
608 .priority = MCE_PRIO_UC,
611 static int mce_default_notifier(struct notifier_block *nb, unsigned long val,
614 struct mce *m = (struct mce *)data;
619 if (mca_cfg.print_all || !m->kflags)
625 static struct notifier_block mce_default_nb = {
626 .notifier_call = mce_default_notifier,
627 /* lowest prio, we want it to run last. */
628 .priority = MCE_PRIO_LOWEST,
632 * Read ADDR and MISC registers.
634 static noinstr void mce_read_aux(struct mce *m, int i)
636 if (m->status & MCI_STATUS_MISCV)
637 m->misc = mce_rdmsrl(mca_msr_reg(i, MCA_MISC));
639 if (m->status & MCI_STATUS_ADDRV) {
640 m->addr = mce_rdmsrl(mca_msr_reg(i, MCA_ADDR));
643 * Mask the reported address by the reported granularity.
645 if (mca_cfg.ser && (m->status & MCI_STATUS_MISCV)) {
646 u8 shift = MCI_MISC_ADDR_LSB(m->misc);
651 smca_extract_err_addr(m);
654 if (mce_flags.smca) {
655 m->ipid = mce_rdmsrl(MSR_AMD64_SMCA_MCx_IPID(i));
657 if (m->status & MCI_STATUS_SYNDV)
658 m->synd = mce_rdmsrl(MSR_AMD64_SMCA_MCx_SYND(i));
662 DEFINE_PER_CPU(unsigned, mce_poll_count);
665 * Poll for corrected events or events that happened before reset.
666 * Those are just logged through /dev/mcelog.
668 * This is executed in standard interrupt context.
670 * Note: spec recommends to panic for fatal unsignalled
671 * errors here. However this would be quite problematic --
672 * we would need to reimplement the Monarch handling and
673 * it would mess up the exclusion between exception handler
674 * and poll handler -- * so we skip this for now.
675 * These cases should not happen anyways, or only when the CPU
676 * is already totally * confused. In this case it's likely it will
677 * not fully execute the machine check handler either.
679 bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
681 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
682 bool error_seen = false;
686 this_cpu_inc(mce_poll_count);
688 mce_gather_info(&m, NULL);
690 if (flags & MCP_TIMESTAMP)
693 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
694 if (!mce_banks[i].ctl || !test_bit(i, *b))
702 m.status = mce_rdmsrl(mca_msr_reg(i, MCA_STATUS));
705 * Update storm tracking here, before checking for the
706 * MCI_STATUS_VAL bit. Valid corrected errors count
707 * towards declaring, or maintaining, storm status. No
708 * error in a bank counts towards avoiding, or ending,
711 if (!mca_cfg.cmci_disabled)
714 /* If this entry is not valid, ignore it */
715 if (!(m.status & MCI_STATUS_VAL))
719 * If we are logging everything (at CPU online) or this
720 * is a corrected error, then we must log it.
722 if ((flags & MCP_UC) || !(m.status & MCI_STATUS_UC))
726 * Newer Intel systems that support software error
727 * recovery need to make additional checks. Other
728 * CPUs should skip over uncorrected errors, but log
732 if (m.status & MCI_STATUS_UC)
737 /* Log "not enabled" (speculative) errors */
738 if (!(m.status & MCI_STATUS_EN))
742 * Log UCNA (SDM: 15.6.3 "UCR Error Classification")
743 * UC == 1 && PCC == 0 && S == 0
745 if (!(m.status & MCI_STATUS_PCC) && !(m.status & MCI_STATUS_S))
749 * Skip anything else. Presumption is that our read of this
750 * bank is racing with a machine check. Leave the log alone
751 * for do_machine_check() to deal with it.
758 if (flags & MCP_DONTLOG)
762 m.severity = mce_severity(&m, NULL, NULL, false);
764 * Don't get the IP here because it's unlikely to
765 * have anything to do with the actual error location.
768 if (mca_cfg.dont_log_ce && !mce_usable_address(&m))
771 if (flags & MCP_QUEUE_LOG)
772 mce_gen_pool_add(&m);
778 * Clear state for this bank.
780 mce_wrmsrl(mca_msr_reg(i, MCA_STATUS), 0);
784 * Don't clear MCG_STATUS here because it's only defined for
792 EXPORT_SYMBOL_GPL(machine_check_poll);
795 * During IFU recovery Sandy Bridge -EP4S processors set the RIPV and
796 * EIPV bits in MCG_STATUS to zero on the affected logical processor (SDM
797 * Vol 3B Table 15-20). But this confuses both the code that determines
798 * whether the machine check occurred in kernel or user mode, and also
799 * the severity assessment code. Pretend that EIPV was set, and take the
800 * ip/cs values from the pt_regs that mce_gather_info() ignored earlier.
802 static __always_inline void
803 quirk_sandybridge_ifu(int bank, struct mce *m, struct pt_regs *regs)
807 if ((m->mcgstatus & (MCG_STATUS_EIPV|MCG_STATUS_RIPV)) != 0)
809 if ((m->status & (MCI_STATUS_OVER|MCI_STATUS_UC|
810 MCI_STATUS_EN|MCI_STATUS_MISCV|MCI_STATUS_ADDRV|
811 MCI_STATUS_PCC|MCI_STATUS_S|MCI_STATUS_AR|
813 (MCI_STATUS_UC|MCI_STATUS_EN|
814 MCI_STATUS_MISCV|MCI_STATUS_ADDRV|MCI_STATUS_S|
815 MCI_STATUS_AR|MCACOD_INSTR))
818 m->mcgstatus |= MCG_STATUS_EIPV;
824 * Disable fast string copy and return from the MCE handler upon the first SRAR
825 * MCE on bank 1 due to a CPU erratum on Intel Skylake/Cascade Lake/Cooper Lake
827 * The fast string copy instructions ("REP; MOVS*") could consume an
828 * uncorrectable memory error in the cache line _right after_ the desired region
829 * to copy and raise an MCE with RIP pointing to the instruction _after_ the
831 * This mitigation addresses the issue completely with the caveat of performance
832 * degradation on the CPU affected. This is still better than the OS crashing on
833 * MCEs raised on an irrelevant process due to "REP; MOVS*" accesses from a
834 * kernel context (e.g., copy_page).
836 * Returns true when fast string copy on CPU has been disabled.
838 static noinstr bool quirk_skylake_repmov(void)
840 u64 mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
841 u64 misc_enable = mce_rdmsrl(MSR_IA32_MISC_ENABLE);
845 * Apply the quirk only to local machine checks, i.e., no broadcast
848 if (!(mcgstatus & MCG_STATUS_LMCES) ||
849 !(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING))
852 mc1_status = mce_rdmsrl(MSR_IA32_MCx_STATUS(1));
854 /* Check for a software-recoverable data fetch error. */
856 (MCI_STATUS_VAL | MCI_STATUS_OVER | MCI_STATUS_UC | MCI_STATUS_EN |
857 MCI_STATUS_ADDRV | MCI_STATUS_MISCV | MCI_STATUS_PCC |
858 MCI_STATUS_AR | MCI_STATUS_S)) ==
859 (MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
860 MCI_STATUS_ADDRV | MCI_STATUS_MISCV |
861 MCI_STATUS_AR | MCI_STATUS_S)) {
862 misc_enable &= ~MSR_IA32_MISC_ENABLE_FAST_STRING;
863 mce_wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
864 mce_wrmsrl(MSR_IA32_MCx_STATUS(1), 0);
866 instrumentation_begin();
867 pr_err_once("Erratum detected, disable fast string copy instructions.\n");
868 instrumentation_end();
877 * Some Zen-based Instruction Fetch Units set EIPV=RIPV=0 on poison consumption
878 * errors. This means mce_gather_info() will not save the "ip" and "cs" registers.
880 * However, the context is still valid, so save the "cs" register for later use.
882 * The "ip" register is truly unknown, so don't save it or fixup EIPV/RIPV.
884 * The Instruction Fetch Unit is at MCA bank 1 for all affected systems.
886 static __always_inline void quirk_zen_ifu(int bank, struct mce *m, struct pt_regs *regs)
890 if (!(m->status & MCI_STATUS_POISON))
897 * Do a quick check if any of the events requires a panic.
898 * This decides if we keep the events around or clear them.
900 static __always_inline int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp,
901 struct pt_regs *regs)
906 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
907 m->status = mce_rdmsrl(mca_msr_reg(i, MCA_STATUS));
908 if (!(m->status & MCI_STATUS_VAL))
911 arch___set_bit(i, validp);
912 if (mce_flags.snb_ifu_quirk)
913 quirk_sandybridge_ifu(i, m, regs);
915 if (mce_flags.zen_ifu_quirk)
916 quirk_zen_ifu(i, m, regs);
919 if (mce_severity(m, regs, &tmp, true) >= MCE_PANIC_SEVERITY) {
929 * Variable to establish order between CPUs while scanning.
930 * Each CPU spins initially until executing is equal its number.
932 static atomic_t mce_executing;
935 * Defines order of CPUs on entry. First CPU becomes Monarch.
937 static atomic_t mce_callin;
940 * Track which CPUs entered the MCA broadcast synchronization and which not in
941 * order to print holdouts.
943 static cpumask_t mce_missing_cpus = CPU_MASK_ALL;
946 * Check if a timeout waiting for other CPUs happened.
948 static noinstr int mce_timed_out(u64 *t, const char *msg)
952 /* Enable instrumentation around calls to external facilities */
953 instrumentation_begin();
956 * The others already did panic for some reason.
957 * Bail out like in a timeout.
958 * rmb() to tell the compiler that system_state
959 * might have been modified by someone else.
962 if (atomic_read(&mce_panicked))
964 if (!mca_cfg.monarch_timeout)
966 if ((s64)*t < SPINUNIT) {
967 if (cpumask_and(&mce_missing_cpus, cpu_online_mask, &mce_missing_cpus))
968 pr_emerg("CPUs not responding to MCE broadcast (may include false positives): %*pbl\n",
969 cpumask_pr_args(&mce_missing_cpus));
970 mce_panic(msg, NULL, NULL);
978 touch_nmi_watchdog();
980 instrumentation_end();
986 * The Monarch's reign. The Monarch is the CPU who entered
987 * the machine check handler first. It waits for the others to
988 * raise the exception too and then grades them. When any
989 * error is fatal panic. Only then let the others continue.
991 * The other CPUs entering the MCE handler will be controlled by the
992 * Monarch. They are called Subjects.
994 * This way we prevent any potential data corruption in a unrecoverable case
995 * and also makes sure always all CPU's errors are examined.
997 * Also this detects the case of a machine check event coming from outer
998 * space (not detected by any CPUs) In this case some external agent wants
999 * us to shut down, so panic too.
1001 * The other CPUs might still decide to panic if the handler happens
1002 * in a unrecoverable place, but in this case the system is in a semi-stable
1003 * state and won't corrupt anything by itself. It's ok to let the others
1004 * continue for a bit first.
1006 * All the spin loops have timeouts; when a timeout happens a CPU
1007 * typically elects itself to be Monarch.
1009 static void mce_reign(void)
1012 struct mce *m = NULL;
1013 int global_worst = 0;
1017 * This CPU is the Monarch and the other CPUs have run
1018 * through their handlers.
1019 * Grade the severity of the errors of all the CPUs.
1021 for_each_possible_cpu(cpu) {
1022 struct mce *mtmp = &per_cpu(mces_seen, cpu);
1024 if (mtmp->severity > global_worst) {
1025 global_worst = mtmp->severity;
1026 m = &per_cpu(mces_seen, cpu);
1031 * Cannot recover? Panic here then.
1032 * This dumps all the mces in the log buffer and stops the
1035 if (m && global_worst >= MCE_PANIC_SEVERITY) {
1036 /* call mce_severity() to get "msg" for panic */
1037 mce_severity(m, NULL, &msg, true);
1038 mce_panic("Fatal machine check", m, msg);
1042 * For UC somewhere we let the CPU who detects it handle it.
1043 * Also must let continue the others, otherwise the handling
1044 * CPU could deadlock on a lock.
1048 * No machine check event found. Must be some external
1049 * source or one CPU is hung. Panic.
1051 if (global_worst <= MCE_KEEP_SEVERITY)
1052 mce_panic("Fatal machine check from unknown source", NULL, NULL);
1055 * Now clear all the mces_seen so that they don't reappear on
1058 for_each_possible_cpu(cpu)
1059 memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce));
1062 static atomic_t global_nwo;
1065 * Start of Monarch synchronization. This waits until all CPUs have
1066 * entered the exception handler and then determines if any of them
1067 * saw a fatal event that requires panic. Then it executes them
1068 * in the entry order.
1069 * TBD double check parallel CPU hotunplug
1071 static noinstr int mce_start(int *no_way_out)
1073 u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC;
1074 int order, ret = -1;
1079 raw_atomic_add(*no_way_out, &global_nwo);
1081 * Rely on the implied barrier below, such that global_nwo
1082 * is updated before mce_callin.
1084 order = raw_atomic_inc_return(&mce_callin);
1085 arch_cpumask_clear_cpu(smp_processor_id(), &mce_missing_cpus);
1087 /* Enable instrumentation around calls to external facilities */
1088 instrumentation_begin();
1091 * Wait for everyone.
1093 while (raw_atomic_read(&mce_callin) != num_online_cpus()) {
1094 if (mce_timed_out(&timeout,
1095 "Timeout: Not all CPUs entered broadcast exception handler")) {
1096 raw_atomic_set(&global_nwo, 0);
1103 * mce_callin should be read before global_nwo
1109 * Monarch: Starts executing now, the others wait.
1111 raw_atomic_set(&mce_executing, 1);
1114 * Subject: Now start the scanning loop one by one in
1115 * the original callin order.
1116 * This way when there are any shared banks it will be
1117 * only seen by one CPU before cleared, avoiding duplicates.
1119 while (raw_atomic_read(&mce_executing) < order) {
1120 if (mce_timed_out(&timeout,
1121 "Timeout: Subject CPUs unable to finish machine check processing")) {
1122 raw_atomic_set(&global_nwo, 0);
1130 * Cache the global no_way_out state.
1132 *no_way_out = raw_atomic_read(&global_nwo);
1137 instrumentation_end();
1143 * Synchronize between CPUs after main scanning loop.
1144 * This invokes the bulk of the Monarch processing.
1146 static noinstr int mce_end(int order)
1148 u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC;
1151 /* Allow instrumentation around external facilities. */
1152 instrumentation_begin();
1160 * Allow others to run.
1162 atomic_inc(&mce_executing);
1166 * Monarch: Wait for everyone to go through their scanning
1169 while (atomic_read(&mce_executing) <= num_online_cpus()) {
1170 if (mce_timed_out(&timeout,
1171 "Timeout: Monarch CPU unable to finish machine check processing"))
1181 * Subject: Wait for Monarch to finish.
1183 while (atomic_read(&mce_executing) != 0) {
1184 if (mce_timed_out(&timeout,
1185 "Timeout: Monarch CPU did not finish machine check processing"))
1191 * Don't reset anything. That's done by the Monarch.
1198 * Reset all global state.
1201 atomic_set(&global_nwo, 0);
1202 atomic_set(&mce_callin, 0);
1203 cpumask_setall(&mce_missing_cpus);
1207 * Let others run again.
1209 atomic_set(&mce_executing, 0);
1212 instrumentation_end();
1217 static __always_inline void mce_clear_state(unsigned long *toclear)
1221 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
1222 if (arch_test_bit(i, toclear))
1223 mce_wrmsrl(mca_msr_reg(i, MCA_STATUS), 0);
1228 * Cases where we avoid rendezvous handler timeout:
1229 * 1) If this CPU is offline.
1231 * 2) If crashing_cpu was set, e.g. we're entering kdump and we need to
1232 * skip those CPUs which remain looping in the 1st kernel - see
1233 * crash_nmi_callback().
1235 * Note: there still is a small window between kexec-ing and the new,
1236 * kdump kernel establishing a new #MC handler where a broadcasted MCE
1237 * might not get handled properly.
1239 static noinstr bool mce_check_crashing_cpu(void)
1241 unsigned int cpu = smp_processor_id();
1243 if (arch_cpu_is_offline(cpu) ||
1244 (crashing_cpu != -1 && crashing_cpu != cpu)) {
1247 mcgstatus = __rdmsr(MSR_IA32_MCG_STATUS);
1249 if (boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) {
1250 if (mcgstatus & MCG_STATUS_LMCES)
1254 if (mcgstatus & MCG_STATUS_RIPV) {
1255 __wrmsr(MSR_IA32_MCG_STATUS, 0, 0);
1262 static __always_inline int
1263 __mc_scan_banks(struct mce *m, struct pt_regs *regs, struct mce *final,
1264 unsigned long *toclear, unsigned long *valid_banks, int no_way_out,
1267 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
1268 struct mca_config *cfg = &mca_cfg;
1269 int severity, i, taint = 0;
1271 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
1272 arch___clear_bit(i, toclear);
1273 if (!arch_test_bit(i, valid_banks))
1276 if (!mce_banks[i].ctl)
1283 m->status = mce_rdmsrl(mca_msr_reg(i, MCA_STATUS));
1284 if (!(m->status & MCI_STATUS_VAL))
1288 * Corrected or non-signaled errors are handled by
1289 * machine_check_poll(). Leave them alone, unless this panics.
1291 if (!(m->status & (cfg->ser ? MCI_STATUS_S : MCI_STATUS_UC)) &&
1295 /* Set taint even when machine check was not enabled. */
1298 severity = mce_severity(m, regs, NULL, true);
1301 * When machine check was for corrected/deferred handler don't
1302 * touch, unless we're panicking.
1304 if ((severity == MCE_KEEP_SEVERITY ||
1305 severity == MCE_UCNA_SEVERITY) && !no_way_out)
1308 arch___set_bit(i, toclear);
1310 /* Machine check event was not enabled. Clear, but ignore. */
1311 if (severity == MCE_NO_SEVERITY)
1316 /* assuming valid severity level != 0 */
1317 m->severity = severity;
1320 * Enable instrumentation around the mce_log() call which is
1321 * done in #MC context, where instrumentation is disabled.
1323 instrumentation_begin();
1325 instrumentation_end();
1327 if (severity > *worst) {
1333 /* mce_clear_state will clear *final, save locally for use later */
1339 static void kill_me_now(struct callback_head *ch)
1341 struct task_struct *p = container_of(ch, struct task_struct, mce_kill_me);
1347 static void kill_me_maybe(struct callback_head *cb)
1349 struct task_struct *p = container_of(cb, struct task_struct, mce_kill_me);
1350 int flags = MF_ACTION_REQUIRED;
1355 pr_err("Uncorrected hardware memory error in user-access at %llx", p->mce_addr);
1358 flags |= MF_MUST_KILL;
1360 pfn = (p->mce_addr & MCI_ADDR_PHYSADDR) >> PAGE_SHIFT;
1361 ret = memory_failure(pfn, flags);
1363 set_mce_nospec(pfn);
1369 * -EHWPOISON from memory_failure() means that it already sent SIGBUS
1370 * to the current process with the proper error info,
1371 * -EOPNOTSUPP means hwpoison_filter() filtered the error event,
1373 * In both cases, no further processing is required.
1375 if (ret == -EHWPOISON || ret == -EOPNOTSUPP)
1378 pr_err("Memory error not recovered");
1382 static void kill_me_never(struct callback_head *cb)
1384 struct task_struct *p = container_of(cb, struct task_struct, mce_kill_me);
1388 pr_err("Kernel accessed poison in user space at %llx\n", p->mce_addr);
1389 pfn = (p->mce_addr & MCI_ADDR_PHYSADDR) >> PAGE_SHIFT;
1390 if (!memory_failure(pfn, 0))
1391 set_mce_nospec(pfn);
1394 static void queue_task_work(struct mce *m, char *msg, void (*func)(struct callback_head *))
1396 int count = ++current->mce_count;
1398 /* First call, save all the details */
1400 current->mce_addr = m->addr;
1401 current->mce_kflags = m->kflags;
1402 current->mce_ripv = !!(m->mcgstatus & MCG_STATUS_RIPV);
1403 current->mce_whole_page = whole_page(m);
1404 current->mce_kill_me.func = func;
1407 /* Ten is likely overkill. Don't expect more than two faults before task_work() */
1409 mce_panic("Too many consecutive machine checks while accessing user data", m, msg);
1411 /* Second or later call, make sure page address matches the one from first call */
1412 if (count > 1 && (current->mce_addr >> PAGE_SHIFT) != (m->addr >> PAGE_SHIFT))
1413 mce_panic("Consecutive machine checks to different user pages", m, msg);
1415 /* Do not call task_work_add() more than once */
1419 task_work_add(current, ¤t->mce_kill_me, TWA_RESUME);
1422 /* Handle unconfigured int18 (should never happen) */
1423 static noinstr void unexpected_machine_check(struct pt_regs *regs)
1425 instrumentation_begin();
1426 pr_err("CPU#%d: Unexpected int18 (Machine Check)\n",
1427 smp_processor_id());
1428 instrumentation_end();
1432 * The actual machine check handler. This only handles real exceptions when
1433 * something got corrupted coming in through int 18.
1435 * This is executed in #MC context not subject to normal locking rules.
1436 * This implies that most kernel services cannot be safely used. Don't even
1437 * think about putting a printk in there!
1439 * On Intel systems this is entered on all CPUs in parallel through
1440 * MCE broadcast. However some CPUs might be broken beyond repair,
1441 * so be always careful when synchronizing with others.
1443 * Tracing and kprobes are disabled: if we interrupted a kernel context
1444 * with IF=1, we need to minimize stack usage. There are also recursion
1445 * issues: if the machine check was due to a failure of the memory
1446 * backing the user stack, tracing that reads the user stack will cause
1447 * potentially infinite recursion.
1449 * Currently, the #MC handler calls out to a number of external facilities
1450 * and, therefore, allows instrumentation around them. The optimal thing to
1451 * have would be to do the absolutely minimal work required in #MC context
1452 * and have instrumentation disabled only around that. Further processing can
1453 * then happen in process context where instrumentation is allowed. Achieving
1454 * that requires careful auditing and modifications. Until then, the code
1455 * allows instrumentation temporarily, where required. *
1457 noinstr void do_machine_check(struct pt_regs *regs)
1459 int worst = 0, order, no_way_out, kill_current_task, lmce, taint = 0;
1460 DECLARE_BITMAP(valid_banks, MAX_NR_BANKS) = { 0 };
1461 DECLARE_BITMAP(toclear, MAX_NR_BANKS) = { 0 };
1462 struct mce m, *final;
1465 if (unlikely(mce_flags.p5))
1466 return pentium_machine_check(regs);
1467 else if (unlikely(mce_flags.winchip))
1468 return winchip_machine_check(regs);
1469 else if (unlikely(!mca_cfg.initialized))
1470 return unexpected_machine_check(regs);
1472 if (mce_flags.skx_repmov_quirk && quirk_skylake_repmov())
1476 * Establish sequential order between the CPUs entering the machine
1482 * If no_way_out gets set, there is no safe way to recover from this
1488 * If kill_current_task is not set, there might be a way to recover from this
1491 kill_current_task = 0;
1494 * MCEs are always local on AMD. Same is determined by MCG_STATUS_LMCES
1499 this_cpu_inc(mce_exception_count);
1501 mce_gather_info(&m, regs);
1504 final = this_cpu_ptr(&mces_seen);
1507 no_way_out = mce_no_way_out(&m, &msg, valid_banks, regs);
1512 * When no restart IP might need to kill or panic.
1513 * Assume the worst for now, but if we find the
1514 * severity is MCE_AR_SEVERITY we have other options.
1516 if (!(m.mcgstatus & MCG_STATUS_RIPV))
1517 kill_current_task = 1;
1519 * Check if this MCE is signaled to only this logical processor,
1520 * on Intel, Zhaoxin only.
1522 if (m.cpuvendor == X86_VENDOR_INTEL ||
1523 m.cpuvendor == X86_VENDOR_ZHAOXIN)
1524 lmce = m.mcgstatus & MCG_STATUS_LMCES;
1527 * Local machine check may already know that we have to panic.
1528 * Broadcast machine check begins rendezvous in mce_start()
1529 * Go through all banks in exclusion of the other CPUs. This way we
1530 * don't report duplicated events on shared banks because the first one
1531 * to see it will clear it.
1535 mce_panic("Fatal local machine check", &m, msg);
1537 order = mce_start(&no_way_out);
1540 taint = __mc_scan_banks(&m, regs, final, toclear, valid_banks, no_way_out, &worst);
1543 mce_clear_state(toclear);
1546 * Do most of the synchronization with other CPUs.
1547 * When there's any problem use only local no_way_out state.
1550 if (mce_end(order) < 0) {
1552 no_way_out = worst >= MCE_PANIC_SEVERITY;
1555 mce_panic("Fatal machine check on current CPU", &m, msg);
1559 * If there was a fatal machine check we should have
1560 * already called mce_panic earlier in this function.
1561 * Since we re-read the banks, we might have found
1562 * something new. Check again to see if we found a
1563 * fatal error. We call "mce_severity()" again to
1564 * make sure we have the right "msg".
1566 if (worst >= MCE_PANIC_SEVERITY) {
1567 mce_severity(&m, regs, &msg, true);
1568 mce_panic("Local fatal machine check!", &m, msg);
1573 * Enable instrumentation around the external facilities like task_work_add()
1574 * (via queue_task_work()), fixup_exception() etc. For now, that is. Fixing this
1575 * properly would need a lot more involved reorganization.
1577 instrumentation_begin();
1580 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
1582 if (worst != MCE_AR_SEVERITY && !kill_current_task)
1585 /* Fault was in user mode and we need to take some action */
1586 if ((m.cs & 3) == 3) {
1587 /* If this triggers there is no way to recover. Die hard. */
1588 BUG_ON(!on_thread_stack() || !user_mode(regs));
1590 if (!mce_usable_address(&m))
1591 queue_task_work(&m, msg, kill_me_now);
1593 queue_task_work(&m, msg, kill_me_maybe);
1597 * Handle an MCE which has happened in kernel space but from
1598 * which the kernel can recover: ex_has_fault_handler() has
1599 * already verified that the rIP at which the error happened is
1600 * a rIP from which the kernel can recover (by jumping to
1601 * recovery code specified in _ASM_EXTABLE_FAULT()) and the
1602 * corresponding exception handler which would do that is the
1605 if (m.kflags & MCE_IN_KERNEL_RECOV) {
1606 if (!fixup_exception(regs, X86_TRAP_MC, 0, 0))
1607 mce_panic("Failed kernel mode recovery", &m, msg);
1610 if (m.kflags & MCE_IN_KERNEL_COPYIN)
1611 queue_task_work(&m, msg, kill_me_never);
1615 instrumentation_end();
1618 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1620 EXPORT_SYMBOL_GPL(do_machine_check);
1622 #ifndef CONFIG_MEMORY_FAILURE
1623 int memory_failure(unsigned long pfn, int flags)
1625 /* mce_severity() should not hand us an ACTION_REQUIRED error */
1626 BUG_ON(flags & MF_ACTION_REQUIRED);
1627 pr_err("Uncorrected memory error in page 0x%lx ignored\n"
1628 "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n",
1636 * Periodic polling timer for "silent" machine check errors. If the
1637 * poller finds an MCE, poll 2x faster. When the poller finds no more
1638 * errors, poll 2x slower (up to check_interval seconds).
1640 static unsigned long check_interval = INITIAL_CHECK_INTERVAL;
1642 static DEFINE_PER_CPU(unsigned long, mce_next_interval); /* in jiffies */
1643 static DEFINE_PER_CPU(struct timer_list, mce_timer);
1645 static void __start_timer(struct timer_list *t, unsigned long interval)
1647 unsigned long when = jiffies + interval;
1648 unsigned long flags;
1650 local_irq_save(flags);
1652 if (!timer_pending(t) || time_before(when, t->expires))
1653 mod_timer(t, round_jiffies(when));
1655 local_irq_restore(flags);
1658 static void mc_poll_banks_default(void)
1660 machine_check_poll(0, this_cpu_ptr(&mce_poll_banks));
1663 void (*mc_poll_banks)(void) = mc_poll_banks_default;
1665 static void mce_timer_fn(struct timer_list *t)
1667 struct timer_list *cpu_t = this_cpu_ptr(&mce_timer);
1670 WARN_ON(cpu_t != t);
1672 iv = __this_cpu_read(mce_next_interval);
1674 if (mce_available(this_cpu_ptr(&cpu_info)))
1678 * Alert userspace if needed. If we logged an MCE, reduce the polling
1679 * interval, otherwise increase the polling interval.
1681 if (mce_notify_irq())
1682 iv = max(iv / 2, (unsigned long) HZ/100);
1684 iv = min(iv * 2, round_jiffies_relative(check_interval * HZ));
1686 if (mce_get_storm_mode()) {
1687 __start_timer(t, HZ);
1689 __this_cpu_write(mce_next_interval, iv);
1690 __start_timer(t, iv);
1695 * When a storm starts on any bank on this CPU, switch to polling
1696 * once per second. When the storm ends, revert to the default
1699 void mce_timer_kick(bool storm)
1701 struct timer_list *t = this_cpu_ptr(&mce_timer);
1703 mce_set_storm_mode(storm);
1706 __start_timer(t, HZ);
1708 __this_cpu_write(mce_next_interval, check_interval * HZ);
1711 /* Must not be called in IRQ context where del_timer_sync() can deadlock */
1712 static void mce_timer_delete_all(void)
1716 for_each_online_cpu(cpu)
1717 del_timer_sync(&per_cpu(mce_timer, cpu));
1721 * Notify the user(s) about new machine check events.
1722 * Can be called from interrupt context, but not from machine check/NMI
1725 int mce_notify_irq(void)
1727 /* Not more than two messages every minute */
1728 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
1730 if (test_and_clear_bit(0, &mce_need_notify)) {
1733 if (__ratelimit(&ratelimit))
1734 pr_info(HW_ERR "Machine check events logged\n");
1740 EXPORT_SYMBOL_GPL(mce_notify_irq);
1742 static void __mcheck_cpu_mce_banks_init(void)
1744 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
1745 u8 n_banks = this_cpu_read(mce_num_banks);
1748 for (i = 0; i < n_banks; i++) {
1749 struct mce_bank *b = &mce_banks[i];
1752 * Init them all, __mcheck_cpu_apply_quirks() is going to apply
1753 * the required vendor quirks before
1754 * __mcheck_cpu_init_clear_banks() does the final bank setup.
1762 * Initialize Machine Checks for a CPU.
1764 static void __mcheck_cpu_cap_init(void)
1769 rdmsrl(MSR_IA32_MCG_CAP, cap);
1771 b = cap & MCG_BANKCNT_MASK;
1773 if (b > MAX_NR_BANKS) {
1774 pr_warn("CPU%d: Using only %u machine check banks out of %u\n",
1775 smp_processor_id(), MAX_NR_BANKS, b);
1779 this_cpu_write(mce_num_banks, b);
1781 __mcheck_cpu_mce_banks_init();
1783 /* Use accurate RIP reporting if available. */
1784 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
1785 mca_cfg.rip_msr = MSR_IA32_MCG_EIP;
1787 if (cap & MCG_SER_P)
1791 static void __mcheck_cpu_init_generic(void)
1793 enum mcp_flags m_fl = 0;
1794 mce_banks_t all_banks;
1797 if (!mca_cfg.bootlog)
1801 * Log the machine checks left over from the previous reset. Log them
1802 * only, do not start processing them. That will happen in mcheck_late_init()
1803 * when all consumers have been registered on the notifier chain.
1805 bitmap_fill(all_banks, MAX_NR_BANKS);
1806 machine_check_poll(MCP_UC | MCP_QUEUE_LOG | m_fl, &all_banks);
1808 cr4_set_bits(X86_CR4_MCE);
1810 rdmsrl(MSR_IA32_MCG_CAP, cap);
1811 if (cap & MCG_CTL_P)
1812 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
1815 static void __mcheck_cpu_init_clear_banks(void)
1817 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
1820 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
1821 struct mce_bank *b = &mce_banks[i];
1825 wrmsrl(mca_msr_reg(i, MCA_CTL), b->ctl);
1826 wrmsrl(mca_msr_reg(i, MCA_STATUS), 0);
1831 * Do a final check to see if there are any unused/RAZ banks.
1833 * This must be done after the banks have been initialized and any quirks have
1836 * Do not call this from any user-initiated flows, e.g. CPU hotplug or sysfs.
1837 * Otherwise, a user who disables a bank will not be able to re-enable it
1838 * without a system reboot.
1840 static void __mcheck_cpu_check_banks(void)
1842 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
1846 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
1847 struct mce_bank *b = &mce_banks[i];
1852 rdmsrl(mca_msr_reg(i, MCA_CTL), msrval);
1857 /* Add per CPU specific workarounds here */
1858 static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
1860 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
1861 struct mca_config *cfg = &mca_cfg;
1863 if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
1864 pr_info("unknown CPU type - not enabling MCE support\n");
1868 /* This should be disabled by the BIOS, but isn't always */
1869 if (c->x86_vendor == X86_VENDOR_AMD) {
1870 if (c->x86 == 15 && this_cpu_read(mce_num_banks) > 4) {
1872 * disable GART TBL walk error reporting, which
1873 * trips off incorrectly with the IOMMU & 3ware
1876 clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
1878 if (c->x86 < 0x11 && cfg->bootlog < 0) {
1880 * Lots of broken BIOS around that don't clear them
1881 * by default and leave crap in there. Don't log:
1886 * Various K7s with broken bank 0 around. Always disable
1889 if (c->x86 == 6 && this_cpu_read(mce_num_banks) > 0)
1890 mce_banks[0].ctl = 0;
1893 * overflow_recov is supported for F15h Models 00h-0fh
1894 * even though we don't have a CPUID bit for it.
1896 if (c->x86 == 0x15 && c->x86_model <= 0xf)
1897 mce_flags.overflow_recov = 1;
1899 if (c->x86 >= 0x17 && c->x86 <= 0x1A)
1900 mce_flags.zen_ifu_quirk = 1;
1904 if (c->x86_vendor == X86_VENDOR_INTEL) {
1906 * SDM documents that on family 6 bank 0 should not be written
1907 * because it aliases to another special BIOS controlled
1909 * But it's not aliased anymore on model 0x1a+
1910 * Don't ignore bank 0 completely because there could be a
1911 * valid event later, merely don't write CTL0.
1914 if (c->x86 == 6 && c->x86_model < 0x1A && this_cpu_read(mce_num_banks) > 0)
1915 mce_banks[0].init = false;
1918 * All newer Intel systems support MCE broadcasting. Enable
1919 * synchronization with a one second timeout.
1921 if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
1922 cfg->monarch_timeout < 0)
1923 cfg->monarch_timeout = USEC_PER_SEC;
1926 * There are also broken BIOSes on some Pentium M and
1929 if (c->x86 == 6 && c->x86_model <= 13 && cfg->bootlog < 0)
1932 if (c->x86 == 6 && c->x86_model == 45)
1933 mce_flags.snb_ifu_quirk = 1;
1936 * Skylake, Cascacde Lake and Cooper Lake require a quirk on
1939 if (c->x86 == 6 && c->x86_model == INTEL_FAM6_SKYLAKE_X)
1940 mce_flags.skx_repmov_quirk = 1;
1943 if (c->x86_vendor == X86_VENDOR_ZHAOXIN) {
1945 * All newer Zhaoxin CPUs support MCE broadcasting. Enable
1946 * synchronization with a one second timeout.
1948 if (c->x86 > 6 || (c->x86_model == 0x19 || c->x86_model == 0x1f)) {
1949 if (cfg->monarch_timeout < 0)
1950 cfg->monarch_timeout = USEC_PER_SEC;
1954 if (cfg->monarch_timeout < 0)
1955 cfg->monarch_timeout = 0;
1956 if (cfg->bootlog != 0)
1957 cfg->panic_timeout = 30;
1962 static int __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c)
1967 switch (c->x86_vendor) {
1968 case X86_VENDOR_INTEL:
1969 intel_p5_mcheck_init(c);
1972 case X86_VENDOR_CENTAUR:
1973 winchip_mcheck_init(c);
1974 mce_flags.winchip = 1;
1984 * Init basic CPU features needed for early decoding of MCEs.
1986 static void __mcheck_cpu_init_early(struct cpuinfo_x86 *c)
1988 if (c->x86_vendor == X86_VENDOR_AMD || c->x86_vendor == X86_VENDOR_HYGON) {
1989 mce_flags.overflow_recov = !!cpu_has(c, X86_FEATURE_OVERFLOW_RECOV);
1990 mce_flags.succor = !!cpu_has(c, X86_FEATURE_SUCCOR);
1991 mce_flags.smca = !!cpu_has(c, X86_FEATURE_SMCA);
1992 mce_flags.amd_threshold = 1;
1996 static void mce_centaur_feature_init(struct cpuinfo_x86 *c)
1998 struct mca_config *cfg = &mca_cfg;
2001 * All newer Centaur CPUs support MCE broadcasting. Enable
2002 * synchronization with a one second timeout.
2004 if ((c->x86 == 6 && c->x86_model == 0xf && c->x86_stepping >= 0xe) ||
2006 if (cfg->monarch_timeout < 0)
2007 cfg->monarch_timeout = USEC_PER_SEC;
2011 static void mce_zhaoxin_feature_init(struct cpuinfo_x86 *c)
2013 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
2016 * These CPUs have MCA bank 8 which reports only one error type called
2017 * SVAD (System View Address Decoder). The reporting of that error is
2018 * controlled by IA32_MC8.CTL.0.
2020 * If enabled, prefetching on these CPUs will cause SVAD MCE when
2021 * virtual machines start and result in a system panic. Always disable
2022 * bank 8 SVAD error by default.
2024 if ((c->x86 == 7 && c->x86_model == 0x1b) ||
2025 (c->x86_model == 0x19 || c->x86_model == 0x1f)) {
2026 if (this_cpu_read(mce_num_banks) > 8)
2027 mce_banks[8].ctl = 0;
2034 static void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c)
2039 static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
2041 switch (c->x86_vendor) {
2042 case X86_VENDOR_INTEL:
2043 mce_intel_feature_init(c);
2046 case X86_VENDOR_AMD: {
2047 mce_amd_feature_init(c);
2051 case X86_VENDOR_HYGON:
2052 mce_hygon_feature_init(c);
2055 case X86_VENDOR_CENTAUR:
2056 mce_centaur_feature_init(c);
2059 case X86_VENDOR_ZHAOXIN:
2060 mce_zhaoxin_feature_init(c);
2068 static void __mcheck_cpu_clear_vendor(struct cpuinfo_x86 *c)
2070 switch (c->x86_vendor) {
2071 case X86_VENDOR_INTEL:
2072 mce_intel_feature_clear(c);
2075 case X86_VENDOR_ZHAOXIN:
2076 mce_zhaoxin_feature_clear(c);
2084 static void mce_start_timer(struct timer_list *t)
2086 unsigned long iv = check_interval * HZ;
2088 if (mca_cfg.ignore_ce || !iv)
2091 this_cpu_write(mce_next_interval, iv);
2092 __start_timer(t, iv);
2095 static void __mcheck_cpu_setup_timer(void)
2097 struct timer_list *t = this_cpu_ptr(&mce_timer);
2099 timer_setup(t, mce_timer_fn, TIMER_PINNED);
2102 static void __mcheck_cpu_init_timer(void)
2104 struct timer_list *t = this_cpu_ptr(&mce_timer);
2106 timer_setup(t, mce_timer_fn, TIMER_PINNED);
2110 bool filter_mce(struct mce *m)
2112 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
2113 return amd_filter_mce(m);
2114 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2115 return intel_filter_mce(m);
2120 static __always_inline void exc_machine_check_kernel(struct pt_regs *regs)
2122 irqentry_state_t irq_state;
2124 WARN_ON_ONCE(user_mode(regs));
2127 * Only required when from kernel mode. See
2128 * mce_check_crashing_cpu() for details.
2130 if (mca_cfg.initialized && mce_check_crashing_cpu())
2133 irq_state = irqentry_nmi_enter(regs);
2135 do_machine_check(regs);
2137 irqentry_nmi_exit(regs, irq_state);
2140 static __always_inline void exc_machine_check_user(struct pt_regs *regs)
2142 irqentry_enter_from_user_mode(regs);
2144 do_machine_check(regs);
2146 irqentry_exit_to_user_mode(regs);
2149 #ifdef CONFIG_X86_64
2150 /* MCE hit kernel mode */
2151 DEFINE_IDTENTRY_MCE(exc_machine_check)
2155 dr7 = local_db_save();
2156 exc_machine_check_kernel(regs);
2157 local_db_restore(dr7);
2160 /* The user mode variant. */
2161 DEFINE_IDTENTRY_MCE_USER(exc_machine_check)
2165 dr7 = local_db_save();
2166 exc_machine_check_user(regs);
2167 local_db_restore(dr7);
2170 /* 32bit unified entry point */
2171 DEFINE_IDTENTRY_RAW(exc_machine_check)
2175 dr7 = local_db_save();
2176 if (user_mode(regs))
2177 exc_machine_check_user(regs);
2179 exc_machine_check_kernel(regs);
2180 local_db_restore(dr7);
2185 * Called for each booted CPU to set up machine checks.
2186 * Must be called with preempt off:
2188 void mcheck_cpu_init(struct cpuinfo_x86 *c)
2190 if (mca_cfg.disabled)
2193 if (__mcheck_cpu_ancient_init(c))
2196 if (!mce_available(c))
2199 __mcheck_cpu_cap_init();
2201 if (__mcheck_cpu_apply_quirks(c) < 0) {
2202 mca_cfg.disabled = 1;
2206 if (mce_gen_pool_init()) {
2207 mca_cfg.disabled = 1;
2208 pr_emerg("Couldn't allocate MCE records pool!\n");
2212 mca_cfg.initialized = 1;
2214 __mcheck_cpu_init_early(c);
2215 __mcheck_cpu_init_generic();
2216 __mcheck_cpu_init_vendor(c);
2217 __mcheck_cpu_init_clear_banks();
2218 __mcheck_cpu_check_banks();
2219 __mcheck_cpu_setup_timer();
2223 * Called for each booted CPU to clear some machine checks opt-ins
2225 void mcheck_cpu_clear(struct cpuinfo_x86 *c)
2227 if (mca_cfg.disabled)
2230 if (!mce_available(c))
2234 * Possibly to clear general settings generic to x86
2235 * __mcheck_cpu_clear_generic(c);
2237 __mcheck_cpu_clear_vendor(c);
2241 static void __mce_disable_bank(void *arg)
2243 int bank = *((int *)arg);
2244 __clear_bit(bank, this_cpu_ptr(mce_poll_banks));
2245 cmci_disable_bank(bank);
2248 void mce_disable_bank(int bank)
2250 if (bank >= this_cpu_read(mce_num_banks)) {
2252 "Ignoring request to disable invalid MCA bank %d.\n",
2256 set_bit(bank, mce_banks_ce_disabled);
2257 on_each_cpu(__mce_disable_bank, &bank, 1);
2261 * mce=off Disables machine check
2262 * mce=no_cmci Disables CMCI
2263 * mce=no_lmce Disables LMCE
2264 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
2265 * mce=print_all Print all machine check logs to console
2266 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
2267 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
2268 * monarchtimeout is how long to wait for other CPUs on machine
2269 * check, or 0 to not wait
2270 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD Fam10h
2272 * mce=nobootlog Don't log MCEs from before booting.
2273 * mce=bios_cmci_threshold Don't program the CMCI threshold
2274 * mce=recovery force enable copy_mc_fragile()
2276 static int __init mcheck_enable(char *str)
2278 struct mca_config *cfg = &mca_cfg;
2286 if (!strcmp(str, "off"))
2288 else if (!strcmp(str, "no_cmci"))
2289 cfg->cmci_disabled = true;
2290 else if (!strcmp(str, "no_lmce"))
2291 cfg->lmce_disabled = 1;
2292 else if (!strcmp(str, "dont_log_ce"))
2293 cfg->dont_log_ce = true;
2294 else if (!strcmp(str, "print_all"))
2295 cfg->print_all = true;
2296 else if (!strcmp(str, "ignore_ce"))
2297 cfg->ignore_ce = true;
2298 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
2299 cfg->bootlog = (str[0] == 'b');
2300 else if (!strcmp(str, "bios_cmci_threshold"))
2301 cfg->bios_cmci_threshold = 1;
2302 else if (!strcmp(str, "recovery"))
2304 else if (isdigit(str[0]))
2305 get_option(&str, &(cfg->monarch_timeout));
2307 pr_info("mce argument %s ignored. Please use /sys\n", str);
2312 __setup("mce", mcheck_enable);
2314 int __init mcheck_init(void)
2316 mce_register_decode_chain(&early_nb);
2317 mce_register_decode_chain(&mce_uc_nb);
2318 mce_register_decode_chain(&mce_default_nb);
2320 INIT_WORK(&mce_work, mce_gen_pool_process);
2321 init_irq_work(&mce_irq_work, mce_irq_work_cb);
2327 * mce_syscore: PM support
2331 * Disable machine checks on suspend and shutdown. We can't really handle
2334 static void mce_disable_error_reporting(void)
2336 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
2339 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
2340 struct mce_bank *b = &mce_banks[i];
2343 wrmsrl(mca_msr_reg(i, MCA_CTL), 0);
2348 static void vendor_disable_error_reporting(void)
2351 * Don't clear on Intel or AMD or Hygon or Zhaoxin CPUs. Some of these
2352 * MSRs are socket-wide. Disabling them for just a single offlined CPU
2353 * is bad, since it will inhibit reporting for all shared resources on
2354 * the socket like the last level cache (LLC), the integrated memory
2355 * controller (iMC), etc.
2357 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL ||
2358 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON ||
2359 boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
2360 boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN)
2363 mce_disable_error_reporting();
2366 static int mce_syscore_suspend(void)
2368 vendor_disable_error_reporting();
2372 static void mce_syscore_shutdown(void)
2374 vendor_disable_error_reporting();
2378 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
2379 * Only one CPU is active at this time, the others get re-added later using
2382 static void mce_syscore_resume(void)
2384 __mcheck_cpu_init_generic();
2385 __mcheck_cpu_init_vendor(raw_cpu_ptr(&cpu_info));
2386 __mcheck_cpu_init_clear_banks();
2389 static struct syscore_ops mce_syscore_ops = {
2390 .suspend = mce_syscore_suspend,
2391 .shutdown = mce_syscore_shutdown,
2392 .resume = mce_syscore_resume,
2396 * mce_device: Sysfs support
2399 static void mce_cpu_restart(void *data)
2401 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2403 __mcheck_cpu_init_generic();
2404 __mcheck_cpu_init_clear_banks();
2405 __mcheck_cpu_init_timer();
2408 /* Reinit MCEs after user configuration changes */
2409 static void mce_restart(void)
2411 mce_timer_delete_all();
2412 on_each_cpu(mce_cpu_restart, NULL, 1);
2413 mce_schedule_work();
2416 /* Toggle features for corrected errors */
2417 static void mce_disable_cmci(void *data)
2419 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2424 static void mce_enable_ce(void *all)
2426 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2431 __mcheck_cpu_init_timer();
2434 static struct bus_type mce_subsys = {
2435 .name = "machinecheck",
2436 .dev_name = "machinecheck",
2439 DEFINE_PER_CPU(struct device *, mce_device);
2441 static inline struct mce_bank_dev *attr_to_bank(struct device_attribute *attr)
2443 return container_of(attr, struct mce_bank_dev, attr);
2446 static ssize_t show_bank(struct device *s, struct device_attribute *attr,
2449 u8 bank = attr_to_bank(attr)->bank;
2452 if (bank >= per_cpu(mce_num_banks, s->id))
2455 b = &per_cpu(mce_banks_array, s->id)[bank];
2460 return sprintf(buf, "%llx\n", b->ctl);
2463 static ssize_t set_bank(struct device *s, struct device_attribute *attr,
2464 const char *buf, size_t size)
2466 u8 bank = attr_to_bank(attr)->bank;
2470 if (kstrtou64(buf, 0, &new) < 0)
2473 if (bank >= per_cpu(mce_num_banks, s->id))
2476 b = &per_cpu(mce_banks_array, s->id)[bank];
2487 static ssize_t set_ignore_ce(struct device *s,
2488 struct device_attribute *attr,
2489 const char *buf, size_t size)
2493 if (kstrtou64(buf, 0, &new) < 0)
2496 mutex_lock(&mce_sysfs_mutex);
2497 if (mca_cfg.ignore_ce ^ !!new) {
2499 /* disable ce features */
2500 mce_timer_delete_all();
2501 on_each_cpu(mce_disable_cmci, NULL, 1);
2502 mca_cfg.ignore_ce = true;
2504 /* enable ce features */
2505 mca_cfg.ignore_ce = false;
2506 on_each_cpu(mce_enable_ce, (void *)1, 1);
2509 mutex_unlock(&mce_sysfs_mutex);
2514 static ssize_t set_cmci_disabled(struct device *s,
2515 struct device_attribute *attr,
2516 const char *buf, size_t size)
2520 if (kstrtou64(buf, 0, &new) < 0)
2523 mutex_lock(&mce_sysfs_mutex);
2524 if (mca_cfg.cmci_disabled ^ !!new) {
2527 on_each_cpu(mce_disable_cmci, NULL, 1);
2528 mca_cfg.cmci_disabled = true;
2531 mca_cfg.cmci_disabled = false;
2532 on_each_cpu(mce_enable_ce, NULL, 1);
2535 mutex_unlock(&mce_sysfs_mutex);
2540 static ssize_t store_int_with_restart(struct device *s,
2541 struct device_attribute *attr,
2542 const char *buf, size_t size)
2544 unsigned long old_check_interval = check_interval;
2545 ssize_t ret = device_store_ulong(s, attr, buf, size);
2547 if (check_interval == old_check_interval)
2550 mutex_lock(&mce_sysfs_mutex);
2552 mutex_unlock(&mce_sysfs_mutex);
2557 static DEVICE_INT_ATTR(monarch_timeout, 0644, mca_cfg.monarch_timeout);
2558 static DEVICE_BOOL_ATTR(dont_log_ce, 0644, mca_cfg.dont_log_ce);
2559 static DEVICE_BOOL_ATTR(print_all, 0644, mca_cfg.print_all);
2561 static struct dev_ext_attribute dev_attr_check_interval = {
2562 __ATTR(check_interval, 0644, device_show_int, store_int_with_restart),
2566 static struct dev_ext_attribute dev_attr_ignore_ce = {
2567 __ATTR(ignore_ce, 0644, device_show_bool, set_ignore_ce),
2571 static struct dev_ext_attribute dev_attr_cmci_disabled = {
2572 __ATTR(cmci_disabled, 0644, device_show_bool, set_cmci_disabled),
2573 &mca_cfg.cmci_disabled
2576 static struct device_attribute *mce_device_attrs[] = {
2577 &dev_attr_check_interval.attr,
2578 #ifdef CONFIG_X86_MCELOG_LEGACY
2581 &dev_attr_monarch_timeout.attr,
2582 &dev_attr_dont_log_ce.attr,
2583 &dev_attr_print_all.attr,
2584 &dev_attr_ignore_ce.attr,
2585 &dev_attr_cmci_disabled.attr,
2589 static cpumask_var_t mce_device_initialized;
2591 static void mce_device_release(struct device *dev)
2596 /* Per CPU device init. All of the CPUs still share the same bank device: */
2597 static int mce_device_create(unsigned int cpu)
2603 dev = per_cpu(mce_device, cpu);
2607 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
2611 dev->bus = &mce_subsys;
2612 dev->release = &mce_device_release;
2614 err = device_register(dev);
2620 for (i = 0; mce_device_attrs[i]; i++) {
2621 err = device_create_file(dev, mce_device_attrs[i]);
2625 for (j = 0; j < per_cpu(mce_num_banks, cpu); j++) {
2626 err = device_create_file(dev, &mce_bank_devs[j].attr);
2630 cpumask_set_cpu(cpu, mce_device_initialized);
2631 per_cpu(mce_device, cpu) = dev;
2636 device_remove_file(dev, &mce_bank_devs[j].attr);
2639 device_remove_file(dev, mce_device_attrs[i]);
2641 device_unregister(dev);
2646 static void mce_device_remove(unsigned int cpu)
2648 struct device *dev = per_cpu(mce_device, cpu);
2651 if (!cpumask_test_cpu(cpu, mce_device_initialized))
2654 for (i = 0; mce_device_attrs[i]; i++)
2655 device_remove_file(dev, mce_device_attrs[i]);
2657 for (i = 0; i < per_cpu(mce_num_banks, cpu); i++)
2658 device_remove_file(dev, &mce_bank_devs[i].attr);
2660 device_unregister(dev);
2661 cpumask_clear_cpu(cpu, mce_device_initialized);
2662 per_cpu(mce_device, cpu) = NULL;
2665 /* Make sure there are no machine checks on offlined CPUs. */
2666 static void mce_disable_cpu(void)
2668 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2671 if (!cpuhp_tasks_frozen)
2674 vendor_disable_error_reporting();
2677 static void mce_reenable_cpu(void)
2679 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
2682 if (!mce_available(raw_cpu_ptr(&cpu_info)))
2685 if (!cpuhp_tasks_frozen)
2687 for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
2688 struct mce_bank *b = &mce_banks[i];
2691 wrmsrl(mca_msr_reg(i, MCA_CTL), b->ctl);
2695 static int mce_cpu_dead(unsigned int cpu)
2697 /* intentionally ignoring frozen here */
2698 if (!cpuhp_tasks_frozen)
2703 static int mce_cpu_online(unsigned int cpu)
2705 struct timer_list *t = this_cpu_ptr(&mce_timer);
2708 mce_device_create(cpu);
2710 ret = mce_threshold_create_device(cpu);
2712 mce_device_remove(cpu);
2720 static int mce_cpu_pre_down(unsigned int cpu)
2722 struct timer_list *t = this_cpu_ptr(&mce_timer);
2726 mce_threshold_remove_device(cpu);
2727 mce_device_remove(cpu);
2731 static __init void mce_init_banks(void)
2735 for (i = 0; i < MAX_NR_BANKS; i++) {
2736 struct mce_bank_dev *b = &mce_bank_devs[i];
2737 struct device_attribute *a = &b->attr;
2741 sysfs_attr_init(&a->attr);
2742 a->attr.name = b->attrname;
2743 snprintf(b->attrname, ATTR_LEN, "bank%d", i);
2745 a->attr.mode = 0644;
2746 a->show = show_bank;
2747 a->store = set_bank;
2752 * When running on XEN, this initcall is ordered against the XEN mcelog
2755 * device_initcall(xen_late_init_mcelog);
2756 * device_initcall_sync(mcheck_init_device);
2758 static __init int mcheck_init_device(void)
2763 * Check if we have a spare virtual bit. This will only become
2764 * a problem if/when we move beyond 5-level page tables.
2766 MAYBE_BUILD_BUG_ON(__VIRTUAL_MASK_SHIFT >= 63);
2768 if (!mce_available(&boot_cpu_data)) {
2773 if (!zalloc_cpumask_var(&mce_device_initialized, GFP_KERNEL)) {
2780 err = subsys_system_register(&mce_subsys, NULL);
2784 err = cpuhp_setup_state(CPUHP_X86_MCE_DEAD, "x86/mce:dead", NULL,
2790 * Invokes mce_cpu_online() on all CPUs which are online when
2791 * the state is installed.
2793 err = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "x86/mce:online",
2794 mce_cpu_online, mce_cpu_pre_down);
2796 goto err_out_online;
2798 register_syscore_ops(&mce_syscore_ops);
2803 cpuhp_remove_state(CPUHP_X86_MCE_DEAD);
2806 free_cpumask_var(mce_device_initialized);
2809 pr_err("Unable to init MCE device (rc: %d)\n", err);
2813 device_initcall_sync(mcheck_init_device);
2816 * Old style boot options parsing. Only for compatibility.
2818 static int __init mcheck_disable(char *str)
2820 mca_cfg.disabled = 1;
2823 __setup("nomce", mcheck_disable);
2825 #ifdef CONFIG_DEBUG_FS
2826 struct dentry *mce_get_debugfs_dir(void)
2828 static struct dentry *dmce;
2831 dmce = debugfs_create_dir("mce", NULL);
2836 static void mce_reset(void)
2838 atomic_set(&mce_fake_panicked, 0);
2839 atomic_set(&mce_executing, 0);
2840 atomic_set(&mce_callin, 0);
2841 atomic_set(&global_nwo, 0);
2842 cpumask_setall(&mce_missing_cpus);
2845 static int fake_panic_get(void *data, u64 *val)
2851 static int fake_panic_set(void *data, u64 val)
2858 DEFINE_DEBUGFS_ATTRIBUTE(fake_panic_fops, fake_panic_get, fake_panic_set,
2861 static void __init mcheck_debugfs_init(void)
2863 struct dentry *dmce;
2865 dmce = mce_get_debugfs_dir();
2866 debugfs_create_file_unsafe("fake_panic", 0444, dmce, NULL,
2870 static void __init mcheck_debugfs_init(void) { }
2873 static int __init mcheck_late_init(void)
2875 if (mca_cfg.recovery)
2876 enable_copy_mc_fragile();
2878 mcheck_debugfs_init();
2881 * Flush out everything that has been logged during early boot, now that
2882 * everything has been initialized (workqueues, decoders, ...).
2884 mce_schedule_work();
2888 late_initcall(mcheck_late_init);