arch/x86/include/asm/vmx.h

   1 /*
   2  * vmx.h: VMX Architecture related definitions
   3  * Copyright (c) 2004, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
  16  * Place - Suite 330, Boston, MA 02111-1307 USA.
  17  *
  18  * A few random additions are:
  19  * Copyright (C) 2006 Qumranet
  20  *    Avi Kivity <avi@qumranet.com>
  21  *    Yaniv Kamay <yaniv@qumranet.com>
  22  *
  23  */
  24 #ifndef VMX_H
  25 #define VMX_H
  26
  27
  28 #include <linux/bitops.h>
  29 #include <linux/types.h>
  30 #include <uapi/asm/vmx.h>
  31
  32 /*
  33  * Definitions of Primary Processor-Based VM-Execution Controls.
  34  */
  35 #define CPU_BASED_VIRTUAL_INTR_PENDING          0x00000004
  36 #define CPU_BASED_USE_TSC_OFFSETING             0x00000008
  37 #define CPU_BASED_HLT_EXITING                   0x00000080
  38 #define CPU_BASED_INVLPG_EXITING                0x00000200
  39 #define CPU_BASED_MWAIT_EXITING                 0x00000400
  40 #define CPU_BASED_RDPMC_EXITING                 0x00000800
  41 #define CPU_BASED_RDTSC_EXITING                 0x00001000
  42 #define CPU_BASED_CR3_LOAD_EXITING              0x00008000
  43 #define CPU_BASED_CR3_STORE_EXITING             0x00010000
  44 #define CPU_BASED_CR8_LOAD_EXITING              0x00080000
  45 #define CPU_BASED_CR8_STORE_EXITING             0x00100000
  46 #define CPU_BASED_TPR_SHADOW                    0x00200000
  47 #define CPU_BASED_VIRTUAL_NMI_PENDING           0x00400000
  48 #define CPU_BASED_MOV_DR_EXITING                0x00800000
  49 #define CPU_BASED_UNCOND_IO_EXITING             0x01000000
  50 #define CPU_BASED_USE_IO_BITMAPS                0x02000000
  51 #define CPU_BASED_MONITOR_TRAP_FLAG             0x08000000
  52 #define CPU_BASED_USE_MSR_BITMAPS               0x10000000
  53 #define CPU_BASED_MONITOR_EXITING               0x20000000
  54 #define CPU_BASED_PAUSE_EXITING                 0x40000000
  55 #define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS   0x80000000
  56
  57 #define CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR     0x0401e172
  58
  59 /*
  60  * Definitions of Secondary Processor-Based VM-Execution Controls.
  61  */
  62 #define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001
  63 #define SECONDARY_EXEC_ENABLE_EPT               0x00000002
  64 #define SECONDARY_EXEC_DESC                     0x00000004
  65 #define SECONDARY_EXEC_RDTSCP                   0x00000008
  66 #define SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE   0x00000010
  67 #define SECONDARY_EXEC_ENABLE_VPID              0x00000020
  68 #define SECONDARY_EXEC_WBINVD_EXITING           0x00000040
  69 #define SECONDARY_EXEC_UNRESTRICTED_GUEST       0x00000080
  70 #define SECONDARY_EXEC_APIC_REGISTER_VIRT       0x00000100
  71 #define SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY    0x00000200
  72 #define SECONDARY_EXEC_PAUSE_LOOP_EXITING       0x00000400
  73 #define SECONDARY_EXEC_RDRAND_EXITING           0x00000800
  74 #define SECONDARY_EXEC_ENABLE_INVPCID           0x00001000
  75 #define SECONDARY_EXEC_ENABLE_VMFUNC            0x00002000
  76 #define SECONDARY_EXEC_SHADOW_VMCS              0x00004000
  77 #define SECONDARY_EXEC_ENCLS_EXITING            0x00008000
  78 #define SECONDARY_EXEC_RDSEED_EXITING           0x00010000
  79 #define SECONDARY_EXEC_ENABLE_PML               0x00020000
  80 #define SECONDARY_EXEC_PT_CONCEAL_VMX           0x00080000
  81 #define SECONDARY_EXEC_XSAVES                   0x00100000
  82 #define SECONDARY_EXEC_PT_USE_GPA               0x01000000
  83 #define SECONDARY_EXEC_MODE_BASED_EPT_EXEC      0x00400000
  84 #define SECONDARY_EXEC_TSC_SCALING              0x02000000
  85
  86 #define PIN_BASED_EXT_INTR_MASK                 0x00000001
  87 #define PIN_BASED_NMI_EXITING                   0x00000008
  88 #define PIN_BASED_VIRTUAL_NMIS                  0x00000020
  89 #define PIN_BASED_VMX_PREEMPTION_TIMER          0x00000040
  90 #define PIN_BASED_POSTED_INTR                   0x00000080
  91
  92 #define PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR     0x00000016
  93
  94 #define VM_EXIT_SAVE_DEBUG_CONTROLS             0x00000004
  95 #define VM_EXIT_HOST_ADDR_SPACE_SIZE            0x00000200
  96 #define VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL      0x00001000
  97 #define VM_EXIT_ACK_INTR_ON_EXIT                0x00008000
  98 #define VM_EXIT_SAVE_IA32_PAT                   0x00040000
  99 #define VM_EXIT_LOAD_IA32_PAT                   0x00080000
 100 #define VM_EXIT_SAVE_IA32_EFER                  0x00100000
 101 #define VM_EXIT_LOAD_IA32_EFER                  0x00200000
 102 #define VM_EXIT_SAVE_VMX_PREEMPTION_TIMER       0x00400000
 103 #define VM_EXIT_CLEAR_BNDCFGS                   0x00800000
 104 #define VM_EXIT_PT_CONCEAL_PIP                  0x01000000
 105 #define VM_EXIT_CLEAR_IA32_RTIT_CTL             0x02000000
 106
 107 #define VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR       0x00036dff
 108
 109 #define VM_ENTRY_LOAD_DEBUG_CONTROLS            0x00000004
 110 #define VM_ENTRY_IA32E_MODE                     0x00000200
 111 #define VM_ENTRY_SMM                            0x00000400
 112 #define VM_ENTRY_DEACT_DUAL_MONITOR             0x00000800
 113 #define VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL     0x00002000
 114 #define VM_ENTRY_LOAD_IA32_PAT                  0x00004000
 115 #define VM_ENTRY_LOAD_IA32_EFER                 0x00008000
 116 #define VM_ENTRY_LOAD_BNDCFGS                   0x00010000
 117 #define VM_ENTRY_PT_CONCEAL_PIP                 0x00020000
 118 #define VM_ENTRY_LOAD_IA32_RTIT_CTL             0x00040000
 119
 120 #define VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR      0x000011ff
 121
 122 #define VMX_MISC_PREEMPTION_TIMER_RATE_MASK     0x0000001f
 123 #define VMX_MISC_SAVE_EFER_LMA                  0x00000020
 124 #define VMX_MISC_ACTIVITY_HLT                   0x00000040
 125 #define VMX_MISC_ZERO_LEN_INS                   0x40000000
 126
 127 /* VMFUNC functions */
 128 #define VMX_VMFUNC_EPTP_SWITCHING               0x00000001
 129 #define VMFUNC_EPTP_ENTRIES  512
 130
 131 static inline u32 vmx_basic_vmcs_revision_id(u64 vmx_basic)
 132 {
 133         return vmx_basic & GENMASK_ULL(30, 0);
 134 }
 135
 136 static inline u32 vmx_basic_vmcs_size(u64 vmx_basic)
 137 {
 138         return (vmx_basic & GENMASK_ULL(44, 32)) >> 32;
 139 }
 140
 141 static inline int vmx_misc_preemption_timer_rate(u64 vmx_misc)
 142 {
 143         return vmx_misc & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
 144 }
 145
 146 static inline int vmx_misc_cr3_count(u64 vmx_misc)
 147 {
 148         return (vmx_misc & GENMASK_ULL(24, 16)) >> 16;
 149 }
 150
 151 static inline int vmx_misc_max_msr(u64 vmx_misc)
 152 {
 153         return (vmx_misc & GENMASK_ULL(27, 25)) >> 25;
 154 }
 155
 156 static inline int vmx_misc_mseg_revid(u64 vmx_misc)
 157 {
 158         return (vmx_misc & GENMASK_ULL(63, 32)) >> 32;
 159 }
 160
 161 /* VMCS Encodings */
 162 enum vmcs_field {
 163         VIRTUAL_PROCESSOR_ID            = 0x00000000,
 164         POSTED_INTR_NV                  = 0x00000002,
 165         GUEST_ES_SELECTOR               = 0x00000800,
 166         GUEST_CS_SELECTOR               = 0x00000802,
 167         GUEST_SS_SELECTOR               = 0x00000804,
 168         GUEST_DS_SELECTOR               = 0x00000806,
 169         GUEST_FS_SELECTOR               = 0x00000808,
 170         GUEST_GS_SELECTOR               = 0x0000080a,
 171         GUEST_LDTR_SELECTOR             = 0x0000080c,
 172         GUEST_TR_SELECTOR               = 0x0000080e,
 173         GUEST_INTR_STATUS               = 0x00000810,
 174         GUEST_PML_INDEX                 = 0x00000812,
 175         HOST_ES_SELECTOR                = 0x00000c00,
 176         HOST_CS_SELECTOR                = 0x00000c02,
 177         HOST_SS_SELECTOR                = 0x00000c04,
 178         HOST_DS_SELECTOR                = 0x00000c06,
 179         HOST_FS_SELECTOR                = 0x00000c08,
 180         HOST_GS_SELECTOR                = 0x00000c0a,
 181         HOST_TR_SELECTOR                = 0x00000c0c,
 182         IO_BITMAP_A                     = 0x00002000,
 183         IO_BITMAP_A_HIGH                = 0x00002001,
 184         IO_BITMAP_B                     = 0x00002002,
 185         IO_BITMAP_B_HIGH                = 0x00002003,
 186         MSR_BITMAP                      = 0x00002004,
 187         MSR_BITMAP_HIGH                 = 0x00002005,
 188         VM_EXIT_MSR_STORE_ADDR          = 0x00002006,
 189         VM_EXIT_MSR_STORE_ADDR_HIGH     = 0x00002007,
 190         VM_EXIT_MSR_LOAD_ADDR           = 0x00002008,
 191         VM_EXIT_MSR_LOAD_ADDR_HIGH      = 0x00002009,
 192         VM_ENTRY_MSR_LOAD_ADDR          = 0x0000200a,
 193         VM_ENTRY_MSR_LOAD_ADDR_HIGH     = 0x0000200b,
 194         PML_ADDRESS                     = 0x0000200e,
 195         PML_ADDRESS_HIGH                = 0x0000200f,
 196         TSC_OFFSET                      = 0x00002010,
 197         TSC_OFFSET_HIGH                 = 0x00002011,
 198         VIRTUAL_APIC_PAGE_ADDR          = 0x00002012,
 199         VIRTUAL_APIC_PAGE_ADDR_HIGH     = 0x00002013,
 200         APIC_ACCESS_ADDR                = 0x00002014,
 201         APIC_ACCESS_ADDR_HIGH           = 0x00002015,
 202         POSTED_INTR_DESC_ADDR           = 0x00002016,
 203         POSTED_INTR_DESC_ADDR_HIGH      = 0x00002017,
 204         VM_FUNCTION_CONTROL             = 0x00002018,
 205         VM_FUNCTION_CONTROL_HIGH        = 0x00002019,
 206         EPT_POINTER                     = 0x0000201a,
 207         EPT_POINTER_HIGH                = 0x0000201b,
 208         EOI_EXIT_BITMAP0                = 0x0000201c,
 209         EOI_EXIT_BITMAP0_HIGH           = 0x0000201d,
 210         EOI_EXIT_BITMAP1                = 0x0000201e,
 211         EOI_EXIT_BITMAP1_HIGH           = 0x0000201f,
 212         EOI_EXIT_BITMAP2                = 0x00002020,
 213         EOI_EXIT_BITMAP2_HIGH           = 0x00002021,
 214         EOI_EXIT_BITMAP3                = 0x00002022,
 215         EOI_EXIT_BITMAP3_HIGH           = 0x00002023,
 216         EPTP_LIST_ADDRESS               = 0x00002024,
 217         EPTP_LIST_ADDRESS_HIGH          = 0x00002025,
 218         VMREAD_BITMAP                   = 0x00002026,
 219         VMREAD_BITMAP_HIGH              = 0x00002027,
 220         VMWRITE_BITMAP                  = 0x00002028,
 221         VMWRITE_BITMAP_HIGH             = 0x00002029,
 222         XSS_EXIT_BITMAP                 = 0x0000202C,
 223         XSS_EXIT_BITMAP_HIGH            = 0x0000202D,
 224         ENCLS_EXITING_BITMAP            = 0x0000202E,
 225         ENCLS_EXITING_BITMAP_HIGH       = 0x0000202F,
 226         TSC_MULTIPLIER                  = 0x00002032,
 227         TSC_MULTIPLIER_HIGH             = 0x00002033,
 228         GUEST_PHYSICAL_ADDRESS          = 0x00002400,
 229         GUEST_PHYSICAL_ADDRESS_HIGH     = 0x00002401,
 230         VMCS_LINK_POINTER               = 0x00002800,
 231         VMCS_LINK_POINTER_HIGH          = 0x00002801,
 232         GUEST_IA32_DEBUGCTL             = 0x00002802,
 233         GUEST_IA32_DEBUGCTL_HIGH        = 0x00002803,
 234         GUEST_IA32_PAT                  = 0x00002804,
 235         GUEST_IA32_PAT_HIGH             = 0x00002805,
 236         GUEST_IA32_EFER                 = 0x00002806,
 237         GUEST_IA32_EFER_HIGH            = 0x00002807,
 238         GUEST_IA32_PERF_GLOBAL_CTRL     = 0x00002808,
 239         GUEST_IA32_PERF_GLOBAL_CTRL_HIGH= 0x00002809,
 240         GUEST_PDPTR0                    = 0x0000280a,
 241         GUEST_PDPTR0_HIGH               = 0x0000280b,
 242         GUEST_PDPTR1                    = 0x0000280c,
 243         GUEST_PDPTR1_HIGH               = 0x0000280d,
 244         GUEST_PDPTR2                    = 0x0000280e,
 245         GUEST_PDPTR2_HIGH               = 0x0000280f,
 246         GUEST_PDPTR3                    = 0x00002810,
 247         GUEST_PDPTR3_HIGH               = 0x00002811,
 248         GUEST_BNDCFGS                   = 0x00002812,
 249         GUEST_BNDCFGS_HIGH              = 0x00002813,
 250         GUEST_IA32_RTIT_CTL             = 0x00002814,
 251         GUEST_IA32_RTIT_CTL_HIGH        = 0x00002815,
 252         HOST_IA32_PAT                   = 0x00002c00,
 253         HOST_IA32_PAT_HIGH              = 0x00002c01,
 254         HOST_IA32_EFER                  = 0x00002c02,
 255         HOST_IA32_EFER_HIGH             = 0x00002c03,
 256         HOST_IA32_PERF_GLOBAL_CTRL      = 0x00002c04,
 257         HOST_IA32_PERF_GLOBAL_CTRL_HIGH = 0x00002c05,
 258         PIN_BASED_VM_EXEC_CONTROL       = 0x00004000,
 259         CPU_BASED_VM_EXEC_CONTROL       = 0x00004002,
 260         EXCEPTION_BITMAP                = 0x00004004,
 261         PAGE_FAULT_ERROR_CODE_MASK      = 0x00004006,
 262         PAGE_FAULT_ERROR_CODE_MATCH     = 0x00004008,
 263         CR3_TARGET_COUNT                = 0x0000400a,
 264         VM_EXIT_CONTROLS                = 0x0000400c,
 265         VM_EXIT_MSR_STORE_COUNT         = 0x0000400e,
 266         VM_EXIT_MSR_LOAD_COUNT          = 0x00004010,
 267         VM_ENTRY_CONTROLS               = 0x00004012,
 268         VM_ENTRY_MSR_LOAD_COUNT         = 0x00004014,
 269         VM_ENTRY_INTR_INFO_FIELD        = 0x00004016,
 270         VM_ENTRY_EXCEPTION_ERROR_CODE   = 0x00004018,
 271         VM_ENTRY_INSTRUCTION_LEN        = 0x0000401a,
 272         TPR_THRESHOLD                   = 0x0000401c,
 273         SECONDARY_VM_EXEC_CONTROL       = 0x0000401e,
 274         PLE_GAP                         = 0x00004020,
 275         PLE_WINDOW                      = 0x00004022,
 276         VM_INSTRUCTION_ERROR            = 0x00004400,
 277         VM_EXIT_REASON                  = 0x00004402,
 278         VM_EXIT_INTR_INFO               = 0x00004404,
 279         VM_EXIT_INTR_ERROR_CODE         = 0x00004406,
 280         IDT_VECTORING_INFO_FIELD        = 0x00004408,
 281         IDT_VECTORING_ERROR_CODE        = 0x0000440a,
 282         VM_EXIT_INSTRUCTION_LEN         = 0x0000440c,
 283         VMX_INSTRUCTION_INFO            = 0x0000440e,
 284         GUEST_ES_LIMIT                  = 0x00004800,
 285         GUEST_CS_LIMIT                  = 0x00004802,
 286         GUEST_SS_LIMIT                  = 0x00004804,
 287         GUEST_DS_LIMIT                  = 0x00004806,
 288         GUEST_FS_LIMIT                  = 0x00004808,
 289         GUEST_GS_LIMIT                  = 0x0000480a,
 290         GUEST_LDTR_LIMIT                = 0x0000480c,
 291         GUEST_TR_LIMIT                  = 0x0000480e,
 292         GUEST_GDTR_LIMIT                = 0x00004810,
 293         GUEST_IDTR_LIMIT                = 0x00004812,
 294         GUEST_ES_AR_BYTES               = 0x00004814,
 295         GUEST_CS_AR_BYTES               = 0x00004816,
 296         GUEST_SS_AR_BYTES               = 0x00004818,
 297         GUEST_DS_AR_BYTES               = 0x0000481a,
 298         GUEST_FS_AR_BYTES               = 0x0000481c,
 299         GUEST_GS_AR_BYTES               = 0x0000481e,
 300         GUEST_LDTR_AR_BYTES             = 0x00004820,
 301         GUEST_TR_AR_BYTES               = 0x00004822,
 302         GUEST_INTERRUPTIBILITY_INFO     = 0x00004824,
 303         GUEST_ACTIVITY_STATE            = 0X00004826,
 304         GUEST_SYSENTER_CS               = 0x0000482A,
 305         VMX_PREEMPTION_TIMER_VALUE      = 0x0000482E,
 306         HOST_IA32_SYSENTER_CS           = 0x00004c00,
 307         CR0_GUEST_HOST_MASK             = 0x00006000,
 308         CR4_GUEST_HOST_MASK             = 0x00006002,
 309         CR0_READ_SHADOW                 = 0x00006004,
 310         CR4_READ_SHADOW                 = 0x00006006,
 311         CR3_TARGET_VALUE0               = 0x00006008,
 312         CR3_TARGET_VALUE1               = 0x0000600a,
 313         CR3_TARGET_VALUE2               = 0x0000600c,
 314         CR3_TARGET_VALUE3               = 0x0000600e,
 315         EXIT_QUALIFICATION              = 0x00006400,
 316         GUEST_LINEAR_ADDRESS            = 0x0000640a,
 317         GUEST_CR0                       = 0x00006800,
 318         GUEST_CR3                       = 0x00006802,
 319         GUEST_CR4                       = 0x00006804,
 320         GUEST_ES_BASE                   = 0x00006806,
 321         GUEST_CS_BASE                   = 0x00006808,
 322         GUEST_SS_BASE                   = 0x0000680a,
 323         GUEST_DS_BASE                   = 0x0000680c,
 324         GUEST_FS_BASE                   = 0x0000680e,
 325         GUEST_GS_BASE                   = 0x00006810,
 326         GUEST_LDTR_BASE                 = 0x00006812,
 327         GUEST_TR_BASE                   = 0x00006814,
 328         GUEST_GDTR_BASE                 = 0x00006816,
 329         GUEST_IDTR_BASE                 = 0x00006818,
 330         GUEST_DR7                       = 0x0000681a,
 331         GUEST_RSP                       = 0x0000681c,
 332         GUEST_RIP                       = 0x0000681e,
 333         GUEST_RFLAGS                    = 0x00006820,
 334         GUEST_PENDING_DBG_EXCEPTIONS    = 0x00006822,
 335         GUEST_SYSENTER_ESP              = 0x00006824,
 336         GUEST_SYSENTER_EIP              = 0x00006826,
 337         HOST_CR0                        = 0x00006c00,
 338         HOST_CR3                        = 0x00006c02,
 339         HOST_CR4                        = 0x00006c04,
 340         HOST_FS_BASE                    = 0x00006c06,
 341         HOST_GS_BASE                    = 0x00006c08,
 342         HOST_TR_BASE                    = 0x00006c0a,
 343         HOST_GDTR_BASE                  = 0x00006c0c,
 344         HOST_IDTR_BASE                  = 0x00006c0e,
 345         HOST_IA32_SYSENTER_ESP          = 0x00006c10,
 346         HOST_IA32_SYSENTER_EIP          = 0x00006c12,
 347         HOST_RSP                        = 0x00006c14,
 348         HOST_RIP                        = 0x00006c16,
 349 };
 350
 351 /*
 352  * Interruption-information format
 353  */
 354 #define INTR_INFO_VECTOR_MASK           0xff            /* 7:0 */
 355 #define INTR_INFO_INTR_TYPE_MASK        0x700           /* 10:8 */
 356 #define INTR_INFO_DELIVER_CODE_MASK     0x800           /* 11 */
 357 #define INTR_INFO_UNBLOCK_NMI           0x1000          /* 12 */
 358 #define INTR_INFO_VALID_MASK            0x80000000      /* 31 */
 359 #define INTR_INFO_RESVD_BITS_MASK       0x7ffff000
 360
 361 #define VECTORING_INFO_VECTOR_MASK              INTR_INFO_VECTOR_MASK
 362 #define VECTORING_INFO_TYPE_MASK                INTR_INFO_INTR_TYPE_MASK
 363 #define VECTORING_INFO_DELIVER_CODE_MASK        INTR_INFO_DELIVER_CODE_MASK
 364 #define VECTORING_INFO_VALID_MASK               INTR_INFO_VALID_MASK
 365
 366 #define INTR_TYPE_EXT_INTR              (0 << 8) /* external interrupt */
 367 #define INTR_TYPE_RESERVED              (1 << 8) /* reserved */
 368 #define INTR_TYPE_NMI_INTR              (2 << 8) /* NMI */
 369 #define INTR_TYPE_HARD_EXCEPTION        (3 << 8) /* processor exception */
 370 #define INTR_TYPE_SOFT_INTR             (4 << 8) /* software interrupt */
 371 #define INTR_TYPE_PRIV_SW_EXCEPTION     (5 << 8) /* ICE breakpoint - undocumented */
 372 #define INTR_TYPE_SOFT_EXCEPTION        (6 << 8) /* software exception */
 373 #define INTR_TYPE_OTHER_EVENT           (7 << 8) /* other event */
 374
 375 /* GUEST_INTERRUPTIBILITY_INFO flags. */
 376 #define GUEST_INTR_STATE_STI            0x00000001
 377 #define GUEST_INTR_STATE_MOV_SS         0x00000002
 378 #define GUEST_INTR_STATE_SMI            0x00000004
 379 #define GUEST_INTR_STATE_NMI            0x00000008
 380
 381 /* GUEST_ACTIVITY_STATE flags */
 382 #define GUEST_ACTIVITY_ACTIVE           0
 383 #define GUEST_ACTIVITY_HLT              1
 384 #define GUEST_ACTIVITY_SHUTDOWN         2
 385 #define GUEST_ACTIVITY_WAIT_SIPI        3
 386
 387 /*
 388  * Exit Qualifications for MOV for Control Register Access
 389  */
 390 #define CONTROL_REG_ACCESS_NUM          0x7     /* 2:0, number of control reg.*/
 391 #define CONTROL_REG_ACCESS_TYPE         0x30    /* 5:4, access type */
 392 #define CONTROL_REG_ACCESS_REG          0xf00   /* 10:8, general purpose reg. */
 393 #define LMSW_SOURCE_DATA_SHIFT 16
 394 #define LMSW_SOURCE_DATA  (0xFFFF << LMSW_SOURCE_DATA_SHIFT) /* 16:31 lmsw source */
 395 #define REG_EAX                         (0 << 8)
 396 #define REG_ECX                         (1 << 8)
 397 #define REG_EDX                         (2 << 8)
 398 #define REG_EBX                         (3 << 8)
 399 #define REG_ESP                         (4 << 8)
 400 #define REG_EBP                         (5 << 8)
 401 #define REG_ESI                         (6 << 8)
 402 #define REG_EDI                         (7 << 8)
 403 #define REG_R8                         (8 << 8)
 404 #define REG_R9                         (9 << 8)
 405 #define REG_R10                        (10 << 8)
 406 #define REG_R11                        (11 << 8)
 407 #define REG_R12                        (12 << 8)
 408 #define REG_R13                        (13 << 8)
 409 #define REG_R14                        (14 << 8)
 410 #define REG_R15                        (15 << 8)
 411
 412 /*
 413  * Exit Qualifications for MOV for Debug Register Access
 414  */
 415 #define DEBUG_REG_ACCESS_NUM            0x7     /* 2:0, number of debug reg. */
 416 #define DEBUG_REG_ACCESS_TYPE           0x10    /* 4, direction of access */
 417 #define TYPE_MOV_TO_DR                  (0 << 4)
 418 #define TYPE_MOV_FROM_DR                (1 << 4)
 419 #define DEBUG_REG_ACCESS_REG(eq)        (((eq) >> 8) & 0xf) /* 11:8, general purpose reg. */
 420
 421
 422 /*
 423  * Exit Qualifications for APIC-Access
 424  */
 425 #define APIC_ACCESS_OFFSET              0xfff   /* 11:0, offset within the APIC page */
 426 #define APIC_ACCESS_TYPE                0xf000  /* 15:12, access type */
 427 #define TYPE_LINEAR_APIC_INST_READ      (0 << 12)
 428 #define TYPE_LINEAR_APIC_INST_WRITE     (1 << 12)
 429 #define TYPE_LINEAR_APIC_INST_FETCH     (2 << 12)
 430 #define TYPE_LINEAR_APIC_EVENT          (3 << 12)
 431 #define TYPE_PHYSICAL_APIC_EVENT        (10 << 12)
 432 #define TYPE_PHYSICAL_APIC_INST         (15 << 12)
 433
 434 /* segment AR in VMCS -- these are different from what LAR reports */
 435 #define VMX_SEGMENT_AR_L_MASK (1 << 13)
 436
 437 #define VMX_AR_TYPE_ACCESSES_MASK 1
 438 #define VMX_AR_TYPE_READABLE_MASK (1 << 1)
 439 #define VMX_AR_TYPE_WRITEABLE_MASK (1 << 2)
 440 #define VMX_AR_TYPE_CODE_MASK (1 << 3)
 441 #define VMX_AR_TYPE_MASK 0x0f
 442 #define VMX_AR_TYPE_BUSY_64_TSS 11
 443 #define VMX_AR_TYPE_BUSY_32_TSS 11
 444 #define VMX_AR_TYPE_BUSY_16_TSS 3
 445 #define VMX_AR_TYPE_LDT 2
 446
 447 #define VMX_AR_UNUSABLE_MASK (1 << 16)
 448 #define VMX_AR_S_MASK (1 << 4)
 449 #define VMX_AR_P_MASK (1 << 7)
 450 #define VMX_AR_L_MASK (1 << 13)
 451 #define VMX_AR_DB_MASK (1 << 14)
 452 #define VMX_AR_G_MASK (1 << 15)
 453 #define VMX_AR_DPL_SHIFT 5
 454 #define VMX_AR_DPL(ar) (((ar) >> VMX_AR_DPL_SHIFT) & 3)
 455
 456 #define VMX_AR_RESERVD_MASK 0xfffe0f00
 457
 458 #define TSS_PRIVATE_MEMSLOT                     (KVM_USER_MEM_SLOTS + 0)
 459 #define APIC_ACCESS_PAGE_PRIVATE_MEMSLOT        (KVM_USER_MEM_SLOTS + 1)
 460 #define IDENTITY_PAGETABLE_PRIVATE_MEMSLOT      (KVM_USER_MEM_SLOTS + 2)
 461
 462 #define VMX_NR_VPIDS                            (1 << 16)
 463 #define VMX_VPID_EXTENT_INDIVIDUAL_ADDR         0
 464 #define VMX_VPID_EXTENT_SINGLE_CONTEXT          1
 465 #define VMX_VPID_EXTENT_ALL_CONTEXT             2
 466 #define VMX_VPID_EXTENT_SINGLE_NON_GLOBAL       3
 467
 468 #define VMX_EPT_EXTENT_CONTEXT                  1
 469 #define VMX_EPT_EXTENT_GLOBAL                   2
 470 #define VMX_EPT_EXTENT_SHIFT                    24
 471
 472 #define VMX_EPT_EXECUTE_ONLY_BIT                (1ull)
 473 #define VMX_EPT_PAGE_WALK_4_BIT                 (1ull << 6)
 474 #define VMX_EPT_PAGE_WALK_5_BIT                 (1ull << 7)
 475 #define VMX_EPTP_UC_BIT                         (1ull << 8)
 476 #define VMX_EPTP_WB_BIT                         (1ull << 14)
 477 #define VMX_EPT_2MB_PAGE_BIT                    (1ull << 16)
 478 #define VMX_EPT_1GB_PAGE_BIT                    (1ull << 17)
 479 #define VMX_EPT_INVEPT_BIT                      (1ull << 20)
 480 #define VMX_EPT_AD_BIT                              (1ull << 21)
 481 #define VMX_EPT_EXTENT_CONTEXT_BIT              (1ull << 25)
 482 #define VMX_EPT_EXTENT_GLOBAL_BIT               (1ull << 26)
 483
 484 #define VMX_VPID_INVVPID_BIT                    (1ull << 0) /* (32 - 32) */
 485 #define VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT     (1ull << 8) /* (40 - 32) */
 486 #define VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT      (1ull << 9) /* (41 - 32) */
 487 #define VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT      (1ull << 10) /* (42 - 32) */
 488 #define VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT   (1ull << 11) /* (43 - 32) */
 489
 490 #define VMX_EPT_MT_EPTE_SHIFT                   3
 491 #define VMX_EPTP_PWL_MASK                       0x38ull
 492 #define VMX_EPTP_PWL_4                          0x18ull
 493 #define VMX_EPTP_PWL_5                          0x20ull
 494 #define VMX_EPTP_AD_ENABLE_BIT                  (1ull << 6)
 495 #define VMX_EPTP_MT_MASK                        0x7ull
 496 #define VMX_EPTP_MT_WB                          0x6ull
 497 #define VMX_EPTP_MT_UC                          0x0ull
 498 #define VMX_EPT_READABLE_MASK                   0x1ull
 499 #define VMX_EPT_WRITABLE_MASK                   0x2ull
 500 #define VMX_EPT_EXECUTABLE_MASK                 0x4ull
 501 #define VMX_EPT_IPAT_BIT                        (1ull << 6)
 502 #define VMX_EPT_ACCESS_BIT                      (1ull << 8)
 503 #define VMX_EPT_DIRTY_BIT                       (1ull << 9)
 504 #define VMX_EPT_RWX_MASK                        (VMX_EPT_READABLE_MASK |       \
 505                                                  VMX_EPT_WRITABLE_MASK |       \
 506                                                  VMX_EPT_EXECUTABLE_MASK)
 507 #define VMX_EPT_MT_MASK                         (7ull << VMX_EPT_MT_EPTE_SHIFT)
 508
 509 /* The mask to use to trigger an EPT Misconfiguration in order to track MMIO */
 510 #define VMX_EPT_MISCONFIG_WX_VALUE              (VMX_EPT_WRITABLE_MASK |       \
 511                                                  VMX_EPT_EXECUTABLE_MASK)
 512
 513 #define VMX_EPT_IDENTITY_PAGETABLE_ADDR         0xfffbc000ul
 514
 515 struct vmx_msr_entry {
 516         u32 index;
 517         u32 reserved;
 518         u64 value;
 519 } __aligned(16);
 520
 521 /*
 522  * Exit Qualifications for entry failure during or after loading guest state
 523  */
 524 #define ENTRY_FAIL_DEFAULT              0
 525 #define ENTRY_FAIL_PDPTE                2
 526 #define ENTRY_FAIL_NMI                  3
 527 #define ENTRY_FAIL_VMCS_LINK_PTR        4
 528
 529 /*
 530  * Exit Qualifications for EPT Violations
 531  */
 532 #define EPT_VIOLATION_ACC_READ_BIT      0
 533 #define EPT_VIOLATION_ACC_WRITE_BIT     1
 534 #define EPT_VIOLATION_ACC_INSTR_BIT     2
 535 #define EPT_VIOLATION_READABLE_BIT      3
 536 #define EPT_VIOLATION_WRITABLE_BIT      4
 537 #define EPT_VIOLATION_EXECUTABLE_BIT    5
 538 #define EPT_VIOLATION_GVA_TRANSLATED_BIT 8
 539 #define EPT_VIOLATION_ACC_READ          (1 << EPT_VIOLATION_ACC_READ_BIT)
 540 #define EPT_VIOLATION_ACC_WRITE         (1 << EPT_VIOLATION_ACC_WRITE_BIT)
 541 #define EPT_VIOLATION_ACC_INSTR         (1 << EPT_VIOLATION_ACC_INSTR_BIT)
 542 #define EPT_VIOLATION_READABLE          (1 << EPT_VIOLATION_READABLE_BIT)
 543 #define EPT_VIOLATION_WRITABLE          (1 << EPT_VIOLATION_WRITABLE_BIT)
 544 #define EPT_VIOLATION_EXECUTABLE        (1 << EPT_VIOLATION_EXECUTABLE_BIT)
 545 #define EPT_VIOLATION_GVA_TRANSLATED    (1 << EPT_VIOLATION_GVA_TRANSLATED_BIT)
 546
 547 /*
 548  * VM-instruction error numbers
 549  */
 550 enum vm_instruction_error_number {
 551         VMXERR_VMCALL_IN_VMX_ROOT_OPERATION = 1,
 552         VMXERR_VMCLEAR_INVALID_ADDRESS = 2,
 553         VMXERR_VMCLEAR_VMXON_POINTER = 3,
 554         VMXERR_VMLAUNCH_NONCLEAR_VMCS = 4,
 555         VMXERR_VMRESUME_NONLAUNCHED_VMCS = 5,
 556         VMXERR_VMRESUME_AFTER_VMXOFF = 6,
 557         VMXERR_ENTRY_INVALID_CONTROL_FIELD = 7,
 558         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD = 8,
 559         VMXERR_VMPTRLD_INVALID_ADDRESS = 9,
 560         VMXERR_VMPTRLD_VMXON_POINTER = 10,
 561         VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID = 11,
 562         VMXERR_UNSUPPORTED_VMCS_COMPONENT = 12,
 563         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT = 13,
 564         VMXERR_VMXON_IN_VMX_ROOT_OPERATION = 15,
 565         VMXERR_ENTRY_INVALID_EXECUTIVE_VMCS_POINTER = 16,
 566         VMXERR_ENTRY_NONLAUNCHED_EXECUTIVE_VMCS = 17,
 567         VMXERR_ENTRY_EXECUTIVE_VMCS_POINTER_NOT_VMXON_POINTER = 18,
 568         VMXERR_VMCALL_NONCLEAR_VMCS = 19,
 569         VMXERR_VMCALL_INVALID_VM_EXIT_CONTROL_FIELDS = 20,
 570         VMXERR_VMCALL_INCORRECT_MSEG_REVISION_ID = 22,
 571         VMXERR_VMXOFF_UNDER_DUAL_MONITOR_TREATMENT_OF_SMIS_AND_SMM = 23,
 572         VMXERR_VMCALL_INVALID_SMM_MONITOR_FEATURES = 24,
 573         VMXERR_ENTRY_INVALID_VM_EXECUTION_CONTROL_FIELDS_IN_EXECUTIVE_VMCS = 25,
 574         VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS = 26,
 575         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID = 28,
 576 };
 577
 578 enum vmx_l1d_flush_state {
 579         VMENTER_L1D_FLUSH_AUTO,
 580         VMENTER_L1D_FLUSH_NEVER,
 581         VMENTER_L1D_FLUSH_COND,
 582         VMENTER_L1D_FLUSH_ALWAYS,
 583         VMENTER_L1D_FLUSH_EPT_DISABLED,
 584         VMENTER_L1D_FLUSH_NOT_REQUIRED,
 585 };
 586
 587 extern enum vmx_l1d_flush_state l1tf_vmx_mitigation;
 588
 589 #endif