2 * Performance events x86 architecture code
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
16 #include <linux/capability.h>
17 #include <linux/notifier.h>
18 #include <linux/hardirq.h>
19 #include <linux/kprobes.h>
20 #include <linux/export.h>
21 #include <linux/init.h>
22 #include <linux/kdebug.h>
23 #include <linux/sched/mm.h>
24 #include <linux/sched/clock.h>
25 #include <linux/uaccess.h>
26 #include <linux/slab.h>
27 #include <linux/cpu.h>
28 #include <linux/bitops.h>
29 #include <linux/device.h>
30 #include <linux/nospec.h>
31 #include <linux/static_call.h>
34 #include <asm/stacktrace.h>
37 #include <asm/alternative.h>
38 #include <asm/mmu_context.h>
39 #include <asm/tlbflush.h>
40 #include <asm/timer.h>
43 #include <asm/unwind.h>
45 #include "perf_event.h"
47 struct x86_pmu x86_pmu __read_mostly;
48 static struct pmu pmu;
50 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
55 DEFINE_STATIC_KEY_FALSE(rdpmc_never_available_key);
56 DEFINE_STATIC_KEY_FALSE(rdpmc_always_available_key);
57 DEFINE_STATIC_KEY_FALSE(perf_is_hybrid);
60 * This here uses DEFINE_STATIC_CALL_NULL() to get a static_call defined
61 * from just a typename, as opposed to an actual function.
63 DEFINE_STATIC_CALL_NULL(x86_pmu_handle_irq, *x86_pmu.handle_irq);
64 DEFINE_STATIC_CALL_NULL(x86_pmu_disable_all, *x86_pmu.disable_all);
65 DEFINE_STATIC_CALL_NULL(x86_pmu_enable_all, *x86_pmu.enable_all);
66 DEFINE_STATIC_CALL_NULL(x86_pmu_enable, *x86_pmu.enable);
67 DEFINE_STATIC_CALL_NULL(x86_pmu_disable, *x86_pmu.disable);
69 DEFINE_STATIC_CALL_NULL(x86_pmu_assign, *x86_pmu.assign);
71 DEFINE_STATIC_CALL_NULL(x86_pmu_add, *x86_pmu.add);
72 DEFINE_STATIC_CALL_NULL(x86_pmu_del, *x86_pmu.del);
73 DEFINE_STATIC_CALL_NULL(x86_pmu_read, *x86_pmu.read);
75 DEFINE_STATIC_CALL_NULL(x86_pmu_set_period, *x86_pmu.set_period);
76 DEFINE_STATIC_CALL_NULL(x86_pmu_update, *x86_pmu.update);
78 DEFINE_STATIC_CALL_NULL(x86_pmu_schedule_events, *x86_pmu.schedule_events);
79 DEFINE_STATIC_CALL_NULL(x86_pmu_get_event_constraints, *x86_pmu.get_event_constraints);
80 DEFINE_STATIC_CALL_NULL(x86_pmu_put_event_constraints, *x86_pmu.put_event_constraints);
82 DEFINE_STATIC_CALL_NULL(x86_pmu_start_scheduling, *x86_pmu.start_scheduling);
83 DEFINE_STATIC_CALL_NULL(x86_pmu_commit_scheduling, *x86_pmu.commit_scheduling);
84 DEFINE_STATIC_CALL_NULL(x86_pmu_stop_scheduling, *x86_pmu.stop_scheduling);
86 DEFINE_STATIC_CALL_NULL(x86_pmu_sched_task, *x86_pmu.sched_task);
87 DEFINE_STATIC_CALL_NULL(x86_pmu_swap_task_ctx, *x86_pmu.swap_task_ctx);
89 DEFINE_STATIC_CALL_NULL(x86_pmu_drain_pebs, *x86_pmu.drain_pebs);
90 DEFINE_STATIC_CALL_NULL(x86_pmu_pebs_aliases, *x86_pmu.pebs_aliases);
93 * This one is magic, it will get called even when PMU init fails (because
94 * there is no PMU), in which case it should simply return NULL.
96 DEFINE_STATIC_CALL_RET0(x86_pmu_guest_get_msrs, *x86_pmu.guest_get_msrs);
98 u64 __read_mostly hw_cache_event_ids
99 [PERF_COUNT_HW_CACHE_MAX]
100 [PERF_COUNT_HW_CACHE_OP_MAX]
101 [PERF_COUNT_HW_CACHE_RESULT_MAX];
102 u64 __read_mostly hw_cache_extra_regs
103 [PERF_COUNT_HW_CACHE_MAX]
104 [PERF_COUNT_HW_CACHE_OP_MAX]
105 [PERF_COUNT_HW_CACHE_RESULT_MAX];
108 * Propagate event elapsed time into the generic event.
109 * Can only be executed on the CPU where the event is active.
110 * Returns the delta events processed.
112 u64 x86_perf_event_update(struct perf_event *event)
114 struct hw_perf_event *hwc = &event->hw;
115 int shift = 64 - x86_pmu.cntval_bits;
116 u64 prev_raw_count, new_raw_count;
119 if (unlikely(!hwc->event_base))
122 if (unlikely(is_topdown_count(event)) && x86_pmu.update_topdown_event)
123 return x86_pmu.update_topdown_event(event);
126 * Careful: an NMI might modify the previous event value.
128 * Our tactic to handle this is to first atomically read and
129 * exchange a new raw count - then add that new-prev delta
130 * count to the generic event atomically:
133 prev_raw_count = local64_read(&hwc->prev_count);
134 rdpmcl(hwc->event_base_rdpmc, new_raw_count);
136 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
137 new_raw_count) != prev_raw_count)
141 * Now we have the new raw value and have updated the prev
142 * timestamp already. We can now calculate the elapsed delta
143 * (event-)time and add that to the generic event.
145 * Careful, not all hw sign-extends above the physical width
148 delta = (new_raw_count << shift) - (prev_raw_count << shift);
151 local64_add(delta, &event->count);
152 local64_sub(delta, &hwc->period_left);
154 return new_raw_count;
158 * Find and validate any extra registers to set up.
160 static int x86_pmu_extra_regs(u64 config, struct perf_event *event)
162 struct extra_reg *extra_regs = hybrid(event->pmu, extra_regs);
163 struct hw_perf_event_extra *reg;
164 struct extra_reg *er;
166 reg = &event->hw.extra_reg;
171 for (er = extra_regs; er->msr; er++) {
172 if (er->event != (config & er->config_mask))
174 if (event->attr.config1 & ~er->valid_mask)
176 /* Check if the extra msrs can be safely accessed*/
177 if (!er->extra_msr_access)
181 reg->config = event->attr.config1;
188 static atomic_t active_events;
189 static atomic_t pmc_refcount;
190 static DEFINE_MUTEX(pmc_reserve_mutex);
192 #ifdef CONFIG_X86_LOCAL_APIC
194 static inline int get_possible_num_counters(void)
196 int i, num_counters = x86_pmu.num_counters;
201 for (i = 0; i < x86_pmu.num_hybrid_pmus; i++)
202 num_counters = max_t(int, num_counters, x86_pmu.hybrid_pmu[i].num_counters);
207 static bool reserve_pmc_hardware(void)
209 int i, num_counters = get_possible_num_counters();
211 for (i = 0; i < num_counters; i++) {
212 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i)))
216 for (i = 0; i < num_counters; i++) {
217 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i)))
224 for (i--; i >= 0; i--)
225 release_evntsel_nmi(x86_pmu_config_addr(i));
230 for (i--; i >= 0; i--)
231 release_perfctr_nmi(x86_pmu_event_addr(i));
236 static void release_pmc_hardware(void)
238 int i, num_counters = get_possible_num_counters();
240 for (i = 0; i < num_counters; i++) {
241 release_perfctr_nmi(x86_pmu_event_addr(i));
242 release_evntsel_nmi(x86_pmu_config_addr(i));
248 static bool reserve_pmc_hardware(void) { return true; }
249 static void release_pmc_hardware(void) {}
253 bool check_hw_exists(struct pmu *pmu, int num_counters, int num_counters_fixed)
255 u64 val, val_fail = -1, val_new= ~0;
256 int i, reg, reg_fail = -1, ret = 0;
261 * Check to see if the BIOS enabled any of the counters, if so
264 for (i = 0; i < num_counters; i++) {
265 reg = x86_pmu_config_addr(i);
266 ret = rdmsrl_safe(reg, &val);
269 if (val & ARCH_PERFMON_EVENTSEL_ENABLE) {
278 if (num_counters_fixed) {
279 reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
280 ret = rdmsrl_safe(reg, &val);
283 for (i = 0; i < num_counters_fixed; i++) {
284 if (fixed_counter_disabled(i, pmu))
286 if (val & (0x03ULL << i*4)) {
295 * If all the counters are enabled, the below test will always
296 * fail. The tools will also become useless in this scenario.
297 * Just fail and disable the hardware counters.
300 if (reg_safe == -1) {
306 * Read the current value, change it and read it back to see if it
307 * matches, this is needed to detect certain hardware emulators
308 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
310 reg = x86_pmu_event_addr(reg_safe);
311 if (rdmsrl_safe(reg, &val))
314 ret = wrmsrl_safe(reg, val);
315 ret |= rdmsrl_safe(reg, &val_new);
316 if (ret || val != val_new)
320 * We still allow the PMU driver to operate:
323 pr_cont("Broken BIOS detected, complain to your hardware vendor.\n");
324 pr_err(FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n",
331 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
332 pr_cont("PMU not available due to virtualization, using software events only.\n");
334 pr_cont("Broken PMU hardware detected, using software events only.\n");
335 pr_err("Failed to access perfctr msr (MSR %x is %Lx)\n",
342 static void hw_perf_event_destroy(struct perf_event *event)
344 x86_release_hardware();
345 atomic_dec(&active_events);
348 void hw_perf_lbr_event_destroy(struct perf_event *event)
350 hw_perf_event_destroy(event);
352 /* undo the lbr/bts event accounting */
353 x86_del_exclusive(x86_lbr_exclusive_lbr);
356 static inline int x86_pmu_initialized(void)
358 return x86_pmu.handle_irq != NULL;
362 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event)
364 struct perf_event_attr *attr = &event->attr;
365 unsigned int cache_type, cache_op, cache_result;
368 config = attr->config;
370 cache_type = (config >> 0) & 0xff;
371 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
373 cache_type = array_index_nospec(cache_type, PERF_COUNT_HW_CACHE_MAX);
375 cache_op = (config >> 8) & 0xff;
376 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
378 cache_op = array_index_nospec(cache_op, PERF_COUNT_HW_CACHE_OP_MAX);
380 cache_result = (config >> 16) & 0xff;
381 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
383 cache_result = array_index_nospec(cache_result, PERF_COUNT_HW_CACHE_RESULT_MAX);
385 val = hybrid_var(event->pmu, hw_cache_event_ids)[cache_type][cache_op][cache_result];
393 attr->config1 = hybrid_var(event->pmu, hw_cache_extra_regs)[cache_type][cache_op][cache_result];
394 return x86_pmu_extra_regs(val, event);
397 int x86_reserve_hardware(void)
401 if (!atomic_inc_not_zero(&pmc_refcount)) {
402 mutex_lock(&pmc_reserve_mutex);
403 if (atomic_read(&pmc_refcount) == 0) {
404 if (!reserve_pmc_hardware()) {
407 reserve_ds_buffers();
408 reserve_lbr_buffers();
412 atomic_inc(&pmc_refcount);
413 mutex_unlock(&pmc_reserve_mutex);
419 void x86_release_hardware(void)
421 if (atomic_dec_and_mutex_lock(&pmc_refcount, &pmc_reserve_mutex)) {
422 release_pmc_hardware();
423 release_ds_buffers();
424 release_lbr_buffers();
425 mutex_unlock(&pmc_reserve_mutex);
430 * Check if we can create event of a certain type (that no conflicting events
433 int x86_add_exclusive(unsigned int what)
438 * When lbr_pt_coexist we allow PT to coexist with either LBR or BTS.
439 * LBR and BTS are still mutually exclusive.
441 if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt)
444 if (!atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what])) {
445 mutex_lock(&pmc_reserve_mutex);
446 for (i = 0; i < ARRAY_SIZE(x86_pmu.lbr_exclusive); i++) {
447 if (i != what && atomic_read(&x86_pmu.lbr_exclusive[i]))
450 atomic_inc(&x86_pmu.lbr_exclusive[what]);
451 mutex_unlock(&pmc_reserve_mutex);
455 atomic_inc(&active_events);
459 mutex_unlock(&pmc_reserve_mutex);
463 void x86_del_exclusive(unsigned int what)
465 atomic_dec(&active_events);
468 * See the comment in x86_add_exclusive().
470 if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt)
473 atomic_dec(&x86_pmu.lbr_exclusive[what]);
476 int x86_setup_perfctr(struct perf_event *event)
478 struct perf_event_attr *attr = &event->attr;
479 struct hw_perf_event *hwc = &event->hw;
482 if (!is_sampling_event(event)) {
483 hwc->sample_period = x86_pmu.max_period;
484 hwc->last_period = hwc->sample_period;
485 local64_set(&hwc->period_left, hwc->sample_period);
488 if (attr->type == event->pmu->type)
489 return x86_pmu_extra_regs(event->attr.config, event);
491 if (attr->type == PERF_TYPE_HW_CACHE)
492 return set_ext_hw_attr(hwc, event);
494 if (attr->config >= x86_pmu.max_events)
497 attr->config = array_index_nospec((unsigned long)attr->config, x86_pmu.max_events);
502 config = x86_pmu.event_map(attr->config);
510 hwc->config |= config;
516 * check that branch_sample_type is compatible with
517 * settings needed for precise_ip > 1 which implies
518 * using the LBR to capture ALL taken branches at the
519 * priv levels of the measurement
521 static inline int precise_br_compat(struct perf_event *event)
523 u64 m = event->attr.branch_sample_type;
526 /* must capture all branches */
527 if (!(m & PERF_SAMPLE_BRANCH_ANY))
530 m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER;
532 if (!event->attr.exclude_user)
533 b |= PERF_SAMPLE_BRANCH_USER;
535 if (!event->attr.exclude_kernel)
536 b |= PERF_SAMPLE_BRANCH_KERNEL;
539 * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86
545 int x86_pmu_max_precise(void)
549 /* Support for constant skid */
550 if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) {
553 /* Support for IP fixup */
554 if (x86_pmu.lbr_nr || x86_pmu.intel_cap.pebs_format >= 2)
557 if (x86_pmu.pebs_prec_dist)
563 int x86_pmu_hw_config(struct perf_event *event)
565 if (event->attr.precise_ip) {
566 int precise = x86_pmu_max_precise();
568 if (event->attr.precise_ip > precise)
571 /* There's no sense in having PEBS for non sampling events: */
572 if (!is_sampling_event(event))
576 * check that PEBS LBR correction does not conflict with
577 * whatever the user is asking with attr->branch_sample_type
579 if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format < 2) {
580 u64 *br_type = &event->attr.branch_sample_type;
582 if (has_branch_stack(event)) {
583 if (!precise_br_compat(event))
586 /* branch_sample_type is compatible */
590 * user did not specify branch_sample_type
592 * For PEBS fixups, we capture all
593 * the branches at the priv level of the
596 *br_type = PERF_SAMPLE_BRANCH_ANY;
598 if (!event->attr.exclude_user)
599 *br_type |= PERF_SAMPLE_BRANCH_USER;
601 if (!event->attr.exclude_kernel)
602 *br_type |= PERF_SAMPLE_BRANCH_KERNEL;
606 if (event->attr.branch_sample_type & PERF_SAMPLE_BRANCH_CALL_STACK)
607 event->attach_state |= PERF_ATTACH_TASK_DATA;
611 * (keep 'enabled' bit clear for now)
613 event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
616 * Count user and OS events unless requested not to
618 if (!event->attr.exclude_user)
619 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
620 if (!event->attr.exclude_kernel)
621 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
623 if (event->attr.type == event->pmu->type)
624 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
626 if (event->attr.sample_period && x86_pmu.limit_period) {
627 if (x86_pmu.limit_period(event, event->attr.sample_period) >
628 event->attr.sample_period)
632 /* sample_regs_user never support XMM registers */
633 if (unlikely(event->attr.sample_regs_user & PERF_REG_EXTENDED_MASK))
636 * Besides the general purpose registers, XMM registers may
637 * be collected in PEBS on some platforms, e.g. Icelake
639 if (unlikely(event->attr.sample_regs_intr & PERF_REG_EXTENDED_MASK)) {
640 if (!(event->pmu->capabilities & PERF_PMU_CAP_EXTENDED_REGS))
643 if (!event->attr.precise_ip)
647 return x86_setup_perfctr(event);
651 * Setup the hardware configuration for a given attr_type
653 static int __x86_pmu_event_init(struct perf_event *event)
657 if (!x86_pmu_initialized())
660 err = x86_reserve_hardware();
664 atomic_inc(&active_events);
665 event->destroy = hw_perf_event_destroy;
668 event->hw.last_cpu = -1;
669 event->hw.last_tag = ~0ULL;
672 event->hw.extra_reg.idx = EXTRA_REG_NONE;
673 event->hw.branch_reg.idx = EXTRA_REG_NONE;
675 return x86_pmu.hw_config(event);
678 void x86_pmu_disable_all(void)
680 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
683 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
684 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
687 if (!test_bit(idx, cpuc->active_mask))
689 rdmsrl(x86_pmu_config_addr(idx), val);
690 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
692 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
693 wrmsrl(x86_pmu_config_addr(idx), val);
694 if (is_counter_pair(hwc))
695 wrmsrl(x86_pmu_config_addr(idx + 1), 0);
699 struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr, void *data)
701 return static_call(x86_pmu_guest_get_msrs)(nr, data);
703 EXPORT_SYMBOL_GPL(perf_guest_get_msrs);
706 * There may be PMI landing after enabled=0. The PMI hitting could be before or
709 * If PMI hits before disable_all, the PMU will be disabled in the NMI handler.
710 * It will not be re-enabled in the NMI handler again, because enabled=0. After
711 * handling the NMI, disable_all will be called, which will not change the
712 * state either. If PMI hits after disable_all, the PMU is already disabled
713 * before entering NMI handler. The NMI handler will not change the state
716 * So either situation is harmless.
718 static void x86_pmu_disable(struct pmu *pmu)
720 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
722 if (!x86_pmu_initialized())
732 static_call(x86_pmu_disable_all)();
735 void x86_pmu_enable_all(int added)
737 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
740 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
741 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
743 if (!test_bit(idx, cpuc->active_mask))
746 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
750 static inline int is_x86_event(struct perf_event *event)
755 return event->pmu == &pmu;
757 for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) {
758 if (event->pmu == &x86_pmu.hybrid_pmu[i].pmu)
765 struct pmu *x86_get_pmu(unsigned int cpu)
767 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
770 * All CPUs of the hybrid type have been offline.
771 * The x86_get_pmu() should not be invoked.
773 if (WARN_ON_ONCE(!cpuc->pmu))
779 * Event scheduler state:
781 * Assign events iterating over all events and counters, beginning
782 * with events with least weights first. Keep the current iterator
783 * state in struct sched_state.
787 int event; /* event index */
788 int counter; /* counter index */
789 int unassigned; /* number of events to be assigned left */
790 int nr_gp; /* number of GP counters used */
794 /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */
795 #define SCHED_STATES_MAX 2
802 struct event_constraint **constraints;
803 struct sched_state state;
804 struct sched_state saved[SCHED_STATES_MAX];
808 * Initialize iterator that runs through all events and counters.
810 static void perf_sched_init(struct perf_sched *sched, struct event_constraint **constraints,
811 int num, int wmin, int wmax, int gpmax)
815 memset(sched, 0, sizeof(*sched));
816 sched->max_events = num;
817 sched->max_weight = wmax;
818 sched->max_gp = gpmax;
819 sched->constraints = constraints;
821 for (idx = 0; idx < num; idx++) {
822 if (constraints[idx]->weight == wmin)
826 sched->state.event = idx; /* start with min weight */
827 sched->state.weight = wmin;
828 sched->state.unassigned = num;
831 static void perf_sched_save_state(struct perf_sched *sched)
833 if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX))
836 sched->saved[sched->saved_states] = sched->state;
837 sched->saved_states++;
840 static bool perf_sched_restore_state(struct perf_sched *sched)
842 if (!sched->saved_states)
845 sched->saved_states--;
846 sched->state = sched->saved[sched->saved_states];
848 /* this assignment didn't work out */
849 /* XXX broken vs EVENT_PAIR */
850 sched->state.used &= ~BIT_ULL(sched->state.counter);
852 /* try the next one */
853 sched->state.counter++;
859 * Select a counter for the current event to schedule. Return true on
862 static bool __perf_sched_find_counter(struct perf_sched *sched)
864 struct event_constraint *c;
867 if (!sched->state.unassigned)
870 if (sched->state.event >= sched->max_events)
873 c = sched->constraints[sched->state.event];
874 /* Prefer fixed purpose counters */
875 if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) {
876 idx = INTEL_PMC_IDX_FIXED;
877 for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) {
878 u64 mask = BIT_ULL(idx);
880 if (sched->state.used & mask)
883 sched->state.used |= mask;
888 /* Grab the first unused counter starting with idx */
889 idx = sched->state.counter;
890 for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) {
891 u64 mask = BIT_ULL(idx);
893 if (c->flags & PERF_X86_EVENT_PAIR)
896 if (sched->state.used & mask)
899 if (sched->state.nr_gp++ >= sched->max_gp)
902 sched->state.used |= mask;
909 sched->state.counter = idx;
912 perf_sched_save_state(sched);
917 static bool perf_sched_find_counter(struct perf_sched *sched)
919 while (!__perf_sched_find_counter(sched)) {
920 if (!perf_sched_restore_state(sched))
928 * Go through all unassigned events and find the next one to schedule.
929 * Take events with the least weight first. Return true on success.
931 static bool perf_sched_next_event(struct perf_sched *sched)
933 struct event_constraint *c;
935 if (!sched->state.unassigned || !--sched->state.unassigned)
940 sched->state.event++;
941 if (sched->state.event >= sched->max_events) {
943 sched->state.event = 0;
944 sched->state.weight++;
945 if (sched->state.weight > sched->max_weight)
948 c = sched->constraints[sched->state.event];
949 } while (c->weight != sched->state.weight);
951 sched->state.counter = 0; /* start with first counter */
957 * Assign a counter for each event.
959 int perf_assign_events(struct event_constraint **constraints, int n,
960 int wmin, int wmax, int gpmax, int *assign)
962 struct perf_sched sched;
964 perf_sched_init(&sched, constraints, n, wmin, wmax, gpmax);
967 if (!perf_sched_find_counter(&sched))
970 assign[sched.state.event] = sched.state.counter;
971 } while (perf_sched_next_event(&sched));
973 return sched.state.unassigned;
975 EXPORT_SYMBOL_GPL(perf_assign_events);
977 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
979 int num_counters = hybrid(cpuc->pmu, num_counters);
980 struct event_constraint *c;
981 struct perf_event *e;
982 int n0, i, wmin, wmax, unsched = 0;
983 struct hw_perf_event *hwc;
987 * Compute the number of events already present; see x86_pmu_add(),
988 * validate_group() and x86_pmu_commit_txn(). For the former two
989 * cpuc->n_events hasn't been updated yet, while for the latter
990 * cpuc->n_txn contains the number of events added in the current
994 if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
997 static_call_cond(x86_pmu_start_scheduling)(cpuc);
999 for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) {
1000 c = cpuc->event_constraint[i];
1003 * Previously scheduled events should have a cached constraint,
1004 * while new events should not have one.
1006 WARN_ON_ONCE((c && i >= n0) || (!c && i < n0));
1009 * Request constraints for new events; or for those events that
1010 * have a dynamic constraint -- for those the constraint can
1011 * change due to external factors (sibling state, allow_tfa).
1013 if (!c || (c->flags & PERF_X86_EVENT_DYNAMIC)) {
1014 c = static_call(x86_pmu_get_event_constraints)(cpuc, i, cpuc->event_list[i]);
1015 cpuc->event_constraint[i] = c;
1018 wmin = min(wmin, c->weight);
1019 wmax = max(wmax, c->weight);
1023 * fastpath, try to reuse previous register
1025 for (i = 0; i < n; i++) {
1028 hwc = &cpuc->event_list[i]->hw;
1029 c = cpuc->event_constraint[i];
1031 /* never assigned */
1035 /* constraint still honored */
1036 if (!test_bit(hwc->idx, c->idxmsk))
1039 mask = BIT_ULL(hwc->idx);
1040 if (is_counter_pair(hwc))
1043 /* not already used */
1044 if (used_mask & mask)
1050 assign[i] = hwc->idx;
1055 int gpmax = num_counters;
1058 * Do not allow scheduling of more than half the available
1061 * This helps avoid counter starvation of sibling thread by
1062 * ensuring at most half the counters cannot be in exclusive
1063 * mode. There is no designated counters for the limits. Any
1064 * N/2 counters can be used. This helps with events with
1065 * specific counter constraints.
1067 if (is_ht_workaround_enabled() && !cpuc->is_fake &&
1068 READ_ONCE(cpuc->excl_cntrs->exclusive_present))
1072 * Reduce the amount of available counters to allow fitting
1073 * the extra Merge events needed by large increment events.
1075 if (x86_pmu.flags & PMU_FL_PAIR) {
1076 gpmax = num_counters - cpuc->n_pair;
1077 WARN_ON(gpmax <= 0);
1080 unsched = perf_assign_events(cpuc->event_constraint, n, wmin,
1081 wmax, gpmax, assign);
1085 * In case of success (unsched = 0), mark events as committed,
1086 * so we do not put_constraint() in case new events are added
1087 * and fail to be scheduled
1089 * We invoke the lower level commit callback to lock the resource
1091 * We do not need to do all of this in case we are called to
1092 * validate an event group (assign == NULL)
1094 if (!unsched && assign) {
1095 for (i = 0; i < n; i++)
1096 static_call_cond(x86_pmu_commit_scheduling)(cpuc, i, assign[i]);
1098 for (i = n0; i < n; i++) {
1099 e = cpuc->event_list[i];
1102 * release events that failed scheduling
1104 static_call_cond(x86_pmu_put_event_constraints)(cpuc, e);
1106 cpuc->event_constraint[i] = NULL;
1110 static_call_cond(x86_pmu_stop_scheduling)(cpuc);
1112 return unsched ? -EINVAL : 0;
1115 static int add_nr_metric_event(struct cpu_hw_events *cpuc,
1116 struct perf_event *event)
1118 if (is_metric_event(event)) {
1119 if (cpuc->n_metric == INTEL_TD_METRIC_NUM)
1122 cpuc->n_txn_metric++;
1128 static void del_nr_metric_event(struct cpu_hw_events *cpuc,
1129 struct perf_event *event)
1131 if (is_metric_event(event))
1135 static int collect_event(struct cpu_hw_events *cpuc, struct perf_event *event,
1136 int max_count, int n)
1138 union perf_capabilities intel_cap = hybrid(cpuc->pmu, intel_cap);
1140 if (intel_cap.perf_metrics && add_nr_metric_event(cpuc, event))
1143 if (n >= max_count + cpuc->n_metric)
1146 cpuc->event_list[n] = event;
1147 if (is_counter_pair(&event->hw)) {
1156 * dogrp: true if must collect siblings events (group)
1157 * returns total number of events and error code
1159 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
1161 int num_counters = hybrid(cpuc->pmu, num_counters);
1162 int num_counters_fixed = hybrid(cpuc->pmu, num_counters_fixed);
1163 struct perf_event *event;
1166 max_count = num_counters + num_counters_fixed;
1168 /* current number of events already accepted */
1170 if (!cpuc->n_events)
1171 cpuc->pebs_output = 0;
1173 if (!cpuc->is_fake && leader->attr.precise_ip) {
1175 * For PEBS->PT, if !aux_event, the group leader (PT) went
1176 * away, the group was broken down and this singleton event
1177 * can't schedule any more.
1179 if (is_pebs_pt(leader) && !leader->aux_event)
1183 * pebs_output: 0: no PEBS so far, 1: PT, 2: DS
1185 if (cpuc->pebs_output &&
1186 cpuc->pebs_output != is_pebs_pt(leader) + 1)
1189 cpuc->pebs_output = is_pebs_pt(leader) + 1;
1192 if (is_x86_event(leader)) {
1193 if (collect_event(cpuc, leader, max_count, n))
1201 for_each_sibling_event(event, leader) {
1202 if (!is_x86_event(event) || event->state <= PERF_EVENT_STATE_OFF)
1205 if (collect_event(cpuc, event, max_count, n))
1213 static inline void x86_assign_hw_event(struct perf_event *event,
1214 struct cpu_hw_events *cpuc, int i)
1216 struct hw_perf_event *hwc = &event->hw;
1219 idx = hwc->idx = cpuc->assign[i];
1220 hwc->last_cpu = smp_processor_id();
1221 hwc->last_tag = ++cpuc->tags[i];
1223 static_call_cond(x86_pmu_assign)(event, idx);
1226 case INTEL_PMC_IDX_FIXED_BTS:
1227 case INTEL_PMC_IDX_FIXED_VLBR:
1228 hwc->config_base = 0;
1229 hwc->event_base = 0;
1232 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END:
1233 /* All the metric events are mapped onto the fixed counter 3. */
1234 idx = INTEL_PMC_IDX_FIXED_SLOTS;
1236 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS-1:
1237 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
1238 hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 +
1239 (idx - INTEL_PMC_IDX_FIXED);
1240 hwc->event_base_rdpmc = (idx - INTEL_PMC_IDX_FIXED) |
1241 INTEL_PMC_FIXED_RDPMC_BASE;
1245 hwc->config_base = x86_pmu_config_addr(hwc->idx);
1246 hwc->event_base = x86_pmu_event_addr(hwc->idx);
1247 hwc->event_base_rdpmc = x86_pmu_rdpmc_index(hwc->idx);
1253 * x86_perf_rdpmc_index - Return PMC counter used for event
1254 * @event: the perf_event to which the PMC counter was assigned
1256 * The counter assigned to this performance event may change if interrupts
1257 * are enabled. This counter should thus never be used while interrupts are
1258 * enabled. Before this function is used to obtain the assigned counter the
1259 * event should be checked for validity using, for example,
1260 * perf_event_read_local(), within the same interrupt disabled section in
1261 * which this counter is planned to be used.
1263 * Return: The index of the performance monitoring counter assigned to
1266 int x86_perf_rdpmc_index(struct perf_event *event)
1268 lockdep_assert_irqs_disabled();
1270 return event->hw.event_base_rdpmc;
1273 static inline int match_prev_assignment(struct hw_perf_event *hwc,
1274 struct cpu_hw_events *cpuc,
1277 return hwc->idx == cpuc->assign[i] &&
1278 hwc->last_cpu == smp_processor_id() &&
1279 hwc->last_tag == cpuc->tags[i];
1282 static void x86_pmu_start(struct perf_event *event, int flags);
1284 static void x86_pmu_enable(struct pmu *pmu)
1286 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1287 struct perf_event *event;
1288 struct hw_perf_event *hwc;
1289 int i, added = cpuc->n_added;
1291 if (!x86_pmu_initialized())
1297 if (cpuc->n_added) {
1298 int n_running = cpuc->n_events - cpuc->n_added;
1300 * apply assignment obtained either from
1301 * hw_perf_group_sched_in() or x86_pmu_enable()
1303 * step1: save events moving to new counters
1305 for (i = 0; i < n_running; i++) {
1306 event = cpuc->event_list[i];
1310 * we can avoid reprogramming counter if:
1311 * - assigned same counter as last time
1312 * - running on same CPU as last time
1313 * - no other event has used the counter since
1315 if (hwc->idx == -1 ||
1316 match_prev_assignment(hwc, cpuc, i))
1320 * Ensure we don't accidentally enable a stopped
1321 * counter simply because we rescheduled.
1323 if (hwc->state & PERF_HES_STOPPED)
1324 hwc->state |= PERF_HES_ARCH;
1326 x86_pmu_stop(event, PERF_EF_UPDATE);
1330 * step2: reprogram moved events into new counters
1332 for (i = 0; i < cpuc->n_events; i++) {
1333 event = cpuc->event_list[i];
1336 if (!match_prev_assignment(hwc, cpuc, i))
1337 x86_assign_hw_event(event, cpuc, i);
1338 else if (i < n_running)
1341 if (hwc->state & PERF_HES_ARCH)
1345 * if cpuc->enabled = 0, then no wrmsr as
1346 * per x86_pmu_enable_event()
1348 x86_pmu_start(event, PERF_EF_RELOAD);
1351 perf_events_lapic_init();
1357 static_call(x86_pmu_enable_all)(added);
1360 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
1363 * Set the next IRQ period, based on the hwc->period_left value.
1364 * To be called with the event disabled in hw:
1366 int x86_perf_event_set_period(struct perf_event *event)
1368 struct hw_perf_event *hwc = &event->hw;
1369 s64 left = local64_read(&hwc->period_left);
1370 s64 period = hwc->sample_period;
1371 int ret = 0, idx = hwc->idx;
1373 if (unlikely(!hwc->event_base))
1376 if (unlikely(is_topdown_count(event)) &&
1377 x86_pmu.set_topdown_event_period)
1378 return x86_pmu.set_topdown_event_period(event);
1381 * If we are way outside a reasonable range then just skip forward:
1383 if (unlikely(left <= -period)) {
1385 local64_set(&hwc->period_left, left);
1386 hwc->last_period = period;
1390 if (unlikely(left <= 0)) {
1392 local64_set(&hwc->period_left, left);
1393 hwc->last_period = period;
1397 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
1399 if (unlikely(left < 2))
1402 if (left > x86_pmu.max_period)
1403 left = x86_pmu.max_period;
1405 if (x86_pmu.limit_period)
1406 left = x86_pmu.limit_period(event, left);
1408 per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
1411 * The hw event starts counting from this event offset,
1412 * mark it to be able to extra future deltas:
1414 local64_set(&hwc->prev_count, (u64)-left);
1416 wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
1419 * Sign extend the Merge event counter's upper 16 bits since
1420 * we currently declare a 48-bit counter width
1422 if (is_counter_pair(hwc))
1423 wrmsrl(x86_pmu_event_addr(idx + 1), 0xffff);
1426 * Due to erratum on certan cpu we need
1427 * a second write to be sure the register
1428 * is updated properly
1430 if (x86_pmu.perfctr_second_write) {
1431 wrmsrl(hwc->event_base,
1432 (u64)(-left) & x86_pmu.cntval_mask);
1435 perf_event_update_userpage(event);
1440 void x86_pmu_enable_event(struct perf_event *event)
1442 if (__this_cpu_read(cpu_hw_events.enabled))
1443 __x86_pmu_enable_event(&event->hw,
1444 ARCH_PERFMON_EVENTSEL_ENABLE);
1448 * Add a single event to the PMU.
1450 * The event is added to the group of enabled events
1451 * but only if it can be scheduled with existing events.
1453 static int x86_pmu_add(struct perf_event *event, int flags)
1455 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1456 struct hw_perf_event *hwc;
1457 int assign[X86_PMC_IDX_MAX];
1462 n0 = cpuc->n_events;
1463 ret = n = collect_events(cpuc, event, false);
1467 hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
1468 if (!(flags & PERF_EF_START))
1469 hwc->state |= PERF_HES_ARCH;
1472 * If group events scheduling transaction was started,
1473 * skip the schedulability test here, it will be performed
1474 * at commit time (->commit_txn) as a whole.
1476 * If commit fails, we'll call ->del() on all events
1477 * for which ->add() was called.
1479 if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
1482 ret = static_call(x86_pmu_schedule_events)(cpuc, n, assign);
1486 * copy new assignment, now we know it is possible
1487 * will be used by hw_perf_enable()
1489 memcpy(cpuc->assign, assign, n*sizeof(int));
1493 * Commit the collect_events() state. See x86_pmu_del() and
1497 cpuc->n_added += n - n0;
1498 cpuc->n_txn += n - n0;
1501 * This is before x86_pmu_enable() will call x86_pmu_start(),
1502 * so we enable LBRs before an event needs them etc..
1504 static_call_cond(x86_pmu_add)(event);
1511 static void x86_pmu_start(struct perf_event *event, int flags)
1513 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1514 int idx = event->hw.idx;
1516 if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
1519 if (WARN_ON_ONCE(idx == -1))
1522 if (flags & PERF_EF_RELOAD) {
1523 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1524 static_call(x86_pmu_set_period)(event);
1527 event->hw.state = 0;
1529 cpuc->events[idx] = event;
1530 __set_bit(idx, cpuc->active_mask);
1531 static_call(x86_pmu_enable)(event);
1532 perf_event_update_userpage(event);
1535 void perf_event_print_debug(void)
1537 u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1539 int cpu = smp_processor_id();
1540 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1541 int num_counters = hybrid(cpuc->pmu, num_counters);
1542 int num_counters_fixed = hybrid(cpuc->pmu, num_counters_fixed);
1543 struct event_constraint *pebs_constraints = hybrid(cpuc->pmu, pebs_constraints);
1544 unsigned long flags;
1550 local_irq_save(flags);
1552 if (x86_pmu.version >= 2) {
1553 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1554 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1555 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1556 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1559 pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl);
1560 pr_info("CPU#%d: status: %016llx\n", cpu, status);
1561 pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow);
1562 pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed);
1563 if (pebs_constraints) {
1564 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1565 pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs);
1567 if (x86_pmu.lbr_nr) {
1568 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
1569 pr_info("CPU#%d: debugctl: %016llx\n", cpu, debugctl);
1572 pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1574 for (idx = 0; idx < num_counters; idx++) {
1575 rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl);
1576 rdmsrl(x86_pmu_event_addr(idx), pmc_count);
1578 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1580 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1581 cpu, idx, pmc_ctrl);
1582 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1583 cpu, idx, pmc_count);
1584 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1585 cpu, idx, prev_left);
1587 for (idx = 0; idx < num_counters_fixed; idx++) {
1588 if (fixed_counter_disabled(idx, cpuc->pmu))
1590 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1592 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1593 cpu, idx, pmc_count);
1595 local_irq_restore(flags);
1598 void x86_pmu_stop(struct perf_event *event, int flags)
1600 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1601 struct hw_perf_event *hwc = &event->hw;
1603 if (test_bit(hwc->idx, cpuc->active_mask)) {
1604 static_call(x86_pmu_disable)(event);
1605 __clear_bit(hwc->idx, cpuc->active_mask);
1606 cpuc->events[hwc->idx] = NULL;
1607 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
1608 hwc->state |= PERF_HES_STOPPED;
1611 if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
1613 * Drain the remaining delta count out of a event
1614 * that we are disabling:
1616 static_call(x86_pmu_update)(event);
1617 hwc->state |= PERF_HES_UPTODATE;
1621 static void x86_pmu_del(struct perf_event *event, int flags)
1623 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1624 union perf_capabilities intel_cap = hybrid(cpuc->pmu, intel_cap);
1628 * If we're called during a txn, we only need to undo x86_pmu.add.
1629 * The events never got scheduled and ->cancel_txn will truncate
1632 * XXX assumes any ->del() called during a TXN will only be on
1633 * an event added during that same TXN.
1635 if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
1638 __set_bit(event->hw.idx, cpuc->dirty);
1641 * Not a TXN, therefore cleanup properly.
1643 x86_pmu_stop(event, PERF_EF_UPDATE);
1645 for (i = 0; i < cpuc->n_events; i++) {
1646 if (event == cpuc->event_list[i])
1650 if (WARN_ON_ONCE(i == cpuc->n_events)) /* called ->del() without ->add() ? */
1653 /* If we have a newly added event; make sure to decrease n_added. */
1654 if (i >= cpuc->n_events - cpuc->n_added)
1657 static_call_cond(x86_pmu_put_event_constraints)(cpuc, event);
1659 /* Delete the array entry. */
1660 while (++i < cpuc->n_events) {
1661 cpuc->event_list[i-1] = cpuc->event_list[i];
1662 cpuc->event_constraint[i-1] = cpuc->event_constraint[i];
1664 cpuc->event_constraint[i-1] = NULL;
1666 if (intel_cap.perf_metrics)
1667 del_nr_metric_event(cpuc, event);
1669 perf_event_update_userpage(event);
1674 * This is after x86_pmu_stop(); so we disable LBRs after any
1675 * event can need them etc..
1677 static_call_cond(x86_pmu_del)(event);
1680 int x86_pmu_handle_irq(struct pt_regs *regs)
1682 struct perf_sample_data data;
1683 struct cpu_hw_events *cpuc;
1684 struct perf_event *event;
1685 int idx, handled = 0;
1688 cpuc = this_cpu_ptr(&cpu_hw_events);
1691 * Some chipsets need to unmask the LVTPC in a particular spot
1692 * inside the nmi handler. As a result, the unmasking was pushed
1693 * into all the nmi handlers.
1695 * This generic handler doesn't seem to have any issues where the
1696 * unmasking occurs so it was left at the top.
1698 apic_write(APIC_LVTPC, APIC_DM_NMI);
1700 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1701 if (!test_bit(idx, cpuc->active_mask))
1704 event = cpuc->events[idx];
1706 val = static_call(x86_pmu_update)(event);
1707 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1715 if (!static_call(x86_pmu_set_period)(event))
1718 perf_sample_data_init(&data, 0, event->hw.last_period);
1720 if (has_branch_stack(event)) {
1721 data.br_stack = &cpuc->lbr_stack;
1722 data.sample_flags |= PERF_SAMPLE_BRANCH_STACK;
1725 if (perf_event_overflow(event, &data, regs))
1726 x86_pmu_stop(event, 0);
1730 inc_irq_stat(apic_perf_irqs);
1735 void perf_events_lapic_init(void)
1737 if (!x86_pmu.apic || !x86_pmu_initialized())
1741 * Always use NMI for PMU
1743 apic_write(APIC_LVTPC, APIC_DM_NMI);
1747 perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs)
1754 * All PMUs/events that share this PMI handler should make sure to
1755 * increment active_events for their events.
1757 if (!atomic_read(&active_events))
1760 start_clock = sched_clock();
1761 ret = static_call(x86_pmu_handle_irq)(regs);
1762 finish_clock = sched_clock();
1764 perf_sample_event_took(finish_clock - start_clock);
1768 NOKPROBE_SYMBOL(perf_event_nmi_handler);
1770 struct event_constraint emptyconstraint;
1771 struct event_constraint unconstrained;
1773 static int x86_pmu_prepare_cpu(unsigned int cpu)
1775 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1778 for (i = 0 ; i < X86_PERF_KFREE_MAX; i++)
1779 cpuc->kfree_on_online[i] = NULL;
1780 if (x86_pmu.cpu_prepare)
1781 return x86_pmu.cpu_prepare(cpu);
1785 static int x86_pmu_dead_cpu(unsigned int cpu)
1787 if (x86_pmu.cpu_dead)
1788 x86_pmu.cpu_dead(cpu);
1792 static int x86_pmu_online_cpu(unsigned int cpu)
1794 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1797 for (i = 0 ; i < X86_PERF_KFREE_MAX; i++) {
1798 kfree(cpuc->kfree_on_online[i]);
1799 cpuc->kfree_on_online[i] = NULL;
1804 static int x86_pmu_starting_cpu(unsigned int cpu)
1806 if (x86_pmu.cpu_starting)
1807 x86_pmu.cpu_starting(cpu);
1811 static int x86_pmu_dying_cpu(unsigned int cpu)
1813 if (x86_pmu.cpu_dying)
1814 x86_pmu.cpu_dying(cpu);
1818 static void __init pmu_check_apic(void)
1820 if (boot_cpu_has(X86_FEATURE_APIC))
1824 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1825 pr_info("no hardware sampling interrupt available.\n");
1828 * If we have a PMU initialized but no APIC
1829 * interrupts, we cannot sample hardware
1830 * events (user-space has to fall back and
1831 * sample via a hrtimer based software event):
1833 pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
1837 static struct attribute_group x86_pmu_format_group __ro_after_init = {
1842 ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr, char *page)
1844 struct perf_pmu_events_attr *pmu_attr =
1845 container_of(attr, struct perf_pmu_events_attr, attr);
1848 if (pmu_attr->id < x86_pmu.max_events)
1849 config = x86_pmu.event_map(pmu_attr->id);
1851 /* string trumps id */
1852 if (pmu_attr->event_str)
1853 return sprintf(page, "%s\n", pmu_attr->event_str);
1855 return x86_pmu.events_sysfs_show(page, config);
1857 EXPORT_SYMBOL_GPL(events_sysfs_show);
1859 ssize_t events_ht_sysfs_show(struct device *dev, struct device_attribute *attr,
1862 struct perf_pmu_events_ht_attr *pmu_attr =
1863 container_of(attr, struct perf_pmu_events_ht_attr, attr);
1866 * Report conditional events depending on Hyper-Threading.
1868 * This is overly conservative as usually the HT special
1869 * handling is not needed if the other CPU thread is idle.
1871 * Note this does not (and cannot) handle the case when thread
1872 * siblings are invisible, for example with virtualization
1873 * if they are owned by some other guest. The user tool
1874 * has to re-read when a thread sibling gets onlined later.
1876 return sprintf(page, "%s",
1877 topology_max_smt_threads() > 1 ?
1878 pmu_attr->event_str_ht :
1879 pmu_attr->event_str_noht);
1882 ssize_t events_hybrid_sysfs_show(struct device *dev,
1883 struct device_attribute *attr,
1886 struct perf_pmu_events_hybrid_attr *pmu_attr =
1887 container_of(attr, struct perf_pmu_events_hybrid_attr, attr);
1888 struct x86_hybrid_pmu *pmu;
1889 const char *str, *next_str;
1892 if (hweight64(pmu_attr->pmu_type) == 1)
1893 return sprintf(page, "%s", pmu_attr->event_str);
1896 * Hybrid PMUs may support the same event name, but with different
1897 * event encoding, e.g., the mem-loads event on an Atom PMU has
1898 * different event encoding from a Core PMU.
1900 * The event_str includes all event encodings. Each event encoding
1901 * is divided by ";". The order of the event encodings must follow
1902 * the order of the hybrid PMU index.
1904 pmu = container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
1906 str = pmu_attr->event_str;
1907 for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) {
1908 if (!(x86_pmu.hybrid_pmu[i].cpu_type & pmu_attr->pmu_type))
1910 if (x86_pmu.hybrid_pmu[i].cpu_type & pmu->cpu_type) {
1911 next_str = strchr(str, ';');
1913 return snprintf(page, next_str - str + 1, "%s", str);
1915 return sprintf(page, "%s", str);
1917 str = strchr(str, ';');
1923 EXPORT_SYMBOL_GPL(events_hybrid_sysfs_show);
1925 EVENT_ATTR(cpu-cycles, CPU_CYCLES );
1926 EVENT_ATTR(instructions, INSTRUCTIONS );
1927 EVENT_ATTR(cache-references, CACHE_REFERENCES );
1928 EVENT_ATTR(cache-misses, CACHE_MISSES );
1929 EVENT_ATTR(branch-instructions, BRANCH_INSTRUCTIONS );
1930 EVENT_ATTR(branch-misses, BRANCH_MISSES );
1931 EVENT_ATTR(bus-cycles, BUS_CYCLES );
1932 EVENT_ATTR(stalled-cycles-frontend, STALLED_CYCLES_FRONTEND );
1933 EVENT_ATTR(stalled-cycles-backend, STALLED_CYCLES_BACKEND );
1934 EVENT_ATTR(ref-cycles, REF_CPU_CYCLES );
1936 static struct attribute *empty_attrs;
1938 static struct attribute *events_attr[] = {
1939 EVENT_PTR(CPU_CYCLES),
1940 EVENT_PTR(INSTRUCTIONS),
1941 EVENT_PTR(CACHE_REFERENCES),
1942 EVENT_PTR(CACHE_MISSES),
1943 EVENT_PTR(BRANCH_INSTRUCTIONS),
1944 EVENT_PTR(BRANCH_MISSES),
1945 EVENT_PTR(BUS_CYCLES),
1946 EVENT_PTR(STALLED_CYCLES_FRONTEND),
1947 EVENT_PTR(STALLED_CYCLES_BACKEND),
1948 EVENT_PTR(REF_CPU_CYCLES),
1953 * Remove all undefined events (x86_pmu.event_map(id) == 0)
1954 * out of events_attr attributes.
1957 is_visible(struct kobject *kobj, struct attribute *attr, int idx)
1959 struct perf_pmu_events_attr *pmu_attr;
1961 if (idx >= x86_pmu.max_events)
1964 pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr.attr);
1966 return pmu_attr->event_str || x86_pmu.event_map(idx) ? attr->mode : 0;
1969 static struct attribute_group x86_pmu_events_group __ro_after_init = {
1971 .attrs = events_attr,
1972 .is_visible = is_visible,
1975 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event)
1977 u64 umask = (config & ARCH_PERFMON_EVENTSEL_UMASK) >> 8;
1978 u64 cmask = (config & ARCH_PERFMON_EVENTSEL_CMASK) >> 24;
1979 bool edge = (config & ARCH_PERFMON_EVENTSEL_EDGE);
1980 bool pc = (config & ARCH_PERFMON_EVENTSEL_PIN_CONTROL);
1981 bool any = (config & ARCH_PERFMON_EVENTSEL_ANY);
1982 bool inv = (config & ARCH_PERFMON_EVENTSEL_INV);
1986 * We have whole page size to spend and just little data
1987 * to write, so we can safely use sprintf.
1989 ret = sprintf(page, "event=0x%02llx", event);
1992 ret += sprintf(page + ret, ",umask=0x%02llx", umask);
1995 ret += sprintf(page + ret, ",edge");
1998 ret += sprintf(page + ret, ",pc");
2001 ret += sprintf(page + ret, ",any");
2004 ret += sprintf(page + ret, ",inv");
2007 ret += sprintf(page + ret, ",cmask=0x%02llx", cmask);
2009 ret += sprintf(page + ret, "\n");
2014 static struct attribute_group x86_pmu_attr_group;
2015 static struct attribute_group x86_pmu_caps_group;
2017 static void x86_pmu_static_call_update(void)
2019 static_call_update(x86_pmu_handle_irq, x86_pmu.handle_irq);
2020 static_call_update(x86_pmu_disable_all, x86_pmu.disable_all);
2021 static_call_update(x86_pmu_enable_all, x86_pmu.enable_all);
2022 static_call_update(x86_pmu_enable, x86_pmu.enable);
2023 static_call_update(x86_pmu_disable, x86_pmu.disable);
2025 static_call_update(x86_pmu_assign, x86_pmu.assign);
2027 static_call_update(x86_pmu_add, x86_pmu.add);
2028 static_call_update(x86_pmu_del, x86_pmu.del);
2029 static_call_update(x86_pmu_read, x86_pmu.read);
2031 static_call_update(x86_pmu_set_period, x86_pmu.set_period);
2032 static_call_update(x86_pmu_update, x86_pmu.update);
2034 static_call_update(x86_pmu_schedule_events, x86_pmu.schedule_events);
2035 static_call_update(x86_pmu_get_event_constraints, x86_pmu.get_event_constraints);
2036 static_call_update(x86_pmu_put_event_constraints, x86_pmu.put_event_constraints);
2038 static_call_update(x86_pmu_start_scheduling, x86_pmu.start_scheduling);
2039 static_call_update(x86_pmu_commit_scheduling, x86_pmu.commit_scheduling);
2040 static_call_update(x86_pmu_stop_scheduling, x86_pmu.stop_scheduling);
2042 static_call_update(x86_pmu_sched_task, x86_pmu.sched_task);
2043 static_call_update(x86_pmu_swap_task_ctx, x86_pmu.swap_task_ctx);
2045 static_call_update(x86_pmu_drain_pebs, x86_pmu.drain_pebs);
2046 static_call_update(x86_pmu_pebs_aliases, x86_pmu.pebs_aliases);
2048 static_call_update(x86_pmu_guest_get_msrs, x86_pmu.guest_get_msrs);
2051 static void _x86_pmu_read(struct perf_event *event)
2053 static_call(x86_pmu_update)(event);
2056 void x86_pmu_show_pmu_cap(int num_counters, int num_counters_fixed,
2059 pr_info("... version: %d\n", x86_pmu.version);
2060 pr_info("... bit width: %d\n", x86_pmu.cntval_bits);
2061 pr_info("... generic registers: %d\n", num_counters);
2062 pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask);
2063 pr_info("... max period: %016Lx\n", x86_pmu.max_period);
2064 pr_info("... fixed-purpose events: %lu\n",
2065 hweight64((((1ULL << num_counters_fixed) - 1)
2066 << INTEL_PMC_IDX_FIXED) & intel_ctrl));
2067 pr_info("... event mask: %016Lx\n", intel_ctrl);
2071 * The generic code is not hybrid friendly. The hybrid_pmu->pmu
2072 * of the first registered PMU is unconditionally assigned to
2073 * each possible cpuctx->ctx.pmu.
2074 * Update the correct hybrid PMU to the cpuctx->ctx.pmu.
2076 void x86_pmu_update_cpu_context(struct pmu *pmu, int cpu)
2078 struct perf_cpu_context *cpuctx;
2080 if (!pmu->pmu_cpu_context)
2083 cpuctx = per_cpu_ptr(pmu->pmu_cpu_context, cpu);
2084 cpuctx->ctx.pmu = pmu;
2087 static int __init init_hw_perf_events(void)
2089 struct x86_pmu_quirk *quirk;
2092 pr_info("Performance Events: ");
2094 switch (boot_cpu_data.x86_vendor) {
2095 case X86_VENDOR_INTEL:
2096 err = intel_pmu_init();
2098 case X86_VENDOR_AMD:
2099 err = amd_pmu_init();
2101 case X86_VENDOR_HYGON:
2102 err = amd_pmu_init();
2103 x86_pmu.name = "HYGON";
2105 case X86_VENDOR_ZHAOXIN:
2106 case X86_VENDOR_CENTAUR:
2107 err = zhaoxin_pmu_init();
2113 pr_cont("no PMU driver, software events only.\n");
2120 /* sanity check that the hardware exists or is emulated */
2121 if (!check_hw_exists(&pmu, x86_pmu.num_counters, x86_pmu.num_counters_fixed))
2124 pr_cont("%s PMU driver.\n", x86_pmu.name);
2126 x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */
2128 for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next)
2131 if (!x86_pmu.intel_ctrl)
2132 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
2134 perf_events_lapic_init();
2135 register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI");
2137 unconstrained = (struct event_constraint)
2138 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
2139 0, x86_pmu.num_counters, 0, 0);
2141 x86_pmu_format_group.attrs = x86_pmu.format_attrs;
2143 if (!x86_pmu.events_sysfs_show)
2144 x86_pmu_events_group.attrs = &empty_attrs;
2146 pmu.attr_update = x86_pmu.attr_update;
2149 x86_pmu_show_pmu_cap(x86_pmu.num_counters,
2150 x86_pmu.num_counters_fixed,
2151 x86_pmu.intel_ctrl);
2155 x86_pmu.read = _x86_pmu_read;
2157 if (!x86_pmu.guest_get_msrs)
2158 x86_pmu.guest_get_msrs = (void *)&__static_call_return0;
2160 if (!x86_pmu.set_period)
2161 x86_pmu.set_period = x86_perf_event_set_period;
2163 if (!x86_pmu.update)
2164 x86_pmu.update = x86_perf_event_update;
2166 x86_pmu_static_call_update();
2169 * Install callbacks. Core will call them for each online
2172 err = cpuhp_setup_state(CPUHP_PERF_X86_PREPARE, "perf/x86:prepare",
2173 x86_pmu_prepare_cpu, x86_pmu_dead_cpu);
2177 err = cpuhp_setup_state(CPUHP_AP_PERF_X86_STARTING,
2178 "perf/x86:starting", x86_pmu_starting_cpu,
2183 err = cpuhp_setup_state(CPUHP_AP_PERF_X86_ONLINE, "perf/x86:online",
2184 x86_pmu_online_cpu, NULL);
2189 err = perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
2193 u8 cpu_type = get_this_hybrid_cpu_type();
2194 struct x86_hybrid_pmu *hybrid_pmu;
2197 if (!cpu_type && x86_pmu.get_hybrid_cpu_type)
2198 cpu_type = x86_pmu.get_hybrid_cpu_type();
2200 for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) {
2201 hybrid_pmu = &x86_pmu.hybrid_pmu[i];
2203 hybrid_pmu->pmu = pmu;
2204 hybrid_pmu->pmu.type = -1;
2205 hybrid_pmu->pmu.attr_update = x86_pmu.attr_update;
2206 hybrid_pmu->pmu.capabilities |= PERF_PMU_CAP_HETEROGENEOUS_CPUS;
2207 hybrid_pmu->pmu.capabilities |= PERF_PMU_CAP_EXTENDED_HW_TYPE;
2209 err = perf_pmu_register(&hybrid_pmu->pmu, hybrid_pmu->name,
2210 (hybrid_pmu->cpu_type == hybrid_big) ? PERF_TYPE_RAW : -1);
2214 if (cpu_type == hybrid_pmu->cpu_type)
2215 x86_pmu_update_cpu_context(&hybrid_pmu->pmu, raw_smp_processor_id());
2218 if (i < x86_pmu.num_hybrid_pmus) {
2219 for (j = 0; j < i; j++)
2220 perf_pmu_unregister(&x86_pmu.hybrid_pmu[j].pmu);
2221 pr_warn("Failed to register hybrid PMUs\n");
2222 kfree(x86_pmu.hybrid_pmu);
2223 x86_pmu.hybrid_pmu = NULL;
2224 x86_pmu.num_hybrid_pmus = 0;
2232 cpuhp_remove_state(CPUHP_AP_PERF_X86_ONLINE);
2234 cpuhp_remove_state(CPUHP_AP_PERF_X86_STARTING);
2236 cpuhp_remove_state(CPUHP_PERF_X86_PREPARE);
2238 memset(&x86_pmu, 0, sizeof(x86_pmu));
2241 early_initcall(init_hw_perf_events);
2243 static void x86_pmu_read(struct perf_event *event)
2245 static_call(x86_pmu_read)(event);
2249 * Start group events scheduling transaction
2250 * Set the flag to make pmu::enable() not perform the
2251 * schedulability test, it will be performed at commit time
2253 * We only support PERF_PMU_TXN_ADD transactions. Save the
2254 * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD
2257 static void x86_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags)
2259 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2261 WARN_ON_ONCE(cpuc->txn_flags); /* txn already in flight */
2263 cpuc->txn_flags = txn_flags;
2264 if (txn_flags & ~PERF_PMU_TXN_ADD)
2267 perf_pmu_disable(pmu);
2268 __this_cpu_write(cpu_hw_events.n_txn, 0);
2269 __this_cpu_write(cpu_hw_events.n_txn_pair, 0);
2270 __this_cpu_write(cpu_hw_events.n_txn_metric, 0);
2274 * Stop group events scheduling transaction
2275 * Clear the flag and pmu::enable() will perform the
2276 * schedulability test.
2278 static void x86_pmu_cancel_txn(struct pmu *pmu)
2280 unsigned int txn_flags;
2281 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2283 WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */
2285 txn_flags = cpuc->txn_flags;
2286 cpuc->txn_flags = 0;
2287 if (txn_flags & ~PERF_PMU_TXN_ADD)
2291 * Truncate collected array by the number of events added in this
2292 * transaction. See x86_pmu_add() and x86_pmu_*_txn().
2294 __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn));
2295 __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn));
2296 __this_cpu_sub(cpu_hw_events.n_pair, __this_cpu_read(cpu_hw_events.n_txn_pair));
2297 __this_cpu_sub(cpu_hw_events.n_metric, __this_cpu_read(cpu_hw_events.n_txn_metric));
2298 perf_pmu_enable(pmu);
2302 * Commit group events scheduling transaction
2303 * Perform the group schedulability test as a whole
2304 * Return 0 if success
2306 * Does not cancel the transaction on failure; expects the caller to do this.
2308 static int x86_pmu_commit_txn(struct pmu *pmu)
2310 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2311 int assign[X86_PMC_IDX_MAX];
2314 WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */
2316 if (cpuc->txn_flags & ~PERF_PMU_TXN_ADD) {
2317 cpuc->txn_flags = 0;
2323 if (!x86_pmu_initialized())
2326 ret = static_call(x86_pmu_schedule_events)(cpuc, n, assign);
2331 * copy new assignment, now we know it is possible
2332 * will be used by hw_perf_enable()
2334 memcpy(cpuc->assign, assign, n*sizeof(int));
2336 cpuc->txn_flags = 0;
2337 perf_pmu_enable(pmu);
2341 * a fake_cpuc is used to validate event groups. Due to
2342 * the extra reg logic, we need to also allocate a fake
2343 * per_core and per_cpu structure. Otherwise, group events
2344 * using extra reg may conflict without the kernel being
2345 * able to catch this when the last event gets added to
2348 static void free_fake_cpuc(struct cpu_hw_events *cpuc)
2350 intel_cpuc_finish(cpuc);
2354 static struct cpu_hw_events *allocate_fake_cpuc(struct pmu *event_pmu)
2356 struct cpu_hw_events *cpuc;
2359 cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL);
2361 return ERR_PTR(-ENOMEM);
2365 struct x86_hybrid_pmu *h_pmu;
2367 h_pmu = hybrid_pmu(event_pmu);
2368 if (cpumask_empty(&h_pmu->supported_cpus))
2370 cpu = cpumask_first(&h_pmu->supported_cpus);
2372 cpu = raw_smp_processor_id();
2373 cpuc->pmu = event_pmu;
2375 if (intel_cpuc_prepare(cpuc, cpu))
2380 free_fake_cpuc(cpuc);
2381 return ERR_PTR(-ENOMEM);
2385 * validate that we can schedule this event
2387 static int validate_event(struct perf_event *event)
2389 struct cpu_hw_events *fake_cpuc;
2390 struct event_constraint *c;
2393 fake_cpuc = allocate_fake_cpuc(event->pmu);
2394 if (IS_ERR(fake_cpuc))
2395 return PTR_ERR(fake_cpuc);
2397 c = x86_pmu.get_event_constraints(fake_cpuc, 0, event);
2399 if (!c || !c->weight)
2402 if (x86_pmu.put_event_constraints)
2403 x86_pmu.put_event_constraints(fake_cpuc, event);
2405 free_fake_cpuc(fake_cpuc);
2411 * validate a single event group
2413 * validation include:
2414 * - check events are compatible which each other
2415 * - events do not compete for the same counter
2416 * - number of events <= number of counters
2418 * validation ensures the group can be loaded onto the
2419 * PMU if it was the only group available.
2421 static int validate_group(struct perf_event *event)
2423 struct perf_event *leader = event->group_leader;
2424 struct cpu_hw_events *fake_cpuc;
2425 int ret = -EINVAL, n;
2428 * Reject events from different hybrid PMUs.
2431 struct perf_event *sibling;
2432 struct pmu *pmu = NULL;
2434 if (is_x86_event(leader))
2437 for_each_sibling_event(sibling, leader) {
2438 if (!is_x86_event(sibling))
2442 else if (pmu != sibling->pmu)
2447 fake_cpuc = allocate_fake_cpuc(event->pmu);
2448 if (IS_ERR(fake_cpuc))
2449 return PTR_ERR(fake_cpuc);
2451 * the event is not yet connected with its
2452 * siblings therefore we must first collect
2453 * existing siblings, then add the new event
2454 * before we can simulate the scheduling
2456 n = collect_events(fake_cpuc, leader, true);
2460 fake_cpuc->n_events = n;
2461 n = collect_events(fake_cpuc, event, false);
2465 fake_cpuc->n_events = 0;
2466 ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
2469 free_fake_cpuc(fake_cpuc);
2473 static int x86_pmu_event_init(struct perf_event *event)
2475 struct x86_hybrid_pmu *pmu = NULL;
2478 if ((event->attr.type != event->pmu->type) &&
2479 (event->attr.type != PERF_TYPE_HARDWARE) &&
2480 (event->attr.type != PERF_TYPE_HW_CACHE))
2483 if (is_hybrid() && (event->cpu != -1)) {
2484 pmu = hybrid_pmu(event->pmu);
2485 if (!cpumask_test_cpu(event->cpu, &pmu->supported_cpus))
2489 err = __x86_pmu_event_init(event);
2491 if (event->group_leader != event)
2492 err = validate_group(event);
2494 err = validate_event(event);
2498 event->destroy(event);
2499 event->destroy = NULL;
2502 if (READ_ONCE(x86_pmu.attr_rdpmc) &&
2503 !(event->hw.flags & PERF_X86_EVENT_LARGE_PEBS))
2504 event->hw.flags |= PERF_EVENT_FLAG_USER_READ_CNT;
2509 void perf_clear_dirty_counters(void)
2511 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2514 /* Don't need to clear the assigned counter. */
2515 for (i = 0; i < cpuc->n_events; i++)
2516 __clear_bit(cpuc->assign[i], cpuc->dirty);
2518 if (bitmap_empty(cpuc->dirty, X86_PMC_IDX_MAX))
2521 for_each_set_bit(i, cpuc->dirty, X86_PMC_IDX_MAX) {
2522 if (i >= INTEL_PMC_IDX_FIXED) {
2523 /* Metrics and fake events don't have corresponding HW counters. */
2524 if ((i - INTEL_PMC_IDX_FIXED) >= hybrid(cpuc->pmu, num_counters_fixed))
2527 wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + (i - INTEL_PMC_IDX_FIXED), 0);
2529 wrmsrl(x86_pmu_event_addr(i), 0);
2533 bitmap_zero(cpuc->dirty, X86_PMC_IDX_MAX);
2536 static void x86_pmu_event_mapped(struct perf_event *event, struct mm_struct *mm)
2538 if (!(event->hw.flags & PERF_EVENT_FLAG_USER_READ_CNT))
2542 * This function relies on not being called concurrently in two
2543 * tasks in the same mm. Otherwise one task could observe
2544 * perf_rdpmc_allowed > 1 and return all the way back to
2545 * userspace with CR4.PCE clear while another task is still
2546 * doing on_each_cpu_mask() to propagate CR4.PCE.
2548 * For now, this can't happen because all callers hold mmap_lock
2549 * for write. If this changes, we'll need a different solution.
2551 mmap_assert_write_locked(mm);
2553 if (atomic_inc_return(&mm->context.perf_rdpmc_allowed) == 1)
2554 on_each_cpu_mask(mm_cpumask(mm), cr4_update_pce, NULL, 1);
2557 static void x86_pmu_event_unmapped(struct perf_event *event, struct mm_struct *mm)
2559 if (!(event->hw.flags & PERF_EVENT_FLAG_USER_READ_CNT))
2562 if (atomic_dec_and_test(&mm->context.perf_rdpmc_allowed))
2563 on_each_cpu_mask(mm_cpumask(mm), cr4_update_pce, NULL, 1);
2566 static int x86_pmu_event_idx(struct perf_event *event)
2568 struct hw_perf_event *hwc = &event->hw;
2570 if (!(hwc->flags & PERF_EVENT_FLAG_USER_READ_CNT))
2573 if (is_metric_idx(hwc->idx))
2574 return INTEL_PMC_FIXED_RDPMC_METRICS + 1;
2576 return hwc->event_base_rdpmc + 1;
2579 static ssize_t get_attr_rdpmc(struct device *cdev,
2580 struct device_attribute *attr,
2583 return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc);
2586 static ssize_t set_attr_rdpmc(struct device *cdev,
2587 struct device_attribute *attr,
2588 const char *buf, size_t count)
2593 ret = kstrtoul(buf, 0, &val);
2600 if (x86_pmu.attr_rdpmc_broken)
2603 if (val != x86_pmu.attr_rdpmc) {
2605 * Changing into or out of never available or always available,
2606 * aka perf-event-bypassing mode. This path is extremely slow,
2607 * but only root can trigger it, so it's okay.
2610 static_branch_inc(&rdpmc_never_available_key);
2611 else if (x86_pmu.attr_rdpmc == 0)
2612 static_branch_dec(&rdpmc_never_available_key);
2615 static_branch_inc(&rdpmc_always_available_key);
2616 else if (x86_pmu.attr_rdpmc == 2)
2617 static_branch_dec(&rdpmc_always_available_key);
2619 on_each_cpu(cr4_update_pce, NULL, 1);
2620 x86_pmu.attr_rdpmc = val;
2626 static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc);
2628 static struct attribute *x86_pmu_attrs[] = {
2629 &dev_attr_rdpmc.attr,
2633 static struct attribute_group x86_pmu_attr_group __ro_after_init = {
2634 .attrs = x86_pmu_attrs,
2637 static ssize_t max_precise_show(struct device *cdev,
2638 struct device_attribute *attr,
2641 return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu_max_precise());
2644 static DEVICE_ATTR_RO(max_precise);
2646 static struct attribute *x86_pmu_caps_attrs[] = {
2647 &dev_attr_max_precise.attr,
2651 static struct attribute_group x86_pmu_caps_group __ro_after_init = {
2653 .attrs = x86_pmu_caps_attrs,
2656 static const struct attribute_group *x86_pmu_attr_groups[] = {
2657 &x86_pmu_attr_group,
2658 &x86_pmu_format_group,
2659 &x86_pmu_events_group,
2660 &x86_pmu_caps_group,
2664 static void x86_pmu_sched_task(struct perf_event_context *ctx, bool sched_in)
2666 static_call_cond(x86_pmu_sched_task)(ctx, sched_in);
2669 static void x86_pmu_swap_task_ctx(struct perf_event_context *prev,
2670 struct perf_event_context *next)
2672 static_call_cond(x86_pmu_swap_task_ctx)(prev, next);
2675 void perf_check_microcode(void)
2677 if (x86_pmu.check_microcode)
2678 x86_pmu.check_microcode();
2681 static int x86_pmu_check_period(struct perf_event *event, u64 value)
2683 if (x86_pmu.check_period && x86_pmu.check_period(event, value))
2686 if (value && x86_pmu.limit_period) {
2687 if (x86_pmu.limit_period(event, value) > value)
2694 static int x86_pmu_aux_output_match(struct perf_event *event)
2696 if (!(pmu.capabilities & PERF_PMU_CAP_AUX_OUTPUT))
2699 if (x86_pmu.aux_output_match)
2700 return x86_pmu.aux_output_match(event);
2705 static int x86_pmu_filter_match(struct perf_event *event)
2707 if (x86_pmu.filter_match)
2708 return x86_pmu.filter_match(event);
2713 static struct pmu pmu = {
2714 .pmu_enable = x86_pmu_enable,
2715 .pmu_disable = x86_pmu_disable,
2717 .attr_groups = x86_pmu_attr_groups,
2719 .event_init = x86_pmu_event_init,
2721 .event_mapped = x86_pmu_event_mapped,
2722 .event_unmapped = x86_pmu_event_unmapped,
2726 .start = x86_pmu_start,
2727 .stop = x86_pmu_stop,
2728 .read = x86_pmu_read,
2730 .start_txn = x86_pmu_start_txn,
2731 .cancel_txn = x86_pmu_cancel_txn,
2732 .commit_txn = x86_pmu_commit_txn,
2734 .event_idx = x86_pmu_event_idx,
2735 .sched_task = x86_pmu_sched_task,
2736 .swap_task_ctx = x86_pmu_swap_task_ctx,
2737 .check_period = x86_pmu_check_period,
2739 .aux_output_match = x86_pmu_aux_output_match,
2741 .filter_match = x86_pmu_filter_match,
2744 void arch_perf_update_userpage(struct perf_event *event,
2745 struct perf_event_mmap_page *userpg, u64 now)
2747 struct cyc2ns_data data;
2750 userpg->cap_user_time = 0;
2751 userpg->cap_user_time_zero = 0;
2752 userpg->cap_user_rdpmc =
2753 !!(event->hw.flags & PERF_EVENT_FLAG_USER_READ_CNT);
2754 userpg->pmc_width = x86_pmu.cntval_bits;
2756 if (!using_native_sched_clock() || !sched_clock_stable())
2759 cyc2ns_read_begin(&data);
2761 offset = data.cyc2ns_offset + __sched_clock_offset;
2764 * Internal timekeeping for enabled/running/stopped times
2765 * is always in the local_clock domain.
2767 userpg->cap_user_time = 1;
2768 userpg->time_mult = data.cyc2ns_mul;
2769 userpg->time_shift = data.cyc2ns_shift;
2770 userpg->time_offset = offset - now;
2773 * cap_user_time_zero doesn't make sense when we're using a different
2774 * time base for the records.
2776 if (!event->attr.use_clockid) {
2777 userpg->cap_user_time_zero = 1;
2778 userpg->time_zero = offset;
2785 * Determine whether the regs were taken from an irq/exception handler rather
2786 * than from perf_arch_fetch_caller_regs().
2788 static bool perf_hw_regs(struct pt_regs *regs)
2790 return regs->flags & X86_EFLAGS_FIXED;
2794 perf_callchain_kernel(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs)
2796 struct unwind_state state;
2799 if (perf_guest_state()) {
2800 /* TODO: We don't support guest os callchain now */
2804 if (perf_callchain_store(entry, regs->ip))
2807 if (perf_hw_regs(regs))
2808 unwind_start(&state, current, regs, NULL);
2810 unwind_start(&state, current, NULL, (void *)regs->sp);
2812 for (; !unwind_done(&state); unwind_next_frame(&state)) {
2813 addr = unwind_get_return_address(&state);
2814 if (!addr || perf_callchain_store(entry, addr))
2820 valid_user_frame(const void __user *fp, unsigned long size)
2822 return __access_ok(fp, size);
2825 static unsigned long get_segment_base(unsigned int segment)
2827 struct desc_struct *desc;
2828 unsigned int idx = segment >> 3;
2830 if ((segment & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2831 #ifdef CONFIG_MODIFY_LDT_SYSCALL
2832 struct ldt_struct *ldt;
2834 /* IRQs are off, so this synchronizes with smp_store_release */
2835 ldt = READ_ONCE(current->active_mm->context.ldt);
2836 if (!ldt || idx >= ldt->nr_entries)
2839 desc = &ldt->entries[idx];
2844 if (idx >= GDT_ENTRIES)
2847 desc = raw_cpu_ptr(gdt_page.gdt) + idx;
2850 return get_desc_base(desc);
2853 #ifdef CONFIG_IA32_EMULATION
2855 #include <linux/compat.h>
2858 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry_ctx *entry)
2860 /* 32-bit process in 64-bit kernel. */
2861 unsigned long ss_base, cs_base;
2862 struct stack_frame_ia32 frame;
2863 const struct stack_frame_ia32 __user *fp;
2865 if (user_64bit_mode(regs))
2868 cs_base = get_segment_base(regs->cs);
2869 ss_base = get_segment_base(regs->ss);
2871 fp = compat_ptr(ss_base + regs->bp);
2872 pagefault_disable();
2873 while (entry->nr < entry->max_stack) {
2874 if (!valid_user_frame(fp, sizeof(frame)))
2877 if (__get_user(frame.next_frame, &fp->next_frame))
2879 if (__get_user(frame.return_address, &fp->return_address))
2882 perf_callchain_store(entry, cs_base + frame.return_address);
2883 fp = compat_ptr(ss_base + frame.next_frame);
2890 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry_ctx *entry)
2897 perf_callchain_user(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs)
2899 struct stack_frame frame;
2900 const struct stack_frame __user *fp;
2902 if (perf_guest_state()) {
2903 /* TODO: We don't support guest os callchain now */
2908 * We don't know what to do with VM86 stacks.. ignore them for now.
2910 if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM))
2913 fp = (void __user *)regs->bp;
2915 perf_callchain_store(entry, regs->ip);
2917 if (!nmi_uaccess_okay())
2920 if (perf_callchain_user32(regs, entry))
2923 pagefault_disable();
2924 while (entry->nr < entry->max_stack) {
2925 if (!valid_user_frame(fp, sizeof(frame)))
2928 if (__get_user(frame.next_frame, &fp->next_frame))
2930 if (__get_user(frame.return_address, &fp->return_address))
2933 perf_callchain_store(entry, frame.return_address);
2934 fp = (void __user *)frame.next_frame;
2940 * Deal with code segment offsets for the various execution modes:
2942 * VM86 - the good olde 16 bit days, where the linear address is
2943 * 20 bits and we use regs->ip + 0x10 * regs->cs.
2945 * IA32 - Where we need to look at GDT/LDT segment descriptor tables
2946 * to figure out what the 32bit base address is.
2948 * X32 - has TIF_X32 set, but is running in x86_64
2950 * X86_64 - CS,DS,SS,ES are all zero based.
2952 static unsigned long code_segment_base(struct pt_regs *regs)
2955 * For IA32 we look at the GDT/LDT segment base to convert the
2956 * effective IP to a linear address.
2959 #ifdef CONFIG_X86_32
2961 * If we are in VM86 mode, add the segment offset to convert to a
2964 if (regs->flags & X86_VM_MASK)
2965 return 0x10 * regs->cs;
2967 if (user_mode(regs) && regs->cs != __USER_CS)
2968 return get_segment_base(regs->cs);
2970 if (user_mode(regs) && !user_64bit_mode(regs) &&
2971 regs->cs != __USER32_CS)
2972 return get_segment_base(regs->cs);
2977 unsigned long perf_instruction_pointer(struct pt_regs *regs)
2979 if (perf_guest_state())
2980 return perf_guest_get_ip();
2982 return regs->ip + code_segment_base(regs);
2985 unsigned long perf_misc_flags(struct pt_regs *regs)
2987 unsigned int guest_state = perf_guest_state();
2991 if (guest_state & PERF_GUEST_USER)
2992 misc |= PERF_RECORD_MISC_GUEST_USER;
2994 misc |= PERF_RECORD_MISC_GUEST_KERNEL;
2996 if (user_mode(regs))
2997 misc |= PERF_RECORD_MISC_USER;
2999 misc |= PERF_RECORD_MISC_KERNEL;
3002 if (regs->flags & PERF_EFLAGS_EXACT)
3003 misc |= PERF_RECORD_MISC_EXACT_IP;
3008 void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
3010 if (!x86_pmu_initialized()) {
3011 memset(cap, 0, sizeof(*cap));
3015 cap->version = x86_pmu.version;
3017 * KVM doesn't support the hybrid PMU yet.
3018 * Return the common value in global x86_pmu,
3019 * which available for all cores.
3021 cap->num_counters_gp = x86_pmu.num_counters;
3022 cap->num_counters_fixed = x86_pmu.num_counters_fixed;
3023 cap->bit_width_gp = x86_pmu.cntval_bits;
3024 cap->bit_width_fixed = x86_pmu.cntval_bits;
3025 cap->events_mask = (unsigned int)x86_pmu.events_maskl;
3026 cap->events_mask_len = x86_pmu.events_mask_len;
3027 cap->pebs_ept = x86_pmu.pebs_ept;
3029 EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability);
3031 u64 perf_get_hw_event_config(int hw_event)
3033 int max = x86_pmu.max_events;
3036 return x86_pmu.event_map(array_index_nospec(hw_event, max));
3040 EXPORT_SYMBOL_GPL(perf_get_hw_event_config);