2 * Performance events x86 architecture code
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
16 #include <linux/capability.h>
17 #include <linux/notifier.h>
18 #include <linux/hardirq.h>
19 #include <linux/kprobes.h>
20 #include <linux/export.h>
21 #include <linux/init.h>
22 #include <linux/kdebug.h>
23 #include <linux/sched/mm.h>
24 #include <linux/sched/clock.h>
25 #include <linux/uaccess.h>
26 #include <linux/slab.h>
27 #include <linux/cpu.h>
28 #include <linux/bitops.h>
29 #include <linux/device.h>
30 #include <linux/nospec.h>
31 #include <linux/static_call.h>
34 #include <asm/stacktrace.h>
37 #include <asm/alternative.h>
38 #include <asm/mmu_context.h>
39 #include <asm/tlbflush.h>
40 #include <asm/timer.h>
43 #include <asm/unwind.h>
45 #include "perf_event.h"
47 struct x86_pmu x86_pmu __read_mostly;
48 static struct pmu pmu;
50 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
55 DEFINE_STATIC_KEY_FALSE(rdpmc_never_available_key);
56 DEFINE_STATIC_KEY_FALSE(rdpmc_always_available_key);
57 DEFINE_STATIC_KEY_FALSE(perf_is_hybrid);
60 * This here uses DEFINE_STATIC_CALL_NULL() to get a static_call defined
61 * from just a typename, as opposed to an actual function.
63 DEFINE_STATIC_CALL_NULL(x86_pmu_handle_irq, *x86_pmu.handle_irq);
64 DEFINE_STATIC_CALL_NULL(x86_pmu_disable_all, *x86_pmu.disable_all);
65 DEFINE_STATIC_CALL_NULL(x86_pmu_enable_all, *x86_pmu.enable_all);
66 DEFINE_STATIC_CALL_NULL(x86_pmu_enable, *x86_pmu.enable);
67 DEFINE_STATIC_CALL_NULL(x86_pmu_disable, *x86_pmu.disable);
69 DEFINE_STATIC_CALL_NULL(x86_pmu_add, *x86_pmu.add);
70 DEFINE_STATIC_CALL_NULL(x86_pmu_del, *x86_pmu.del);
71 DEFINE_STATIC_CALL_NULL(x86_pmu_read, *x86_pmu.read);
73 DEFINE_STATIC_CALL_NULL(x86_pmu_schedule_events, *x86_pmu.schedule_events);
74 DEFINE_STATIC_CALL_NULL(x86_pmu_get_event_constraints, *x86_pmu.get_event_constraints);
75 DEFINE_STATIC_CALL_NULL(x86_pmu_put_event_constraints, *x86_pmu.put_event_constraints);
77 DEFINE_STATIC_CALL_NULL(x86_pmu_start_scheduling, *x86_pmu.start_scheduling);
78 DEFINE_STATIC_CALL_NULL(x86_pmu_commit_scheduling, *x86_pmu.commit_scheduling);
79 DEFINE_STATIC_CALL_NULL(x86_pmu_stop_scheduling, *x86_pmu.stop_scheduling);
81 DEFINE_STATIC_CALL_NULL(x86_pmu_sched_task, *x86_pmu.sched_task);
82 DEFINE_STATIC_CALL_NULL(x86_pmu_swap_task_ctx, *x86_pmu.swap_task_ctx);
84 DEFINE_STATIC_CALL_NULL(x86_pmu_drain_pebs, *x86_pmu.drain_pebs);
85 DEFINE_STATIC_CALL_NULL(x86_pmu_pebs_aliases, *x86_pmu.pebs_aliases);
88 * This one is magic, it will get called even when PMU init fails (because
89 * there is no PMU), in which case it should simply return NULL.
91 DEFINE_STATIC_CALL_RET0(x86_pmu_guest_get_msrs, *x86_pmu.guest_get_msrs);
93 u64 __read_mostly hw_cache_event_ids
94 [PERF_COUNT_HW_CACHE_MAX]
95 [PERF_COUNT_HW_CACHE_OP_MAX]
96 [PERF_COUNT_HW_CACHE_RESULT_MAX];
97 u64 __read_mostly hw_cache_extra_regs
98 [PERF_COUNT_HW_CACHE_MAX]
99 [PERF_COUNT_HW_CACHE_OP_MAX]
100 [PERF_COUNT_HW_CACHE_RESULT_MAX];
103 * Propagate event elapsed time into the generic event.
104 * Can only be executed on the CPU where the event is active.
105 * Returns the delta events processed.
107 u64 x86_perf_event_update(struct perf_event *event)
109 struct hw_perf_event *hwc = &event->hw;
110 int shift = 64 - x86_pmu.cntval_bits;
111 u64 prev_raw_count, new_raw_count;
114 if (unlikely(!hwc->event_base))
117 if (unlikely(is_topdown_count(event)) && x86_pmu.update_topdown_event)
118 return x86_pmu.update_topdown_event(event);
121 * Careful: an NMI might modify the previous event value.
123 * Our tactic to handle this is to first atomically read and
124 * exchange a new raw count - then add that new-prev delta
125 * count to the generic event atomically:
128 prev_raw_count = local64_read(&hwc->prev_count);
129 rdpmcl(hwc->event_base_rdpmc, new_raw_count);
131 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
132 new_raw_count) != prev_raw_count)
136 * Now we have the new raw value and have updated the prev
137 * timestamp already. We can now calculate the elapsed delta
138 * (event-)time and add that to the generic event.
140 * Careful, not all hw sign-extends above the physical width
143 delta = (new_raw_count << shift) - (prev_raw_count << shift);
146 local64_add(delta, &event->count);
147 local64_sub(delta, &hwc->period_left);
149 return new_raw_count;
153 * Find and validate any extra registers to set up.
155 static int x86_pmu_extra_regs(u64 config, struct perf_event *event)
157 struct extra_reg *extra_regs = hybrid(event->pmu, extra_regs);
158 struct hw_perf_event_extra *reg;
159 struct extra_reg *er;
161 reg = &event->hw.extra_reg;
166 for (er = extra_regs; er->msr; er++) {
167 if (er->event != (config & er->config_mask))
169 if (event->attr.config1 & ~er->valid_mask)
171 /* Check if the extra msrs can be safely accessed*/
172 if (!er->extra_msr_access)
176 reg->config = event->attr.config1;
183 static atomic_t active_events;
184 static atomic_t pmc_refcount;
185 static DEFINE_MUTEX(pmc_reserve_mutex);
187 #ifdef CONFIG_X86_LOCAL_APIC
189 static inline int get_possible_num_counters(void)
191 int i, num_counters = x86_pmu.num_counters;
196 for (i = 0; i < x86_pmu.num_hybrid_pmus; i++)
197 num_counters = max_t(int, num_counters, x86_pmu.hybrid_pmu[i].num_counters);
202 static bool reserve_pmc_hardware(void)
204 int i, num_counters = get_possible_num_counters();
206 for (i = 0; i < num_counters; i++) {
207 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i)))
211 for (i = 0; i < num_counters; i++) {
212 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i)))
219 for (i--; i >= 0; i--)
220 release_evntsel_nmi(x86_pmu_config_addr(i));
225 for (i--; i >= 0; i--)
226 release_perfctr_nmi(x86_pmu_event_addr(i));
231 static void release_pmc_hardware(void)
233 int i, num_counters = get_possible_num_counters();
235 for (i = 0; i < num_counters; i++) {
236 release_perfctr_nmi(x86_pmu_event_addr(i));
237 release_evntsel_nmi(x86_pmu_config_addr(i));
243 static bool reserve_pmc_hardware(void) { return true; }
244 static void release_pmc_hardware(void) {}
248 bool check_hw_exists(struct pmu *pmu, int num_counters, int num_counters_fixed)
250 u64 val, val_fail = -1, val_new= ~0;
251 int i, reg, reg_fail = -1, ret = 0;
256 * Check to see if the BIOS enabled any of the counters, if so
259 for (i = 0; i < num_counters; i++) {
260 reg = x86_pmu_config_addr(i);
261 ret = rdmsrl_safe(reg, &val);
264 if (val & ARCH_PERFMON_EVENTSEL_ENABLE) {
273 if (num_counters_fixed) {
274 reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
275 ret = rdmsrl_safe(reg, &val);
278 for (i = 0; i < num_counters_fixed; i++) {
279 if (fixed_counter_disabled(i, pmu))
281 if (val & (0x03ULL << i*4)) {
290 * If all the counters are enabled, the below test will always
291 * fail. The tools will also become useless in this scenario.
292 * Just fail and disable the hardware counters.
295 if (reg_safe == -1) {
301 * Read the current value, change it and read it back to see if it
302 * matches, this is needed to detect certain hardware emulators
303 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
305 reg = x86_pmu_event_addr(reg_safe);
306 if (rdmsrl_safe(reg, &val))
309 ret = wrmsrl_safe(reg, val);
310 ret |= rdmsrl_safe(reg, &val_new);
311 if (ret || val != val_new)
315 * We still allow the PMU driver to operate:
318 pr_cont("Broken BIOS detected, complain to your hardware vendor.\n");
319 pr_err(FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n",
326 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
327 pr_cont("PMU not available due to virtualization, using software events only.\n");
329 pr_cont("Broken PMU hardware detected, using software events only.\n");
330 pr_err("Failed to access perfctr msr (MSR %x is %Lx)\n",
337 static void hw_perf_event_destroy(struct perf_event *event)
339 x86_release_hardware();
340 atomic_dec(&active_events);
343 void hw_perf_lbr_event_destroy(struct perf_event *event)
345 hw_perf_event_destroy(event);
347 /* undo the lbr/bts event accounting */
348 x86_del_exclusive(x86_lbr_exclusive_lbr);
351 static inline int x86_pmu_initialized(void)
353 return x86_pmu.handle_irq != NULL;
357 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event)
359 struct perf_event_attr *attr = &event->attr;
360 unsigned int cache_type, cache_op, cache_result;
363 config = attr->config;
365 cache_type = (config >> 0) & 0xff;
366 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
368 cache_type = array_index_nospec(cache_type, PERF_COUNT_HW_CACHE_MAX);
370 cache_op = (config >> 8) & 0xff;
371 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
373 cache_op = array_index_nospec(cache_op, PERF_COUNT_HW_CACHE_OP_MAX);
375 cache_result = (config >> 16) & 0xff;
376 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
378 cache_result = array_index_nospec(cache_result, PERF_COUNT_HW_CACHE_RESULT_MAX);
380 val = hybrid_var(event->pmu, hw_cache_event_ids)[cache_type][cache_op][cache_result];
388 attr->config1 = hybrid_var(event->pmu, hw_cache_extra_regs)[cache_type][cache_op][cache_result];
389 return x86_pmu_extra_regs(val, event);
392 int x86_reserve_hardware(void)
396 if (!atomic_inc_not_zero(&pmc_refcount)) {
397 mutex_lock(&pmc_reserve_mutex);
398 if (atomic_read(&pmc_refcount) == 0) {
399 if (!reserve_pmc_hardware())
402 reserve_ds_buffers();
405 atomic_inc(&pmc_refcount);
406 mutex_unlock(&pmc_reserve_mutex);
412 void x86_release_hardware(void)
414 if (atomic_dec_and_mutex_lock(&pmc_refcount, &pmc_reserve_mutex)) {
415 release_pmc_hardware();
416 release_ds_buffers();
417 release_lbr_buffers();
418 mutex_unlock(&pmc_reserve_mutex);
423 * Check if we can create event of a certain type (that no conflicting events
426 int x86_add_exclusive(unsigned int what)
431 * When lbr_pt_coexist we allow PT to coexist with either LBR or BTS.
432 * LBR and BTS are still mutually exclusive.
434 if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt)
437 if (!atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what])) {
438 mutex_lock(&pmc_reserve_mutex);
439 for (i = 0; i < ARRAY_SIZE(x86_pmu.lbr_exclusive); i++) {
440 if (i != what && atomic_read(&x86_pmu.lbr_exclusive[i]))
443 atomic_inc(&x86_pmu.lbr_exclusive[what]);
444 mutex_unlock(&pmc_reserve_mutex);
448 atomic_inc(&active_events);
452 mutex_unlock(&pmc_reserve_mutex);
456 void x86_del_exclusive(unsigned int what)
458 atomic_dec(&active_events);
461 * See the comment in x86_add_exclusive().
463 if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt)
466 atomic_dec(&x86_pmu.lbr_exclusive[what]);
469 int x86_setup_perfctr(struct perf_event *event)
471 struct perf_event_attr *attr = &event->attr;
472 struct hw_perf_event *hwc = &event->hw;
475 if (!is_sampling_event(event)) {
476 hwc->sample_period = x86_pmu.max_period;
477 hwc->last_period = hwc->sample_period;
478 local64_set(&hwc->period_left, hwc->sample_period);
481 if (attr->type == event->pmu->type)
482 return x86_pmu_extra_regs(event->attr.config, event);
484 if (attr->type == PERF_TYPE_HW_CACHE)
485 return set_ext_hw_attr(hwc, event);
487 if (attr->config >= x86_pmu.max_events)
490 attr->config = array_index_nospec((unsigned long)attr->config, x86_pmu.max_events);
495 config = x86_pmu.event_map(attr->config);
503 hwc->config |= config;
509 * check that branch_sample_type is compatible with
510 * settings needed for precise_ip > 1 which implies
511 * using the LBR to capture ALL taken branches at the
512 * priv levels of the measurement
514 static inline int precise_br_compat(struct perf_event *event)
516 u64 m = event->attr.branch_sample_type;
519 /* must capture all branches */
520 if (!(m & PERF_SAMPLE_BRANCH_ANY))
523 m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER;
525 if (!event->attr.exclude_user)
526 b |= PERF_SAMPLE_BRANCH_USER;
528 if (!event->attr.exclude_kernel)
529 b |= PERF_SAMPLE_BRANCH_KERNEL;
532 * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86
538 int x86_pmu_max_precise(void)
542 /* Support for constant skid */
543 if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) {
546 /* Support for IP fixup */
547 if (x86_pmu.lbr_nr || x86_pmu.intel_cap.pebs_format >= 2)
550 if (x86_pmu.pebs_prec_dist)
556 int x86_pmu_hw_config(struct perf_event *event)
558 if (event->attr.precise_ip) {
559 int precise = x86_pmu_max_precise();
561 if (event->attr.precise_ip > precise)
564 /* There's no sense in having PEBS for non sampling events: */
565 if (!is_sampling_event(event))
569 * check that PEBS LBR correction does not conflict with
570 * whatever the user is asking with attr->branch_sample_type
572 if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format < 2) {
573 u64 *br_type = &event->attr.branch_sample_type;
575 if (has_branch_stack(event)) {
576 if (!precise_br_compat(event))
579 /* branch_sample_type is compatible */
583 * user did not specify branch_sample_type
585 * For PEBS fixups, we capture all
586 * the branches at the priv level of the
589 *br_type = PERF_SAMPLE_BRANCH_ANY;
591 if (!event->attr.exclude_user)
592 *br_type |= PERF_SAMPLE_BRANCH_USER;
594 if (!event->attr.exclude_kernel)
595 *br_type |= PERF_SAMPLE_BRANCH_KERNEL;
599 if (event->attr.branch_sample_type & PERF_SAMPLE_BRANCH_CALL_STACK)
600 event->attach_state |= PERF_ATTACH_TASK_DATA;
604 * (keep 'enabled' bit clear for now)
606 event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
609 * Count user and OS events unless requested not to
611 if (!event->attr.exclude_user)
612 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
613 if (!event->attr.exclude_kernel)
614 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
616 if (event->attr.type == event->pmu->type)
617 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
619 if (event->attr.sample_period && x86_pmu.limit_period) {
620 if (x86_pmu.limit_period(event, event->attr.sample_period) >
621 event->attr.sample_period)
625 /* sample_regs_user never support XMM registers */
626 if (unlikely(event->attr.sample_regs_user & PERF_REG_EXTENDED_MASK))
629 * Besides the general purpose registers, XMM registers may
630 * be collected in PEBS on some platforms, e.g. Icelake
632 if (unlikely(event->attr.sample_regs_intr & PERF_REG_EXTENDED_MASK)) {
633 if (!(event->pmu->capabilities & PERF_PMU_CAP_EXTENDED_REGS))
636 if (!event->attr.precise_ip)
640 return x86_setup_perfctr(event);
644 * Setup the hardware configuration for a given attr_type
646 static int __x86_pmu_event_init(struct perf_event *event)
650 if (!x86_pmu_initialized())
653 err = x86_reserve_hardware();
657 atomic_inc(&active_events);
658 event->destroy = hw_perf_event_destroy;
661 event->hw.last_cpu = -1;
662 event->hw.last_tag = ~0ULL;
665 event->hw.extra_reg.idx = EXTRA_REG_NONE;
666 event->hw.branch_reg.idx = EXTRA_REG_NONE;
668 return x86_pmu.hw_config(event);
671 void x86_pmu_disable_all(void)
673 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
676 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
677 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
680 if (!test_bit(idx, cpuc->active_mask))
682 rdmsrl(x86_pmu_config_addr(idx), val);
683 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
685 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
686 wrmsrl(x86_pmu_config_addr(idx), val);
687 if (is_counter_pair(hwc))
688 wrmsrl(x86_pmu_config_addr(idx + 1), 0);
692 struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
694 return static_call(x86_pmu_guest_get_msrs)(nr);
696 EXPORT_SYMBOL_GPL(perf_guest_get_msrs);
699 * There may be PMI landing after enabled=0. The PMI hitting could be before or
702 * If PMI hits before disable_all, the PMU will be disabled in the NMI handler.
703 * It will not be re-enabled in the NMI handler again, because enabled=0. After
704 * handling the NMI, disable_all will be called, which will not change the
705 * state either. If PMI hits after disable_all, the PMU is already disabled
706 * before entering NMI handler. The NMI handler will not change the state
709 * So either situation is harmless.
711 static void x86_pmu_disable(struct pmu *pmu)
713 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
715 if (!x86_pmu_initialized())
725 static_call(x86_pmu_disable_all)();
728 void x86_pmu_enable_all(int added)
730 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
733 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
734 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
736 if (!test_bit(idx, cpuc->active_mask))
739 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
743 static inline int is_x86_event(struct perf_event *event)
748 return event->pmu == &pmu;
750 for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) {
751 if (event->pmu == &x86_pmu.hybrid_pmu[i].pmu)
758 struct pmu *x86_get_pmu(unsigned int cpu)
760 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
763 * All CPUs of the hybrid type have been offline.
764 * The x86_get_pmu() should not be invoked.
766 if (WARN_ON_ONCE(!cpuc->pmu))
772 * Event scheduler state:
774 * Assign events iterating over all events and counters, beginning
775 * with events with least weights first. Keep the current iterator
776 * state in struct sched_state.
780 int event; /* event index */
781 int counter; /* counter index */
782 int unassigned; /* number of events to be assigned left */
783 int nr_gp; /* number of GP counters used */
787 /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */
788 #define SCHED_STATES_MAX 2
795 struct event_constraint **constraints;
796 struct sched_state state;
797 struct sched_state saved[SCHED_STATES_MAX];
801 * Initialize iterator that runs through all events and counters.
803 static void perf_sched_init(struct perf_sched *sched, struct event_constraint **constraints,
804 int num, int wmin, int wmax, int gpmax)
808 memset(sched, 0, sizeof(*sched));
809 sched->max_events = num;
810 sched->max_weight = wmax;
811 sched->max_gp = gpmax;
812 sched->constraints = constraints;
814 for (idx = 0; idx < num; idx++) {
815 if (constraints[idx]->weight == wmin)
819 sched->state.event = idx; /* start with min weight */
820 sched->state.weight = wmin;
821 sched->state.unassigned = num;
824 static void perf_sched_save_state(struct perf_sched *sched)
826 if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX))
829 sched->saved[sched->saved_states] = sched->state;
830 sched->saved_states++;
833 static bool perf_sched_restore_state(struct perf_sched *sched)
835 if (!sched->saved_states)
838 sched->saved_states--;
839 sched->state = sched->saved[sched->saved_states];
841 /* this assignment didn't work out */
842 /* XXX broken vs EVENT_PAIR */
843 sched->state.used &= ~BIT_ULL(sched->state.counter);
845 /* try the next one */
846 sched->state.counter++;
852 * Select a counter for the current event to schedule. Return true on
855 static bool __perf_sched_find_counter(struct perf_sched *sched)
857 struct event_constraint *c;
860 if (!sched->state.unassigned)
863 if (sched->state.event >= sched->max_events)
866 c = sched->constraints[sched->state.event];
867 /* Prefer fixed purpose counters */
868 if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) {
869 idx = INTEL_PMC_IDX_FIXED;
870 for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) {
871 u64 mask = BIT_ULL(idx);
873 if (sched->state.used & mask)
876 sched->state.used |= mask;
881 /* Grab the first unused counter starting with idx */
882 idx = sched->state.counter;
883 for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) {
884 u64 mask = BIT_ULL(idx);
886 if (c->flags & PERF_X86_EVENT_PAIR)
889 if (sched->state.used & mask)
892 if (sched->state.nr_gp++ >= sched->max_gp)
895 sched->state.used |= mask;
902 sched->state.counter = idx;
905 perf_sched_save_state(sched);
910 static bool perf_sched_find_counter(struct perf_sched *sched)
912 while (!__perf_sched_find_counter(sched)) {
913 if (!perf_sched_restore_state(sched))
921 * Go through all unassigned events and find the next one to schedule.
922 * Take events with the least weight first. Return true on success.
924 static bool perf_sched_next_event(struct perf_sched *sched)
926 struct event_constraint *c;
928 if (!sched->state.unassigned || !--sched->state.unassigned)
933 sched->state.event++;
934 if (sched->state.event >= sched->max_events) {
936 sched->state.event = 0;
937 sched->state.weight++;
938 if (sched->state.weight > sched->max_weight)
941 c = sched->constraints[sched->state.event];
942 } while (c->weight != sched->state.weight);
944 sched->state.counter = 0; /* start with first counter */
950 * Assign a counter for each event.
952 int perf_assign_events(struct event_constraint **constraints, int n,
953 int wmin, int wmax, int gpmax, int *assign)
955 struct perf_sched sched;
957 perf_sched_init(&sched, constraints, n, wmin, wmax, gpmax);
960 if (!perf_sched_find_counter(&sched))
963 assign[sched.state.event] = sched.state.counter;
964 } while (perf_sched_next_event(&sched));
966 return sched.state.unassigned;
968 EXPORT_SYMBOL_GPL(perf_assign_events);
970 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
972 int num_counters = hybrid(cpuc->pmu, num_counters);
973 struct event_constraint *c;
974 struct perf_event *e;
975 int n0, i, wmin, wmax, unsched = 0;
976 struct hw_perf_event *hwc;
980 * Compute the number of events already present; see x86_pmu_add(),
981 * validate_group() and x86_pmu_commit_txn(). For the former two
982 * cpuc->n_events hasn't been updated yet, while for the latter
983 * cpuc->n_txn contains the number of events added in the current
987 if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
990 static_call_cond(x86_pmu_start_scheduling)(cpuc);
992 for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) {
993 c = cpuc->event_constraint[i];
996 * Previously scheduled events should have a cached constraint,
997 * while new events should not have one.
999 WARN_ON_ONCE((c && i >= n0) || (!c && i < n0));
1002 * Request constraints for new events; or for those events that
1003 * have a dynamic constraint -- for those the constraint can
1004 * change due to external factors (sibling state, allow_tfa).
1006 if (!c || (c->flags & PERF_X86_EVENT_DYNAMIC)) {
1007 c = static_call(x86_pmu_get_event_constraints)(cpuc, i, cpuc->event_list[i]);
1008 cpuc->event_constraint[i] = c;
1011 wmin = min(wmin, c->weight);
1012 wmax = max(wmax, c->weight);
1016 * fastpath, try to reuse previous register
1018 for (i = 0; i < n; i++) {
1021 hwc = &cpuc->event_list[i]->hw;
1022 c = cpuc->event_constraint[i];
1024 /* never assigned */
1028 /* constraint still honored */
1029 if (!test_bit(hwc->idx, c->idxmsk))
1032 mask = BIT_ULL(hwc->idx);
1033 if (is_counter_pair(hwc))
1036 /* not already used */
1037 if (used_mask & mask)
1043 assign[i] = hwc->idx;
1048 int gpmax = num_counters;
1051 * Do not allow scheduling of more than half the available
1054 * This helps avoid counter starvation of sibling thread by
1055 * ensuring at most half the counters cannot be in exclusive
1056 * mode. There is no designated counters for the limits. Any
1057 * N/2 counters can be used. This helps with events with
1058 * specific counter constraints.
1060 if (is_ht_workaround_enabled() && !cpuc->is_fake &&
1061 READ_ONCE(cpuc->excl_cntrs->exclusive_present))
1065 * Reduce the amount of available counters to allow fitting
1066 * the extra Merge events needed by large increment events.
1068 if (x86_pmu.flags & PMU_FL_PAIR) {
1069 gpmax = num_counters - cpuc->n_pair;
1070 WARN_ON(gpmax <= 0);
1073 unsched = perf_assign_events(cpuc->event_constraint, n, wmin,
1074 wmax, gpmax, assign);
1078 * In case of success (unsched = 0), mark events as committed,
1079 * so we do not put_constraint() in case new events are added
1080 * and fail to be scheduled
1082 * We invoke the lower level commit callback to lock the resource
1084 * We do not need to do all of this in case we are called to
1085 * validate an event group (assign == NULL)
1087 if (!unsched && assign) {
1088 for (i = 0; i < n; i++) {
1089 e = cpuc->event_list[i];
1090 static_call_cond(x86_pmu_commit_scheduling)(cpuc, i, assign[i]);
1093 for (i = n0; i < n; i++) {
1094 e = cpuc->event_list[i];
1097 * release events that failed scheduling
1099 static_call_cond(x86_pmu_put_event_constraints)(cpuc, e);
1101 cpuc->event_constraint[i] = NULL;
1105 static_call_cond(x86_pmu_stop_scheduling)(cpuc);
1107 return unsched ? -EINVAL : 0;
1110 static int add_nr_metric_event(struct cpu_hw_events *cpuc,
1111 struct perf_event *event)
1113 if (is_metric_event(event)) {
1114 if (cpuc->n_metric == INTEL_TD_METRIC_NUM)
1117 cpuc->n_txn_metric++;
1123 static void del_nr_metric_event(struct cpu_hw_events *cpuc,
1124 struct perf_event *event)
1126 if (is_metric_event(event))
1130 static int collect_event(struct cpu_hw_events *cpuc, struct perf_event *event,
1131 int max_count, int n)
1133 union perf_capabilities intel_cap = hybrid(cpuc->pmu, intel_cap);
1135 if (intel_cap.perf_metrics && add_nr_metric_event(cpuc, event))
1138 if (n >= max_count + cpuc->n_metric)
1141 cpuc->event_list[n] = event;
1142 if (is_counter_pair(&event->hw)) {
1151 * dogrp: true if must collect siblings events (group)
1152 * returns total number of events and error code
1154 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
1156 int num_counters = hybrid(cpuc->pmu, num_counters);
1157 int num_counters_fixed = hybrid(cpuc->pmu, num_counters_fixed);
1158 struct perf_event *event;
1161 max_count = num_counters + num_counters_fixed;
1163 /* current number of events already accepted */
1165 if (!cpuc->n_events)
1166 cpuc->pebs_output = 0;
1168 if (!cpuc->is_fake && leader->attr.precise_ip) {
1170 * For PEBS->PT, if !aux_event, the group leader (PT) went
1171 * away, the group was broken down and this singleton event
1172 * can't schedule any more.
1174 if (is_pebs_pt(leader) && !leader->aux_event)
1178 * pebs_output: 0: no PEBS so far, 1: PT, 2: DS
1180 if (cpuc->pebs_output &&
1181 cpuc->pebs_output != is_pebs_pt(leader) + 1)
1184 cpuc->pebs_output = is_pebs_pt(leader) + 1;
1187 if (is_x86_event(leader)) {
1188 if (collect_event(cpuc, leader, max_count, n))
1196 for_each_sibling_event(event, leader) {
1197 if (!is_x86_event(event) || event->state <= PERF_EVENT_STATE_OFF)
1200 if (collect_event(cpuc, event, max_count, n))
1208 static inline void x86_assign_hw_event(struct perf_event *event,
1209 struct cpu_hw_events *cpuc, int i)
1211 struct hw_perf_event *hwc = &event->hw;
1214 idx = hwc->idx = cpuc->assign[i];
1215 hwc->last_cpu = smp_processor_id();
1216 hwc->last_tag = ++cpuc->tags[i];
1219 case INTEL_PMC_IDX_FIXED_BTS:
1220 case INTEL_PMC_IDX_FIXED_VLBR:
1221 hwc->config_base = 0;
1222 hwc->event_base = 0;
1225 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END:
1226 /* All the metric events are mapped onto the fixed counter 3. */
1227 idx = INTEL_PMC_IDX_FIXED_SLOTS;
1229 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS-1:
1230 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
1231 hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 +
1232 (idx - INTEL_PMC_IDX_FIXED);
1233 hwc->event_base_rdpmc = (idx - INTEL_PMC_IDX_FIXED) |
1234 INTEL_PMC_FIXED_RDPMC_BASE;
1238 hwc->config_base = x86_pmu_config_addr(hwc->idx);
1239 hwc->event_base = x86_pmu_event_addr(hwc->idx);
1240 hwc->event_base_rdpmc = x86_pmu_rdpmc_index(hwc->idx);
1246 * x86_perf_rdpmc_index - Return PMC counter used for event
1247 * @event: the perf_event to which the PMC counter was assigned
1249 * The counter assigned to this performance event may change if interrupts
1250 * are enabled. This counter should thus never be used while interrupts are
1251 * enabled. Before this function is used to obtain the assigned counter the
1252 * event should be checked for validity using, for example,
1253 * perf_event_read_local(), within the same interrupt disabled section in
1254 * which this counter is planned to be used.
1256 * Return: The index of the performance monitoring counter assigned to
1259 int x86_perf_rdpmc_index(struct perf_event *event)
1261 lockdep_assert_irqs_disabled();
1263 return event->hw.event_base_rdpmc;
1266 static inline int match_prev_assignment(struct hw_perf_event *hwc,
1267 struct cpu_hw_events *cpuc,
1270 return hwc->idx == cpuc->assign[i] &&
1271 hwc->last_cpu == smp_processor_id() &&
1272 hwc->last_tag == cpuc->tags[i];
1275 static void x86_pmu_start(struct perf_event *event, int flags);
1277 static void x86_pmu_enable(struct pmu *pmu)
1279 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1280 struct perf_event *event;
1281 struct hw_perf_event *hwc;
1282 int i, added = cpuc->n_added;
1284 if (!x86_pmu_initialized())
1290 if (cpuc->n_added) {
1291 int n_running = cpuc->n_events - cpuc->n_added;
1293 * apply assignment obtained either from
1294 * hw_perf_group_sched_in() or x86_pmu_enable()
1296 * step1: save events moving to new counters
1298 for (i = 0; i < n_running; i++) {
1299 event = cpuc->event_list[i];
1303 * we can avoid reprogramming counter if:
1304 * - assigned same counter as last time
1305 * - running on same CPU as last time
1306 * - no other event has used the counter since
1308 if (hwc->idx == -1 ||
1309 match_prev_assignment(hwc, cpuc, i))
1313 * Ensure we don't accidentally enable a stopped
1314 * counter simply because we rescheduled.
1316 if (hwc->state & PERF_HES_STOPPED)
1317 hwc->state |= PERF_HES_ARCH;
1319 x86_pmu_stop(event, PERF_EF_UPDATE);
1323 * step2: reprogram moved events into new counters
1325 for (i = 0; i < cpuc->n_events; i++) {
1326 event = cpuc->event_list[i];
1329 if (!match_prev_assignment(hwc, cpuc, i))
1330 x86_assign_hw_event(event, cpuc, i);
1331 else if (i < n_running)
1334 if (hwc->state & PERF_HES_ARCH)
1337 x86_pmu_start(event, PERF_EF_RELOAD);
1340 perf_events_lapic_init();
1346 static_call(x86_pmu_enable_all)(added);
1349 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
1352 * Set the next IRQ period, based on the hwc->period_left value.
1353 * To be called with the event disabled in hw:
1355 int x86_perf_event_set_period(struct perf_event *event)
1357 struct hw_perf_event *hwc = &event->hw;
1358 s64 left = local64_read(&hwc->period_left);
1359 s64 period = hwc->sample_period;
1360 int ret = 0, idx = hwc->idx;
1362 if (unlikely(!hwc->event_base))
1365 if (unlikely(is_topdown_count(event)) &&
1366 x86_pmu.set_topdown_event_period)
1367 return x86_pmu.set_topdown_event_period(event);
1370 * If we are way outside a reasonable range then just skip forward:
1372 if (unlikely(left <= -period)) {
1374 local64_set(&hwc->period_left, left);
1375 hwc->last_period = period;
1379 if (unlikely(left <= 0)) {
1381 local64_set(&hwc->period_left, left);
1382 hwc->last_period = period;
1386 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
1388 if (unlikely(left < 2))
1391 if (left > x86_pmu.max_period)
1392 left = x86_pmu.max_period;
1394 if (x86_pmu.limit_period)
1395 left = x86_pmu.limit_period(event, left);
1397 per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
1400 * The hw event starts counting from this event offset,
1401 * mark it to be able to extra future deltas:
1403 local64_set(&hwc->prev_count, (u64)-left);
1405 wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
1408 * Sign extend the Merge event counter's upper 16 bits since
1409 * we currently declare a 48-bit counter width
1411 if (is_counter_pair(hwc))
1412 wrmsrl(x86_pmu_event_addr(idx + 1), 0xffff);
1415 * Due to erratum on certan cpu we need
1416 * a second write to be sure the register
1417 * is updated properly
1419 if (x86_pmu.perfctr_second_write) {
1420 wrmsrl(hwc->event_base,
1421 (u64)(-left) & x86_pmu.cntval_mask);
1424 perf_event_update_userpage(event);
1429 void x86_pmu_enable_event(struct perf_event *event)
1431 if (__this_cpu_read(cpu_hw_events.enabled))
1432 __x86_pmu_enable_event(&event->hw,
1433 ARCH_PERFMON_EVENTSEL_ENABLE);
1437 * Add a single event to the PMU.
1439 * The event is added to the group of enabled events
1440 * but only if it can be scheduled with existing events.
1442 static int x86_pmu_add(struct perf_event *event, int flags)
1444 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1445 struct hw_perf_event *hwc;
1446 int assign[X86_PMC_IDX_MAX];
1451 n0 = cpuc->n_events;
1452 ret = n = collect_events(cpuc, event, false);
1456 hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
1457 if (!(flags & PERF_EF_START))
1458 hwc->state |= PERF_HES_ARCH;
1461 * If group events scheduling transaction was started,
1462 * skip the schedulability test here, it will be performed
1463 * at commit time (->commit_txn) as a whole.
1465 * If commit fails, we'll call ->del() on all events
1466 * for which ->add() was called.
1468 if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
1471 ret = static_call(x86_pmu_schedule_events)(cpuc, n, assign);
1475 * copy new assignment, now we know it is possible
1476 * will be used by hw_perf_enable()
1478 memcpy(cpuc->assign, assign, n*sizeof(int));
1482 * Commit the collect_events() state. See x86_pmu_del() and
1486 cpuc->n_added += n - n0;
1487 cpuc->n_txn += n - n0;
1490 * This is before x86_pmu_enable() will call x86_pmu_start(),
1491 * so we enable LBRs before an event needs them etc..
1493 static_call_cond(x86_pmu_add)(event);
1500 static void x86_pmu_start(struct perf_event *event, int flags)
1502 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1503 int idx = event->hw.idx;
1505 if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
1508 if (WARN_ON_ONCE(idx == -1))
1511 if (flags & PERF_EF_RELOAD) {
1512 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1513 x86_perf_event_set_period(event);
1516 event->hw.state = 0;
1518 cpuc->events[idx] = event;
1519 __set_bit(idx, cpuc->active_mask);
1520 static_call(x86_pmu_enable)(event);
1521 perf_event_update_userpage(event);
1524 void perf_event_print_debug(void)
1526 u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1528 int cpu = smp_processor_id();
1529 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1530 int num_counters = hybrid(cpuc->pmu, num_counters);
1531 int num_counters_fixed = hybrid(cpuc->pmu, num_counters_fixed);
1532 struct event_constraint *pebs_constraints = hybrid(cpuc->pmu, pebs_constraints);
1533 unsigned long flags;
1539 local_irq_save(flags);
1541 if (x86_pmu.version >= 2) {
1542 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1543 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1544 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1545 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1548 pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl);
1549 pr_info("CPU#%d: status: %016llx\n", cpu, status);
1550 pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow);
1551 pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed);
1552 if (pebs_constraints) {
1553 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1554 pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs);
1556 if (x86_pmu.lbr_nr) {
1557 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
1558 pr_info("CPU#%d: debugctl: %016llx\n", cpu, debugctl);
1561 pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1563 for (idx = 0; idx < num_counters; idx++) {
1564 rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl);
1565 rdmsrl(x86_pmu_event_addr(idx), pmc_count);
1567 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1569 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1570 cpu, idx, pmc_ctrl);
1571 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1572 cpu, idx, pmc_count);
1573 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1574 cpu, idx, prev_left);
1576 for (idx = 0; idx < num_counters_fixed; idx++) {
1577 if (fixed_counter_disabled(idx, cpuc->pmu))
1579 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1581 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1582 cpu, idx, pmc_count);
1584 local_irq_restore(flags);
1587 void x86_pmu_stop(struct perf_event *event, int flags)
1589 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1590 struct hw_perf_event *hwc = &event->hw;
1592 if (test_bit(hwc->idx, cpuc->active_mask)) {
1593 static_call(x86_pmu_disable)(event);
1594 __clear_bit(hwc->idx, cpuc->active_mask);
1595 cpuc->events[hwc->idx] = NULL;
1596 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
1597 hwc->state |= PERF_HES_STOPPED;
1600 if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
1602 * Drain the remaining delta count out of a event
1603 * that we are disabling:
1605 x86_perf_event_update(event);
1606 hwc->state |= PERF_HES_UPTODATE;
1610 static void x86_pmu_del(struct perf_event *event, int flags)
1612 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1613 union perf_capabilities intel_cap = hybrid(cpuc->pmu, intel_cap);
1617 * If we're called during a txn, we only need to undo x86_pmu.add.
1618 * The events never got scheduled and ->cancel_txn will truncate
1621 * XXX assumes any ->del() called during a TXN will only be on
1622 * an event added during that same TXN.
1624 if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
1628 * Not a TXN, therefore cleanup properly.
1630 x86_pmu_stop(event, PERF_EF_UPDATE);
1632 for (i = 0; i < cpuc->n_events; i++) {
1633 if (event == cpuc->event_list[i])
1637 if (WARN_ON_ONCE(i == cpuc->n_events)) /* called ->del() without ->add() ? */
1640 /* If we have a newly added event; make sure to decrease n_added. */
1641 if (i >= cpuc->n_events - cpuc->n_added)
1644 static_call_cond(x86_pmu_put_event_constraints)(cpuc, event);
1646 /* Delete the array entry. */
1647 while (++i < cpuc->n_events) {
1648 cpuc->event_list[i-1] = cpuc->event_list[i];
1649 cpuc->event_constraint[i-1] = cpuc->event_constraint[i];
1651 cpuc->event_constraint[i-1] = NULL;
1653 if (intel_cap.perf_metrics)
1654 del_nr_metric_event(cpuc, event);
1656 perf_event_update_userpage(event);
1661 * This is after x86_pmu_stop(); so we disable LBRs after any
1662 * event can need them etc..
1664 static_call_cond(x86_pmu_del)(event);
1667 int x86_pmu_handle_irq(struct pt_regs *regs)
1669 struct perf_sample_data data;
1670 struct cpu_hw_events *cpuc;
1671 struct perf_event *event;
1672 int idx, handled = 0;
1675 cpuc = this_cpu_ptr(&cpu_hw_events);
1678 * Some chipsets need to unmask the LVTPC in a particular spot
1679 * inside the nmi handler. As a result, the unmasking was pushed
1680 * into all the nmi handlers.
1682 * This generic handler doesn't seem to have any issues where the
1683 * unmasking occurs so it was left at the top.
1685 apic_write(APIC_LVTPC, APIC_DM_NMI);
1687 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1688 if (!test_bit(idx, cpuc->active_mask))
1691 event = cpuc->events[idx];
1693 val = x86_perf_event_update(event);
1694 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1701 perf_sample_data_init(&data, 0, event->hw.last_period);
1703 if (!x86_perf_event_set_period(event))
1706 if (perf_event_overflow(event, &data, regs))
1707 x86_pmu_stop(event, 0);
1711 inc_irq_stat(apic_perf_irqs);
1716 void perf_events_lapic_init(void)
1718 if (!x86_pmu.apic || !x86_pmu_initialized())
1722 * Always use NMI for PMU
1724 apic_write(APIC_LVTPC, APIC_DM_NMI);
1728 perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs)
1735 * All PMUs/events that share this PMI handler should make sure to
1736 * increment active_events for their events.
1738 if (!atomic_read(&active_events))
1741 start_clock = sched_clock();
1742 ret = static_call(x86_pmu_handle_irq)(regs);
1743 finish_clock = sched_clock();
1745 perf_sample_event_took(finish_clock - start_clock);
1749 NOKPROBE_SYMBOL(perf_event_nmi_handler);
1751 struct event_constraint emptyconstraint;
1752 struct event_constraint unconstrained;
1754 static int x86_pmu_prepare_cpu(unsigned int cpu)
1756 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1759 for (i = 0 ; i < X86_PERF_KFREE_MAX; i++)
1760 cpuc->kfree_on_online[i] = NULL;
1761 if (x86_pmu.cpu_prepare)
1762 return x86_pmu.cpu_prepare(cpu);
1766 static int x86_pmu_dead_cpu(unsigned int cpu)
1768 if (x86_pmu.cpu_dead)
1769 x86_pmu.cpu_dead(cpu);
1773 static int x86_pmu_online_cpu(unsigned int cpu)
1775 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1778 for (i = 0 ; i < X86_PERF_KFREE_MAX; i++) {
1779 kfree(cpuc->kfree_on_online[i]);
1780 cpuc->kfree_on_online[i] = NULL;
1785 static int x86_pmu_starting_cpu(unsigned int cpu)
1787 if (x86_pmu.cpu_starting)
1788 x86_pmu.cpu_starting(cpu);
1792 static int x86_pmu_dying_cpu(unsigned int cpu)
1794 if (x86_pmu.cpu_dying)
1795 x86_pmu.cpu_dying(cpu);
1799 static void __init pmu_check_apic(void)
1801 if (boot_cpu_has(X86_FEATURE_APIC))
1805 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1806 pr_info("no hardware sampling interrupt available.\n");
1809 * If we have a PMU initialized but no APIC
1810 * interrupts, we cannot sample hardware
1811 * events (user-space has to fall back and
1812 * sample via a hrtimer based software event):
1814 pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
1818 static struct attribute_group x86_pmu_format_group __ro_after_init = {
1823 ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr, char *page)
1825 struct perf_pmu_events_attr *pmu_attr =
1826 container_of(attr, struct perf_pmu_events_attr, attr);
1829 if (pmu_attr->id < x86_pmu.max_events)
1830 config = x86_pmu.event_map(pmu_attr->id);
1832 /* string trumps id */
1833 if (pmu_attr->event_str)
1834 return sprintf(page, "%s", pmu_attr->event_str);
1836 return x86_pmu.events_sysfs_show(page, config);
1838 EXPORT_SYMBOL_GPL(events_sysfs_show);
1840 ssize_t events_ht_sysfs_show(struct device *dev, struct device_attribute *attr,
1843 struct perf_pmu_events_ht_attr *pmu_attr =
1844 container_of(attr, struct perf_pmu_events_ht_attr, attr);
1847 * Report conditional events depending on Hyper-Threading.
1849 * This is overly conservative as usually the HT special
1850 * handling is not needed if the other CPU thread is idle.
1852 * Note this does not (and cannot) handle the case when thread
1853 * siblings are invisible, for example with virtualization
1854 * if they are owned by some other guest. The user tool
1855 * has to re-read when a thread sibling gets onlined later.
1857 return sprintf(page, "%s",
1858 topology_max_smt_threads() > 1 ?
1859 pmu_attr->event_str_ht :
1860 pmu_attr->event_str_noht);
1863 ssize_t events_hybrid_sysfs_show(struct device *dev,
1864 struct device_attribute *attr,
1867 struct perf_pmu_events_hybrid_attr *pmu_attr =
1868 container_of(attr, struct perf_pmu_events_hybrid_attr, attr);
1869 struct x86_hybrid_pmu *pmu;
1870 const char *str, *next_str;
1873 if (hweight64(pmu_attr->pmu_type) == 1)
1874 return sprintf(page, "%s", pmu_attr->event_str);
1877 * Hybrid PMUs may support the same event name, but with different
1878 * event encoding, e.g., the mem-loads event on an Atom PMU has
1879 * different event encoding from a Core PMU.
1881 * The event_str includes all event encodings. Each event encoding
1882 * is divided by ";". The order of the event encodings must follow
1883 * the order of the hybrid PMU index.
1885 pmu = container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
1887 str = pmu_attr->event_str;
1888 for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) {
1889 if (!(x86_pmu.hybrid_pmu[i].cpu_type & pmu_attr->pmu_type))
1891 if (x86_pmu.hybrid_pmu[i].cpu_type & pmu->cpu_type) {
1892 next_str = strchr(str, ';');
1894 return snprintf(page, next_str - str + 1, "%s", str);
1896 return sprintf(page, "%s", str);
1898 str = strchr(str, ';');
1904 EXPORT_SYMBOL_GPL(events_hybrid_sysfs_show);
1906 EVENT_ATTR(cpu-cycles, CPU_CYCLES );
1907 EVENT_ATTR(instructions, INSTRUCTIONS );
1908 EVENT_ATTR(cache-references, CACHE_REFERENCES );
1909 EVENT_ATTR(cache-misses, CACHE_MISSES );
1910 EVENT_ATTR(branch-instructions, BRANCH_INSTRUCTIONS );
1911 EVENT_ATTR(branch-misses, BRANCH_MISSES );
1912 EVENT_ATTR(bus-cycles, BUS_CYCLES );
1913 EVENT_ATTR(stalled-cycles-frontend, STALLED_CYCLES_FRONTEND );
1914 EVENT_ATTR(stalled-cycles-backend, STALLED_CYCLES_BACKEND );
1915 EVENT_ATTR(ref-cycles, REF_CPU_CYCLES );
1917 static struct attribute *empty_attrs;
1919 static struct attribute *events_attr[] = {
1920 EVENT_PTR(CPU_CYCLES),
1921 EVENT_PTR(INSTRUCTIONS),
1922 EVENT_PTR(CACHE_REFERENCES),
1923 EVENT_PTR(CACHE_MISSES),
1924 EVENT_PTR(BRANCH_INSTRUCTIONS),
1925 EVENT_PTR(BRANCH_MISSES),
1926 EVENT_PTR(BUS_CYCLES),
1927 EVENT_PTR(STALLED_CYCLES_FRONTEND),
1928 EVENT_PTR(STALLED_CYCLES_BACKEND),
1929 EVENT_PTR(REF_CPU_CYCLES),
1934 * Remove all undefined events (x86_pmu.event_map(id) == 0)
1935 * out of events_attr attributes.
1938 is_visible(struct kobject *kobj, struct attribute *attr, int idx)
1940 struct perf_pmu_events_attr *pmu_attr;
1942 if (idx >= x86_pmu.max_events)
1945 pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr.attr);
1947 return pmu_attr->event_str || x86_pmu.event_map(idx) ? attr->mode : 0;
1950 static struct attribute_group x86_pmu_events_group __ro_after_init = {
1952 .attrs = events_attr,
1953 .is_visible = is_visible,
1956 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event)
1958 u64 umask = (config & ARCH_PERFMON_EVENTSEL_UMASK) >> 8;
1959 u64 cmask = (config & ARCH_PERFMON_EVENTSEL_CMASK) >> 24;
1960 bool edge = (config & ARCH_PERFMON_EVENTSEL_EDGE);
1961 bool pc = (config & ARCH_PERFMON_EVENTSEL_PIN_CONTROL);
1962 bool any = (config & ARCH_PERFMON_EVENTSEL_ANY);
1963 bool inv = (config & ARCH_PERFMON_EVENTSEL_INV);
1967 * We have whole page size to spend and just little data
1968 * to write, so we can safely use sprintf.
1970 ret = sprintf(page, "event=0x%02llx", event);
1973 ret += sprintf(page + ret, ",umask=0x%02llx", umask);
1976 ret += sprintf(page + ret, ",edge");
1979 ret += sprintf(page + ret, ",pc");
1982 ret += sprintf(page + ret, ",any");
1985 ret += sprintf(page + ret, ",inv");
1988 ret += sprintf(page + ret, ",cmask=0x%02llx", cmask);
1990 ret += sprintf(page + ret, "\n");
1995 static struct attribute_group x86_pmu_attr_group;
1996 static struct attribute_group x86_pmu_caps_group;
1998 static void x86_pmu_static_call_update(void)
2000 static_call_update(x86_pmu_handle_irq, x86_pmu.handle_irq);
2001 static_call_update(x86_pmu_disable_all, x86_pmu.disable_all);
2002 static_call_update(x86_pmu_enable_all, x86_pmu.enable_all);
2003 static_call_update(x86_pmu_enable, x86_pmu.enable);
2004 static_call_update(x86_pmu_disable, x86_pmu.disable);
2006 static_call_update(x86_pmu_add, x86_pmu.add);
2007 static_call_update(x86_pmu_del, x86_pmu.del);
2008 static_call_update(x86_pmu_read, x86_pmu.read);
2010 static_call_update(x86_pmu_schedule_events, x86_pmu.schedule_events);
2011 static_call_update(x86_pmu_get_event_constraints, x86_pmu.get_event_constraints);
2012 static_call_update(x86_pmu_put_event_constraints, x86_pmu.put_event_constraints);
2014 static_call_update(x86_pmu_start_scheduling, x86_pmu.start_scheduling);
2015 static_call_update(x86_pmu_commit_scheduling, x86_pmu.commit_scheduling);
2016 static_call_update(x86_pmu_stop_scheduling, x86_pmu.stop_scheduling);
2018 static_call_update(x86_pmu_sched_task, x86_pmu.sched_task);
2019 static_call_update(x86_pmu_swap_task_ctx, x86_pmu.swap_task_ctx);
2021 static_call_update(x86_pmu_drain_pebs, x86_pmu.drain_pebs);
2022 static_call_update(x86_pmu_pebs_aliases, x86_pmu.pebs_aliases);
2024 static_call_update(x86_pmu_guest_get_msrs, x86_pmu.guest_get_msrs);
2027 static void _x86_pmu_read(struct perf_event *event)
2029 x86_perf_event_update(event);
2032 void x86_pmu_show_pmu_cap(int num_counters, int num_counters_fixed,
2035 pr_info("... version: %d\n", x86_pmu.version);
2036 pr_info("... bit width: %d\n", x86_pmu.cntval_bits);
2037 pr_info("... generic registers: %d\n", num_counters);
2038 pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask);
2039 pr_info("... max period: %016Lx\n", x86_pmu.max_period);
2040 pr_info("... fixed-purpose events: %lu\n",
2041 hweight64((((1ULL << num_counters_fixed) - 1)
2042 << INTEL_PMC_IDX_FIXED) & intel_ctrl));
2043 pr_info("... event mask: %016Lx\n", intel_ctrl);
2047 * The generic code is not hybrid friendly. The hybrid_pmu->pmu
2048 * of the first registered PMU is unconditionally assigned to
2049 * each possible cpuctx->ctx.pmu.
2050 * Update the correct hybrid PMU to the cpuctx->ctx.pmu.
2052 void x86_pmu_update_cpu_context(struct pmu *pmu, int cpu)
2054 struct perf_cpu_context *cpuctx;
2056 if (!pmu->pmu_cpu_context)
2059 cpuctx = per_cpu_ptr(pmu->pmu_cpu_context, cpu);
2060 cpuctx->ctx.pmu = pmu;
2063 static int __init init_hw_perf_events(void)
2065 struct x86_pmu_quirk *quirk;
2068 pr_info("Performance Events: ");
2070 switch (boot_cpu_data.x86_vendor) {
2071 case X86_VENDOR_INTEL:
2072 err = intel_pmu_init();
2074 case X86_VENDOR_AMD:
2075 err = amd_pmu_init();
2077 case X86_VENDOR_HYGON:
2078 err = amd_pmu_init();
2079 x86_pmu.name = "HYGON";
2081 case X86_VENDOR_ZHAOXIN:
2082 case X86_VENDOR_CENTAUR:
2083 err = zhaoxin_pmu_init();
2089 pr_cont("no PMU driver, software events only.\n");
2095 /* sanity check that the hardware exists or is emulated */
2096 if (!check_hw_exists(&pmu, x86_pmu.num_counters, x86_pmu.num_counters_fixed))
2099 pr_cont("%s PMU driver.\n", x86_pmu.name);
2101 x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */
2103 for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next)
2106 if (!x86_pmu.intel_ctrl)
2107 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
2109 perf_events_lapic_init();
2110 register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI");
2112 unconstrained = (struct event_constraint)
2113 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
2114 0, x86_pmu.num_counters, 0, 0);
2116 x86_pmu_format_group.attrs = x86_pmu.format_attrs;
2118 if (!x86_pmu.events_sysfs_show)
2119 x86_pmu_events_group.attrs = &empty_attrs;
2121 pmu.attr_update = x86_pmu.attr_update;
2124 x86_pmu_show_pmu_cap(x86_pmu.num_counters,
2125 x86_pmu.num_counters_fixed,
2126 x86_pmu.intel_ctrl);
2130 x86_pmu.read = _x86_pmu_read;
2132 if (!x86_pmu.guest_get_msrs)
2133 x86_pmu.guest_get_msrs = (void *)&__static_call_return0;
2135 x86_pmu_static_call_update();
2138 * Install callbacks. Core will call them for each online
2141 err = cpuhp_setup_state(CPUHP_PERF_X86_PREPARE, "perf/x86:prepare",
2142 x86_pmu_prepare_cpu, x86_pmu_dead_cpu);
2146 err = cpuhp_setup_state(CPUHP_AP_PERF_X86_STARTING,
2147 "perf/x86:starting", x86_pmu_starting_cpu,
2152 err = cpuhp_setup_state(CPUHP_AP_PERF_X86_ONLINE, "perf/x86:online",
2153 x86_pmu_online_cpu, NULL);
2158 err = perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
2162 u8 cpu_type = get_this_hybrid_cpu_type();
2163 struct x86_hybrid_pmu *hybrid_pmu;
2166 if (!cpu_type && x86_pmu.get_hybrid_cpu_type)
2167 cpu_type = x86_pmu.get_hybrid_cpu_type();
2169 for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) {
2170 hybrid_pmu = &x86_pmu.hybrid_pmu[i];
2172 hybrid_pmu->pmu = pmu;
2173 hybrid_pmu->pmu.type = -1;
2174 hybrid_pmu->pmu.attr_update = x86_pmu.attr_update;
2175 hybrid_pmu->pmu.capabilities |= PERF_PMU_CAP_HETEROGENEOUS_CPUS;
2176 hybrid_pmu->pmu.capabilities |= PERF_PMU_CAP_EXTENDED_HW_TYPE;
2178 err = perf_pmu_register(&hybrid_pmu->pmu, hybrid_pmu->name,
2179 (hybrid_pmu->cpu_type == hybrid_big) ? PERF_TYPE_RAW : -1);
2183 if (cpu_type == hybrid_pmu->cpu_type)
2184 x86_pmu_update_cpu_context(&hybrid_pmu->pmu, raw_smp_processor_id());
2187 if (i < x86_pmu.num_hybrid_pmus) {
2188 for (j = 0; j < i; j++)
2189 perf_pmu_unregister(&x86_pmu.hybrid_pmu[j].pmu);
2190 pr_warn("Failed to register hybrid PMUs\n");
2191 kfree(x86_pmu.hybrid_pmu);
2192 x86_pmu.hybrid_pmu = NULL;
2193 x86_pmu.num_hybrid_pmus = 0;
2201 cpuhp_remove_state(CPUHP_AP_PERF_X86_ONLINE);
2203 cpuhp_remove_state(CPUHP_AP_PERF_X86_STARTING);
2205 cpuhp_remove_state(CPUHP_PERF_X86_PREPARE);
2208 early_initcall(init_hw_perf_events);
2210 static void x86_pmu_read(struct perf_event *event)
2212 static_call(x86_pmu_read)(event);
2216 * Start group events scheduling transaction
2217 * Set the flag to make pmu::enable() not perform the
2218 * schedulability test, it will be performed at commit time
2220 * We only support PERF_PMU_TXN_ADD transactions. Save the
2221 * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD
2224 static void x86_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags)
2226 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2228 WARN_ON_ONCE(cpuc->txn_flags); /* txn already in flight */
2230 cpuc->txn_flags = txn_flags;
2231 if (txn_flags & ~PERF_PMU_TXN_ADD)
2234 perf_pmu_disable(pmu);
2235 __this_cpu_write(cpu_hw_events.n_txn, 0);
2236 __this_cpu_write(cpu_hw_events.n_txn_pair, 0);
2237 __this_cpu_write(cpu_hw_events.n_txn_metric, 0);
2241 * Stop group events scheduling transaction
2242 * Clear the flag and pmu::enable() will perform the
2243 * schedulability test.
2245 static void x86_pmu_cancel_txn(struct pmu *pmu)
2247 unsigned int txn_flags;
2248 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2250 WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */
2252 txn_flags = cpuc->txn_flags;
2253 cpuc->txn_flags = 0;
2254 if (txn_flags & ~PERF_PMU_TXN_ADD)
2258 * Truncate collected array by the number of events added in this
2259 * transaction. See x86_pmu_add() and x86_pmu_*_txn().
2261 __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn));
2262 __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn));
2263 __this_cpu_sub(cpu_hw_events.n_pair, __this_cpu_read(cpu_hw_events.n_txn_pair));
2264 __this_cpu_sub(cpu_hw_events.n_metric, __this_cpu_read(cpu_hw_events.n_txn_metric));
2265 perf_pmu_enable(pmu);
2269 * Commit group events scheduling transaction
2270 * Perform the group schedulability test as a whole
2271 * Return 0 if success
2273 * Does not cancel the transaction on failure; expects the caller to do this.
2275 static int x86_pmu_commit_txn(struct pmu *pmu)
2277 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2278 int assign[X86_PMC_IDX_MAX];
2281 WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */
2283 if (cpuc->txn_flags & ~PERF_PMU_TXN_ADD) {
2284 cpuc->txn_flags = 0;
2290 if (!x86_pmu_initialized())
2293 ret = static_call(x86_pmu_schedule_events)(cpuc, n, assign);
2298 * copy new assignment, now we know it is possible
2299 * will be used by hw_perf_enable()
2301 memcpy(cpuc->assign, assign, n*sizeof(int));
2303 cpuc->txn_flags = 0;
2304 perf_pmu_enable(pmu);
2308 * a fake_cpuc is used to validate event groups. Due to
2309 * the extra reg logic, we need to also allocate a fake
2310 * per_core and per_cpu structure. Otherwise, group events
2311 * using extra reg may conflict without the kernel being
2312 * able to catch this when the last event gets added to
2315 static void free_fake_cpuc(struct cpu_hw_events *cpuc)
2317 intel_cpuc_finish(cpuc);
2321 static struct cpu_hw_events *allocate_fake_cpuc(struct pmu *event_pmu)
2323 struct cpu_hw_events *cpuc;
2326 cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL);
2328 return ERR_PTR(-ENOMEM);
2332 struct x86_hybrid_pmu *h_pmu;
2334 h_pmu = hybrid_pmu(event_pmu);
2335 if (cpumask_empty(&h_pmu->supported_cpus))
2337 cpu = cpumask_first(&h_pmu->supported_cpus);
2339 cpu = raw_smp_processor_id();
2340 cpuc->pmu = event_pmu;
2342 if (intel_cpuc_prepare(cpuc, cpu))
2347 free_fake_cpuc(cpuc);
2348 return ERR_PTR(-ENOMEM);
2352 * validate that we can schedule this event
2354 static int validate_event(struct perf_event *event)
2356 struct cpu_hw_events *fake_cpuc;
2357 struct event_constraint *c;
2360 fake_cpuc = allocate_fake_cpuc(event->pmu);
2361 if (IS_ERR(fake_cpuc))
2362 return PTR_ERR(fake_cpuc);
2364 c = x86_pmu.get_event_constraints(fake_cpuc, 0, event);
2366 if (!c || !c->weight)
2369 if (x86_pmu.put_event_constraints)
2370 x86_pmu.put_event_constraints(fake_cpuc, event);
2372 free_fake_cpuc(fake_cpuc);
2378 * validate a single event group
2380 * validation include:
2381 * - check events are compatible which each other
2382 * - events do not compete for the same counter
2383 * - number of events <= number of counters
2385 * validation ensures the group can be loaded onto the
2386 * PMU if it was the only group available.
2388 static int validate_group(struct perf_event *event)
2390 struct perf_event *leader = event->group_leader;
2391 struct cpu_hw_events *fake_cpuc;
2392 int ret = -EINVAL, n;
2395 * Reject events from different hybrid PMUs.
2398 struct perf_event *sibling;
2399 struct pmu *pmu = NULL;
2401 if (is_x86_event(leader))
2404 for_each_sibling_event(sibling, leader) {
2405 if (!is_x86_event(sibling))
2409 else if (pmu != sibling->pmu)
2414 fake_cpuc = allocate_fake_cpuc(event->pmu);
2415 if (IS_ERR(fake_cpuc))
2416 return PTR_ERR(fake_cpuc);
2418 * the event is not yet connected with its
2419 * siblings therefore we must first collect
2420 * existing siblings, then add the new event
2421 * before we can simulate the scheduling
2423 n = collect_events(fake_cpuc, leader, true);
2427 fake_cpuc->n_events = n;
2428 n = collect_events(fake_cpuc, event, false);
2432 fake_cpuc->n_events = 0;
2433 ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
2436 free_fake_cpuc(fake_cpuc);
2440 static int x86_pmu_event_init(struct perf_event *event)
2442 struct x86_hybrid_pmu *pmu = NULL;
2445 if ((event->attr.type != event->pmu->type) &&
2446 (event->attr.type != PERF_TYPE_HARDWARE) &&
2447 (event->attr.type != PERF_TYPE_HW_CACHE))
2450 if (is_hybrid() && (event->cpu != -1)) {
2451 pmu = hybrid_pmu(event->pmu);
2452 if (!cpumask_test_cpu(event->cpu, &pmu->supported_cpus))
2456 err = __x86_pmu_event_init(event);
2458 if (event->group_leader != event)
2459 err = validate_group(event);
2461 err = validate_event(event);
2465 event->destroy(event);
2468 if (READ_ONCE(x86_pmu.attr_rdpmc) &&
2469 !(event->hw.flags & PERF_X86_EVENT_LARGE_PEBS))
2470 event->hw.flags |= PERF_X86_EVENT_RDPMC_ALLOWED;
2475 static void x86_pmu_event_mapped(struct perf_event *event, struct mm_struct *mm)
2477 if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
2481 * This function relies on not being called concurrently in two
2482 * tasks in the same mm. Otherwise one task could observe
2483 * perf_rdpmc_allowed > 1 and return all the way back to
2484 * userspace with CR4.PCE clear while another task is still
2485 * doing on_each_cpu_mask() to propagate CR4.PCE.
2487 * For now, this can't happen because all callers hold mmap_lock
2488 * for write. If this changes, we'll need a different solution.
2490 mmap_assert_write_locked(mm);
2492 if (atomic_inc_return(&mm->context.perf_rdpmc_allowed) == 1)
2493 on_each_cpu_mask(mm_cpumask(mm), cr4_update_pce, NULL, 1);
2496 static void x86_pmu_event_unmapped(struct perf_event *event, struct mm_struct *mm)
2499 if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
2502 if (atomic_dec_and_test(&mm->context.perf_rdpmc_allowed))
2503 on_each_cpu_mask(mm_cpumask(mm), cr4_update_pce, NULL, 1);
2506 static int x86_pmu_event_idx(struct perf_event *event)
2508 struct hw_perf_event *hwc = &event->hw;
2510 if (!(hwc->flags & PERF_X86_EVENT_RDPMC_ALLOWED))
2513 if (is_metric_idx(hwc->idx))
2514 return INTEL_PMC_FIXED_RDPMC_METRICS + 1;
2516 return hwc->event_base_rdpmc + 1;
2519 static ssize_t get_attr_rdpmc(struct device *cdev,
2520 struct device_attribute *attr,
2523 return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc);
2526 static ssize_t set_attr_rdpmc(struct device *cdev,
2527 struct device_attribute *attr,
2528 const char *buf, size_t count)
2533 ret = kstrtoul(buf, 0, &val);
2540 if (x86_pmu.attr_rdpmc_broken)
2543 if (val != x86_pmu.attr_rdpmc) {
2545 * Changing into or out of never available or always available,
2546 * aka perf-event-bypassing mode. This path is extremely slow,
2547 * but only root can trigger it, so it's okay.
2550 static_branch_inc(&rdpmc_never_available_key);
2551 else if (x86_pmu.attr_rdpmc == 0)
2552 static_branch_dec(&rdpmc_never_available_key);
2555 static_branch_inc(&rdpmc_always_available_key);
2556 else if (x86_pmu.attr_rdpmc == 2)
2557 static_branch_dec(&rdpmc_always_available_key);
2559 on_each_cpu(cr4_update_pce, NULL, 1);
2560 x86_pmu.attr_rdpmc = val;
2566 static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc);
2568 static struct attribute *x86_pmu_attrs[] = {
2569 &dev_attr_rdpmc.attr,
2573 static struct attribute_group x86_pmu_attr_group __ro_after_init = {
2574 .attrs = x86_pmu_attrs,
2577 static ssize_t max_precise_show(struct device *cdev,
2578 struct device_attribute *attr,
2581 return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu_max_precise());
2584 static DEVICE_ATTR_RO(max_precise);
2586 static struct attribute *x86_pmu_caps_attrs[] = {
2587 &dev_attr_max_precise.attr,
2591 static struct attribute_group x86_pmu_caps_group __ro_after_init = {
2593 .attrs = x86_pmu_caps_attrs,
2596 static const struct attribute_group *x86_pmu_attr_groups[] = {
2597 &x86_pmu_attr_group,
2598 &x86_pmu_format_group,
2599 &x86_pmu_events_group,
2600 &x86_pmu_caps_group,
2604 static void x86_pmu_sched_task(struct perf_event_context *ctx, bool sched_in)
2606 static_call_cond(x86_pmu_sched_task)(ctx, sched_in);
2609 static void x86_pmu_swap_task_ctx(struct perf_event_context *prev,
2610 struct perf_event_context *next)
2612 static_call_cond(x86_pmu_swap_task_ctx)(prev, next);
2615 void perf_check_microcode(void)
2617 if (x86_pmu.check_microcode)
2618 x86_pmu.check_microcode();
2621 static int x86_pmu_check_period(struct perf_event *event, u64 value)
2623 if (x86_pmu.check_period && x86_pmu.check_period(event, value))
2626 if (value && x86_pmu.limit_period) {
2627 if (x86_pmu.limit_period(event, value) > value)
2634 static int x86_pmu_aux_output_match(struct perf_event *event)
2636 if (!(pmu.capabilities & PERF_PMU_CAP_AUX_OUTPUT))
2639 if (x86_pmu.aux_output_match)
2640 return x86_pmu.aux_output_match(event);
2645 static int x86_pmu_filter_match(struct perf_event *event)
2647 if (x86_pmu.filter_match)
2648 return x86_pmu.filter_match(event);
2653 static struct pmu pmu = {
2654 .pmu_enable = x86_pmu_enable,
2655 .pmu_disable = x86_pmu_disable,
2657 .attr_groups = x86_pmu_attr_groups,
2659 .event_init = x86_pmu_event_init,
2661 .event_mapped = x86_pmu_event_mapped,
2662 .event_unmapped = x86_pmu_event_unmapped,
2666 .start = x86_pmu_start,
2667 .stop = x86_pmu_stop,
2668 .read = x86_pmu_read,
2670 .start_txn = x86_pmu_start_txn,
2671 .cancel_txn = x86_pmu_cancel_txn,
2672 .commit_txn = x86_pmu_commit_txn,
2674 .event_idx = x86_pmu_event_idx,
2675 .sched_task = x86_pmu_sched_task,
2676 .swap_task_ctx = x86_pmu_swap_task_ctx,
2677 .check_period = x86_pmu_check_period,
2679 .aux_output_match = x86_pmu_aux_output_match,
2681 .filter_match = x86_pmu_filter_match,
2684 void arch_perf_update_userpage(struct perf_event *event,
2685 struct perf_event_mmap_page *userpg, u64 now)
2687 struct cyc2ns_data data;
2690 userpg->cap_user_time = 0;
2691 userpg->cap_user_time_zero = 0;
2692 userpg->cap_user_rdpmc =
2693 !!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED);
2694 userpg->pmc_width = x86_pmu.cntval_bits;
2696 if (!using_native_sched_clock() || !sched_clock_stable())
2699 cyc2ns_read_begin(&data);
2701 offset = data.cyc2ns_offset + __sched_clock_offset;
2704 * Internal timekeeping for enabled/running/stopped times
2705 * is always in the local_clock domain.
2707 userpg->cap_user_time = 1;
2708 userpg->time_mult = data.cyc2ns_mul;
2709 userpg->time_shift = data.cyc2ns_shift;
2710 userpg->time_offset = offset - now;
2713 * cap_user_time_zero doesn't make sense when we're using a different
2714 * time base for the records.
2716 if (!event->attr.use_clockid) {
2717 userpg->cap_user_time_zero = 1;
2718 userpg->time_zero = offset;
2725 * Determine whether the regs were taken from an irq/exception handler rather
2726 * than from perf_arch_fetch_caller_regs().
2728 static bool perf_hw_regs(struct pt_regs *regs)
2730 return regs->flags & X86_EFLAGS_FIXED;
2734 perf_callchain_kernel(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs)
2736 struct unwind_state state;
2739 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2740 /* TODO: We don't support guest os callchain now */
2744 if (perf_callchain_store(entry, regs->ip))
2747 if (perf_hw_regs(regs))
2748 unwind_start(&state, current, regs, NULL);
2750 unwind_start(&state, current, NULL, (void *)regs->sp);
2752 for (; !unwind_done(&state); unwind_next_frame(&state)) {
2753 addr = unwind_get_return_address(&state);
2754 if (!addr || perf_callchain_store(entry, addr))
2760 valid_user_frame(const void __user *fp, unsigned long size)
2762 return (__range_not_ok(fp, size, TASK_SIZE) == 0);
2765 static unsigned long get_segment_base(unsigned int segment)
2767 struct desc_struct *desc;
2768 unsigned int idx = segment >> 3;
2770 if ((segment & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2771 #ifdef CONFIG_MODIFY_LDT_SYSCALL
2772 struct ldt_struct *ldt;
2774 /* IRQs are off, so this synchronizes with smp_store_release */
2775 ldt = READ_ONCE(current->active_mm->context.ldt);
2776 if (!ldt || idx >= ldt->nr_entries)
2779 desc = &ldt->entries[idx];
2784 if (idx >= GDT_ENTRIES)
2787 desc = raw_cpu_ptr(gdt_page.gdt) + idx;
2790 return get_desc_base(desc);
2793 #ifdef CONFIG_IA32_EMULATION
2795 #include <linux/compat.h>
2798 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry_ctx *entry)
2800 /* 32-bit process in 64-bit kernel. */
2801 unsigned long ss_base, cs_base;
2802 struct stack_frame_ia32 frame;
2803 const struct stack_frame_ia32 __user *fp;
2805 if (user_64bit_mode(regs))
2808 cs_base = get_segment_base(regs->cs);
2809 ss_base = get_segment_base(regs->ss);
2811 fp = compat_ptr(ss_base + regs->bp);
2812 pagefault_disable();
2813 while (entry->nr < entry->max_stack) {
2814 if (!valid_user_frame(fp, sizeof(frame)))
2817 if (__get_user(frame.next_frame, &fp->next_frame))
2819 if (__get_user(frame.return_address, &fp->return_address))
2822 perf_callchain_store(entry, cs_base + frame.return_address);
2823 fp = compat_ptr(ss_base + frame.next_frame);
2830 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry_ctx *entry)
2837 perf_callchain_user(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs)
2839 struct stack_frame frame;
2840 const struct stack_frame __user *fp;
2842 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2843 /* TODO: We don't support guest os callchain now */
2848 * We don't know what to do with VM86 stacks.. ignore them for now.
2850 if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM))
2853 fp = (void __user *)regs->bp;
2855 perf_callchain_store(entry, regs->ip);
2857 if (!nmi_uaccess_okay())
2860 if (perf_callchain_user32(regs, entry))
2863 pagefault_disable();
2864 while (entry->nr < entry->max_stack) {
2865 if (!valid_user_frame(fp, sizeof(frame)))
2868 if (__get_user(frame.next_frame, &fp->next_frame))
2870 if (__get_user(frame.return_address, &fp->return_address))
2873 perf_callchain_store(entry, frame.return_address);
2874 fp = (void __user *)frame.next_frame;
2880 * Deal with code segment offsets for the various execution modes:
2882 * VM86 - the good olde 16 bit days, where the linear address is
2883 * 20 bits and we use regs->ip + 0x10 * regs->cs.
2885 * IA32 - Where we need to look at GDT/LDT segment descriptor tables
2886 * to figure out what the 32bit base address is.
2888 * X32 - has TIF_X32 set, but is running in x86_64
2890 * X86_64 - CS,DS,SS,ES are all zero based.
2892 static unsigned long code_segment_base(struct pt_regs *regs)
2895 * For IA32 we look at the GDT/LDT segment base to convert the
2896 * effective IP to a linear address.
2899 #ifdef CONFIG_X86_32
2901 * If we are in VM86 mode, add the segment offset to convert to a
2904 if (regs->flags & X86_VM_MASK)
2905 return 0x10 * regs->cs;
2907 if (user_mode(regs) && regs->cs != __USER_CS)
2908 return get_segment_base(regs->cs);
2910 if (user_mode(regs) && !user_64bit_mode(regs) &&
2911 regs->cs != __USER32_CS)
2912 return get_segment_base(regs->cs);
2917 unsigned long perf_instruction_pointer(struct pt_regs *regs)
2919 if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
2920 return perf_guest_cbs->get_guest_ip();
2922 return regs->ip + code_segment_base(regs);
2925 unsigned long perf_misc_flags(struct pt_regs *regs)
2929 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2930 if (perf_guest_cbs->is_user_mode())
2931 misc |= PERF_RECORD_MISC_GUEST_USER;
2933 misc |= PERF_RECORD_MISC_GUEST_KERNEL;
2935 if (user_mode(regs))
2936 misc |= PERF_RECORD_MISC_USER;
2938 misc |= PERF_RECORD_MISC_KERNEL;
2941 if (regs->flags & PERF_EFLAGS_EXACT)
2942 misc |= PERF_RECORD_MISC_EXACT_IP;
2947 void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
2949 cap->version = x86_pmu.version;
2951 * KVM doesn't support the hybrid PMU yet.
2952 * Return the common value in global x86_pmu,
2953 * which available for all cores.
2955 cap->num_counters_gp = x86_pmu.num_counters;
2956 cap->num_counters_fixed = x86_pmu.num_counters_fixed;
2957 cap->bit_width_gp = x86_pmu.cntval_bits;
2958 cap->bit_width_fixed = x86_pmu.cntval_bits;
2959 cap->events_mask = (unsigned int)x86_pmu.events_maskl;
2960 cap->events_mask_len = x86_pmu.events_mask_len;
2962 EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability);