2 * Performance events x86 architecture code
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
16 #include <linux/capability.h>
17 #include <linux/notifier.h>
18 #include <linux/hardirq.h>
19 #include <linux/kprobes.h>
20 #include <linux/export.h>
21 #include <linux/init.h>
22 #include <linux/kdebug.h>
23 #include <linux/sched/mm.h>
24 #include <linux/sched/clock.h>
25 #include <linux/uaccess.h>
26 #include <linux/slab.h>
27 #include <linux/cpu.h>
28 #include <linux/bitops.h>
29 #include <linux/device.h>
30 #include <linux/nospec.h>
31 #include <linux/static_call.h>
34 #include <asm/stacktrace.h>
37 #include <asm/alternative.h>
38 #include <asm/mmu_context.h>
39 #include <asm/tlbflush.h>
40 #include <asm/timer.h>
43 #include <asm/unwind.h>
45 #include "perf_event.h"
47 struct x86_pmu x86_pmu __read_mostly;
49 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
53 DEFINE_STATIC_KEY_FALSE(rdpmc_never_available_key);
54 DEFINE_STATIC_KEY_FALSE(rdpmc_always_available_key);
57 * This here uses DEFINE_STATIC_CALL_NULL() to get a static_call defined
58 * from just a typename, as opposed to an actual function.
60 DEFINE_STATIC_CALL_NULL(x86_pmu_handle_irq, *x86_pmu.handle_irq);
61 DEFINE_STATIC_CALL_NULL(x86_pmu_disable_all, *x86_pmu.disable_all);
62 DEFINE_STATIC_CALL_NULL(x86_pmu_enable_all, *x86_pmu.enable_all);
63 DEFINE_STATIC_CALL_NULL(x86_pmu_enable, *x86_pmu.enable);
64 DEFINE_STATIC_CALL_NULL(x86_pmu_disable, *x86_pmu.disable);
66 DEFINE_STATIC_CALL_NULL(x86_pmu_add, *x86_pmu.add);
67 DEFINE_STATIC_CALL_NULL(x86_pmu_del, *x86_pmu.del);
68 DEFINE_STATIC_CALL_NULL(x86_pmu_read, *x86_pmu.read);
70 DEFINE_STATIC_CALL_NULL(x86_pmu_schedule_events, *x86_pmu.schedule_events);
71 DEFINE_STATIC_CALL_NULL(x86_pmu_get_event_constraints, *x86_pmu.get_event_constraints);
72 DEFINE_STATIC_CALL_NULL(x86_pmu_put_event_constraints, *x86_pmu.put_event_constraints);
74 DEFINE_STATIC_CALL_NULL(x86_pmu_start_scheduling, *x86_pmu.start_scheduling);
75 DEFINE_STATIC_CALL_NULL(x86_pmu_commit_scheduling, *x86_pmu.commit_scheduling);
76 DEFINE_STATIC_CALL_NULL(x86_pmu_stop_scheduling, *x86_pmu.stop_scheduling);
78 DEFINE_STATIC_CALL_NULL(x86_pmu_sched_task, *x86_pmu.sched_task);
79 DEFINE_STATIC_CALL_NULL(x86_pmu_swap_task_ctx, *x86_pmu.swap_task_ctx);
81 DEFINE_STATIC_CALL_NULL(x86_pmu_drain_pebs, *x86_pmu.drain_pebs);
82 DEFINE_STATIC_CALL_NULL(x86_pmu_pebs_aliases, *x86_pmu.pebs_aliases);
85 * This one is magic, it will get called even when PMU init fails (because
86 * there is no PMU), in which case it should simply return NULL.
88 DEFINE_STATIC_CALL_RET0(x86_pmu_guest_get_msrs, *x86_pmu.guest_get_msrs);
90 u64 __read_mostly hw_cache_event_ids
91 [PERF_COUNT_HW_CACHE_MAX]
92 [PERF_COUNT_HW_CACHE_OP_MAX]
93 [PERF_COUNT_HW_CACHE_RESULT_MAX];
94 u64 __read_mostly hw_cache_extra_regs
95 [PERF_COUNT_HW_CACHE_MAX]
96 [PERF_COUNT_HW_CACHE_OP_MAX]
97 [PERF_COUNT_HW_CACHE_RESULT_MAX];
100 * Propagate event elapsed time into the generic event.
101 * Can only be executed on the CPU where the event is active.
102 * Returns the delta events processed.
104 u64 x86_perf_event_update(struct perf_event *event)
106 struct hw_perf_event *hwc = &event->hw;
107 int shift = 64 - x86_pmu.cntval_bits;
108 u64 prev_raw_count, new_raw_count;
111 if (unlikely(!hwc->event_base))
114 if (unlikely(is_topdown_count(event)) && x86_pmu.update_topdown_event)
115 return x86_pmu.update_topdown_event(event);
118 * Careful: an NMI might modify the previous event value.
120 * Our tactic to handle this is to first atomically read and
121 * exchange a new raw count - then add that new-prev delta
122 * count to the generic event atomically:
125 prev_raw_count = local64_read(&hwc->prev_count);
126 rdpmcl(hwc->event_base_rdpmc, new_raw_count);
128 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
129 new_raw_count) != prev_raw_count)
133 * Now we have the new raw value and have updated the prev
134 * timestamp already. We can now calculate the elapsed delta
135 * (event-)time and add that to the generic event.
137 * Careful, not all hw sign-extends above the physical width
140 delta = (new_raw_count << shift) - (prev_raw_count << shift);
143 local64_add(delta, &event->count);
144 local64_sub(delta, &hwc->period_left);
146 return new_raw_count;
150 * Find and validate any extra registers to set up.
152 static int x86_pmu_extra_regs(u64 config, struct perf_event *event)
154 struct hw_perf_event_extra *reg;
155 struct extra_reg *er;
157 reg = &event->hw.extra_reg;
159 if (!x86_pmu.extra_regs)
162 for (er = x86_pmu.extra_regs; er->msr; er++) {
163 if (er->event != (config & er->config_mask))
165 if (event->attr.config1 & ~er->valid_mask)
167 /* Check if the extra msrs can be safely accessed*/
168 if (!er->extra_msr_access)
172 reg->config = event->attr.config1;
179 static atomic_t active_events;
180 static atomic_t pmc_refcount;
181 static DEFINE_MUTEX(pmc_reserve_mutex);
183 #ifdef CONFIG_X86_LOCAL_APIC
185 static bool reserve_pmc_hardware(void)
189 for (i = 0; i < x86_pmu.num_counters; i++) {
190 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i)))
194 for (i = 0; i < x86_pmu.num_counters; i++) {
195 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i)))
202 for (i--; i >= 0; i--)
203 release_evntsel_nmi(x86_pmu_config_addr(i));
205 i = x86_pmu.num_counters;
208 for (i--; i >= 0; i--)
209 release_perfctr_nmi(x86_pmu_event_addr(i));
214 static void release_pmc_hardware(void)
218 for (i = 0; i < x86_pmu.num_counters; i++) {
219 release_perfctr_nmi(x86_pmu_event_addr(i));
220 release_evntsel_nmi(x86_pmu_config_addr(i));
226 static bool reserve_pmc_hardware(void) { return true; }
227 static void release_pmc_hardware(void) {}
231 static bool check_hw_exists(void)
233 u64 val, val_fail = -1, val_new= ~0;
234 int i, reg, reg_fail = -1, ret = 0;
239 * Check to see if the BIOS enabled any of the counters, if so
242 for (i = 0; i < x86_pmu.num_counters; i++) {
243 reg = x86_pmu_config_addr(i);
244 ret = rdmsrl_safe(reg, &val);
247 if (val & ARCH_PERFMON_EVENTSEL_ENABLE) {
256 if (x86_pmu.num_counters_fixed) {
257 reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
258 ret = rdmsrl_safe(reg, &val);
261 for (i = 0; i < x86_pmu.num_counters_fixed; i++) {
262 if (fixed_counter_disabled(i))
264 if (val & (0x03 << i*4)) {
273 * If all the counters are enabled, the below test will always
274 * fail. The tools will also become useless in this scenario.
275 * Just fail and disable the hardware counters.
278 if (reg_safe == -1) {
284 * Read the current value, change it and read it back to see if it
285 * matches, this is needed to detect certain hardware emulators
286 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
288 reg = x86_pmu_event_addr(reg_safe);
289 if (rdmsrl_safe(reg, &val))
292 ret = wrmsrl_safe(reg, val);
293 ret |= rdmsrl_safe(reg, &val_new);
294 if (ret || val != val_new)
298 * We still allow the PMU driver to operate:
301 pr_cont("Broken BIOS detected, complain to your hardware vendor.\n");
302 pr_err(FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n",
309 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
310 pr_cont("PMU not available due to virtualization, using software events only.\n");
312 pr_cont("Broken PMU hardware detected, using software events only.\n");
313 pr_err("Failed to access perfctr msr (MSR %x is %Lx)\n",
320 static void hw_perf_event_destroy(struct perf_event *event)
322 x86_release_hardware();
323 atomic_dec(&active_events);
326 void hw_perf_lbr_event_destroy(struct perf_event *event)
328 hw_perf_event_destroy(event);
330 /* undo the lbr/bts event accounting */
331 x86_del_exclusive(x86_lbr_exclusive_lbr);
334 static inline int x86_pmu_initialized(void)
336 return x86_pmu.handle_irq != NULL;
340 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event)
342 struct perf_event_attr *attr = &event->attr;
343 unsigned int cache_type, cache_op, cache_result;
346 config = attr->config;
348 cache_type = (config >> 0) & 0xff;
349 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
351 cache_type = array_index_nospec(cache_type, PERF_COUNT_HW_CACHE_MAX);
353 cache_op = (config >> 8) & 0xff;
354 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
356 cache_op = array_index_nospec(cache_op, PERF_COUNT_HW_CACHE_OP_MAX);
358 cache_result = (config >> 16) & 0xff;
359 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
361 cache_result = array_index_nospec(cache_result, PERF_COUNT_HW_CACHE_RESULT_MAX);
363 val = hw_cache_event_ids[cache_type][cache_op][cache_result];
372 attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result];
373 return x86_pmu_extra_regs(val, event);
376 int x86_reserve_hardware(void)
380 if (!atomic_inc_not_zero(&pmc_refcount)) {
381 mutex_lock(&pmc_reserve_mutex);
382 if (atomic_read(&pmc_refcount) == 0) {
383 if (!reserve_pmc_hardware())
386 reserve_ds_buffers();
389 atomic_inc(&pmc_refcount);
390 mutex_unlock(&pmc_reserve_mutex);
396 void x86_release_hardware(void)
398 if (atomic_dec_and_mutex_lock(&pmc_refcount, &pmc_reserve_mutex)) {
399 release_pmc_hardware();
400 release_ds_buffers();
401 release_lbr_buffers();
402 mutex_unlock(&pmc_reserve_mutex);
407 * Check if we can create event of a certain type (that no conflicting events
410 int x86_add_exclusive(unsigned int what)
415 * When lbr_pt_coexist we allow PT to coexist with either LBR or BTS.
416 * LBR and BTS are still mutually exclusive.
418 if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt)
421 if (!atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what])) {
422 mutex_lock(&pmc_reserve_mutex);
423 for (i = 0; i < ARRAY_SIZE(x86_pmu.lbr_exclusive); i++) {
424 if (i != what && atomic_read(&x86_pmu.lbr_exclusive[i]))
427 atomic_inc(&x86_pmu.lbr_exclusive[what]);
428 mutex_unlock(&pmc_reserve_mutex);
432 atomic_inc(&active_events);
436 mutex_unlock(&pmc_reserve_mutex);
440 void x86_del_exclusive(unsigned int what)
442 atomic_dec(&active_events);
445 * See the comment in x86_add_exclusive().
447 if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt)
450 atomic_dec(&x86_pmu.lbr_exclusive[what]);
453 int x86_setup_perfctr(struct perf_event *event)
455 struct perf_event_attr *attr = &event->attr;
456 struct hw_perf_event *hwc = &event->hw;
459 if (!is_sampling_event(event)) {
460 hwc->sample_period = x86_pmu.max_period;
461 hwc->last_period = hwc->sample_period;
462 local64_set(&hwc->period_left, hwc->sample_period);
465 if (attr->type == PERF_TYPE_RAW)
466 return x86_pmu_extra_regs(event->attr.config, event);
468 if (attr->type == PERF_TYPE_HW_CACHE)
469 return set_ext_hw_attr(hwc, event);
471 if (attr->config >= x86_pmu.max_events)
474 attr->config = array_index_nospec((unsigned long)attr->config, x86_pmu.max_events);
479 config = x86_pmu.event_map(attr->config);
487 hwc->config |= config;
493 * check that branch_sample_type is compatible with
494 * settings needed for precise_ip > 1 which implies
495 * using the LBR to capture ALL taken branches at the
496 * priv levels of the measurement
498 static inline int precise_br_compat(struct perf_event *event)
500 u64 m = event->attr.branch_sample_type;
503 /* must capture all branches */
504 if (!(m & PERF_SAMPLE_BRANCH_ANY))
507 m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER;
509 if (!event->attr.exclude_user)
510 b |= PERF_SAMPLE_BRANCH_USER;
512 if (!event->attr.exclude_kernel)
513 b |= PERF_SAMPLE_BRANCH_KERNEL;
516 * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86
522 int x86_pmu_max_precise(void)
526 /* Support for constant skid */
527 if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) {
530 /* Support for IP fixup */
531 if (x86_pmu.lbr_nr || x86_pmu.intel_cap.pebs_format >= 2)
534 if (x86_pmu.pebs_prec_dist)
540 int x86_pmu_hw_config(struct perf_event *event)
542 if (event->attr.precise_ip) {
543 int precise = x86_pmu_max_precise();
545 if (event->attr.precise_ip > precise)
548 /* There's no sense in having PEBS for non sampling events: */
549 if (!is_sampling_event(event))
553 * check that PEBS LBR correction does not conflict with
554 * whatever the user is asking with attr->branch_sample_type
556 if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format < 2) {
557 u64 *br_type = &event->attr.branch_sample_type;
559 if (has_branch_stack(event)) {
560 if (!precise_br_compat(event))
563 /* branch_sample_type is compatible */
567 * user did not specify branch_sample_type
569 * For PEBS fixups, we capture all
570 * the branches at the priv level of the
573 *br_type = PERF_SAMPLE_BRANCH_ANY;
575 if (!event->attr.exclude_user)
576 *br_type |= PERF_SAMPLE_BRANCH_USER;
578 if (!event->attr.exclude_kernel)
579 *br_type |= PERF_SAMPLE_BRANCH_KERNEL;
583 if (event->attr.branch_sample_type & PERF_SAMPLE_BRANCH_CALL_STACK)
584 event->attach_state |= PERF_ATTACH_TASK_DATA;
588 * (keep 'enabled' bit clear for now)
590 event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
593 * Count user and OS events unless requested not to
595 if (!event->attr.exclude_user)
596 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
597 if (!event->attr.exclude_kernel)
598 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
600 if (event->attr.type == PERF_TYPE_RAW)
601 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
603 if (event->attr.sample_period && x86_pmu.limit_period) {
604 if (x86_pmu.limit_period(event, event->attr.sample_period) >
605 event->attr.sample_period)
609 /* sample_regs_user never support XMM registers */
610 if (unlikely(event->attr.sample_regs_user & PERF_REG_EXTENDED_MASK))
613 * Besides the general purpose registers, XMM registers may
614 * be collected in PEBS on some platforms, e.g. Icelake
616 if (unlikely(event->attr.sample_regs_intr & PERF_REG_EXTENDED_MASK)) {
617 if (!(event->pmu->capabilities & PERF_PMU_CAP_EXTENDED_REGS))
620 if (!event->attr.precise_ip)
624 return x86_setup_perfctr(event);
628 * Setup the hardware configuration for a given attr_type
630 static int __x86_pmu_event_init(struct perf_event *event)
634 if (!x86_pmu_initialized())
637 err = x86_reserve_hardware();
641 atomic_inc(&active_events);
642 event->destroy = hw_perf_event_destroy;
645 event->hw.last_cpu = -1;
646 event->hw.last_tag = ~0ULL;
649 event->hw.extra_reg.idx = EXTRA_REG_NONE;
650 event->hw.branch_reg.idx = EXTRA_REG_NONE;
652 return x86_pmu.hw_config(event);
655 void x86_pmu_disable_all(void)
657 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
660 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
661 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
664 if (!test_bit(idx, cpuc->active_mask))
666 rdmsrl(x86_pmu_config_addr(idx), val);
667 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
669 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
670 wrmsrl(x86_pmu_config_addr(idx), val);
671 if (is_counter_pair(hwc))
672 wrmsrl(x86_pmu_config_addr(idx + 1), 0);
676 struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
678 return static_call(x86_pmu_guest_get_msrs)(nr);
680 EXPORT_SYMBOL_GPL(perf_guest_get_msrs);
683 * There may be PMI landing after enabled=0. The PMI hitting could be before or
686 * If PMI hits before disable_all, the PMU will be disabled in the NMI handler.
687 * It will not be re-enabled in the NMI handler again, because enabled=0. After
688 * handling the NMI, disable_all will be called, which will not change the
689 * state either. If PMI hits after disable_all, the PMU is already disabled
690 * before entering NMI handler. The NMI handler will not change the state
693 * So either situation is harmless.
695 static void x86_pmu_disable(struct pmu *pmu)
697 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
699 if (!x86_pmu_initialized())
709 static_call(x86_pmu_disable_all)();
712 void x86_pmu_enable_all(int added)
714 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
717 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
718 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
720 if (!test_bit(idx, cpuc->active_mask))
723 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
727 static struct pmu pmu;
729 static inline int is_x86_event(struct perf_event *event)
731 return event->pmu == &pmu;
734 struct pmu *x86_get_pmu(void)
739 * Event scheduler state:
741 * Assign events iterating over all events and counters, beginning
742 * with events with least weights first. Keep the current iterator
743 * state in struct sched_state.
747 int event; /* event index */
748 int counter; /* counter index */
749 int unassigned; /* number of events to be assigned left */
750 int nr_gp; /* number of GP counters used */
754 /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */
755 #define SCHED_STATES_MAX 2
762 struct event_constraint **constraints;
763 struct sched_state state;
764 struct sched_state saved[SCHED_STATES_MAX];
768 * Initialize iterator that runs through all events and counters.
770 static void perf_sched_init(struct perf_sched *sched, struct event_constraint **constraints,
771 int num, int wmin, int wmax, int gpmax)
775 memset(sched, 0, sizeof(*sched));
776 sched->max_events = num;
777 sched->max_weight = wmax;
778 sched->max_gp = gpmax;
779 sched->constraints = constraints;
781 for (idx = 0; idx < num; idx++) {
782 if (constraints[idx]->weight == wmin)
786 sched->state.event = idx; /* start with min weight */
787 sched->state.weight = wmin;
788 sched->state.unassigned = num;
791 static void perf_sched_save_state(struct perf_sched *sched)
793 if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX))
796 sched->saved[sched->saved_states] = sched->state;
797 sched->saved_states++;
800 static bool perf_sched_restore_state(struct perf_sched *sched)
802 if (!sched->saved_states)
805 sched->saved_states--;
806 sched->state = sched->saved[sched->saved_states];
808 /* this assignment didn't work out */
809 /* XXX broken vs EVENT_PAIR */
810 sched->state.used &= ~BIT_ULL(sched->state.counter);
812 /* try the next one */
813 sched->state.counter++;
819 * Select a counter for the current event to schedule. Return true on
822 static bool __perf_sched_find_counter(struct perf_sched *sched)
824 struct event_constraint *c;
827 if (!sched->state.unassigned)
830 if (sched->state.event >= sched->max_events)
833 c = sched->constraints[sched->state.event];
834 /* Prefer fixed purpose counters */
835 if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) {
836 idx = INTEL_PMC_IDX_FIXED;
837 for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) {
838 u64 mask = BIT_ULL(idx);
840 if (sched->state.used & mask)
843 sched->state.used |= mask;
848 /* Grab the first unused counter starting with idx */
849 idx = sched->state.counter;
850 for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) {
851 u64 mask = BIT_ULL(idx);
853 if (c->flags & PERF_X86_EVENT_PAIR)
856 if (sched->state.used & mask)
859 if (sched->state.nr_gp++ >= sched->max_gp)
862 sched->state.used |= mask;
869 sched->state.counter = idx;
872 perf_sched_save_state(sched);
877 static bool perf_sched_find_counter(struct perf_sched *sched)
879 while (!__perf_sched_find_counter(sched)) {
880 if (!perf_sched_restore_state(sched))
888 * Go through all unassigned events and find the next one to schedule.
889 * Take events with the least weight first. Return true on success.
891 static bool perf_sched_next_event(struct perf_sched *sched)
893 struct event_constraint *c;
895 if (!sched->state.unassigned || !--sched->state.unassigned)
900 sched->state.event++;
901 if (sched->state.event >= sched->max_events) {
903 sched->state.event = 0;
904 sched->state.weight++;
905 if (sched->state.weight > sched->max_weight)
908 c = sched->constraints[sched->state.event];
909 } while (c->weight != sched->state.weight);
911 sched->state.counter = 0; /* start with first counter */
917 * Assign a counter for each event.
919 int perf_assign_events(struct event_constraint **constraints, int n,
920 int wmin, int wmax, int gpmax, int *assign)
922 struct perf_sched sched;
924 perf_sched_init(&sched, constraints, n, wmin, wmax, gpmax);
927 if (!perf_sched_find_counter(&sched))
930 assign[sched.state.event] = sched.state.counter;
931 } while (perf_sched_next_event(&sched));
933 return sched.state.unassigned;
935 EXPORT_SYMBOL_GPL(perf_assign_events);
937 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
939 struct event_constraint *c;
940 struct perf_event *e;
941 int n0, i, wmin, wmax, unsched = 0;
942 struct hw_perf_event *hwc;
946 * Compute the number of events already present; see x86_pmu_add(),
947 * validate_group() and x86_pmu_commit_txn(). For the former two
948 * cpuc->n_events hasn't been updated yet, while for the latter
949 * cpuc->n_txn contains the number of events added in the current
953 if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
956 static_call_cond(x86_pmu_start_scheduling)(cpuc);
958 for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) {
959 c = cpuc->event_constraint[i];
962 * Previously scheduled events should have a cached constraint,
963 * while new events should not have one.
965 WARN_ON_ONCE((c && i >= n0) || (!c && i < n0));
968 * Request constraints for new events; or for those events that
969 * have a dynamic constraint -- for those the constraint can
970 * change due to external factors (sibling state, allow_tfa).
972 if (!c || (c->flags & PERF_X86_EVENT_DYNAMIC)) {
973 c = static_call(x86_pmu_get_event_constraints)(cpuc, i, cpuc->event_list[i]);
974 cpuc->event_constraint[i] = c;
977 wmin = min(wmin, c->weight);
978 wmax = max(wmax, c->weight);
982 * fastpath, try to reuse previous register
984 for (i = 0; i < n; i++) {
987 hwc = &cpuc->event_list[i]->hw;
988 c = cpuc->event_constraint[i];
994 /* constraint still honored */
995 if (!test_bit(hwc->idx, c->idxmsk))
998 mask = BIT_ULL(hwc->idx);
999 if (is_counter_pair(hwc))
1002 /* not already used */
1003 if (used_mask & mask)
1009 assign[i] = hwc->idx;
1014 int gpmax = x86_pmu.num_counters;
1017 * Do not allow scheduling of more than half the available
1020 * This helps avoid counter starvation of sibling thread by
1021 * ensuring at most half the counters cannot be in exclusive
1022 * mode. There is no designated counters for the limits. Any
1023 * N/2 counters can be used. This helps with events with
1024 * specific counter constraints.
1026 if (is_ht_workaround_enabled() && !cpuc->is_fake &&
1027 READ_ONCE(cpuc->excl_cntrs->exclusive_present))
1031 * Reduce the amount of available counters to allow fitting
1032 * the extra Merge events needed by large increment events.
1034 if (x86_pmu.flags & PMU_FL_PAIR) {
1035 gpmax = x86_pmu.num_counters - cpuc->n_pair;
1036 WARN_ON(gpmax <= 0);
1039 unsched = perf_assign_events(cpuc->event_constraint, n, wmin,
1040 wmax, gpmax, assign);
1044 * In case of success (unsched = 0), mark events as committed,
1045 * so we do not put_constraint() in case new events are added
1046 * and fail to be scheduled
1048 * We invoke the lower level commit callback to lock the resource
1050 * We do not need to do all of this in case we are called to
1051 * validate an event group (assign == NULL)
1053 if (!unsched && assign) {
1054 for (i = 0; i < n; i++) {
1055 e = cpuc->event_list[i];
1056 static_call_cond(x86_pmu_commit_scheduling)(cpuc, i, assign[i]);
1059 for (i = n0; i < n; i++) {
1060 e = cpuc->event_list[i];
1063 * release events that failed scheduling
1065 static_call_cond(x86_pmu_put_event_constraints)(cpuc, e);
1067 cpuc->event_constraint[i] = NULL;
1071 static_call_cond(x86_pmu_stop_scheduling)(cpuc);
1073 return unsched ? -EINVAL : 0;
1076 static int add_nr_metric_event(struct cpu_hw_events *cpuc,
1077 struct perf_event *event)
1079 if (is_metric_event(event)) {
1080 if (cpuc->n_metric == INTEL_TD_METRIC_NUM)
1083 cpuc->n_txn_metric++;
1089 static void del_nr_metric_event(struct cpu_hw_events *cpuc,
1090 struct perf_event *event)
1092 if (is_metric_event(event))
1096 static int collect_event(struct cpu_hw_events *cpuc, struct perf_event *event,
1097 int max_count, int n)
1100 if (x86_pmu.intel_cap.perf_metrics && add_nr_metric_event(cpuc, event))
1103 if (n >= max_count + cpuc->n_metric)
1106 cpuc->event_list[n] = event;
1107 if (is_counter_pair(&event->hw)) {
1116 * dogrp: true if must collect siblings events (group)
1117 * returns total number of events and error code
1119 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
1121 struct perf_event *event;
1124 max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
1126 /* current number of events already accepted */
1128 if (!cpuc->n_events)
1129 cpuc->pebs_output = 0;
1131 if (!cpuc->is_fake && leader->attr.precise_ip) {
1133 * For PEBS->PT, if !aux_event, the group leader (PT) went
1134 * away, the group was broken down and this singleton event
1135 * can't schedule any more.
1137 if (is_pebs_pt(leader) && !leader->aux_event)
1141 * pebs_output: 0: no PEBS so far, 1: PT, 2: DS
1143 if (cpuc->pebs_output &&
1144 cpuc->pebs_output != is_pebs_pt(leader) + 1)
1147 cpuc->pebs_output = is_pebs_pt(leader) + 1;
1150 if (is_x86_event(leader)) {
1151 if (collect_event(cpuc, leader, max_count, n))
1159 for_each_sibling_event(event, leader) {
1160 if (!is_x86_event(event) || event->state <= PERF_EVENT_STATE_OFF)
1163 if (collect_event(cpuc, event, max_count, n))
1171 static inline void x86_assign_hw_event(struct perf_event *event,
1172 struct cpu_hw_events *cpuc, int i)
1174 struct hw_perf_event *hwc = &event->hw;
1177 idx = hwc->idx = cpuc->assign[i];
1178 hwc->last_cpu = smp_processor_id();
1179 hwc->last_tag = ++cpuc->tags[i];
1182 case INTEL_PMC_IDX_FIXED_BTS:
1183 case INTEL_PMC_IDX_FIXED_VLBR:
1184 hwc->config_base = 0;
1185 hwc->event_base = 0;
1188 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END:
1189 /* All the metric events are mapped onto the fixed counter 3. */
1190 idx = INTEL_PMC_IDX_FIXED_SLOTS;
1192 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS-1:
1193 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
1194 hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 +
1195 (idx - INTEL_PMC_IDX_FIXED);
1196 hwc->event_base_rdpmc = (idx - INTEL_PMC_IDX_FIXED) |
1197 INTEL_PMC_FIXED_RDPMC_BASE;
1201 hwc->config_base = x86_pmu_config_addr(hwc->idx);
1202 hwc->event_base = x86_pmu_event_addr(hwc->idx);
1203 hwc->event_base_rdpmc = x86_pmu_rdpmc_index(hwc->idx);
1209 * x86_perf_rdpmc_index - Return PMC counter used for event
1210 * @event: the perf_event to which the PMC counter was assigned
1212 * The counter assigned to this performance event may change if interrupts
1213 * are enabled. This counter should thus never be used while interrupts are
1214 * enabled. Before this function is used to obtain the assigned counter the
1215 * event should be checked for validity using, for example,
1216 * perf_event_read_local(), within the same interrupt disabled section in
1217 * which this counter is planned to be used.
1219 * Return: The index of the performance monitoring counter assigned to
1222 int x86_perf_rdpmc_index(struct perf_event *event)
1224 lockdep_assert_irqs_disabled();
1226 return event->hw.event_base_rdpmc;
1229 static inline int match_prev_assignment(struct hw_perf_event *hwc,
1230 struct cpu_hw_events *cpuc,
1233 return hwc->idx == cpuc->assign[i] &&
1234 hwc->last_cpu == smp_processor_id() &&
1235 hwc->last_tag == cpuc->tags[i];
1238 static void x86_pmu_start(struct perf_event *event, int flags);
1240 static void x86_pmu_enable(struct pmu *pmu)
1242 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1243 struct perf_event *event;
1244 struct hw_perf_event *hwc;
1245 int i, added = cpuc->n_added;
1247 if (!x86_pmu_initialized())
1253 if (cpuc->n_added) {
1254 int n_running = cpuc->n_events - cpuc->n_added;
1256 * apply assignment obtained either from
1257 * hw_perf_group_sched_in() or x86_pmu_enable()
1259 * step1: save events moving to new counters
1261 for (i = 0; i < n_running; i++) {
1262 event = cpuc->event_list[i];
1266 * we can avoid reprogramming counter if:
1267 * - assigned same counter as last time
1268 * - running on same CPU as last time
1269 * - no other event has used the counter since
1271 if (hwc->idx == -1 ||
1272 match_prev_assignment(hwc, cpuc, i))
1276 * Ensure we don't accidentally enable a stopped
1277 * counter simply because we rescheduled.
1279 if (hwc->state & PERF_HES_STOPPED)
1280 hwc->state |= PERF_HES_ARCH;
1282 x86_pmu_stop(event, PERF_EF_UPDATE);
1286 * step2: reprogram moved events into new counters
1288 for (i = 0; i < cpuc->n_events; i++) {
1289 event = cpuc->event_list[i];
1292 if (!match_prev_assignment(hwc, cpuc, i))
1293 x86_assign_hw_event(event, cpuc, i);
1294 else if (i < n_running)
1297 if (hwc->state & PERF_HES_ARCH)
1300 x86_pmu_start(event, PERF_EF_RELOAD);
1303 perf_events_lapic_init();
1309 static_call(x86_pmu_enable_all)(added);
1312 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
1315 * Set the next IRQ period, based on the hwc->period_left value.
1316 * To be called with the event disabled in hw:
1318 int x86_perf_event_set_period(struct perf_event *event)
1320 struct hw_perf_event *hwc = &event->hw;
1321 s64 left = local64_read(&hwc->period_left);
1322 s64 period = hwc->sample_period;
1323 int ret = 0, idx = hwc->idx;
1325 if (unlikely(!hwc->event_base))
1328 if (unlikely(is_topdown_count(event)) &&
1329 x86_pmu.set_topdown_event_period)
1330 return x86_pmu.set_topdown_event_period(event);
1333 * If we are way outside a reasonable range then just skip forward:
1335 if (unlikely(left <= -period)) {
1337 local64_set(&hwc->period_left, left);
1338 hwc->last_period = period;
1342 if (unlikely(left <= 0)) {
1344 local64_set(&hwc->period_left, left);
1345 hwc->last_period = period;
1349 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
1351 if (unlikely(left < 2))
1354 if (left > x86_pmu.max_period)
1355 left = x86_pmu.max_period;
1357 if (x86_pmu.limit_period)
1358 left = x86_pmu.limit_period(event, left);
1360 per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
1363 * The hw event starts counting from this event offset,
1364 * mark it to be able to extra future deltas:
1366 local64_set(&hwc->prev_count, (u64)-left);
1368 wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
1371 * Sign extend the Merge event counter's upper 16 bits since
1372 * we currently declare a 48-bit counter width
1374 if (is_counter_pair(hwc))
1375 wrmsrl(x86_pmu_event_addr(idx + 1), 0xffff);
1378 * Due to erratum on certan cpu we need
1379 * a second write to be sure the register
1380 * is updated properly
1382 if (x86_pmu.perfctr_second_write) {
1383 wrmsrl(hwc->event_base,
1384 (u64)(-left) & x86_pmu.cntval_mask);
1387 perf_event_update_userpage(event);
1392 void x86_pmu_enable_event(struct perf_event *event)
1394 if (__this_cpu_read(cpu_hw_events.enabled))
1395 __x86_pmu_enable_event(&event->hw,
1396 ARCH_PERFMON_EVENTSEL_ENABLE);
1400 * Add a single event to the PMU.
1402 * The event is added to the group of enabled events
1403 * but only if it can be scheduled with existing events.
1405 static int x86_pmu_add(struct perf_event *event, int flags)
1407 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1408 struct hw_perf_event *hwc;
1409 int assign[X86_PMC_IDX_MAX];
1414 n0 = cpuc->n_events;
1415 ret = n = collect_events(cpuc, event, false);
1419 hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
1420 if (!(flags & PERF_EF_START))
1421 hwc->state |= PERF_HES_ARCH;
1424 * If group events scheduling transaction was started,
1425 * skip the schedulability test here, it will be performed
1426 * at commit time (->commit_txn) as a whole.
1428 * If commit fails, we'll call ->del() on all events
1429 * for which ->add() was called.
1431 if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
1434 ret = static_call(x86_pmu_schedule_events)(cpuc, n, assign);
1438 * copy new assignment, now we know it is possible
1439 * will be used by hw_perf_enable()
1441 memcpy(cpuc->assign, assign, n*sizeof(int));
1445 * Commit the collect_events() state. See x86_pmu_del() and
1449 cpuc->n_added += n - n0;
1450 cpuc->n_txn += n - n0;
1453 * This is before x86_pmu_enable() will call x86_pmu_start(),
1454 * so we enable LBRs before an event needs them etc..
1456 static_call_cond(x86_pmu_add)(event);
1463 static void x86_pmu_start(struct perf_event *event, int flags)
1465 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1466 int idx = event->hw.idx;
1468 if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
1471 if (WARN_ON_ONCE(idx == -1))
1474 if (flags & PERF_EF_RELOAD) {
1475 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1476 x86_perf_event_set_period(event);
1479 event->hw.state = 0;
1481 cpuc->events[idx] = event;
1482 __set_bit(idx, cpuc->active_mask);
1483 __set_bit(idx, cpuc->running);
1484 static_call(x86_pmu_enable)(event);
1485 perf_event_update_userpage(event);
1488 void perf_event_print_debug(void)
1490 u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1492 struct cpu_hw_events *cpuc;
1493 unsigned long flags;
1496 if (!x86_pmu.num_counters)
1499 local_irq_save(flags);
1501 cpu = smp_processor_id();
1502 cpuc = &per_cpu(cpu_hw_events, cpu);
1504 if (x86_pmu.version >= 2) {
1505 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1506 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1507 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1508 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1511 pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl);
1512 pr_info("CPU#%d: status: %016llx\n", cpu, status);
1513 pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow);
1514 pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed);
1515 if (x86_pmu.pebs_constraints) {
1516 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1517 pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs);
1519 if (x86_pmu.lbr_nr) {
1520 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
1521 pr_info("CPU#%d: debugctl: %016llx\n", cpu, debugctl);
1524 pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1526 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1527 rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl);
1528 rdmsrl(x86_pmu_event_addr(idx), pmc_count);
1530 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1532 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1533 cpu, idx, pmc_ctrl);
1534 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1535 cpu, idx, pmc_count);
1536 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1537 cpu, idx, prev_left);
1539 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1540 if (fixed_counter_disabled(idx))
1542 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1544 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1545 cpu, idx, pmc_count);
1547 local_irq_restore(flags);
1550 void x86_pmu_stop(struct perf_event *event, int flags)
1552 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1553 struct hw_perf_event *hwc = &event->hw;
1555 if (test_bit(hwc->idx, cpuc->active_mask)) {
1556 static_call(x86_pmu_disable)(event);
1557 __clear_bit(hwc->idx, cpuc->active_mask);
1558 cpuc->events[hwc->idx] = NULL;
1559 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
1560 hwc->state |= PERF_HES_STOPPED;
1563 if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
1565 * Drain the remaining delta count out of a event
1566 * that we are disabling:
1568 x86_perf_event_update(event);
1569 hwc->state |= PERF_HES_UPTODATE;
1573 static void x86_pmu_del(struct perf_event *event, int flags)
1575 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1579 * If we're called during a txn, we only need to undo x86_pmu.add.
1580 * The events never got scheduled and ->cancel_txn will truncate
1583 * XXX assumes any ->del() called during a TXN will only be on
1584 * an event added during that same TXN.
1586 if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
1590 * Not a TXN, therefore cleanup properly.
1592 x86_pmu_stop(event, PERF_EF_UPDATE);
1594 for (i = 0; i < cpuc->n_events; i++) {
1595 if (event == cpuc->event_list[i])
1599 if (WARN_ON_ONCE(i == cpuc->n_events)) /* called ->del() without ->add() ? */
1602 /* If we have a newly added event; make sure to decrease n_added. */
1603 if (i >= cpuc->n_events - cpuc->n_added)
1606 static_call_cond(x86_pmu_put_event_constraints)(cpuc, event);
1608 /* Delete the array entry. */
1609 while (++i < cpuc->n_events) {
1610 cpuc->event_list[i-1] = cpuc->event_list[i];
1611 cpuc->event_constraint[i-1] = cpuc->event_constraint[i];
1613 cpuc->event_constraint[i-1] = NULL;
1615 if (x86_pmu.intel_cap.perf_metrics)
1616 del_nr_metric_event(cpuc, event);
1618 perf_event_update_userpage(event);
1623 * This is after x86_pmu_stop(); so we disable LBRs after any
1624 * event can need them etc..
1626 static_call_cond(x86_pmu_del)(event);
1629 int x86_pmu_handle_irq(struct pt_regs *regs)
1631 struct perf_sample_data data;
1632 struct cpu_hw_events *cpuc;
1633 struct perf_event *event;
1634 int idx, handled = 0;
1637 cpuc = this_cpu_ptr(&cpu_hw_events);
1640 * Some chipsets need to unmask the LVTPC in a particular spot
1641 * inside the nmi handler. As a result, the unmasking was pushed
1642 * into all the nmi handlers.
1644 * This generic handler doesn't seem to have any issues where the
1645 * unmasking occurs so it was left at the top.
1647 apic_write(APIC_LVTPC, APIC_DM_NMI);
1649 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1650 if (!test_bit(idx, cpuc->active_mask))
1653 event = cpuc->events[idx];
1655 val = x86_perf_event_update(event);
1656 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1663 perf_sample_data_init(&data, 0, event->hw.last_period);
1665 if (!x86_perf_event_set_period(event))
1668 if (perf_event_overflow(event, &data, regs))
1669 x86_pmu_stop(event, 0);
1673 inc_irq_stat(apic_perf_irqs);
1678 void perf_events_lapic_init(void)
1680 if (!x86_pmu.apic || !x86_pmu_initialized())
1684 * Always use NMI for PMU
1686 apic_write(APIC_LVTPC, APIC_DM_NMI);
1690 perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs)
1697 * All PMUs/events that share this PMI handler should make sure to
1698 * increment active_events for their events.
1700 if (!atomic_read(&active_events))
1703 start_clock = sched_clock();
1704 ret = static_call(x86_pmu_handle_irq)(regs);
1705 finish_clock = sched_clock();
1707 perf_sample_event_took(finish_clock - start_clock);
1711 NOKPROBE_SYMBOL(perf_event_nmi_handler);
1713 struct event_constraint emptyconstraint;
1714 struct event_constraint unconstrained;
1716 static int x86_pmu_prepare_cpu(unsigned int cpu)
1718 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1721 for (i = 0 ; i < X86_PERF_KFREE_MAX; i++)
1722 cpuc->kfree_on_online[i] = NULL;
1723 if (x86_pmu.cpu_prepare)
1724 return x86_pmu.cpu_prepare(cpu);
1728 static int x86_pmu_dead_cpu(unsigned int cpu)
1730 if (x86_pmu.cpu_dead)
1731 x86_pmu.cpu_dead(cpu);
1735 static int x86_pmu_online_cpu(unsigned int cpu)
1737 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1740 for (i = 0 ; i < X86_PERF_KFREE_MAX; i++) {
1741 kfree(cpuc->kfree_on_online[i]);
1742 cpuc->kfree_on_online[i] = NULL;
1747 static int x86_pmu_starting_cpu(unsigned int cpu)
1749 if (x86_pmu.cpu_starting)
1750 x86_pmu.cpu_starting(cpu);
1754 static int x86_pmu_dying_cpu(unsigned int cpu)
1756 if (x86_pmu.cpu_dying)
1757 x86_pmu.cpu_dying(cpu);
1761 static void __init pmu_check_apic(void)
1763 if (boot_cpu_has(X86_FEATURE_APIC))
1767 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1768 pr_info("no hardware sampling interrupt available.\n");
1771 * If we have a PMU initialized but no APIC
1772 * interrupts, we cannot sample hardware
1773 * events (user-space has to fall back and
1774 * sample via a hrtimer based software event):
1776 pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
1780 static struct attribute_group x86_pmu_format_group __ro_after_init = {
1785 ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr, char *page)
1787 struct perf_pmu_events_attr *pmu_attr =
1788 container_of(attr, struct perf_pmu_events_attr, attr);
1791 if (pmu_attr->id < x86_pmu.max_events)
1792 config = x86_pmu.event_map(pmu_attr->id);
1794 /* string trumps id */
1795 if (pmu_attr->event_str)
1796 return sprintf(page, "%s", pmu_attr->event_str);
1798 return x86_pmu.events_sysfs_show(page, config);
1800 EXPORT_SYMBOL_GPL(events_sysfs_show);
1802 ssize_t events_ht_sysfs_show(struct device *dev, struct device_attribute *attr,
1805 struct perf_pmu_events_ht_attr *pmu_attr =
1806 container_of(attr, struct perf_pmu_events_ht_attr, attr);
1809 * Report conditional events depending on Hyper-Threading.
1811 * This is overly conservative as usually the HT special
1812 * handling is not needed if the other CPU thread is idle.
1814 * Note this does not (and cannot) handle the case when thread
1815 * siblings are invisible, for example with virtualization
1816 * if they are owned by some other guest. The user tool
1817 * has to re-read when a thread sibling gets onlined later.
1819 return sprintf(page, "%s",
1820 topology_max_smt_threads() > 1 ?
1821 pmu_attr->event_str_ht :
1822 pmu_attr->event_str_noht);
1825 EVENT_ATTR(cpu-cycles, CPU_CYCLES );
1826 EVENT_ATTR(instructions, INSTRUCTIONS );
1827 EVENT_ATTR(cache-references, CACHE_REFERENCES );
1828 EVENT_ATTR(cache-misses, CACHE_MISSES );
1829 EVENT_ATTR(branch-instructions, BRANCH_INSTRUCTIONS );
1830 EVENT_ATTR(branch-misses, BRANCH_MISSES );
1831 EVENT_ATTR(bus-cycles, BUS_CYCLES );
1832 EVENT_ATTR(stalled-cycles-frontend, STALLED_CYCLES_FRONTEND );
1833 EVENT_ATTR(stalled-cycles-backend, STALLED_CYCLES_BACKEND );
1834 EVENT_ATTR(ref-cycles, REF_CPU_CYCLES );
1836 static struct attribute *empty_attrs;
1838 static struct attribute *events_attr[] = {
1839 EVENT_PTR(CPU_CYCLES),
1840 EVENT_PTR(INSTRUCTIONS),
1841 EVENT_PTR(CACHE_REFERENCES),
1842 EVENT_PTR(CACHE_MISSES),
1843 EVENT_PTR(BRANCH_INSTRUCTIONS),
1844 EVENT_PTR(BRANCH_MISSES),
1845 EVENT_PTR(BUS_CYCLES),
1846 EVENT_PTR(STALLED_CYCLES_FRONTEND),
1847 EVENT_PTR(STALLED_CYCLES_BACKEND),
1848 EVENT_PTR(REF_CPU_CYCLES),
1853 * Remove all undefined events (x86_pmu.event_map(id) == 0)
1854 * out of events_attr attributes.
1857 is_visible(struct kobject *kobj, struct attribute *attr, int idx)
1859 struct perf_pmu_events_attr *pmu_attr;
1861 if (idx >= x86_pmu.max_events)
1864 pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr.attr);
1866 return pmu_attr->event_str || x86_pmu.event_map(idx) ? attr->mode : 0;
1869 static struct attribute_group x86_pmu_events_group __ro_after_init = {
1871 .attrs = events_attr,
1872 .is_visible = is_visible,
1875 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event)
1877 u64 umask = (config & ARCH_PERFMON_EVENTSEL_UMASK) >> 8;
1878 u64 cmask = (config & ARCH_PERFMON_EVENTSEL_CMASK) >> 24;
1879 bool edge = (config & ARCH_PERFMON_EVENTSEL_EDGE);
1880 bool pc = (config & ARCH_PERFMON_EVENTSEL_PIN_CONTROL);
1881 bool any = (config & ARCH_PERFMON_EVENTSEL_ANY);
1882 bool inv = (config & ARCH_PERFMON_EVENTSEL_INV);
1886 * We have whole page size to spend and just little data
1887 * to write, so we can safely use sprintf.
1889 ret = sprintf(page, "event=0x%02llx", event);
1892 ret += sprintf(page + ret, ",umask=0x%02llx", umask);
1895 ret += sprintf(page + ret, ",edge");
1898 ret += sprintf(page + ret, ",pc");
1901 ret += sprintf(page + ret, ",any");
1904 ret += sprintf(page + ret, ",inv");
1907 ret += sprintf(page + ret, ",cmask=0x%02llx", cmask);
1909 ret += sprintf(page + ret, "\n");
1914 static struct attribute_group x86_pmu_attr_group;
1915 static struct attribute_group x86_pmu_caps_group;
1917 static void x86_pmu_static_call_update(void)
1919 static_call_update(x86_pmu_handle_irq, x86_pmu.handle_irq);
1920 static_call_update(x86_pmu_disable_all, x86_pmu.disable_all);
1921 static_call_update(x86_pmu_enable_all, x86_pmu.enable_all);
1922 static_call_update(x86_pmu_enable, x86_pmu.enable);
1923 static_call_update(x86_pmu_disable, x86_pmu.disable);
1925 static_call_update(x86_pmu_add, x86_pmu.add);
1926 static_call_update(x86_pmu_del, x86_pmu.del);
1927 static_call_update(x86_pmu_read, x86_pmu.read);
1929 static_call_update(x86_pmu_schedule_events, x86_pmu.schedule_events);
1930 static_call_update(x86_pmu_get_event_constraints, x86_pmu.get_event_constraints);
1931 static_call_update(x86_pmu_put_event_constraints, x86_pmu.put_event_constraints);
1933 static_call_update(x86_pmu_start_scheduling, x86_pmu.start_scheduling);
1934 static_call_update(x86_pmu_commit_scheduling, x86_pmu.commit_scheduling);
1935 static_call_update(x86_pmu_stop_scheduling, x86_pmu.stop_scheduling);
1937 static_call_update(x86_pmu_sched_task, x86_pmu.sched_task);
1938 static_call_update(x86_pmu_swap_task_ctx, x86_pmu.swap_task_ctx);
1940 static_call_update(x86_pmu_drain_pebs, x86_pmu.drain_pebs);
1941 static_call_update(x86_pmu_pebs_aliases, x86_pmu.pebs_aliases);
1943 static_call_update(x86_pmu_guest_get_msrs, x86_pmu.guest_get_msrs);
1946 static void _x86_pmu_read(struct perf_event *event)
1948 x86_perf_event_update(event);
1951 static int __init init_hw_perf_events(void)
1953 struct x86_pmu_quirk *quirk;
1956 pr_info("Performance Events: ");
1958 switch (boot_cpu_data.x86_vendor) {
1959 case X86_VENDOR_INTEL:
1960 err = intel_pmu_init();
1962 case X86_VENDOR_AMD:
1963 err = amd_pmu_init();
1965 case X86_VENDOR_HYGON:
1966 err = amd_pmu_init();
1967 x86_pmu.name = "HYGON";
1969 case X86_VENDOR_ZHAOXIN:
1970 case X86_VENDOR_CENTAUR:
1971 err = zhaoxin_pmu_init();
1977 pr_cont("no PMU driver, software events only.\n");
1983 /* sanity check that the hardware exists or is emulated */
1984 if (!check_hw_exists())
1987 pr_cont("%s PMU driver.\n", x86_pmu.name);
1989 x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */
1991 for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next)
1994 if (!x86_pmu.intel_ctrl)
1995 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
1997 perf_events_lapic_init();
1998 register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI");
2000 unconstrained = (struct event_constraint)
2001 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
2002 0, x86_pmu.num_counters, 0, 0);
2004 x86_pmu_format_group.attrs = x86_pmu.format_attrs;
2006 if (!x86_pmu.events_sysfs_show)
2007 x86_pmu_events_group.attrs = &empty_attrs;
2009 pmu.attr_update = x86_pmu.attr_update;
2011 pr_info("... version: %d\n", x86_pmu.version);
2012 pr_info("... bit width: %d\n", x86_pmu.cntval_bits);
2013 pr_info("... generic registers: %d\n", x86_pmu.num_counters);
2014 pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask);
2015 pr_info("... max period: %016Lx\n", x86_pmu.max_period);
2016 pr_info("... fixed-purpose events: %lu\n",
2017 hweight64((((1ULL << x86_pmu.num_counters_fixed) - 1)
2018 << INTEL_PMC_IDX_FIXED) & x86_pmu.intel_ctrl));
2019 pr_info("... event mask: %016Lx\n", x86_pmu.intel_ctrl);
2022 x86_pmu.read = _x86_pmu_read;
2024 if (!x86_pmu.guest_get_msrs)
2025 x86_pmu.guest_get_msrs = (void *)&__static_call_return0;
2027 x86_pmu_static_call_update();
2030 * Install callbacks. Core will call them for each online
2033 err = cpuhp_setup_state(CPUHP_PERF_X86_PREPARE, "perf/x86:prepare",
2034 x86_pmu_prepare_cpu, x86_pmu_dead_cpu);
2038 err = cpuhp_setup_state(CPUHP_AP_PERF_X86_STARTING,
2039 "perf/x86:starting", x86_pmu_starting_cpu,
2044 err = cpuhp_setup_state(CPUHP_AP_PERF_X86_ONLINE, "perf/x86:online",
2045 x86_pmu_online_cpu, NULL);
2049 err = perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
2056 cpuhp_remove_state(CPUHP_AP_PERF_X86_ONLINE);
2058 cpuhp_remove_state(CPUHP_AP_PERF_X86_STARTING);
2060 cpuhp_remove_state(CPUHP_PERF_X86_PREPARE);
2063 early_initcall(init_hw_perf_events);
2065 static void x86_pmu_read(struct perf_event *event)
2067 static_call(x86_pmu_read)(event);
2071 * Start group events scheduling transaction
2072 * Set the flag to make pmu::enable() not perform the
2073 * schedulability test, it will be performed at commit time
2075 * We only support PERF_PMU_TXN_ADD transactions. Save the
2076 * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD
2079 static void x86_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags)
2081 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2083 WARN_ON_ONCE(cpuc->txn_flags); /* txn already in flight */
2085 cpuc->txn_flags = txn_flags;
2086 if (txn_flags & ~PERF_PMU_TXN_ADD)
2089 perf_pmu_disable(pmu);
2090 __this_cpu_write(cpu_hw_events.n_txn, 0);
2091 __this_cpu_write(cpu_hw_events.n_txn_pair, 0);
2092 __this_cpu_write(cpu_hw_events.n_txn_metric, 0);
2096 * Stop group events scheduling transaction
2097 * Clear the flag and pmu::enable() will perform the
2098 * schedulability test.
2100 static void x86_pmu_cancel_txn(struct pmu *pmu)
2102 unsigned int txn_flags;
2103 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2105 WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */
2107 txn_flags = cpuc->txn_flags;
2108 cpuc->txn_flags = 0;
2109 if (txn_flags & ~PERF_PMU_TXN_ADD)
2113 * Truncate collected array by the number of events added in this
2114 * transaction. See x86_pmu_add() and x86_pmu_*_txn().
2116 __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn));
2117 __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn));
2118 __this_cpu_sub(cpu_hw_events.n_pair, __this_cpu_read(cpu_hw_events.n_txn_pair));
2119 __this_cpu_sub(cpu_hw_events.n_metric, __this_cpu_read(cpu_hw_events.n_txn_metric));
2120 perf_pmu_enable(pmu);
2124 * Commit group events scheduling transaction
2125 * Perform the group schedulability test as a whole
2126 * Return 0 if success
2128 * Does not cancel the transaction on failure; expects the caller to do this.
2130 static int x86_pmu_commit_txn(struct pmu *pmu)
2132 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2133 int assign[X86_PMC_IDX_MAX];
2136 WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */
2138 if (cpuc->txn_flags & ~PERF_PMU_TXN_ADD) {
2139 cpuc->txn_flags = 0;
2145 if (!x86_pmu_initialized())
2148 ret = static_call(x86_pmu_schedule_events)(cpuc, n, assign);
2153 * copy new assignment, now we know it is possible
2154 * will be used by hw_perf_enable()
2156 memcpy(cpuc->assign, assign, n*sizeof(int));
2158 cpuc->txn_flags = 0;
2159 perf_pmu_enable(pmu);
2163 * a fake_cpuc is used to validate event groups. Due to
2164 * the extra reg logic, we need to also allocate a fake
2165 * per_core and per_cpu structure. Otherwise, group events
2166 * using extra reg may conflict without the kernel being
2167 * able to catch this when the last event gets added to
2170 static void free_fake_cpuc(struct cpu_hw_events *cpuc)
2172 intel_cpuc_finish(cpuc);
2176 static struct cpu_hw_events *allocate_fake_cpuc(void)
2178 struct cpu_hw_events *cpuc;
2179 int cpu = raw_smp_processor_id();
2181 cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL);
2183 return ERR_PTR(-ENOMEM);
2186 if (intel_cpuc_prepare(cpuc, cpu))
2191 free_fake_cpuc(cpuc);
2192 return ERR_PTR(-ENOMEM);
2196 * validate that we can schedule this event
2198 static int validate_event(struct perf_event *event)
2200 struct cpu_hw_events *fake_cpuc;
2201 struct event_constraint *c;
2204 fake_cpuc = allocate_fake_cpuc();
2205 if (IS_ERR(fake_cpuc))
2206 return PTR_ERR(fake_cpuc);
2208 c = x86_pmu.get_event_constraints(fake_cpuc, 0, event);
2210 if (!c || !c->weight)
2213 if (x86_pmu.put_event_constraints)
2214 x86_pmu.put_event_constraints(fake_cpuc, event);
2216 free_fake_cpuc(fake_cpuc);
2222 * validate a single event group
2224 * validation include:
2225 * - check events are compatible which each other
2226 * - events do not compete for the same counter
2227 * - number of events <= number of counters
2229 * validation ensures the group can be loaded onto the
2230 * PMU if it was the only group available.
2232 static int validate_group(struct perf_event *event)
2234 struct perf_event *leader = event->group_leader;
2235 struct cpu_hw_events *fake_cpuc;
2236 int ret = -EINVAL, n;
2238 fake_cpuc = allocate_fake_cpuc();
2239 if (IS_ERR(fake_cpuc))
2240 return PTR_ERR(fake_cpuc);
2242 * the event is not yet connected with its
2243 * siblings therefore we must first collect
2244 * existing siblings, then add the new event
2245 * before we can simulate the scheduling
2247 n = collect_events(fake_cpuc, leader, true);
2251 fake_cpuc->n_events = n;
2252 n = collect_events(fake_cpuc, event, false);
2256 fake_cpuc->n_events = 0;
2257 ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
2260 free_fake_cpuc(fake_cpuc);
2264 static int x86_pmu_event_init(struct perf_event *event)
2269 switch (event->attr.type) {
2271 case PERF_TYPE_HARDWARE:
2272 case PERF_TYPE_HW_CACHE:
2279 err = __x86_pmu_event_init(event);
2282 * we temporarily connect event to its pmu
2283 * such that validate_group() can classify
2284 * it as an x86 event using is_x86_event()
2289 if (event->group_leader != event)
2290 err = validate_group(event);
2292 err = validate_event(event);
2298 event->destroy(event);
2301 if (READ_ONCE(x86_pmu.attr_rdpmc) &&
2302 !(event->hw.flags & PERF_X86_EVENT_LARGE_PEBS))
2303 event->hw.flags |= PERF_X86_EVENT_RDPMC_ALLOWED;
2308 static void x86_pmu_event_mapped(struct perf_event *event, struct mm_struct *mm)
2310 if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
2314 * This function relies on not being called concurrently in two
2315 * tasks in the same mm. Otherwise one task could observe
2316 * perf_rdpmc_allowed > 1 and return all the way back to
2317 * userspace with CR4.PCE clear while another task is still
2318 * doing on_each_cpu_mask() to propagate CR4.PCE.
2320 * For now, this can't happen because all callers hold mmap_lock
2321 * for write. If this changes, we'll need a different solution.
2323 mmap_assert_write_locked(mm);
2325 if (atomic_inc_return(&mm->context.perf_rdpmc_allowed) == 1)
2326 on_each_cpu_mask(mm_cpumask(mm), cr4_update_pce, NULL, 1);
2329 static void x86_pmu_event_unmapped(struct perf_event *event, struct mm_struct *mm)
2332 if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
2335 if (atomic_dec_and_test(&mm->context.perf_rdpmc_allowed))
2336 on_each_cpu_mask(mm_cpumask(mm), cr4_update_pce, NULL, 1);
2339 static int x86_pmu_event_idx(struct perf_event *event)
2341 struct hw_perf_event *hwc = &event->hw;
2343 if (!(hwc->flags & PERF_X86_EVENT_RDPMC_ALLOWED))
2346 if (is_metric_idx(hwc->idx))
2347 return INTEL_PMC_FIXED_RDPMC_METRICS + 1;
2349 return hwc->event_base_rdpmc + 1;
2352 static ssize_t get_attr_rdpmc(struct device *cdev,
2353 struct device_attribute *attr,
2356 return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc);
2359 static ssize_t set_attr_rdpmc(struct device *cdev,
2360 struct device_attribute *attr,
2361 const char *buf, size_t count)
2366 ret = kstrtoul(buf, 0, &val);
2373 if (x86_pmu.attr_rdpmc_broken)
2376 if (val != x86_pmu.attr_rdpmc) {
2378 * Changing into or out of never available or always available,
2379 * aka perf-event-bypassing mode. This path is extremely slow,
2380 * but only root can trigger it, so it's okay.
2383 static_branch_inc(&rdpmc_never_available_key);
2384 else if (x86_pmu.attr_rdpmc == 0)
2385 static_branch_dec(&rdpmc_never_available_key);
2388 static_branch_inc(&rdpmc_always_available_key);
2389 else if (x86_pmu.attr_rdpmc == 2)
2390 static_branch_dec(&rdpmc_always_available_key);
2392 on_each_cpu(cr4_update_pce, NULL, 1);
2393 x86_pmu.attr_rdpmc = val;
2399 static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc);
2401 static struct attribute *x86_pmu_attrs[] = {
2402 &dev_attr_rdpmc.attr,
2406 static struct attribute_group x86_pmu_attr_group __ro_after_init = {
2407 .attrs = x86_pmu_attrs,
2410 static ssize_t max_precise_show(struct device *cdev,
2411 struct device_attribute *attr,
2414 return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu_max_precise());
2417 static DEVICE_ATTR_RO(max_precise);
2419 static struct attribute *x86_pmu_caps_attrs[] = {
2420 &dev_attr_max_precise.attr,
2424 static struct attribute_group x86_pmu_caps_group __ro_after_init = {
2426 .attrs = x86_pmu_caps_attrs,
2429 static const struct attribute_group *x86_pmu_attr_groups[] = {
2430 &x86_pmu_attr_group,
2431 &x86_pmu_format_group,
2432 &x86_pmu_events_group,
2433 &x86_pmu_caps_group,
2437 static void x86_pmu_sched_task(struct perf_event_context *ctx, bool sched_in)
2439 static_call_cond(x86_pmu_sched_task)(ctx, sched_in);
2442 static void x86_pmu_swap_task_ctx(struct perf_event_context *prev,
2443 struct perf_event_context *next)
2445 static_call_cond(x86_pmu_swap_task_ctx)(prev, next);
2448 void perf_check_microcode(void)
2450 if (x86_pmu.check_microcode)
2451 x86_pmu.check_microcode();
2454 static int x86_pmu_check_period(struct perf_event *event, u64 value)
2456 if (x86_pmu.check_period && x86_pmu.check_period(event, value))
2459 if (value && x86_pmu.limit_period) {
2460 if (x86_pmu.limit_period(event, value) > value)
2467 static int x86_pmu_aux_output_match(struct perf_event *event)
2469 if (!(pmu.capabilities & PERF_PMU_CAP_AUX_OUTPUT))
2472 if (x86_pmu.aux_output_match)
2473 return x86_pmu.aux_output_match(event);
2478 static struct pmu pmu = {
2479 .pmu_enable = x86_pmu_enable,
2480 .pmu_disable = x86_pmu_disable,
2482 .attr_groups = x86_pmu_attr_groups,
2484 .event_init = x86_pmu_event_init,
2486 .event_mapped = x86_pmu_event_mapped,
2487 .event_unmapped = x86_pmu_event_unmapped,
2491 .start = x86_pmu_start,
2492 .stop = x86_pmu_stop,
2493 .read = x86_pmu_read,
2495 .start_txn = x86_pmu_start_txn,
2496 .cancel_txn = x86_pmu_cancel_txn,
2497 .commit_txn = x86_pmu_commit_txn,
2499 .event_idx = x86_pmu_event_idx,
2500 .sched_task = x86_pmu_sched_task,
2501 .swap_task_ctx = x86_pmu_swap_task_ctx,
2502 .check_period = x86_pmu_check_period,
2504 .aux_output_match = x86_pmu_aux_output_match,
2507 void arch_perf_update_userpage(struct perf_event *event,
2508 struct perf_event_mmap_page *userpg, u64 now)
2510 struct cyc2ns_data data;
2513 userpg->cap_user_time = 0;
2514 userpg->cap_user_time_zero = 0;
2515 userpg->cap_user_rdpmc =
2516 !!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED);
2517 userpg->pmc_width = x86_pmu.cntval_bits;
2519 if (!using_native_sched_clock() || !sched_clock_stable())
2522 cyc2ns_read_begin(&data);
2524 offset = data.cyc2ns_offset + __sched_clock_offset;
2527 * Internal timekeeping for enabled/running/stopped times
2528 * is always in the local_clock domain.
2530 userpg->cap_user_time = 1;
2531 userpg->time_mult = data.cyc2ns_mul;
2532 userpg->time_shift = data.cyc2ns_shift;
2533 userpg->time_offset = offset - now;
2536 * cap_user_time_zero doesn't make sense when we're using a different
2537 * time base for the records.
2539 if (!event->attr.use_clockid) {
2540 userpg->cap_user_time_zero = 1;
2541 userpg->time_zero = offset;
2548 * Determine whether the regs were taken from an irq/exception handler rather
2549 * than from perf_arch_fetch_caller_regs().
2551 static bool perf_hw_regs(struct pt_regs *regs)
2553 return regs->flags & X86_EFLAGS_FIXED;
2557 perf_callchain_kernel(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs)
2559 struct unwind_state state;
2562 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2563 /* TODO: We don't support guest os callchain now */
2567 if (perf_callchain_store(entry, regs->ip))
2570 if (perf_hw_regs(regs))
2571 unwind_start(&state, current, regs, NULL);
2573 unwind_start(&state, current, NULL, (void *)regs->sp);
2575 for (; !unwind_done(&state); unwind_next_frame(&state)) {
2576 addr = unwind_get_return_address(&state);
2577 if (!addr || perf_callchain_store(entry, addr))
2583 valid_user_frame(const void __user *fp, unsigned long size)
2585 return (__range_not_ok(fp, size, TASK_SIZE) == 0);
2588 static unsigned long get_segment_base(unsigned int segment)
2590 struct desc_struct *desc;
2591 unsigned int idx = segment >> 3;
2593 if ((segment & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2594 #ifdef CONFIG_MODIFY_LDT_SYSCALL
2595 struct ldt_struct *ldt;
2597 /* IRQs are off, so this synchronizes with smp_store_release */
2598 ldt = READ_ONCE(current->active_mm->context.ldt);
2599 if (!ldt || idx >= ldt->nr_entries)
2602 desc = &ldt->entries[idx];
2607 if (idx >= GDT_ENTRIES)
2610 desc = raw_cpu_ptr(gdt_page.gdt) + idx;
2613 return get_desc_base(desc);
2616 #ifdef CONFIG_IA32_EMULATION
2618 #include <linux/compat.h>
2621 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry_ctx *entry)
2623 /* 32-bit process in 64-bit kernel. */
2624 unsigned long ss_base, cs_base;
2625 struct stack_frame_ia32 frame;
2626 const struct stack_frame_ia32 __user *fp;
2628 if (user_64bit_mode(regs))
2631 cs_base = get_segment_base(regs->cs);
2632 ss_base = get_segment_base(regs->ss);
2634 fp = compat_ptr(ss_base + regs->bp);
2635 pagefault_disable();
2636 while (entry->nr < entry->max_stack) {
2637 if (!valid_user_frame(fp, sizeof(frame)))
2640 if (__get_user(frame.next_frame, &fp->next_frame))
2642 if (__get_user(frame.return_address, &fp->return_address))
2645 perf_callchain_store(entry, cs_base + frame.return_address);
2646 fp = compat_ptr(ss_base + frame.next_frame);
2653 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry_ctx *entry)
2660 perf_callchain_user(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs)
2662 struct stack_frame frame;
2663 const struct stack_frame __user *fp;
2665 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2666 /* TODO: We don't support guest os callchain now */
2671 * We don't know what to do with VM86 stacks.. ignore them for now.
2673 if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM))
2676 fp = (void __user *)regs->bp;
2678 perf_callchain_store(entry, regs->ip);
2680 if (!nmi_uaccess_okay())
2683 if (perf_callchain_user32(regs, entry))
2686 pagefault_disable();
2687 while (entry->nr < entry->max_stack) {
2688 if (!valid_user_frame(fp, sizeof(frame)))
2691 if (__get_user(frame.next_frame, &fp->next_frame))
2693 if (__get_user(frame.return_address, &fp->return_address))
2696 perf_callchain_store(entry, frame.return_address);
2697 fp = (void __user *)frame.next_frame;
2703 * Deal with code segment offsets for the various execution modes:
2705 * VM86 - the good olde 16 bit days, where the linear address is
2706 * 20 bits and we use regs->ip + 0x10 * regs->cs.
2708 * IA32 - Where we need to look at GDT/LDT segment descriptor tables
2709 * to figure out what the 32bit base address is.
2711 * X32 - has TIF_X32 set, but is running in x86_64
2713 * X86_64 - CS,DS,SS,ES are all zero based.
2715 static unsigned long code_segment_base(struct pt_regs *regs)
2718 * For IA32 we look at the GDT/LDT segment base to convert the
2719 * effective IP to a linear address.
2722 #ifdef CONFIG_X86_32
2724 * If we are in VM86 mode, add the segment offset to convert to a
2727 if (regs->flags & X86_VM_MASK)
2728 return 0x10 * regs->cs;
2730 if (user_mode(regs) && regs->cs != __USER_CS)
2731 return get_segment_base(regs->cs);
2733 if (user_mode(regs) && !user_64bit_mode(regs) &&
2734 regs->cs != __USER32_CS)
2735 return get_segment_base(regs->cs);
2740 unsigned long perf_instruction_pointer(struct pt_regs *regs)
2742 if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
2743 return perf_guest_cbs->get_guest_ip();
2745 return regs->ip + code_segment_base(regs);
2748 unsigned long perf_misc_flags(struct pt_regs *regs)
2752 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2753 if (perf_guest_cbs->is_user_mode())
2754 misc |= PERF_RECORD_MISC_GUEST_USER;
2756 misc |= PERF_RECORD_MISC_GUEST_KERNEL;
2758 if (user_mode(regs))
2759 misc |= PERF_RECORD_MISC_USER;
2761 misc |= PERF_RECORD_MISC_KERNEL;
2764 if (regs->flags & PERF_EFLAGS_EXACT)
2765 misc |= PERF_RECORD_MISC_EXACT_IP;
2770 void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
2772 cap->version = x86_pmu.version;
2773 cap->num_counters_gp = x86_pmu.num_counters;
2774 cap->num_counters_fixed = x86_pmu.num_counters_fixed;
2775 cap->bit_width_gp = x86_pmu.cntval_bits;
2776 cap->bit_width_fixed = x86_pmu.cntval_bits;
2777 cap->events_mask = (unsigned int)x86_pmu.events_maskl;
2778 cap->events_mask_len = x86_pmu.events_mask_len;
2780 EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability);