1 /* SPDX-License-Identifier: GPL-2.0 */
3 * linux/arch/x86_64/entry.S
5 * Copyright (C) 1991, 1992 Linus Torvalds
6 * Copyright (C) 2000, 2001, 2002 Andi Kleen SuSE Labs
7 * Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
9 * entry.S contains the system-call and fault low-level handling routines.
11 * Some of this is documented in Documentation/arch/x86/entry_64.rst
13 * A note on terminology:
14 * - iret frame: Architecture defined interrupt frame from SS to RIP
15 * at the top of the kernel process stack.
18 * - SYM_FUNC_START/END:Define functions in the symbol table.
19 * - idtentry: Define exception entry points.
21 #include <linux/export.h>
22 #include <linux/linkage.h>
23 #include <asm/segment.h>
24 #include <asm/cache.h>
25 #include <asm/errno.h>
26 #include <asm/asm-offsets.h>
28 #include <asm/unistd.h>
29 #include <asm/thread_info.h>
30 #include <asm/hw_irq.h>
31 #include <asm/page_types.h>
32 #include <asm/irqflags.h>
33 #include <asm/paravirt.h>
34 #include <asm/percpu.h>
37 #include <asm/pgtable_types.h>
38 #include <asm/frame.h>
39 #include <asm/trapnr.h>
40 #include <asm/nospec-branch.h>
41 #include <asm/fsgsbase.h>
42 #include <linux/err.h>
47 .section .entry.text, "ax"
50 * 64-bit SYSCALL instruction entry. Up to 6 arguments in registers.
52 * This is the only entry point used for 64-bit system calls. The
53 * hardware interface is reasonably well designed and the register to
54 * argument mapping Linux uses fits well with the registers that are
55 * available when SYSCALL is used.
57 * SYSCALL instructions can be found inlined in libc implementations as
58 * well as some other programs and libraries. There are also a handful
59 * of SYSCALL instructions in the vDSO used, for example, as a
60 * clock_gettimeofday fallback.
62 * 64-bit SYSCALL saves rip to rcx, clears rflags.RF, then saves rflags to r11,
63 * then loads new ss, cs, and rip from previously programmed MSRs.
64 * rflags gets masked by a value from another MSR (so CLD and CLAC
65 * are not needed). SYSCALL does not save anything on the stack
66 * and does not change rsp.
69 * rax system call number
71 * r11 saved rflags (note: r11 is callee-clobbered register in C ABI)
75 * r10 arg3 (needs to be moved to rcx to conform to C ABI)
78 * (note: r12-r15, rbp, rbx are callee-preserved in C ABI)
80 * Only called from user space.
82 * When user can change pt_regs->foo always force IRET. That is because
83 * it deals with uncanonical addresses better. SYSRET has trouble
84 * with them due to bugs in both AMD and Intel CPUs.
87 SYM_CODE_START(entry_SYSCALL_64)
92 /* tss.sp2 is scratch space. */
93 movq %rsp, PER_CPU_VAR(cpu_tss_rw + TSS_sp2)
94 SWITCH_TO_KERNEL_CR3 scratch_reg=%rsp
95 movq PER_CPU_VAR(pcpu_hot + X86_top_of_stack), %rsp
97 SYM_INNER_LABEL(entry_SYSCALL_64_safe_stack, SYM_L_GLOBAL)
100 /* Construct struct pt_regs on stack */
101 pushq $__USER_DS /* pt_regs->ss */
102 pushq PER_CPU_VAR(cpu_tss_rw + TSS_sp2) /* pt_regs->sp */
103 pushq %r11 /* pt_regs->flags */
104 pushq $__USER_CS /* pt_regs->cs */
105 pushq %rcx /* pt_regs->ip */
106 SYM_INNER_LABEL(entry_SYSCALL_64_after_hwframe, SYM_L_GLOBAL)
107 pushq %rax /* pt_regs->orig_ax */
109 PUSH_AND_CLEAR_REGS rax=$-ENOSYS
113 /* Sign extend the lower 32bit as syscall numbers are treated as int */
116 /* clobbers %rax, make sure it is after saving the syscall nr */
120 call do_syscall_64 /* returns with IRQs disabled */
123 * Try to use SYSRET instead of IRET if we're returning to
124 * a completely clean 64-bit userspace context. If we're not,
125 * go to the slow exit path.
126 * In the Xen PV case we must use iret anyway.
129 ALTERNATIVE "", "jmp swapgs_restore_regs_and_return_to_usermode", \
135 cmpq %rcx, %r11 /* SYSRET requires RCX == RIP */
136 jne swapgs_restore_regs_and_return_to_usermode
139 * On Intel CPUs, SYSRET with non-canonical RCX/RIP will #GP
140 * in kernel space. This essentially lets the user take over
141 * the kernel, since userspace controls RSP.
143 * If width of "canonical tail" ever becomes variable, this will need
144 * to be updated to remain correct on both old and new CPUs.
146 * Change top bits to match most significant bit (47th or 56th bit
147 * depending on paging mode) in the address.
149 #ifdef CONFIG_X86_5LEVEL
150 ALTERNATIVE "shl $(64 - 48), %rcx; sar $(64 - 48), %rcx", \
151 "shl $(64 - 57), %rcx; sar $(64 - 57), %rcx", X86_FEATURE_LA57
153 shl $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx
154 sar $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx
157 /* If this changed %rcx, it was not canonical */
159 jne swapgs_restore_regs_and_return_to_usermode
161 cmpq $__USER_CS, CS(%rsp) /* CS must match SYSRET */
162 jne swapgs_restore_regs_and_return_to_usermode
165 cmpq %r11, EFLAGS(%rsp) /* R11 == RFLAGS */
166 jne swapgs_restore_regs_and_return_to_usermode
169 * SYSCALL clears RF when it saves RFLAGS in R11 and SYSRET cannot
170 * restore RF properly. If the slowpath sets it for whatever reason, we
171 * need to restore it correctly.
173 * SYSRET can restore TF, but unlike IRET, restoring TF results in a
174 * trap from userspace immediately after SYSRET. This would cause an
175 * infinite loop whenever #DB happens with register state that satisfies
176 * the opportunistic SYSRET conditions. For example, single-stepping
179 * movq $stuck_here, %rcx
184 * would never get past 'stuck_here'.
186 testq $(X86_EFLAGS_RF|X86_EFLAGS_TF), %r11
187 jnz swapgs_restore_regs_and_return_to_usermode
189 /* nothing to check for RSP */
191 cmpq $__USER_DS, SS(%rsp) /* SS must match SYSRET */
192 jne swapgs_restore_regs_and_return_to_usermode
195 * We win! This label is here just for ease of understanding
196 * perf profiles. Nothing jumps here.
198 syscall_return_via_sysret:
203 * Now all regs are restored except RSP and RDI.
204 * Save old stack pointer and switch to trampoline stack.
207 movq PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %rsp
208 UNWIND_HINT_END_OF_STACK
210 pushq RSP-RDI(%rdi) /* RSP */
211 pushq (%rdi) /* RDI */
214 * We are on the trampoline stack. All regs except RDI are live.
215 * We can do future final exit work right here.
217 STACKLEAK_ERASE_NOCLOBBER
219 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi
223 SYM_INNER_LABEL(entry_SYSRETQ_unsafe_stack, SYM_L_GLOBAL)
227 SYM_INNER_LABEL(entry_SYSRETQ_end, SYM_L_GLOBAL)
230 SYM_CODE_END(entry_SYSCALL_64)
236 .pushsection .text, "ax"
237 SYM_FUNC_START(__switch_to_asm)
239 * Save callee-saved registers
240 * This must match the order in inactive_task_frame
250 movq %rsp, TASK_threadsp(%rdi)
251 movq TASK_threadsp(%rsi), %rsp
253 #ifdef CONFIG_STACKPROTECTOR
254 movq TASK_stack_canary(%rsi), %rbx
255 movq %rbx, PER_CPU_VAR(fixed_percpu_data) + FIXED_stack_canary
259 * When switching from a shallower to a deeper call stack
260 * the RSB may either underflow or use entries populated
261 * with userspace addresses. On CPUs where those concerns
262 * exist, overwrite the RSB with entries which capture
263 * speculative execution to prevent attack.
265 FILL_RETURN_BUFFER %r12, RSB_CLEAR_LOOPS, X86_FEATURE_RSB_CTXSW
267 /* restore callee-saved registers */
276 SYM_FUNC_END(__switch_to_asm)
280 * A newly forked process directly context switches into this address.
282 * rax: prev task we switched from
283 * rbx: kernel thread func (NULL for user thread)
284 * r12: kernel thread arg
286 .pushsection .text, "ax"
287 SYM_CODE_START(ret_from_fork_asm)
289 * This is the start of the kernel stack; even through there's a
290 * register set at the top, the regset isn't necessarily coherent
291 * (consider kthreads) and one cannot unwind further.
293 * This ensures stack unwinds of kernel threads terminate in a known
296 UNWIND_HINT_END_OF_STACK
297 ANNOTATE_NOENDBR // copy_thread
300 movq %rax, %rdi /* prev */
301 movq %rsp, %rsi /* regs */
302 movq %rbx, %rdx /* fn */
303 movq %r12, %rcx /* fn_arg */
307 * Set the stack state to what is expected for the target function
308 * -- at this point the register set should be a valid user set
309 * and unwind should work normally.
312 jmp swapgs_restore_regs_and_return_to_usermode
313 SYM_CODE_END(ret_from_fork_asm)
316 .macro DEBUG_ENTRY_ASSERT_IRQS_OFF
317 #ifdef CONFIG_DEBUG_ENTRY
320 testl $X86_EFLAGS_IF, %eax
328 SYM_CODE_START(xen_error_entry)
331 PUSH_AND_CLEAR_REGS save_ret=1
332 ENCODE_FRAME_POINTER 8
333 UNTRAIN_RET_FROM_CALL
335 SYM_CODE_END(xen_error_entry)
338 * idtentry_body - Macro to emit code calling the C function
339 * @cfunc: C function to be called
340 * @has_error_code: Hardware pushed error code on stack
342 .macro idtentry_body cfunc has_error_code:req
345 * Call error_entry() and switch to the task stack if from userspace.
347 * When in XENPV, it is already in the task stack, and it can't fault
348 * for native_iret() nor native_load_gs_index() since XENPV uses its
349 * own pvops for IRET and load_gs_index(). And it doesn't need to
350 * switch the CR3. So it can skip invoking error_entry().
352 ALTERNATIVE "call error_entry; movq %rax, %rsp", \
353 "call xen_error_entry", X86_FEATURE_XENPV
358 movq %rsp, %rdi /* pt_regs pointer into 1st argument*/
360 .if \has_error_code == 1
361 movq ORIG_RAX(%rsp), %rsi /* get error code into 2nd argument*/
362 movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */
367 /* For some configurations \cfunc ends up being a noreturn. */
374 * idtentry - Macro to generate entry stubs for simple IDT entries
375 * @vector: Vector number
376 * @asmsym: ASM symbol for the entry point
377 * @cfunc: C function to be called
378 * @has_error_code: Hardware pushed error code on stack
380 * The macro emits code to set up the kernel context for straight forward
381 * and simple IDT entries. No IST stack, no paranoid entry checks.
383 .macro idtentry vector asmsym cfunc has_error_code:req
384 SYM_CODE_START(\asmsym)
386 .if \vector == X86_TRAP_BP
387 /* #BP advances %rip to the next instruction */
388 UNWIND_HINT_IRET_ENTRY offset=\has_error_code*8 signal=0
390 UNWIND_HINT_IRET_ENTRY offset=\has_error_code*8
397 .if \has_error_code == 0
398 pushq $-1 /* ORIG_RAX: no syscall to restart */
401 .if \vector == X86_TRAP_BP
403 * If coming from kernel space, create a 6-word gap to allow the
404 * int3 handler to emulate a call instruction.
406 testb $3, CS-ORIG_RAX(%rsp)
407 jnz .Lfrom_usermode_no_gap_\@
411 UNWIND_HINT_IRET_REGS offset=8
412 .Lfrom_usermode_no_gap_\@:
415 idtentry_body \cfunc \has_error_code
417 _ASM_NOKPROBE(\asmsym)
418 SYM_CODE_END(\asmsym)
422 * Interrupt entry/exit.
424 + The interrupt stubs push (vector) onto the stack, which is the error_code
425 * position of idtentry exceptions, and jump to one of the two idtentry points
428 * common_interrupt is a hotpath, align it to a cache line
430 .macro idtentry_irq vector cfunc
431 .p2align CONFIG_X86_L1_CACHE_SHIFT
432 idtentry \vector asm_\cfunc \cfunc has_error_code=1
436 * System vectors which invoke their handlers directly and are not
437 * going through the regular common device interrupt handling code.
439 .macro idtentry_sysvec vector cfunc
440 idtentry \vector asm_\cfunc \cfunc has_error_code=0
444 * idtentry_mce_db - Macro to generate entry stubs for #MC and #DB
445 * @vector: Vector number
446 * @asmsym: ASM symbol for the entry point
447 * @cfunc: C function to be called
449 * The macro emits code to set up the kernel context for #MC and #DB
451 * If the entry comes from user space it uses the normal entry path
452 * including the return to user space work and preemption checks on
455 * If hits in kernel mode then it needs to go through the paranoid
456 * entry as the exception can hit any random state. No preemption
457 * check on exit to keep the paranoid path simple.
459 .macro idtentry_mce_db vector asmsym cfunc
460 SYM_CODE_START(\asmsym)
461 UNWIND_HINT_IRET_ENTRY
466 pushq $-1 /* ORIG_RAX: no syscall to restart */
469 * If the entry is from userspace, switch stacks and treat it as
472 testb $3, CS-ORIG_RAX(%rsp)
473 jnz .Lfrom_usermode_switch_stack_\@
475 /* paranoid_entry returns GS information for paranoid_exit in EBX. */
480 movq %rsp, %rdi /* pt_regs pointer */
486 /* Switch to the regular task stack and use the noist entry point */
487 .Lfrom_usermode_switch_stack_\@:
488 idtentry_body noist_\cfunc, has_error_code=0
490 _ASM_NOKPROBE(\asmsym)
491 SYM_CODE_END(\asmsym)
494 #ifdef CONFIG_AMD_MEM_ENCRYPT
496 * idtentry_vc - Macro to generate entry stub for #VC
497 * @vector: Vector number
498 * @asmsym: ASM symbol for the entry point
499 * @cfunc: C function to be called
501 * The macro emits code to set up the kernel context for #VC. The #VC handler
502 * runs on an IST stack and needs to be able to cause nested #VC exceptions.
504 * To make this work the #VC entry code tries its best to pretend it doesn't use
505 * an IST stack by switching to the task stack if coming from user-space (which
506 * includes early SYSCALL entry path) or back to the stack in the IRET frame if
507 * entered from kernel-mode.
509 * If entered from kernel-mode the return stack is validated first, and if it is
510 * not safe to use (e.g. because it points to the entry stack) the #VC handler
511 * will switch to a fall-back stack (VC2) and call a special handler function.
513 * The macro is only used for one vector, but it is planned to be extended in
514 * the future for the #HV exception.
516 .macro idtentry_vc vector asmsym cfunc
517 SYM_CODE_START(\asmsym)
518 UNWIND_HINT_IRET_ENTRY
524 * If the entry is from userspace, switch stacks and treat it as
527 testb $3, CS-ORIG_RAX(%rsp)
528 jnz .Lfrom_usermode_switch_stack_\@
531 * paranoid_entry returns SWAPGS flag for paranoid_exit in EBX.
532 * EBX == 0 -> SWAPGS, EBX == 1 -> no SWAPGS
539 * Switch off the IST stack to make it free for nested exceptions. The
540 * vc_switch_off_ist() function will switch back to the interrupted
541 * stack if it is safe to do so. If not it switches to the VC fall-back
544 movq %rsp, %rdi /* pt_regs pointer */
545 call vc_switch_off_ist
546 movq %rax, %rsp /* Switch to new stack */
552 movq ORIG_RAX(%rsp), %rsi /* get error code into 2nd argument*/
553 movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */
555 movq %rsp, %rdi /* pt_regs pointer */
560 * No need to switch back to the IST stack. The current stack is either
561 * identical to the stack in the IRET frame or the VC fall-back stack,
562 * so it is definitely mapped even with PTI enabled.
566 /* Switch to the regular task stack */
567 .Lfrom_usermode_switch_stack_\@:
568 idtentry_body user_\cfunc, has_error_code=1
570 _ASM_NOKPROBE(\asmsym)
571 SYM_CODE_END(\asmsym)
576 * Double fault entry. Straight paranoid. No checks from which context
577 * this comes because for the espfix induced #DF this would do the wrong
580 .macro idtentry_df vector asmsym cfunc
581 SYM_CODE_START(\asmsym)
582 UNWIND_HINT_IRET_ENTRY offset=8
587 /* paranoid_entry returns GS information for paranoid_exit in EBX. */
591 movq %rsp, %rdi /* pt_regs pointer into first argument */
592 movq ORIG_RAX(%rsp), %rsi /* get error code into 2nd argument*/
593 movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */
596 /* For some configurations \cfunc ends up being a noreturn. */
601 _ASM_NOKPROBE(\asmsym)
602 SYM_CODE_END(\asmsym)
606 * Include the defines which emit the idt entries which are shared
607 * shared between 32 and 64 bit and emit the __irqentry_text_* markers
608 * so the stacktrace boundary checks work.
611 .globl __irqentry_text_start
612 __irqentry_text_start:
614 #include <asm/idtentry.h>
617 .globl __irqentry_text_end
621 SYM_CODE_START_LOCAL(common_interrupt_return)
622 SYM_INNER_LABEL(swapgs_restore_regs_and_return_to_usermode, SYM_L_GLOBAL)
624 #ifdef CONFIG_DEBUG_ENTRY
625 /* Assert that pt_regs indicates user mode. */
632 ALTERNATIVE "", "jmp xenpv_restore_regs_and_return_to_usermode", X86_FEATURE_XENPV
638 * The stack is now user RDI, orig_ax, RIP, CS, EFLAGS, RSP, SS.
639 * Save old stack pointer and switch to trampoline stack.
642 movq PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %rsp
643 UNWIND_HINT_END_OF_STACK
645 /* Copy the IRET frame to the trampoline stack. */
646 pushq 6*8(%rdi) /* SS */
647 pushq 5*8(%rdi) /* RSP */
648 pushq 4*8(%rdi) /* EFLAGS */
649 pushq 3*8(%rdi) /* CS */
650 pushq 2*8(%rdi) /* RIP */
652 /* Push user RDI on the trampoline stack. */
656 * We are on the trampoline stack. All regs except RDI are live.
657 * We can do future final exit work right here.
659 STACKLEAK_ERASE_NOCLOBBER
661 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi
669 SYM_INNER_LABEL(restore_regs_and_return_to_kernel, SYM_L_GLOBAL)
670 #ifdef CONFIG_DEBUG_ENTRY
671 /* Assert that pt_regs indicates kernel mode. */
678 addq $8, %rsp /* skip regs->orig_ax */
680 * ARCH_HAS_MEMBARRIER_SYNC_CORE rely on IRET core serialization
681 * when returning from IPI handler.
684 SYM_INNER_LABEL(early_xen_iret_patch, SYM_L_GLOBAL)
687 .long .Lnative_iret - (. + 4)
691 UNWIND_HINT_IRET_REGS
693 * Are we returning to a stack segment from the LDT? Note: in
694 * 64-bit mode SS:RSP on the exception stack is always valid.
696 #ifdef CONFIG_X86_ESPFIX64
697 testb $4, (SS-RIP)(%rsp)
698 jnz native_irq_return_ldt
701 SYM_INNER_LABEL(native_irq_return_iret, SYM_L_GLOBAL)
702 ANNOTATE_NOENDBR // exc_double_fault
704 * This may fault. Non-paranoid faults on return to userspace are
705 * handled by fixup_bad_iret. These include #SS, #GP, and #NP.
706 * Double-faults due to espfix64 are handled in exc_double_fault.
707 * Other faults here are fatal.
711 #ifdef CONFIG_X86_ESPFIX64
712 native_irq_return_ldt:
714 * We are running with user GSBASE. All GPRs contain their user
715 * values. We have a percpu ESPFIX stack that is eight slots
716 * long (see ESPFIX_STACK_SIZE). espfix_waddr points to the bottom
717 * of the ESPFIX stack.
719 * We clobber RAX and RDI in this code. We stash RDI on the
720 * normal stack and RAX on the ESPFIX stack.
722 * The ESPFIX stack layout we set up looks like this:
724 * --- top of ESPFIX stack ---
729 * RIP <-- RSP points here when we're done
730 * RAX <-- espfix_waddr points here
731 * --- bottom of ESPFIX stack ---
734 pushq %rdi /* Stash user RDI */
735 swapgs /* to kernel GS */
736 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdi /* to kernel CR3 */
738 movq PER_CPU_VAR(espfix_waddr), %rdi
739 movq %rax, (0*8)(%rdi) /* user RAX */
740 movq (1*8)(%rsp), %rax /* user RIP */
741 movq %rax, (1*8)(%rdi)
742 movq (2*8)(%rsp), %rax /* user CS */
743 movq %rax, (2*8)(%rdi)
744 movq (3*8)(%rsp), %rax /* user RFLAGS */
745 movq %rax, (3*8)(%rdi)
746 movq (5*8)(%rsp), %rax /* user SS */
747 movq %rax, (5*8)(%rdi)
748 movq (4*8)(%rsp), %rax /* user RSP */
749 movq %rax, (4*8)(%rdi)
750 /* Now RAX == RSP. */
752 andl $0xffff0000, %eax /* RAX = (RSP & 0xffff0000) */
755 * espfix_stack[31:16] == 0. The page tables are set up such that
756 * (espfix_stack | (X & 0xffff0000)) points to a read-only alias of
757 * espfix_waddr for any X. That is, there are 65536 RO aliases of
758 * the same page. Set up RSP so that RSP[31:16] contains the
759 * respective 16 bits of the /userspace/ RSP and RSP nonetheless
760 * still points to an RO alias of the ESPFIX stack.
762 orq PER_CPU_VAR(espfix_stack), %rax
764 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi
765 swapgs /* to user GS */
766 popq %rdi /* Restore user RDI */
769 UNWIND_HINT_IRET_REGS offset=8
772 * At this point, we cannot write to the stack any more, but we can
775 popq %rax /* Restore user RAX */
778 * RSP now points to an ordinary IRET frame, except that the page
779 * is read-only and RSP[31:16] are preloaded with the userspace
780 * values. We can now IRET back to userspace.
782 jmp native_irq_return_iret
784 SYM_CODE_END(common_interrupt_return)
785 _ASM_NOKPROBE(common_interrupt_return)
788 * Reload gs selector with exception handling
791 * Is in entry.text as it shouldn't be instrumented.
793 SYM_FUNC_START(asm_load_gs_index)
797 ANNOTATE_NOENDBR // error_entry
799 2: ALTERNATIVE "", "mfence", X86_BUG_SWAPGS_FENCE
804 /* running with kernelgs */
806 swapgs /* switch back to user gs */
808 /* This can't be a string because the preprocessor needs to see it. */
809 movl $__USER_DS, %eax
812 ALTERNATIVE "", "ZAP_GS", X86_BUG_NULL_SEG
817 _ASM_EXTABLE(.Lgs_change, .Lbad_gs)
819 SYM_FUNC_END(asm_load_gs_index)
820 EXPORT_SYMBOL(asm_load_gs_index)
824 * A note on the "critical region" in our callback handler.
825 * We want to avoid stacking callback handlers due to events occurring
826 * during handling of the last event. To do this, we keep events disabled
827 * until we've done all processing. HOWEVER, we must enable events before
828 * popping the stack frame (can't be done atomically) and so it would still
829 * be possible to get enough handler activations to overflow the stack.
830 * Although unlikely, bugs of that kind are hard to track down, so we'd
831 * like to avoid the possibility.
832 * So, on entry to the handler we detect whether we interrupted an
833 * existing activation in its critical region -- if so, we pop the current
834 * activation and restart the handler using the previous one.
836 * C calling convention: exc_xen_hypervisor_callback(struct *pt_regs)
839 SYM_CODE_START_LOCAL_NOALIGN(exc_xen_hypervisor_callback)
842 * Since we don't modify %rdi, evtchn_do_upall(struct *pt_regs) will
843 * see the correct pointer to the pt_regs
846 movq %rdi, %rsp /* we don't return, adjust the stack frame */
849 call xen_pv_evtchn_do_upcall
852 SYM_CODE_END(exc_xen_hypervisor_callback)
855 * Hypervisor uses this for application faults while it executes.
856 * We get here for two reasons:
857 * 1. Fault while reloading DS, ES, FS or GS
858 * 2. Fault while executing IRET
859 * Category 1 we do not need to fix up as Xen has already reloaded all segment
860 * registers that could be reloaded and zeroed the others.
861 * Category 2 we fix up by killing the current process. We cannot use the
862 * normal Linux return path in this case because if we use the IRET hypercall
863 * to pop the stack frame we end up in an infinite loop of failsafe callbacks.
864 * We distinguish between categories by comparing each saved segment register
865 * with its current contents: any discrepancy means we in category 1.
868 SYM_CODE_START_NOALIGN(xen_failsafe_callback)
869 UNWIND_HINT_UNDEFINED
883 /* All segments match their saved values => Category 2 (Bad IRET). */
888 UNWIND_HINT_IRET_REGS offset=8
889 jmp asm_exc_general_protection
890 1: /* Segment mismatch => Category 1 (Bad segment). Retry the IRET. */
894 UNWIND_HINT_IRET_REGS
895 pushq $-1 /* orig_ax = -1 => not a system call */
899 SYM_CODE_END(xen_failsafe_callback)
900 #endif /* CONFIG_XEN_PV */
903 * Save all registers in pt_regs. Return GSBASE related information
904 * in EBX depending on the availability of the FSGSBASE instructions:
907 * N 0 -> SWAPGS on exit
908 * 1 -> no SWAPGS on exit
910 * Y GSBASE value at entry, must be restored in paranoid_exit
913 * R15 - old SPEC_CTRL
915 SYM_CODE_START(paranoid_entry)
918 PUSH_AND_CLEAR_REGS save_ret=1
919 ENCODE_FRAME_POINTER 8
922 * Always stash CR3 in %r14. This value will be restored,
923 * verbatim, at exit. Needed if paranoid_entry interrupted
924 * another entry that already switched to the user CR3 value
925 * but has not yet returned to userspace.
927 * This is also why CS (stashed in the "iret frame" by the
928 * hardware at entry) can not be used: this may be a return
929 * to kernel code, but with a user CR3 value.
931 * Switching CR3 does not depend on kernel GSBASE so it can
932 * be done before switching to the kernel GSBASE. This is
933 * required for FSGSBASE because the kernel GSBASE has to
934 * be retrieved from a kernel internal table.
936 SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg=%rax save_reg=%r14
939 * Handling GSBASE depends on the availability of FSGSBASE.
941 * Without FSGSBASE the kernel enforces that negative GSBASE
942 * values indicate kernel GSBASE. With FSGSBASE no assumptions
943 * can be made about the GSBASE value when entering from user
946 ALTERNATIVE "jmp .Lparanoid_entry_checkgs", "", X86_FEATURE_FSGSBASE
949 * Read the current GSBASE and store it in %rbx unconditionally,
950 * retrieve and set the current CPUs kernel GSBASE. The stored value
951 * has to be restored in paranoid_exit unconditionally.
953 * The unconditional write to GS base below ensures that no subsequent
954 * loads based on a mispredicted GS base can happen, therefore no LFENCE
957 SAVE_AND_SET_GSBASE scratch_reg=%rax save_reg=%rbx
958 jmp .Lparanoid_gsbase_done
960 .Lparanoid_entry_checkgs:
961 /* EBX = 1 -> kernel GSBASE active, no restore required */
965 * The kernel-enforced convention is a negative GSBASE indicates
966 * a kernel value. No SWAPGS needed on entry and exit.
968 movl $MSR_GS_BASE, %ecx
971 js .Lparanoid_kernel_gsbase
973 /* EBX = 0 -> SWAPGS required on exit */
976 .Lparanoid_kernel_gsbase:
977 FENCE_SWAPGS_KERNEL_ENTRY
978 .Lparanoid_gsbase_done:
981 * Once we have CR3 and %GS setup save and set SPEC_CTRL. Just like
982 * CR3 above, keep the old value in a callee saved register.
984 IBRS_ENTER save_reg=%r15
985 UNTRAIN_RET_FROM_CALL
988 SYM_CODE_END(paranoid_entry)
991 * "Paranoid" exit path from exception stack. This is invoked
992 * only on return from non-NMI IST interrupts that came
995 * We may be returning to very strange contexts (e.g. very early
996 * in syscall entry), so checking for preemption here would
997 * be complicated. Fortunately, there's no good reason to try
998 * to handle preemption here.
1000 * R/EBX contains the GSBASE related information depending on the
1001 * availability of the FSGSBASE instructions:
1004 * N 0 -> SWAPGS on exit
1005 * 1 -> no SWAPGS on exit
1007 * Y User space GSBASE, must be restored unconditionally
1010 * R15 - old SPEC_CTRL
1012 SYM_CODE_START_LOCAL(paranoid_exit)
1016 * Must restore IBRS state before both CR3 and %GS since we need access
1017 * to the per-CPU x86_spec_ctrl_shadow variable.
1019 IBRS_EXIT save_reg=%r15
1022 * The order of operations is important. RESTORE_CR3 requires
1025 * NB to anyone to try to optimize this code: this code does
1026 * not execute at all for exceptions from user mode. Those
1027 * exceptions go through error_return instead.
1029 RESTORE_CR3 scratch_reg=%rax save_reg=%r14
1031 /* Handle the three GSBASE cases */
1032 ALTERNATIVE "jmp .Lparanoid_exit_checkgs", "", X86_FEATURE_FSGSBASE
1034 /* With FSGSBASE enabled, unconditionally restore GSBASE */
1036 jmp restore_regs_and_return_to_kernel
1038 .Lparanoid_exit_checkgs:
1039 /* On non-FSGSBASE systems, conditionally do SWAPGS */
1041 jnz restore_regs_and_return_to_kernel
1043 /* We are returning to a context with user GSBASE */
1045 jmp restore_regs_and_return_to_kernel
1046 SYM_CODE_END(paranoid_exit)
1049 * Switch GS and CR3 if needed.
1051 SYM_CODE_START(error_entry)
1055 PUSH_AND_CLEAR_REGS save_ret=1
1056 ENCODE_FRAME_POINTER 8
1058 testb $3, CS+8(%rsp)
1059 jz .Lerror_kernelspace
1062 * We entered from user mode or we're pretending to have entered
1063 * from user mode due to an IRET fault.
1066 FENCE_SWAPGS_USER_ENTRY
1067 /* We have user CR3. Change to kernel CR3. */
1068 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax
1070 UNTRAIN_RET_FROM_CALL
1072 leaq 8(%rsp), %rdi /* arg0 = pt_regs pointer */
1073 /* Put us onto the real thread stack. */
1077 * There are two places in the kernel that can potentially fault with
1078 * usergs. Handle them here. B stepping K8s sometimes report a
1079 * truncated RIP for IRET exceptions returning to compat mode. Check
1080 * for these here too.
1082 .Lerror_kernelspace:
1083 leaq native_irq_return_iret(%rip), %rcx
1084 cmpq %rcx, RIP+8(%rsp)
1086 movl %ecx, %eax /* zero extend */
1087 cmpq %rax, RIP+8(%rsp)
1089 cmpq $.Lgs_change, RIP+8(%rsp)
1090 jne .Lerror_entry_done_lfence
1093 * hack: .Lgs_change can fail with user gsbase. If this happens, fix up
1094 * gsbase and proceed. We'll fix up the exception and land in
1095 * .Lgs_change's error handler with kernel gsbase.
1100 * Issue an LFENCE to prevent GS speculation, regardless of whether it is a
1101 * kernel or user gsbase.
1103 .Lerror_entry_done_lfence:
1104 FENCE_SWAPGS_KERNEL_ENTRY
1106 leaq 8(%rsp), %rax /* return pt_regs pointer */
1111 /* Fix truncated RIP */
1112 movq %rcx, RIP+8(%rsp)
1117 * We came from an IRET to user mode, so we have user
1118 * gsbase and CR3. Switch to kernel gsbase and CR3:
1121 FENCE_SWAPGS_USER_ENTRY
1122 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax
1124 UNTRAIN_RET_FROM_CALL
1127 * Pretend that the exception came from user mode: set up pt_regs
1128 * as if we faulted immediately after IRET.
1130 leaq 8(%rsp), %rdi /* arg0 = pt_regs pointer */
1134 SYM_CODE_END(error_entry)
1136 SYM_CODE_START_LOCAL(error_return)
1138 DEBUG_ENTRY_ASSERT_IRQS_OFF
1140 jz restore_regs_and_return_to_kernel
1141 jmp swapgs_restore_regs_and_return_to_usermode
1142 SYM_CODE_END(error_return)
1145 * Runs on exception stack. Xen PV does not go through this path at all,
1146 * so we can use real assembly here.
1149 * %r14: Used to save/restore the CR3 of the interrupted context
1150 * when PAGE_TABLE_ISOLATION is in use. Do not clobber.
1152 SYM_CODE_START(asm_exc_nmi)
1153 UNWIND_HINT_IRET_ENTRY
1157 * We allow breakpoints in NMIs. If a breakpoint occurs, then
1158 * the iretq it performs will take us out of NMI context.
1159 * This means that we can have nested NMIs where the next
1160 * NMI is using the top of the stack of the previous NMI. We
1161 * can't let it execute because the nested NMI will corrupt the
1162 * stack of the previous NMI. NMI handlers are not re-entrant
1165 * To handle this case we do the following:
1166 * Check a special location on the stack that contains a
1167 * variable that is set when NMIs are executing.
1168 * The interrupted task's stack is also checked to see if it
1170 * If the variable is not set and the stack is not the NMI
1172 * o Set the special variable on the stack
1173 * o Copy the interrupt frame into an "outermost" location on the
1175 * o Copy the interrupt frame into an "iret" location on the stack
1176 * o Continue processing the NMI
1177 * If the variable is set or the previous stack is the NMI stack:
1178 * o Modify the "iret" location to jump to the repeat_nmi
1179 * o return back to the first NMI
1181 * Now on exit of the first NMI, we first clear the stack variable
1182 * The NMI stack will tell any nested NMIs at that point that it is
1183 * nested. Then we pop the stack normally with iret, and if there was
1184 * a nested NMI that updated the copy interrupt stack frame, a
1185 * jump will be made to the repeat_nmi code that will handle the second
1188 * However, espfix prevents us from directly returning to userspace
1189 * with a single IRET instruction. Similarly, IRET to user mode
1190 * can fault. We therefore handle NMIs from user space like
1191 * other IST entries.
1197 /* Use %rdx as our temp variable throughout */
1200 testb $3, CS-RIP+8(%rsp)
1201 jz .Lnmi_from_kernel
1204 * NMI from user mode. We need to run on the thread stack, but we
1205 * can't go through the normal entry paths: NMIs are masked, and
1206 * we don't want to enable interrupts, because then we'll end
1207 * up in an awkward situation in which IRQs are on but NMIs
1210 * We also must not push anything to the stack before switching
1211 * stacks lest we corrupt the "NMI executing" variable.
1215 FENCE_SWAPGS_USER_ENTRY
1216 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdx
1218 movq PER_CPU_VAR(pcpu_hot + X86_top_of_stack), %rsp
1219 UNWIND_HINT_IRET_REGS base=%rdx offset=8
1220 pushq 5*8(%rdx) /* pt_regs->ss */
1221 pushq 4*8(%rdx) /* pt_regs->rsp */
1222 pushq 3*8(%rdx) /* pt_regs->flags */
1223 pushq 2*8(%rdx) /* pt_regs->cs */
1224 pushq 1*8(%rdx) /* pt_regs->rip */
1225 UNWIND_HINT_IRET_REGS
1226 pushq $-1 /* pt_regs->orig_ax */
1227 PUSH_AND_CLEAR_REGS rdx=(%rdx)
1228 ENCODE_FRAME_POINTER
1234 * At this point we no longer need to worry about stack damage
1235 * due to nesting -- we're on the normal thread stack and we're
1236 * done with the NMI stack.
1243 * Return back to user mode. We must *not* do the normal exit
1244 * work, because we don't want to enable interrupts.
1246 jmp swapgs_restore_regs_and_return_to_usermode
1250 * Here's what our stack frame will look like:
1251 * +---------------------------------------------------------+
1253 * | original Return RSP |
1254 * | original RFLAGS |
1257 * +---------------------------------------------------------+
1258 * | temp storage for rdx |
1259 * +---------------------------------------------------------+
1260 * | "NMI executing" variable |
1261 * +---------------------------------------------------------+
1262 * | iret SS } Copied from "outermost" frame |
1263 * | iret Return RSP } on each loop iteration; overwritten |
1264 * | iret RFLAGS } by a nested NMI to force another |
1265 * | iret CS } iteration if needed. |
1267 * +---------------------------------------------------------+
1268 * | outermost SS } initialized in first_nmi; |
1269 * | outermost Return RSP } will not be changed before |
1270 * | outermost RFLAGS } NMI processing is done. |
1271 * | outermost CS } Copied to "iret" frame on each |
1272 * | outermost RIP } iteration. |
1273 * +---------------------------------------------------------+
1275 * +---------------------------------------------------------+
1277 * The "original" frame is used by hardware. Before re-enabling
1278 * NMIs, we need to be done with it, and we need to leave enough
1279 * space for the asm code here.
1281 * We return by executing IRET while RSP points to the "iret" frame.
1282 * That will either return for real or it will loop back into NMI
1285 * The "outermost" frame is copied to the "iret" frame on each
1286 * iteration of the loop, so each iteration starts with the "iret"
1287 * frame pointing to the final return target.
1291 * Determine whether we're a nested NMI.
1293 * If we interrupted kernel code between repeat_nmi and
1294 * end_repeat_nmi, then we are a nested NMI. We must not
1295 * modify the "iret" frame because it's being written by
1296 * the outer NMI. That's okay; the outer NMI handler is
1297 * about to call exc_nmi() anyway, so we can just resume
1301 movq $repeat_nmi, %rdx
1304 movq $end_repeat_nmi, %rdx
1310 * Now check "NMI executing". If it's set, then we're nested.
1311 * This will not detect if we interrupted an outer NMI just
1318 * Now test if the previous stack was an NMI stack. This covers
1319 * the case where we interrupt an outer NMI after it clears
1320 * "NMI executing" but before IRET. We need to be careful, though:
1321 * there is one case in which RSP could point to the NMI stack
1322 * despite there being no NMI active: naughty userspace controls
1323 * RSP at the very beginning of the SYSCALL targets. We can
1324 * pull a fast one on naughty userspace, though: we program
1325 * SYSCALL to mask DF, so userspace cannot cause DF to be set
1326 * if it controls the kernel's RSP. We set DF before we clear
1330 /* Compare the NMI stack (rdx) with the stack we came from (4*8(%rsp)) */
1331 cmpq %rdx, 4*8(%rsp)
1332 /* If the stack pointer is above the NMI stack, this is a normal NMI */
1335 subq $EXCEPTION_STKSZ, %rdx
1336 cmpq %rdx, 4*8(%rsp)
1337 /* If it is below the NMI stack, it is a normal NMI */
1340 /* Ah, it is within the NMI stack. */
1342 testb $(X86_EFLAGS_DF >> 8), (3*8 + 1)(%rsp)
1343 jz first_nmi /* RSP was user controlled. */
1345 /* This is a nested NMI. */
1349 * Modify the "iret" frame to point to repeat_nmi, forcing another
1350 * iteration of NMI handling.
1353 leaq -10*8(%rsp), %rdx
1360 /* Put stack back */
1366 /* We are returning to kernel mode, so this cannot result in a fault. */
1373 /* Make room for "NMI executing". */
1376 /* Leave room for the "iret" frame */
1379 /* Copy the "original" frame to the "outermost" frame */
1383 UNWIND_HINT_IRET_REGS
1385 /* Everything up to here is safe from nested NMIs */
1387 #ifdef CONFIG_DEBUG_ENTRY
1389 * For ease of testing, unmask NMIs right away. Disabled by
1390 * default because IRET is very expensive.
1393 pushq %rsp /* RSP (minus 8 because of the previous push) */
1394 addq $8, (%rsp) /* Fix up RSP */
1396 pushq $__KERNEL_CS /* CS */
1398 iretq /* continues at repeat_nmi below */
1399 UNWIND_HINT_IRET_REGS
1404 ANNOTATE_NOENDBR // this code
1406 * If there was a nested NMI, the first NMI's iret will return
1407 * here. But NMIs are still enabled and we can take another
1408 * nested NMI. The nested NMI checks the interrupted RIP to see
1409 * if it is between repeat_nmi and end_repeat_nmi, and if so
1410 * it will just return, as we are about to repeat an NMI anyway.
1411 * This makes it safe to copy to the stack frame that a nested
1414 * RSP is pointing to "outermost RIP". gsbase is unknown, but, if
1415 * we're repeating an NMI, gsbase has the same value that it had on
1416 * the first iteration. paranoid_entry will load the kernel
1417 * gsbase if needed before we call exc_nmi(). "NMI executing"
1420 movq $1, 10*8(%rsp) /* Set "NMI executing". */
1423 * Copy the "outermost" frame to the "iret" frame. NMIs that nest
1424 * here must not modify the "iret" frame while we're writing to
1425 * it or it will end up containing garbage.
1433 ANNOTATE_NOENDBR // this code
1436 * Everything below this point can be preempted by a nested NMI.
1437 * If this happens, then the inner NMI will change the "iret"
1438 * frame to point back to repeat_nmi.
1440 pushq $-1 /* ORIG_RAX: no syscall to restart */
1443 * Use paranoid_entry to handle SWAPGS, but no need to use paranoid_exit
1444 * as we should not be calling schedule in NMI context.
1445 * Even with normal interrupts enabled. An NMI should not be
1446 * setting NEED_RESCHED or anything that normal interrupts and
1447 * exceptions might do.
1455 /* Always restore stashed SPEC_CTRL value (see paranoid_entry) */
1456 IBRS_EXIT save_reg=%r15
1458 /* Always restore stashed CR3 value (see paranoid_entry) */
1459 RESTORE_CR3 scratch_reg=%r15 save_reg=%r14
1462 * The above invocation of paranoid_entry stored the GSBASE
1463 * related information in R/EBX depending on the availability
1466 * If FSGSBASE is enabled, restore the saved GSBASE value
1467 * unconditionally, otherwise take the conditional SWAPGS path.
1469 ALTERNATIVE "jmp nmi_no_fsgsbase", "", X86_FEATURE_FSGSBASE
1475 /* EBX == 0 -> invoke SWAPGS */
1486 * Skip orig_ax and the "outermost" frame to point RSP at the "iret"
1487 * at the "iret" frame.
1492 * Clear "NMI executing". Set DF first so that we can easily
1493 * distinguish the remaining code between here and IRET from
1494 * the SYSCALL entry and exit paths.
1496 * We arguably should just inspect RIP instead, but I (Andy) wrote
1497 * this code when I had the misapprehension that Xen PV supported
1498 * NMIs, and Xen PV would break that approach.
1501 movq $0, 5*8(%rsp) /* clear "NMI executing" */
1504 * iretq reads the "iret" frame and exits the NMI stack in a
1505 * single instruction. We are returning to kernel mode, so this
1506 * cannot result in a fault. Similarly, we don't need to worry
1507 * about espfix64 on the way back to kernel mode.
1510 SYM_CODE_END(asm_exc_nmi)
1512 #ifndef CONFIG_IA32_EMULATION
1514 * This handles SYSCALL from 32-bit code. There is no way to program
1515 * MSRs to fully disable 32-bit SYSCALL.
1517 SYM_CODE_START(ignore_sysret)
1518 UNWIND_HINT_END_OF_STACK
1522 SYM_CODE_END(ignore_sysret)
1525 .pushsection .text, "ax"
1527 SYM_CODE_START_NOALIGN(rewind_stack_and_make_dead)
1529 /* Prevent any naive code from trying to unwind to our caller. */
1532 movq PER_CPU_VAR(pcpu_hot + X86_top_of_stack), %rax
1533 leaq -PTREGS_SIZE(%rax), %rsp
1537 SYM_CODE_END(rewind_stack_and_make_dead)