2 * linux/arch/sparc64/kernel/setup.c
4 * Copyright (C) 1995,1996 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
8 #include <linux/errno.h>
9 #include <linux/sched.h>
10 #include <linux/kernel.h>
12 #include <linux/stddef.h>
13 #include <linux/unistd.h>
14 #include <linux/ptrace.h>
16 #include <linux/user.h>
17 #include <linux/screen_info.h>
18 #include <linux/delay.h>
20 #include <linux/seq_file.h>
21 #include <linux/syscalls.h>
22 #include <linux/kdev_t.h>
23 #include <linux/major.h>
24 #include <linux/string.h>
25 #include <linux/init.h>
26 #include <linux/inet.h>
27 #include <linux/console.h>
28 #include <linux/root_dev.h>
29 #include <linux/interrupt.h>
30 #include <linux/cpu.h>
31 #include <linux/initrd.h>
32 #include <linux/module.h>
33 #include <linux/start_kernel.h>
34 #include <linux/bootmem.h>
37 #include <asm/processor.h>
38 #include <asm/oplib.h>
40 #include <asm/pgtable.h>
41 #include <asm/idprom.h>
43 #include <asm/starfire.h>
44 #include <asm/mmu_context.h>
45 #include <asm/timer.h>
46 #include <asm/sections.h>
47 #include <asm/setup.h>
49 #include <asm/ns87303.h>
50 #include <asm/btext.h>
52 #include <asm/mdesc.h>
53 #include <asm/cacheflush.h>
58 #include <net/ipconfig.h>
64 /* Used to synchronize accesses to NatSemi SUPER I/O chip configure
65 * operations in asm/ns87303.h
67 DEFINE_SPINLOCK(ns87303_lock);
68 EXPORT_SYMBOL(ns87303_lock);
70 struct screen_info screen_info = {
71 0, 0, /* orig-x, orig-y */
73 0, /* orig-video-page */
74 0, /* orig-video-mode */
75 128, /* orig-video-cols */
76 0, 0, 0, /* unused, ega_bx, unused */
77 54, /* orig-video-lines */
78 0, /* orig-video-isVGA */
79 16 /* orig-video-points */
83 prom_console_write(struct console *con, const char *s, unsigned int n)
88 /* Exported for mm/init.c:paging_init. */
89 unsigned long cmdline_memory_size = 0;
91 static struct console prom_early_console = {
93 .write = prom_console_write,
94 .flags = CON_PRINTBUFFER | CON_BOOT | CON_ANYTIME,
99 * Process kernel command line switches that are specific to the
100 * SPARC or that require special low-level processing.
102 static void __init process_switch(char c)
109 prom_printf("boot_flags_init: Halt!\n");
113 prom_early_console.flags &= ~CON_BOOT;
116 /* Force UltraSPARC-III P-Cache on. */
117 if (tlb_type != cheetah) {
118 printk("BOOT: Ignoring P-Cache force option.\n");
121 cheetah_pcache_forced_on = 1;
122 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
123 cheetah_enable_pcache();
127 printk("Unknown boot switch (-%c)\n", c);
132 static void __init boot_flags_init(char *commands)
135 /* Move to the start of the next "argument". */
136 while (*commands == ' ')
139 /* Process any command switches, otherwise skip it. */
140 if (*commands == '\0')
142 if (*commands == '-') {
144 while (*commands && *commands != ' ')
145 process_switch(*commands++);
148 if (!strncmp(commands, "mem=", 4))
149 cmdline_memory_size = memparse(commands + 4, &commands);
151 while (*commands && *commands != ' ')
156 extern unsigned short root_flags;
157 extern unsigned short root_dev;
158 extern unsigned short ram_flags;
159 #define RAMDISK_IMAGE_START_MASK 0x07FF
160 #define RAMDISK_PROMPT_FLAG 0x8000
161 #define RAMDISK_LOAD_FLAG 0x4000
163 extern int root_mountflags;
165 char reboot_command[COMMAND_LINE_SIZE];
167 static struct pt_regs fake_swapper_regs = { { 0, }, 0, 0, 0, 0 };
169 static void __init per_cpu_patch(void)
171 struct cpuid_patch_entry *p;
175 if (tlb_type == spitfire && !this_is_starfire)
179 if (tlb_type != hypervisor) {
180 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
181 is_jbus = ((ver >> 32UL) == __JALAPENO_ID ||
182 (ver >> 32UL) == __SERRANO_ID);
186 while (p < &__cpuid_patch_end) {
187 unsigned long addr = p->addr;
192 insns = &p->starfire[0];
197 insns = &p->cheetah_jbus[0];
199 insns = &p->cheetah_safari[0];
202 insns = &p->sun4v[0];
205 prom_printf("Unknown cpu type, halting.\n");
209 *(unsigned int *) (addr + 0) = insns[0];
211 __asm__ __volatile__("flush %0" : : "r" (addr + 0));
213 *(unsigned int *) (addr + 4) = insns[1];
215 __asm__ __volatile__("flush %0" : : "r" (addr + 4));
217 *(unsigned int *) (addr + 8) = insns[2];
219 __asm__ __volatile__("flush %0" : : "r" (addr + 8));
221 *(unsigned int *) (addr + 12) = insns[3];
223 __asm__ __volatile__("flush %0" : : "r" (addr + 12));
229 void sun4v_patch_1insn_range(struct sun4v_1insn_patch_entry *start,
230 struct sun4v_1insn_patch_entry *end)
232 while (start < end) {
233 unsigned long addr = start->addr;
235 *(unsigned int *) (addr + 0) = start->insn;
237 __asm__ __volatile__("flush %0" : : "r" (addr + 0));
243 void sun4v_patch_2insn_range(struct sun4v_2insn_patch_entry *start,
244 struct sun4v_2insn_patch_entry *end)
246 while (start < end) {
247 unsigned long addr = start->addr;
249 *(unsigned int *) (addr + 0) = start->insns[0];
251 __asm__ __volatile__("flush %0" : : "r" (addr + 0));
253 *(unsigned int *) (addr + 4) = start->insns[1];
255 __asm__ __volatile__("flush %0" : : "r" (addr + 4));
261 void sun_m7_patch_2insn_range(struct sun4v_2insn_patch_entry *start,
262 struct sun4v_2insn_patch_entry *end)
264 while (start < end) {
265 unsigned long addr = start->addr;
267 *(unsigned int *) (addr + 0) = start->insns[0];
269 __asm__ __volatile__("flush %0" : : "r" (addr + 0));
271 *(unsigned int *) (addr + 4) = start->insns[1];
273 __asm__ __volatile__("flush %0" : : "r" (addr + 4));
279 static void __init sun4v_patch(void)
281 extern void sun4v_hvapi_init(void);
283 if (tlb_type != hypervisor)
286 sun4v_patch_1insn_range(&__sun4v_1insn_patch,
287 &__sun4v_1insn_patch_end);
289 sun4v_patch_2insn_range(&__sun4v_2insn_patch,
290 &__sun4v_2insn_patch_end);
292 switch (sun4v_chip_type) {
293 case SUN4V_CHIP_SPARC_M7:
294 case SUN4V_CHIP_SPARC_M8:
295 case SUN4V_CHIP_SPARC_SN:
296 sun_m7_patch_2insn_range(&__sun_m7_2insn_patch,
297 &__sun_m7_2insn_patch_end);
303 if (sun4v_chip_type != SUN4V_CHIP_NIAGARA1) {
304 sun4v_patch_1insn_range(&__fast_win_ctrl_1insn_patch,
305 &__fast_win_ctrl_1insn_patch_end);
311 static void __init popc_patch(void)
313 struct popc_3insn_patch_entry *p3;
314 struct popc_6insn_patch_entry *p6;
316 p3 = &__popc_3insn_patch;
317 while (p3 < &__popc_3insn_patch_end) {
318 unsigned long i, addr = p3->addr;
320 for (i = 0; i < 3; i++) {
321 *(unsigned int *) (addr + (i * 4)) = p3->insns[i];
323 __asm__ __volatile__("flush %0"
324 : : "r" (addr + (i * 4)));
330 p6 = &__popc_6insn_patch;
331 while (p6 < &__popc_6insn_patch_end) {
332 unsigned long i, addr = p6->addr;
334 for (i = 0; i < 6; i++) {
335 *(unsigned int *) (addr + (i * 4)) = p6->insns[i];
337 __asm__ __volatile__("flush %0"
338 : : "r" (addr + (i * 4)));
345 static void __init pause_patch(void)
347 struct pause_patch_entry *p;
349 p = &__pause_3insn_patch;
350 while (p < &__pause_3insn_patch_end) {
351 unsigned long i, addr = p->addr;
353 for (i = 0; i < 3; i++) {
354 *(unsigned int *) (addr + (i * 4)) = p->insns[i];
356 __asm__ __volatile__("flush %0"
357 : : "r" (addr + (i * 4)));
364 void __init start_early_boot(void)
373 cpu = hard_smp_processor_id();
374 if (cpu >= NR_CPUS) {
375 prom_printf("Serious problem, boot cpu id (%d) >= NR_CPUS (%d)\n",
379 current_thread_info()->cpu = cpu;
386 /* On Ultra, we support all of the v8 capabilities. */
387 unsigned long sparc64_elf_hwcap = (HWCAP_SPARC_FLUSH | HWCAP_SPARC_STBAR |
388 HWCAP_SPARC_SWAP | HWCAP_SPARC_MULDIV |
390 EXPORT_SYMBOL(sparc64_elf_hwcap);
392 static const char *hwcaps[] = {
393 "flush", "stbar", "swap", "muldiv", "v9",
394 "ultra3", "blkinit", "n2",
396 /* These strings are as they appear in the machine description
397 * 'hwcap-list' property for cpu nodes.
399 "mul32", "div32", "fsmuld", "v8plus", "popc", "vis", "vis2",
400 "ASIBlkInit", "fmaf", "vis3", "hpc", "random", "trans", "fjfmau",
401 "ima", "cspare", "pause", "cbcond", NULL /*reserved for crypto */,
405 static const char *crypto_hwcaps[] = {
406 "aes", "des", "kasumi", "camellia", "md5", "sha1", "sha256",
407 "sha512", "mpmul", "montmul", "montsqr", "crc32c",
410 void cpucap_info(struct seq_file *m)
412 unsigned long caps = sparc64_elf_hwcap;
415 seq_puts(m, "cpucaps\t\t: ");
416 for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
417 unsigned long bit = 1UL << i;
418 if (hwcaps[i] && (caps & bit)) {
419 seq_printf(m, "%s%s",
420 printed ? "," : "", hwcaps[i]);
424 if (caps & HWCAP_SPARC_CRYPTO) {
427 __asm__ __volatile__("rd %%asr26, %0" : "=r" (cfr));
428 for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
429 unsigned long bit = 1UL << i;
431 seq_printf(m, "%s%s",
432 printed ? "," : "", crypto_hwcaps[i]);
440 static void __init report_one_hwcap(int *printed, const char *name)
443 printk(KERN_INFO "CPU CAPS: [");
444 printk(KERN_CONT "%s%s",
445 (*printed) ? "," : "", name);
446 if (++(*printed) == 8) {
447 printk(KERN_CONT "]\n");
452 static void __init report_crypto_hwcaps(int *printed)
457 __asm__ __volatile__("rd %%asr26, %0" : "=r" (cfr));
459 for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
460 unsigned long bit = 1UL << i;
462 report_one_hwcap(printed, crypto_hwcaps[i]);
466 static void __init report_hwcaps(unsigned long caps)
470 for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
471 unsigned long bit = 1UL << i;
472 if (hwcaps[i] && (caps & bit))
473 report_one_hwcap(&printed, hwcaps[i]);
475 if (caps & HWCAP_SPARC_CRYPTO)
476 report_crypto_hwcaps(&printed);
478 printk(KERN_CONT "]\n");
481 static unsigned long __init mdesc_cpu_hwcap_list(void)
483 struct mdesc_handle *hp;
484 unsigned long caps = 0;
493 pn = mdesc_node_by_name(hp, MDESC_NODE_NULL, "cpu");
494 if (pn == MDESC_NODE_NULL)
497 prop = mdesc_get_property(hp, pn, "hwcap-list", &len);
504 for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
505 unsigned long bit = 1UL << i;
507 if (hwcaps[i] && !strcmp(prop, hwcaps[i])) {
512 for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
513 if (!strcmp(prop, crypto_hwcaps[i]))
514 caps |= HWCAP_SPARC_CRYPTO;
517 plen = strlen(prop) + 1;
527 /* This yields a mask that user programs can use to figure out what
528 * instruction set this cpu supports.
530 static void __init init_sparc64_elf_hwcap(void)
532 unsigned long cap = sparc64_elf_hwcap;
533 unsigned long mdesc_caps;
535 if (tlb_type == cheetah || tlb_type == cheetah_plus)
536 cap |= HWCAP_SPARC_ULTRA3;
537 else if (tlb_type == hypervisor) {
538 if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 ||
539 sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
540 sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
541 sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
542 sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
543 sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
544 sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
545 sun4v_chip_type == SUN4V_CHIP_SPARC_M8 ||
546 sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||
547 sun4v_chip_type == SUN4V_CHIP_SPARC64X)
548 cap |= HWCAP_SPARC_BLKINIT;
549 if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
550 sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
551 sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
552 sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
553 sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
554 sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
555 sun4v_chip_type == SUN4V_CHIP_SPARC_M8 ||
556 sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||
557 sun4v_chip_type == SUN4V_CHIP_SPARC64X)
558 cap |= HWCAP_SPARC_N2;
561 cap |= (AV_SPARC_MUL32 | AV_SPARC_DIV32 | AV_SPARC_V8PLUS);
563 mdesc_caps = mdesc_cpu_hwcap_list();
565 if (tlb_type == spitfire)
567 if (tlb_type == cheetah || tlb_type == cheetah_plus)
568 cap |= AV_SPARC_VIS | AV_SPARC_VIS2;
569 if (tlb_type == cheetah_plus) {
570 unsigned long impl, ver;
572 __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
573 impl = ((ver >> 32) & 0xffff);
574 if (impl == PANTHER_IMPL)
575 cap |= AV_SPARC_POPC;
577 if (tlb_type == hypervisor) {
578 if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1)
579 cap |= AV_SPARC_ASI_BLK_INIT;
580 if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
581 sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
582 sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
583 sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
584 sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
585 sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
586 sun4v_chip_type == SUN4V_CHIP_SPARC_M8 ||
587 sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||
588 sun4v_chip_type == SUN4V_CHIP_SPARC64X)
589 cap |= (AV_SPARC_VIS | AV_SPARC_VIS2 |
590 AV_SPARC_ASI_BLK_INIT |
592 if (sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
593 sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
594 sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
595 sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
596 sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
597 sun4v_chip_type == SUN4V_CHIP_SPARC_M8 ||
598 sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||
599 sun4v_chip_type == SUN4V_CHIP_SPARC64X)
600 cap |= (AV_SPARC_VIS3 | AV_SPARC_HPC |
604 sparc64_elf_hwcap = cap | mdesc_caps;
606 report_hwcaps(sparc64_elf_hwcap);
608 if (sparc64_elf_hwcap & AV_SPARC_POPC)
610 if (sparc64_elf_hwcap & AV_SPARC_PAUSE)
614 void __init alloc_irqstack_bootmem(void)
616 unsigned int i, node;
618 for_each_possible_cpu(i) {
619 node = cpu_to_node(i);
621 softirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node),
624 hardirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node),
630 void __init setup_arch(char **cmdline_p)
632 /* Initialize PROM console and command line. */
633 *cmdline_p = prom_getbootargs();
634 strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE);
637 boot_flags_init(*cmdline_p);
638 #ifdef CONFIG_EARLYFB
639 if (btext_find_display())
641 register_console(&prom_early_console);
643 if (tlb_type == hypervisor)
644 printk("ARCH: SUN4V\n");
646 printk("ARCH: SUN4U\n");
648 #ifdef CONFIG_DUMMY_CONSOLE
649 conswitchp = &dummy_con;
655 root_mountflags &= ~MS_RDONLY;
656 ROOT_DEV = old_decode_dev(root_dev);
657 #ifdef CONFIG_BLK_DEV_RAM
658 rd_image_start = ram_flags & RAMDISK_IMAGE_START_MASK;
659 rd_prompt = ((ram_flags & RAMDISK_PROMPT_FLAG) != 0);
660 rd_doload = ((ram_flags & RAMDISK_LOAD_FLAG) != 0);
663 task_thread_info(&init_task)->kregs = &fake_swapper_regs;
666 if (!ic_set_manually) {
667 phandle chosen = prom_finddevice("/chosen");
670 cl = prom_getintdefault (chosen, "client-ip", 0);
671 sv = prom_getintdefault (chosen, "server-ip", 0);
672 gw = prom_getintdefault (chosen, "gateway-ip", 0);
678 #if defined(CONFIG_IP_PNP_BOOTP) || defined(CONFIG_IP_PNP_RARP)
679 ic_proto_enabled = 0;
685 /* Get boot processor trap_block[] setup. */
686 init_cur_cpu_trap(current_thread_info());
689 init_sparc64_elf_hwcap();
690 smp_fill_in_cpu_possible_map();
692 * Once the OF device tree and MDESC have been setup and nr_cpus has
693 * been parsed, we know the list of possible cpus. Therefore we can
694 * allocate the IRQ stacks.
696 alloc_irqstack_bootmem();
699 extern int stop_a_enabled;
701 void sun_do_break(void)
707 flush_user_windows();
711 EXPORT_SYMBOL(sun_do_break);
713 int stop_a_enabled = 1;
714 EXPORT_SYMBOL(stop_a_enabled);