1 /* SPDX-License-Identifier: GPL-2.0 */
3 * S390 low-level entry points.
5 * Copyright IBM Corp. 1999, 2012
6 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
7 * Hartmut Penner (hp@de.ibm.com),
8 * Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com),
9 * Heiko Carstens <heiko.carstens@de.ibm.com>
12 #include <linux/init.h>
13 #include <linux/linkage.h>
14 #include <asm/alternative-asm.h>
15 #include <asm/processor.h>
16 #include <asm/cache.h>
17 #include <asm/ctl_reg.h>
18 #include <asm/dwarf.h>
19 #include <asm/errno.h>
20 #include <asm/ptrace.h>
21 #include <asm/thread_info.h>
22 #include <asm/asm-offsets.h>
23 #include <asm/unistd.h>
27 #include <asm/vx-insn.h>
28 #include <asm/setup.h>
30 #include <asm/export.h>
33 __PT_R1 = __PT_GPRS + 8
34 __PT_R2 = __PT_GPRS + 16
35 __PT_R3 = __PT_GPRS + 24
36 __PT_R4 = __PT_GPRS + 32
37 __PT_R5 = __PT_GPRS + 40
38 __PT_R6 = __PT_GPRS + 48
39 __PT_R7 = __PT_GPRS + 56
40 __PT_R8 = __PT_GPRS + 64
41 __PT_R9 = __PT_GPRS + 72
42 __PT_R10 = __PT_GPRS + 80
43 __PT_R11 = __PT_GPRS + 88
44 __PT_R12 = __PT_GPRS + 96
45 __PT_R13 = __PT_GPRS + 104
46 __PT_R14 = __PT_GPRS + 112
47 __PT_R15 = __PT_GPRS + 120
49 STACK_SHIFT = PAGE_SHIFT + THREAD_SIZE_ORDER
50 STACK_SIZE = 1 << STACK_SHIFT
51 STACK_INIT = STACK_SIZE - STACK_FRAME_OVERHEAD - __PT_SIZE
53 _TIF_WORK = (_TIF_SIGPENDING | _TIF_NOTIFY_RESUME | _TIF_NEED_RESCHED | \
54 _TIF_UPROBE | _TIF_GUARDED_STORAGE | _TIF_PATCH_PENDING)
55 _TIF_TRACE = (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT | _TIF_SECCOMP | \
56 _TIF_SYSCALL_TRACEPOINT)
57 _CIF_WORK = (_CIF_MCCK_PENDING | _CIF_ASCE_PRIMARY | \
58 _CIF_ASCE_SECONDARY | _CIF_FPU)
59 _PIF_WORK = (_PIF_PER_TRAP | _PIF_SYSCALL_RESTART)
61 _LPP_OFFSET = __LC_LPP
63 #define BASED(name) name-cleanup_critical(%r13)
66 #ifdef CONFIG_TRACE_IRQFLAGS
68 brasl %r14,trace_hardirqs_on_caller
73 #ifdef CONFIG_TRACE_IRQFLAGS
75 brasl %r14,trace_hardirqs_off_caller
79 .macro LOCKDEP_SYS_EXIT
81 tm __PT_PSW+1(%r11),0x01 # returning to user ?
83 brasl %r14,lockdep_sys_exit
87 .macro CHECK_STACK stacksize,savearea
88 #ifdef CONFIG_CHECK_STACK
89 tml %r15,\stacksize - CONFIG_STACK_GUARD
95 .macro SWITCH_ASYNC savearea,timer
96 tmhh %r8,0x0001 # interrupting from user ?
99 slg %r14,BASED(.Lcritical_start)
100 clg %r14,BASED(.Lcritical_length)
102 lghi %r11,\savearea # inside critical section, do cleanup
103 brasl %r14,cleanup_critical
104 tmhh %r8,0x0001 # retest problem state after cleanup
106 0: lg %r14,__LC_ASYNC_STACK # are we already on the async stack?
108 srag %r14,%r14,STACK_SHIFT
110 CHECK_STACK 1<<STACK_SHIFT,\savearea
111 aghi %r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
113 1: UPDATE_VTIME %r14,%r15,\timer
114 BPENTER __TI_flags(%r12),_TIF_ISOLATE_BP
115 2: lg %r15,__LC_ASYNC_STACK # load async stack
116 3: la %r11,STACK_FRAME_OVERHEAD(%r15)
119 .macro UPDATE_VTIME w1,w2,enter_timer
120 lg \w1,__LC_EXIT_TIMER
121 lg \w2,__LC_LAST_UPDATE_TIMER
123 slg \w2,__LC_EXIT_TIMER
124 alg \w1,__LC_USER_TIMER
125 alg \w2,__LC_SYSTEM_TIMER
126 stg \w1,__LC_USER_TIMER
127 stg \w2,__LC_SYSTEM_TIMER
128 mvc __LC_LAST_UPDATE_TIMER(8),\enter_timer
132 stg %r8,__LC_RETURN_PSW
133 ni __LC_RETURN_PSW,0xbf
138 #ifdef CONFIG_HAVE_MARCH_Z9_109_FEATURES
139 .insn s,0xb27c0000,\savearea # store clock fast
141 .insn s,0xb2050000,\savearea # store clock
146 * The TSTMSK macro generates a test-under-mask instruction by
147 * calculating the memory offset for the specified mask value.
148 * Mask value can be any constant. The macro shifts the mask
149 * value to calculate the memory offset for the test-under-mask
152 .macro TSTMSK addr, mask, size=8, bytepos=0
153 .if (\bytepos < \size) && (\mask >> 8)
155 .error "Mask exceeds byte boundary"
157 TSTMSK \addr, "(\mask >> 8)", \size, "(\bytepos + 1)"
161 .error "Mask must not be zero"
163 off = \size - \bytepos - 1
168 ALTERNATIVE "", ".long 0xb2e8c000", 82
172 ALTERNATIVE "", ".long 0xb2e8d000", 82
175 .macro BPENTER tif_ptr,tif_mask
176 ALTERNATIVE "TSTMSK \tif_ptr,\tif_mask; jz .+8; .long 0xb2e8d000", \
180 .macro BPEXIT tif_ptr,tif_mask
181 TSTMSK \tif_ptr,\tif_mask
182 ALTERNATIVE "jz .+8; .long 0xb2e8c000", \
183 "jnz .+8; .long 0xb2e8d000", 82
186 #ifdef CONFIG_EXPOLINE
188 .macro GEN_BR_THUNK name,reg,tmp
189 .section .text.\name,"axG",@progbits,\name,comdat
192 .type \name,@function
195 #ifdef CONFIG_HAVE_MARCH_Z10_FEATURES
206 GEN_BR_THUNK __s390x_indirect_jump_r1use_r9,%r9,%r1
207 GEN_BR_THUNK __s390x_indirect_jump_r1use_r14,%r14,%r1
208 GEN_BR_THUNK __s390x_indirect_jump_r11use_r14,%r14,%r11
211 0: brasl %r14,__s390x_indirect_jump_r1use_r9
212 .pushsection .s390_indirect_branches,"a",@progbits
218 0: jg __s390x_indirect_jump_r1use_r14
219 .pushsection .s390_indirect_branches,"a",@progbits
225 0: jg __s390x_indirect_jump_r11use_r14
226 .pushsection .s390_indirect_branches,"a",@progbits
231 #else /* CONFIG_EXPOLINE */
245 #endif /* CONFIG_EXPOLINE */
248 .section .kprobes.text, "ax"
251 * This nop exists only in order to avoid that __switch_to starts at
252 * the beginning of the kprobes text section. In that case we would
253 * have several symbols at the same address. E.g. objdump would take
254 * an arbitrary symbol name when disassembling this code.
255 * With the added nop in between the __switch_to symbol is unique
266 * Scheduler resume function, called by switch_to
267 * gpr2 = (task_struct *) prev
268 * gpr3 = (task_struct *) next
273 stmg %r6,%r15,__SF_GPRS(%r15) # store gprs of prev task
274 lghi %r4,__TASK_stack
275 lghi %r1,__TASK_thread
276 lg %r5,0(%r4,%r3) # start of kernel stack of next
277 stg %r15,__THREAD_ksp(%r1,%r2) # store kernel stack of prev
279 aghi %r15,STACK_INIT # end of kernel stack of next
280 stg %r3,__LC_CURRENT # store task struct of next
281 stg %r15,__LC_KERNEL_STACK # store end of kernel stack
282 lg %r15,__THREAD_ksp(%r1,%r3) # load kernel stack of next
284 mvc __LC_CURRENT_PID(4,%r0),0(%r3) # store pid of next
285 lmg %r6,%r15,__SF_GPRS(%r15) # load gprs of next task
286 ALTERNATIVE "", ".insn s,0xb2800000,_LPP_OFFSET", 40
291 #if IS_ENABLED(CONFIG_KVM)
293 * sie64a calling convention:
294 * %r2 pointer to sie control block
295 * %r3 guest register save area
298 stmg %r6,%r14,__SF_GPRS(%r15) # save kernel registers
300 stg %r2,__SF_SIE_CONTROL(%r15) # save control block pointer
301 stg %r3,__SF_SIE_SAVEAREA(%r15) # save guest register save area
302 xc __SF_SIE_REASON(8,%r15),__SF_SIE_REASON(%r15) # reason code = 0
303 mvc __SF_SIE_FLAGS(8,%r15),__TI_flags(%r12) # copy thread flags
304 TSTMSK __LC_CPU_FLAGS,_CIF_FPU # load guest fp/vx registers ?
305 jno .Lsie_load_guest_gprs
306 brasl %r14,load_fpu_regs # load guest fp/vx regs
307 .Lsie_load_guest_gprs:
308 lmg %r0,%r13,0(%r3) # load guest gprs 0-13
309 lg %r14,__LC_GMAP # get gmap pointer
312 lctlg %c1,%c1,__GMAP_ASCE(%r14) # load primary asce
314 lg %r14,__SF_SIE_CONTROL(%r15) # get control block pointer
315 oi __SIE_PROG0C+3(%r14),1 # we are going into SIE now
316 tm __SIE_PROG20+3(%r14),3 # last exit...
318 TSTMSK __LC_CPU_FLAGS,_CIF_FPU
319 jo .Lsie_skip # exit if fp/vx regs changed
320 BPEXIT __SF_SIE_FLAGS(%r15),(_TIF_ISOLATE_BP|_TIF_ISOLATE_BP_GUEST)
325 BPENTER __SF_SIE_FLAGS(%r15),(_TIF_ISOLATE_BP|_TIF_ISOLATE_BP_GUEST)
327 ni __SIE_PROG0C+3(%r14),0xfe # no longer in SIE
328 lctlg %c1,%c1,__LC_USER_ASCE # load primary asce
330 # some program checks are suppressing. C code (e.g. do_protection_exception)
331 # will rewind the PSW by the ILC, which is often 4 bytes in case of SIE. There
332 # are some corner cases (e.g. runtime instrumentation) where ILC is unpredictable.
333 # Other instructions between sie64a and .Lsie_done should not cause program
334 # interrupts. So lets use 3 nops as a landing pad for all possible rewinds.
335 # See also .Lcleanup_sie
344 lg %r14,__SF_SIE_SAVEAREA(%r15) # load guest register save area
345 stmg %r0,%r13,0(%r14) # save guest gprs 0-13
346 xgr %r0,%r0 # clear guest registers to
347 xgr %r1,%r1 # prevent speculative use
352 lmg %r6,%r14,__SF_GPRS(%r15) # restore kernel registers
353 lg %r2,__SF_SIE_REASON(%r15) # return exit reason code
357 stg %r14,__SF_SIE_REASON(%r15) # set exit reason code
360 EX_TABLE(.Lrewind_pad6,.Lsie_fault)
361 EX_TABLE(.Lrewind_pad4,.Lsie_fault)
362 EX_TABLE(.Lrewind_pad2,.Lsie_fault)
363 EX_TABLE(sie_exit,.Lsie_fault)
364 EXPORT_SYMBOL(sie64a)
365 EXPORT_SYMBOL(sie_exit)
369 * SVC interrupt handler routine. System calls are synchronous events and
370 * are executed with interrupts enabled.
374 stpt __LC_SYNC_ENTER_TIMER
376 stmg %r8,%r15,__LC_SAVE_AREA_SYNC
379 lghi %r13,__TASK_thread
380 lghi %r14,_PIF_SYSCALL
382 lg %r15,__LC_KERNEL_STACK
383 la %r11,STACK_FRAME_OVERHEAD(%r15) # pointer to pt_regs
385 UPDATE_VTIME %r8,%r9,__LC_SYNC_ENTER_TIMER
386 BPENTER __TI_flags(%r12),_TIF_ISOLATE_BP
387 stmg %r0,%r7,__PT_R0(%r11)
388 mvc __PT_R8(64,%r11),__LC_SAVE_AREA_SYNC
389 mvc __PT_PSW(16,%r11),__LC_SVC_OLD_PSW
390 mvc __PT_INT_CODE(4,%r11),__LC_SVC_ILC
391 stg %r14,__PT_FLAGS(%r11)
393 # clear user controlled register to prevent speculative use
395 # load address of system call table
396 lg %r10,__THREAD_sysc_table(%r13,%r12)
397 llgh %r8,__PT_INT_CODE+2(%r11)
398 slag %r8,%r8,2 # shift and test for svc 0
400 # svc 0: system call number in %r1
401 llgfr %r1,%r1 # clear high word in r1
404 sth %r1,__PT_INT_CODE+2(%r11)
407 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
408 stg %r2,__PT_ORIG_GPR2(%r11)
409 stg %r7,STACK_FRAME_OVERHEAD(%r15)
410 lgf %r9,0(%r8,%r10) # get system call add.
411 TSTMSK __TI_flags(%r12),_TIF_TRACE
413 BASR_R14_R9 # call sys_xxxx
414 stg %r2,__PT_R2(%r11) # store return value
419 TSTMSK __PT_FLAGS(%r11),_PIF_WORK
421 TSTMSK __TI_flags(%r12),_TIF_WORK
422 jnz .Lsysc_work # check for work
423 TSTMSK __LC_CPU_FLAGS,_CIF_WORK
425 BPEXIT __TI_flags(%r12),_TIF_ISOLATE_BP
427 lg %r14,__LC_VDSO_PER_CPU
428 lmg %r0,%r10,__PT_R0(%r11)
429 mvc __LC_RETURN_PSW(16),__PT_PSW(%r11)
432 mvc __VDSO_ECTG_BASE(16,%r14),__LC_EXIT_TIMER
433 lmg %r11,%r15,__PT_R11(%r11)
434 lpswe __LC_RETURN_PSW
438 # One of the work bits is on. Find out which one.
441 TSTMSK __LC_CPU_FLAGS,_CIF_MCCK_PENDING
442 jo .Lsysc_mcck_pending
443 TSTMSK __TI_flags(%r12),_TIF_NEED_RESCHED
445 TSTMSK __PT_FLAGS(%r11),_PIF_SYSCALL_RESTART
446 jo .Lsysc_syscall_restart
447 #ifdef CONFIG_UPROBES
448 TSTMSK __TI_flags(%r12),_TIF_UPROBE
449 jo .Lsysc_uprobe_notify
451 TSTMSK __TI_flags(%r12),_TIF_GUARDED_STORAGE
452 jo .Lsysc_guarded_storage
453 TSTMSK __PT_FLAGS(%r11),_PIF_PER_TRAP
455 #ifdef CONFIG_LIVEPATCH
456 TSTMSK __TI_flags(%r12),_TIF_PATCH_PENDING
457 jo .Lsysc_patch_pending # handle live patching just before
458 # signals and possible syscall restart
460 TSTMSK __PT_FLAGS(%r11),_PIF_SYSCALL_RESTART
461 jo .Lsysc_syscall_restart
462 TSTMSK __TI_flags(%r12),_TIF_SIGPENDING
464 TSTMSK __TI_flags(%r12),_TIF_NOTIFY_RESUME
465 jo .Lsysc_notify_resume
466 TSTMSK __LC_CPU_FLAGS,_CIF_FPU
468 TSTMSK __LC_CPU_FLAGS,(_CIF_ASCE_PRIMARY|_CIF_ASCE_SECONDARY)
470 j .Lsysc_return # beware of critical section cleanup
473 # _TIF_NEED_RESCHED is set, call schedule
476 larl %r14,.Lsysc_return
480 # _CIF_MCCK_PENDING is set, call handler
483 larl %r14,.Lsysc_return
484 jg s390_handle_mcck # TIF bit will be cleared by handler
487 # _CIF_ASCE_PRIMARY and/or _CIF_ASCE_SECONDARY set, load user space asce
490 ni __LC_CPU_FLAGS+7,255-_CIF_ASCE_SECONDARY
491 lctlg %c7,%c7,__LC_VDSO_ASCE # load secondary asce
492 TSTMSK __LC_CPU_FLAGS,_CIF_ASCE_PRIMARY
494 #ifndef CONFIG_HAVE_MARCH_Z10_FEATURES
495 tm __LC_STFLE_FAC_LIST+3,0x10 # has MVCOS ?
496 jnz .Lsysc_set_fs_fixup
497 ni __LC_CPU_FLAGS+7,255-_CIF_ASCE_PRIMARY
498 lctlg %c1,%c1,__LC_USER_ASCE # load primary asce
502 larl %r14,.Lsysc_return
506 # CIF_FPU is set, restore floating-point controls and floating-point registers.
509 larl %r14,.Lsysc_return
513 # _TIF_SIGPENDING is set, call do_signal
516 lgr %r2,%r11 # pass pointer to pt_regs
518 TSTMSK __PT_FLAGS(%r11),_PIF_SYSCALL
521 lghi %r13,__TASK_thread
522 lmg %r2,%r7,__PT_R2(%r11) # load svc arguments
523 lghi %r1,0 # svc 0 returns -ENOSYS
527 # _TIF_NOTIFY_RESUME is set, call do_notify_resume
529 .Lsysc_notify_resume:
530 lgr %r2,%r11 # pass pointer to pt_regs
531 larl %r14,.Lsysc_return
535 # _TIF_UPROBE is set, call uprobe_notify_resume
537 #ifdef CONFIG_UPROBES
538 .Lsysc_uprobe_notify:
539 lgr %r2,%r11 # pass pointer to pt_regs
540 larl %r14,.Lsysc_return
541 jg uprobe_notify_resume
545 # _TIF_GUARDED_STORAGE is set, call guarded_storage_load
547 .Lsysc_guarded_storage:
548 lgr %r2,%r11 # pass pointer to pt_regs
549 larl %r14,.Lsysc_return
552 # _TIF_PATCH_PENDING is set, call klp_update_patch_state
554 #ifdef CONFIG_LIVEPATCH
555 .Lsysc_patch_pending:
556 lg %r2,__LC_CURRENT # pass pointer to task struct
557 larl %r14,.Lsysc_return
558 jg klp_update_patch_state
562 # _PIF_PER_TRAP is set, call do_per_trap
565 ni __PT_FLAGS+7(%r11),255-_PIF_PER_TRAP
566 lgr %r2,%r11 # pass pointer to pt_regs
567 larl %r14,.Lsysc_return
571 # _PIF_SYSCALL_RESTART is set, repeat the current system call
573 .Lsysc_syscall_restart:
574 ni __PT_FLAGS+7(%r11),255-_PIF_SYSCALL_RESTART
575 lmg %r1,%r7,__PT_R1(%r11) # load svc arguments
576 lg %r2,__PT_ORIG_GPR2(%r11)
580 # call tracehook_report_syscall_entry/tracehook_report_syscall_exit before
581 # and after the system call
584 lgr %r2,%r11 # pass pointer to pt_regs
586 llgh %r0,__PT_INT_CODE+2(%r11)
587 stg %r0,__PT_R2(%r11)
588 brasl %r14,do_syscall_trace_enter
595 lmg %r3,%r7,__PT_R3(%r11)
596 stg %r7,STACK_FRAME_OVERHEAD(%r15)
597 lg %r2,__PT_ORIG_GPR2(%r11)
598 BASR_R14_R9 # call sys_xxx
599 stg %r2,__PT_R2(%r11) # store return value
601 TSTMSK __TI_flags(%r12),_TIF_TRACE
603 lgr %r2,%r11 # pass pointer to pt_regs
604 larl %r14,.Lsysc_return
605 jg do_syscall_trace_exit
608 # a new process exits the kernel with ret_from_fork
611 la %r11,STACK_FRAME_OVERHEAD(%r15)
613 brasl %r14,schedule_tail
615 ssm __LC_SVC_NEW_PSW # reenable interrupts
616 tm __PT_PSW+1(%r11),0x01 # forking a kernel thread ?
618 # it's a kernel thread
619 lmg %r9,%r10,__PT_R9(%r11) # load gprs
620 ENTRY(kernel_thread_starter)
626 * Program check handler routine
629 ENTRY(pgm_check_handler)
630 stpt __LC_SYNC_ENTER_TIMER
632 stmg %r8,%r15,__LC_SAVE_AREA_SYNC
633 lg %r10,__LC_LAST_BREAK
636 larl %r13,cleanup_critical
637 lmg %r8,%r9,__LC_PGM_OLD_PSW
638 tmhh %r8,0x0001 # test problem state bit
639 jnz 2f # -> fault in user space
640 #if IS_ENABLED(CONFIG_KVM)
641 # cleanup critical section for program checks in sie64a
643 slg %r14,BASED(.Lsie_critical_start)
644 clg %r14,BASED(.Lsie_critical_length)
646 lg %r14,__SF_SIE_CONTROL(%r15) # get control block pointer
647 ni __SIE_PROG0C+3(%r14),0xfe # no longer in SIE
648 lctlg %c1,%c1,__LC_USER_ASCE # load primary asce
649 larl %r9,sie_exit # skip forward to sie_exit
650 lghi %r11,_PIF_GUEST_FAULT
652 0: tmhh %r8,0x4000 # PER bit set in old PSW ?
653 jnz 1f # -> enabled, can't be a double fault
654 tm __LC_PGM_ILC+3,0x80 # check for per exception
655 jnz .Lpgm_svcper # -> single stepped svc
656 1: CHECK_STACK STACK_SIZE,__LC_SAVE_AREA_SYNC
657 aghi %r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
659 2: UPDATE_VTIME %r14,%r15,__LC_SYNC_ENTER_TIMER
660 BPENTER __TI_flags(%r12),_TIF_ISOLATE_BP
661 lg %r15,__LC_KERNEL_STACK
663 aghi %r14,__TASK_thread # pointer to thread_struct
664 lghi %r13,__LC_PGM_TDB
665 tm __LC_PGM_ILC+2,0x02 # check for transaction abort
667 mvc __THREAD_trap_tdb(256,%r14),0(%r13)
668 3: stg %r10,__THREAD_last_break(%r14)
670 la %r11,STACK_FRAME_OVERHEAD(%r15)
671 stmg %r0,%r7,__PT_R0(%r11)
672 # clear user controlled registers to prevent speculative use
681 mvc __PT_R8(64,%r11),__LC_SAVE_AREA_SYNC
682 stmg %r8,%r9,__PT_PSW(%r11)
683 mvc __PT_INT_CODE(4,%r11),__LC_PGM_ILC
684 mvc __PT_INT_PARM_LONG(8,%r11),__LC_TRANS_EXC_CODE
685 stg %r13,__PT_FLAGS(%r11)
686 stg %r10,__PT_ARGS(%r11)
687 tm __LC_PGM_ILC+3,0x80 # check for per exception
689 tmhh %r8,0x0001 # kernel per event ?
691 oi __PT_FLAGS+7(%r11),_PIF_PER_TRAP
692 mvc __THREAD_per_address(8,%r14),__LC_PER_ADDRESS
693 mvc __THREAD_per_cause(2,%r14),__LC_PER_CODE
694 mvc __THREAD_per_paid(1,%r14),__LC_PER_ACCESS_ID
696 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
697 larl %r1,pgm_check_table
698 llgh %r10,__PT_INT_CODE+2(%r11)
702 lgf %r9,0(%r10,%r1) # load address of handler routine
703 lgr %r2,%r11 # pass pointer to pt_regs
704 BASR_R14_R9 # branch to interrupt-handler
707 tm __PT_PSW+1(%r11),0x01 # returning to user ?
709 TSTMSK __PT_FLAGS(%r11),_PIF_SYSCALL
714 # PER event in supervisor state, must be kprobes
718 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
719 lgr %r2,%r11 # pass pointer to pt_regs
720 brasl %r14,do_per_trap
724 # single stepped system call
727 mvc __LC_RETURN_PSW(8),__LC_SVC_NEW_PSW
728 lghi %r13,__TASK_thread
730 stg %r14,__LC_RETURN_PSW+8
731 lghi %r14,_PIF_SYSCALL | _PIF_PER_TRAP
732 lpswe __LC_RETURN_PSW # branch to .Lsysc_per and enable irqs
735 * IO interrupt handler routine
737 ENTRY(io_int_handler)
739 stpt __LC_ASYNC_ENTER_TIMER
741 stmg %r8,%r15,__LC_SAVE_AREA_ASYNC
743 larl %r13,cleanup_critical
744 lmg %r8,%r9,__LC_IO_OLD_PSW
745 SWITCH_ASYNC __LC_SAVE_AREA_ASYNC,__LC_ASYNC_ENTER_TIMER
746 stmg %r0,%r7,__PT_R0(%r11)
747 # clear user controlled registers to prevent speculative use
757 mvc __PT_R8(64,%r11),__LC_SAVE_AREA_ASYNC
758 stmg %r8,%r9,__PT_PSW(%r11)
759 mvc __PT_INT_CODE(12,%r11),__LC_SUBCHANNEL_ID
760 xc __PT_FLAGS(8,%r11),__PT_FLAGS(%r11)
761 TSTMSK __LC_CPU_FLAGS,_CIF_IGNORE_IRQ
764 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
766 lgr %r2,%r11 # pass pointer to pt_regs
767 lghi %r3,IO_INTERRUPT
768 tm __PT_INT_CODE+8(%r11),0x80 # adapter interrupt ?
770 lghi %r3,THIN_INTERRUPT
773 TSTMSK __LC_MACHINE_FLAGS,MACHINE_FLAG_LPAR
777 mvc __PT_INT_CODE(12,%r11),__LC_SUBCHANNEL_ID
783 TSTMSK __TI_flags(%r12),_TIF_WORK
784 jnz .Lio_work # there is work to do (signals etc.)
785 TSTMSK __LC_CPU_FLAGS,_CIF_WORK
788 lg %r14,__LC_VDSO_PER_CPU
789 lmg %r0,%r10,__PT_R0(%r11)
790 mvc __LC_RETURN_PSW(16),__PT_PSW(%r11)
791 tm __PT_PSW+1(%r11),0x01 # returning to user ?
793 BPEXIT __TI_flags(%r12),_TIF_ISOLATE_BP
796 mvc __VDSO_ECTG_BASE(16,%r14),__LC_EXIT_TIMER
798 lmg %r11,%r15,__PT_R11(%r11)
799 lpswe __LC_RETURN_PSW
803 # There is work todo, find out in which context we have been interrupted:
804 # 1) if we return to user space we can do all _TIF_WORK work
805 # 2) if we return to kernel code and kvm is enabled check if we need to
806 # modify the psw to leave SIE
807 # 3) if we return to kernel code and preemptive scheduling is enabled check
808 # the preemption counter and if it is zero call preempt_schedule_irq
809 # Before any work can be done, a switch to the kernel stack is required.
812 tm __PT_PSW+1(%r11),0x01 # returning to user ?
813 jo .Lio_work_user # yes -> do resched & signal
814 #ifdef CONFIG_PREEMPT
815 # check for preemptive scheduling
816 icm %r0,15,__LC_PREEMPT_COUNT
817 jnz .Lio_restore # preemption is disabled
818 TSTMSK __TI_flags(%r12),_TIF_NEED_RESCHED
820 # switch to kernel stack
821 lg %r1,__PT_R15(%r11)
822 aghi %r1,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
823 mvc STACK_FRAME_OVERHEAD(__PT_SIZE,%r1),0(%r11)
824 xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1)
825 la %r11,STACK_FRAME_OVERHEAD(%r1)
827 # TRACE_IRQS_ON already done at .Lio_return, call
828 # TRACE_IRQS_OFF to keep things symmetrical
830 brasl %r14,preempt_schedule_irq
837 # Need to do work before returning to userspace, switch to kernel stack
840 lg %r1,__LC_KERNEL_STACK
841 mvc STACK_FRAME_OVERHEAD(__PT_SIZE,%r1),0(%r11)
842 xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1)
843 la %r11,STACK_FRAME_OVERHEAD(%r1)
847 # One of the work bits is on. Find out which one.
850 TSTMSK __LC_CPU_FLAGS,_CIF_MCCK_PENDING
852 TSTMSK __TI_flags(%r12),_TIF_NEED_RESCHED
854 #ifdef CONFIG_LIVEPATCH
855 TSTMSK __TI_flags(%r12),_TIF_PATCH_PENDING
856 jo .Lio_patch_pending
858 TSTMSK __TI_flags(%r12),_TIF_SIGPENDING
860 TSTMSK __TI_flags(%r12),_TIF_NOTIFY_RESUME
861 jo .Lio_notify_resume
862 TSTMSK __TI_flags(%r12),_TIF_GUARDED_STORAGE
863 jo .Lio_guarded_storage
864 TSTMSK __LC_CPU_FLAGS,_CIF_FPU
866 TSTMSK __LC_CPU_FLAGS,(_CIF_ASCE_PRIMARY|_CIF_ASCE_SECONDARY)
868 j .Lio_return # beware of critical section cleanup
871 # _CIF_MCCK_PENDING is set, call handler
874 # TRACE_IRQS_ON already done at .Lio_return
875 brasl %r14,s390_handle_mcck # TIF bit will be cleared by handler
880 # _CIF_ASCE_PRIMARY and/or CIF_ASCE_SECONDARY set, load user space asce
883 ni __LC_CPU_FLAGS+7,255-_CIF_ASCE_SECONDARY
884 lctlg %c7,%c7,__LC_VDSO_ASCE # load secondary asce
885 TSTMSK __LC_CPU_FLAGS,_CIF_ASCE_PRIMARY
887 #ifndef CONFIG_HAVE_MARCH_Z10_FEATURES
888 tm __LC_STFLE_FAC_LIST+3,0x10 # has MVCOS ?
889 jnz .Lio_set_fs_fixup
890 ni __LC_CPU_FLAGS+7,255-_CIF_ASCE_PRIMARY
891 lctlg %c1,%c1,__LC_USER_ASCE # load primary asce
895 larl %r14,.Lio_return
899 # CIF_FPU is set, restore floating-point controls and floating-point registers.
902 larl %r14,.Lio_return
906 # _TIF_GUARDED_STORAGE is set, call guarded_storage_load
908 .Lio_guarded_storage:
909 # TRACE_IRQS_ON already done at .Lio_return
910 ssm __LC_SVC_NEW_PSW # reenable interrupts
911 lgr %r2,%r11 # pass pointer to pt_regs
912 brasl %r14,gs_load_bc_cb
913 ssm __LC_PGM_NEW_PSW # disable I/O and ext. interrupts
918 # _TIF_NEED_RESCHED is set, call schedule
921 # TRACE_IRQS_ON already done at .Lio_return
922 ssm __LC_SVC_NEW_PSW # reenable interrupts
923 brasl %r14,schedule # call scheduler
924 ssm __LC_PGM_NEW_PSW # disable I/O and ext. interrupts
929 # _TIF_PATCH_PENDING is set, call klp_update_patch_state
931 #ifdef CONFIG_LIVEPATCH
933 lg %r2,__LC_CURRENT # pass pointer to task struct
934 larl %r14,.Lio_return
935 jg klp_update_patch_state
939 # _TIF_SIGPENDING or is set, call do_signal
942 # TRACE_IRQS_ON already done at .Lio_return
943 ssm __LC_SVC_NEW_PSW # reenable interrupts
944 lgr %r2,%r11 # pass pointer to pt_regs
946 ssm __LC_PGM_NEW_PSW # disable I/O and ext. interrupts
951 # _TIF_NOTIFY_RESUME or is set, call do_notify_resume
954 # TRACE_IRQS_ON already done at .Lio_return
955 ssm __LC_SVC_NEW_PSW # reenable interrupts
956 lgr %r2,%r11 # pass pointer to pt_regs
957 brasl %r14,do_notify_resume
958 ssm __LC_PGM_NEW_PSW # disable I/O and ext. interrupts
963 * External interrupt handler routine
965 ENTRY(ext_int_handler)
967 stpt __LC_ASYNC_ENTER_TIMER
969 stmg %r8,%r15,__LC_SAVE_AREA_ASYNC
971 larl %r13,cleanup_critical
972 lmg %r8,%r9,__LC_EXT_OLD_PSW
973 SWITCH_ASYNC __LC_SAVE_AREA_ASYNC,__LC_ASYNC_ENTER_TIMER
974 stmg %r0,%r7,__PT_R0(%r11)
975 # clear user controlled registers to prevent speculative use
985 mvc __PT_R8(64,%r11),__LC_SAVE_AREA_ASYNC
986 stmg %r8,%r9,__PT_PSW(%r11)
987 lghi %r1,__LC_EXT_PARAMS2
988 mvc __PT_INT_CODE(4,%r11),__LC_EXT_CPU_ADDR
989 mvc __PT_INT_PARM(4,%r11),__LC_EXT_PARAMS
990 mvc __PT_INT_PARM_LONG(8,%r11),0(%r1)
991 xc __PT_FLAGS(8,%r11),__PT_FLAGS(%r11)
992 TSTMSK __LC_CPU_FLAGS,_CIF_IGNORE_IRQ
995 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
996 lgr %r2,%r11 # pass pointer to pt_regs
997 lghi %r3,EXT_INTERRUPT
1002 * Load idle PSW. The second "half" of this function is in .Lcleanup_idle.
1005 stg %r3,__SF_EMPTY(%r15)
1006 larl %r1,.Lpsw_idle_lpsw+4
1007 stg %r1,__SF_EMPTY+8(%r15)
1009 larl %r1,smp_cpu_mtid
1012 jz .Lpsw_idle_stcctm
1013 .insn rsy,0xeb0000000017,%r1,5,__SF_EMPTY+16(%r15)
1016 oi __LC_CPU_FLAGS+7,_CIF_ENABLED_WAIT
1018 STCK __CLOCK_IDLE_ENTER(%r2)
1019 stpt __TIMER_IDLE_ENTER(%r2)
1021 lpswe __SF_EMPTY(%r15)
1026 * Store floating-point controls and floating-point or vector register
1027 * depending whether the vector facility is available. A critical section
1028 * cleanup assures that the registers are stored even if interrupted for
1029 * some other work. The CIF_FPU flag is set to trigger a lazy restore
1030 * of the register contents at return from io or a system call.
1032 ENTRY(save_fpu_regs)
1034 aghi %r2,__TASK_thread
1035 TSTMSK __LC_CPU_FLAGS,_CIF_FPU
1036 jo .Lsave_fpu_regs_exit
1037 stfpc __THREAD_FPU_fpc(%r2)
1038 lg %r3,__THREAD_FPU_regs(%r2)
1039 TSTMSK __LC_MACHINE_FLAGS,MACHINE_FLAG_VX
1040 jz .Lsave_fpu_regs_fp # no -> store FP regs
1041 VSTM %v0,%v15,0,%r3 # vstm 0,15,0(3)
1042 VSTM %v16,%v31,256,%r3 # vstm 16,31,256(3)
1043 j .Lsave_fpu_regs_done # -> set CIF_FPU flag
1061 .Lsave_fpu_regs_done:
1062 oi __LC_CPU_FLAGS+7,_CIF_FPU
1063 .Lsave_fpu_regs_exit:
1065 .Lsave_fpu_regs_end:
1066 EXPORT_SYMBOL(save_fpu_regs)
1069 * Load floating-point controls and floating-point or vector registers.
1070 * A critical section cleanup assures that the register contents are
1071 * loaded even if interrupted for some other work.
1073 * There are special calling conventions to fit into sysc and io return work:
1074 * %r15: <kernel stack>
1075 * The function requires:
1080 aghi %r4,__TASK_thread
1081 TSTMSK __LC_CPU_FLAGS,_CIF_FPU
1082 jno .Lload_fpu_regs_exit
1083 lfpc __THREAD_FPU_fpc(%r4)
1084 TSTMSK __LC_MACHINE_FLAGS,MACHINE_FLAG_VX
1085 lg %r4,__THREAD_FPU_regs(%r4) # %r4 <- reg save area
1086 jz .Lload_fpu_regs_fp # -> no VX, load FP regs
1088 VLM %v16,%v31,256,%r4
1089 j .Lload_fpu_regs_done
1107 .Lload_fpu_regs_done:
1108 ni __LC_CPU_FLAGS+7,255-_CIF_FPU
1109 .Lload_fpu_regs_exit:
1111 .Lload_fpu_regs_end:
1116 * Machine check handler routines
1118 ENTRY(mcck_int_handler)
1119 STCK __LC_MCCK_CLOCK
1121 la %r1,4095 # validate r1
1122 spt __LC_CPU_TIMER_SAVE_AREA-4095(%r1) # validate cpu timer
1123 sckc __LC_CLOCK_COMPARATOR # validate comparator
1124 lam %a0,%a15,__LC_AREGS_SAVE_AREA-4095(%r1) # validate acrs
1125 lmg %r0,%r15,__LC_GPREGS_SAVE_AREA-4095(%r1)# validate gprs
1126 lg %r12,__LC_CURRENT
1127 larl %r13,cleanup_critical
1128 lmg %r8,%r9,__LC_MCK_OLD_PSW
1129 TSTMSK __LC_MCCK_CODE,MCCK_CODE_SYSTEM_DAMAGE
1130 jo .Lmcck_panic # yes -> rest of mcck code invalid
1131 TSTMSK __LC_MCCK_CODE,MCCK_CODE_CR_VALID
1132 jno .Lmcck_panic # control registers invalid -> panic
1134 lctlg %c0,%c15,__LC_CREGS_SAVE_AREA-4095(%r14) # validate ctl regs
1136 lg %r11,__LC_MCESAD-4095(%r14) # extended machine check save area
1137 nill %r11,0xfc00 # MCESA_ORIGIN_MASK
1138 TSTMSK __LC_CREGS_SAVE_AREA+16-4095(%r14),CR2_GUARDED_STORAGE
1140 TSTMSK __LC_MCCK_CODE,MCCK_CODE_GS_VALID
1142 .insn rxy,0xe3000000004d,0,__MCESA_GS_SAVE_AREA(%r11) # LGSC
1143 0: l %r14,__LC_FP_CREG_SAVE_AREA-4095(%r14)
1144 TSTMSK __LC_MCCK_CODE,MCCK_CODE_FC_VALID
1148 TSTMSK __LC_MACHINE_FLAGS,MACHINE_FLAG_VX
1150 lghi %r14,__LC_FPREGS_SAVE_AREA
1168 0: VLM %v0,%v15,0,%r11
1169 VLM %v16,%v31,256,%r11
1170 1: lghi %r14,__LC_CPU_TIMER_SAVE_AREA
1171 mvc __LC_MCCK_ENTER_TIMER(8),0(%r14)
1172 TSTMSK __LC_MCCK_CODE,MCCK_CODE_CPU_TIMER_VALID
1174 la %r14,__LC_SYNC_ENTER_TIMER
1175 clc 0(8,%r14),__LC_ASYNC_ENTER_TIMER
1177 la %r14,__LC_ASYNC_ENTER_TIMER
1178 0: clc 0(8,%r14),__LC_EXIT_TIMER
1180 la %r14,__LC_EXIT_TIMER
1181 1: clc 0(8,%r14),__LC_LAST_UPDATE_TIMER
1183 la %r14,__LC_LAST_UPDATE_TIMER
1185 mvc __LC_MCCK_ENTER_TIMER(8),0(%r14)
1186 3: TSTMSK __LC_MCCK_CODE,MCCK_CODE_PSW_MWP_VALID
1188 tmhh %r8,0x0001 # interrupting from user ?
1190 TSTMSK __LC_MCCK_CODE,MCCK_CODE_PSW_IA_VALID
1192 4: SWITCH_ASYNC __LC_GPREGS_SAVE_AREA+64,__LC_MCCK_ENTER_TIMER
1194 lghi %r14,__LC_GPREGS_SAVE_AREA+64
1195 stmg %r0,%r7,__PT_R0(%r11)
1196 # clear user controlled registers to prevent speculative use
1206 mvc __PT_R8(64,%r11),0(%r14)
1207 stmg %r8,%r9,__PT_PSW(%r11)
1208 xc __PT_FLAGS(8,%r11),__PT_FLAGS(%r11)
1209 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
1210 lgr %r2,%r11 # pass pointer to pt_regs
1211 brasl %r14,s390_do_machine_check
1212 tm __PT_PSW+1(%r11),0x01 # returning to user ?
1214 lg %r1,__LC_KERNEL_STACK # switch to kernel stack
1215 mvc STACK_FRAME_OVERHEAD(__PT_SIZE,%r1),0(%r11)
1216 xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1)
1217 la %r11,STACK_FRAME_OVERHEAD(%r1)
1219 ssm __LC_PGM_NEW_PSW # turn dat on, keep irqs off
1220 TSTMSK __LC_CPU_FLAGS,_CIF_MCCK_PENDING
1223 brasl %r14,s390_handle_mcck
1226 lg %r14,__LC_VDSO_PER_CPU
1227 lmg %r0,%r10,__PT_R0(%r11)
1228 mvc __LC_RETURN_MCCK_PSW(16),__PT_PSW(%r11) # move return PSW
1229 tm __LC_RETURN_MCCK_PSW+1,0x01 # returning to user ?
1231 BPEXIT __TI_flags(%r12),_TIF_ISOLATE_BP
1232 stpt __LC_EXIT_TIMER
1233 mvc __VDSO_ECTG_BASE(16,%r14),__LC_EXIT_TIMER
1234 0: lmg %r11,%r15,__PT_R11(%r11)
1235 lpswe __LC_RETURN_MCCK_PSW
1238 lg %r15,__LC_PANIC_STACK
1239 la %r11,STACK_FRAME_OVERHEAD(%r15)
1243 # PSW restart interrupt handler
1245 ENTRY(restart_int_handler)
1246 ALTERNATIVE "", ".insn s,0xb2800000,_LPP_OFFSET", 40
1247 stg %r15,__LC_SAVE_AREA_RESTART
1248 lg %r15,__LC_RESTART_STACK
1249 aghi %r15,-__PT_SIZE # create pt_regs on stack
1250 xc 0(__PT_SIZE,%r15),0(%r15)
1251 stmg %r0,%r14,__PT_R0(%r15)
1252 mvc __PT_R15(8,%r15),__LC_SAVE_AREA_RESTART
1253 mvc __PT_PSW(16,%r15),__LC_RST_OLD_PSW # store restart old psw
1254 aghi %r15,-STACK_FRAME_OVERHEAD # create stack frame on stack
1255 xc 0(STACK_FRAME_OVERHEAD,%r15),0(%r15)
1256 lg %r1,__LC_RESTART_FN # load fn, parm & source cpu
1257 lg %r2,__LC_RESTART_DATA
1258 lg %r3,__LC_RESTART_SOURCE
1259 ltgr %r3,%r3 # test source cpu address
1260 jm 1f # negative -> skip source stop
1261 0: sigp %r4,%r3,SIGP_SENSE # sigp sense to source cpu
1262 brc 10,0b # wait for status stored
1263 1: basr %r14,%r1 # call function
1264 stap __SF_EMPTY(%r15) # store cpu address
1265 llgh %r3,__SF_EMPTY(%r15)
1266 2: sigp %r4,%r3,SIGP_STOP # sigp stop to current cpu
1270 .section .kprobes.text, "ax"
1272 #ifdef CONFIG_CHECK_STACK
1274 * The synchronous or the asynchronous stack overflowed. We are dead.
1275 * No need to properly save the registers, we are going to panic anyway.
1276 * Setup a pt_regs so that show_trace can provide a good call trace.
1279 lg %r15,__LC_PANIC_STACK # change to panic stack
1280 la %r11,STACK_FRAME_OVERHEAD(%r15)
1281 stmg %r0,%r7,__PT_R0(%r11)
1282 stmg %r8,%r9,__PT_PSW(%r11)
1283 mvc __PT_R8(64,%r11),0(%r14)
1284 stg %r10,__PT_ORIG_GPR2(%r11) # store last break to orig_gpr2
1285 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
1286 lgr %r2,%r11 # pass pointer to pt_regs
1287 jg kernel_stack_overflow
1291 #if IS_ENABLED(CONFIG_KVM)
1292 clg %r9,BASED(.Lcleanup_table_sie) # .Lsie_gmap
1294 clg %r9,BASED(.Lcleanup_table_sie+8)# .Lsie_done
1297 clg %r9,BASED(.Lcleanup_table) # system_call
1299 clg %r9,BASED(.Lcleanup_table+8) # .Lsysc_do_svc
1300 jl .Lcleanup_system_call
1301 clg %r9,BASED(.Lcleanup_table+16) # .Lsysc_tif
1303 clg %r9,BASED(.Lcleanup_table+24) # .Lsysc_restore
1304 jl .Lcleanup_sysc_tif
1305 clg %r9,BASED(.Lcleanup_table+32) # .Lsysc_done
1306 jl .Lcleanup_sysc_restore
1307 clg %r9,BASED(.Lcleanup_table+40) # .Lio_tif
1309 clg %r9,BASED(.Lcleanup_table+48) # .Lio_restore
1311 clg %r9,BASED(.Lcleanup_table+56) # .Lio_done
1312 jl .Lcleanup_io_restore
1313 clg %r9,BASED(.Lcleanup_table+64) # psw_idle
1315 clg %r9,BASED(.Lcleanup_table+72) # .Lpsw_idle_end
1317 clg %r9,BASED(.Lcleanup_table+80) # save_fpu_regs
1319 clg %r9,BASED(.Lcleanup_table+88) # .Lsave_fpu_regs_end
1320 jl .Lcleanup_save_fpu_regs
1321 clg %r9,BASED(.Lcleanup_table+96) # load_fpu_regs
1323 clg %r9,BASED(.Lcleanup_table+104) # .Lload_fpu_regs_end
1324 jl .Lcleanup_load_fpu_regs
1332 .quad .Lsysc_restore
1338 .quad .Lpsw_idle_end
1340 .quad .Lsave_fpu_regs_end
1342 .quad .Lload_fpu_regs_end
1344 #if IS_ENABLED(CONFIG_KVM)
1345 .Lcleanup_table_sie:
1350 cghi %r11,__LC_SAVE_AREA_ASYNC #Is this in normal interrupt?
1352 slg %r9,BASED(.Lsie_crit_mcck_start)
1353 clg %r9,BASED(.Lsie_crit_mcck_length)
1355 oi __LC_CPU_FLAGS+7, _CIF_MCCK_GUEST
1356 1: BPENTER __SF_SIE_FLAGS(%r15),(_TIF_ISOLATE_BP|_TIF_ISOLATE_BP_GUEST)
1357 lg %r9,__SF_SIE_CONTROL(%r15) # get control block pointer
1358 ni __SIE_PROG0C+3(%r9),0xfe # no longer in SIE
1359 lctlg %c1,%c1,__LC_USER_ASCE # load primary asce
1360 larl %r9,sie_exit # skip forward to sie_exit
1364 .Lcleanup_system_call:
1365 # check if stpt has been executed
1366 clg %r9,BASED(.Lcleanup_system_call_insn)
1368 mvc __LC_SYNC_ENTER_TIMER(8),__LC_ASYNC_ENTER_TIMER
1369 cghi %r11,__LC_SAVE_AREA_ASYNC
1371 mvc __LC_SYNC_ENTER_TIMER(8),__LC_MCCK_ENTER_TIMER
1372 0: # check if stmg has been executed
1373 clg %r9,BASED(.Lcleanup_system_call_insn+8)
1375 mvc __LC_SAVE_AREA_SYNC(64),0(%r11)
1376 0: # check if base register setup + TIF bit load has been done
1377 clg %r9,BASED(.Lcleanup_system_call_insn+16)
1379 # set up saved register r12 task struct pointer
1381 # set up saved register r13 __TASK_thread offset
1382 mvc 40(8,%r11),BASED(.Lcleanup_system_call_const)
1383 0: # check if the user time update has been done
1384 clg %r9,BASED(.Lcleanup_system_call_insn+24)
1386 lg %r15,__LC_EXIT_TIMER
1387 slg %r15,__LC_SYNC_ENTER_TIMER
1388 alg %r15,__LC_USER_TIMER
1389 stg %r15,__LC_USER_TIMER
1390 0: # check if the system time update has been done
1391 clg %r9,BASED(.Lcleanup_system_call_insn+32)
1393 lg %r15,__LC_LAST_UPDATE_TIMER
1394 slg %r15,__LC_EXIT_TIMER
1395 alg %r15,__LC_SYSTEM_TIMER
1396 stg %r15,__LC_SYSTEM_TIMER
1397 0: # update accounting time stamp
1398 mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
1399 BPENTER __TI_flags(%r12),_TIF_ISOLATE_BP
1400 # set up saved register r11
1401 lg %r15,__LC_KERNEL_STACK
1402 la %r9,STACK_FRAME_OVERHEAD(%r15)
1403 stg %r9,24(%r11) # r11 pt_regs pointer
1405 mvc __PT_R8(64,%r9),__LC_SAVE_AREA_SYNC
1406 stmg %r0,%r7,__PT_R0(%r9)
1407 mvc __PT_PSW(16,%r9),__LC_SVC_OLD_PSW
1408 mvc __PT_INT_CODE(4,%r9),__LC_SVC_ILC
1409 xc __PT_FLAGS(8,%r9),__PT_FLAGS(%r9)
1410 mvi __PT_FLAGS+7(%r9),_PIF_SYSCALL
1411 # setup saved register r15
1412 stg %r15,56(%r11) # r15 stack pointer
1413 # set new psw address and exit
1414 larl %r9,.Lsysc_do_svc
1416 .Lcleanup_system_call_insn:
1420 .quad .Lsysc_vtime+36
1421 .quad .Lsysc_vtime+42
1422 .Lcleanup_system_call_const:
1429 .Lcleanup_sysc_restore:
1430 # check if stpt has been executed
1431 clg %r9,BASED(.Lcleanup_sysc_restore_insn)
1433 mvc __LC_EXIT_TIMER(8),__LC_ASYNC_ENTER_TIMER
1434 cghi %r11,__LC_SAVE_AREA_ASYNC
1436 mvc __LC_EXIT_TIMER(8),__LC_MCCK_ENTER_TIMER
1437 0: clg %r9,BASED(.Lcleanup_sysc_restore_insn+8)
1439 lg %r9,24(%r11) # get saved pointer to pt_regs
1440 mvc __LC_RETURN_PSW(16),__PT_PSW(%r9)
1441 mvc 0(64,%r11),__PT_R8(%r9)
1442 lmg %r0,%r7,__PT_R0(%r9)
1443 1: lmg %r8,%r9,__LC_RETURN_PSW
1445 .Lcleanup_sysc_restore_insn:
1446 .quad .Lsysc_exit_timer
1447 .quad .Lsysc_done - 4
1453 .Lcleanup_io_restore:
1454 # check if stpt has been executed
1455 clg %r9,BASED(.Lcleanup_io_restore_insn)
1457 mvc __LC_EXIT_TIMER(8),__LC_MCCK_ENTER_TIMER
1458 0: clg %r9,BASED(.Lcleanup_io_restore_insn+8)
1460 lg %r9,24(%r11) # get saved r11 pointer to pt_regs
1461 mvc __LC_RETURN_PSW(16),__PT_PSW(%r9)
1462 mvc 0(64,%r11),__PT_R8(%r9)
1463 lmg %r0,%r7,__PT_R0(%r9)
1464 1: lmg %r8,%r9,__LC_RETURN_PSW
1466 .Lcleanup_io_restore_insn:
1467 .quad .Lio_exit_timer
1471 ni __LC_CPU_FLAGS+7,255-_CIF_ENABLED_WAIT
1472 # copy interrupt clock & cpu timer
1473 mvc __CLOCK_IDLE_EXIT(8,%r2),__LC_INT_CLOCK
1474 mvc __TIMER_IDLE_EXIT(8,%r2),__LC_ASYNC_ENTER_TIMER
1475 cghi %r11,__LC_SAVE_AREA_ASYNC
1477 mvc __CLOCK_IDLE_EXIT(8,%r2),__LC_MCCK_CLOCK
1478 mvc __TIMER_IDLE_EXIT(8,%r2),__LC_MCCK_ENTER_TIMER
1479 0: # check if stck & stpt have been executed
1480 clg %r9,BASED(.Lcleanup_idle_insn)
1482 mvc __CLOCK_IDLE_ENTER(8,%r2),__CLOCK_IDLE_EXIT(%r2)
1483 mvc __TIMER_IDLE_ENTER(8,%r2),__TIMER_IDLE_EXIT(%r2)
1484 1: # calculate idle cycles
1486 clg %r9,BASED(.Lcleanup_idle_insn)
1488 larl %r1,smp_cpu_mtid
1492 .insn rsy,0xeb0000000017,%r1,5,__SF_EMPTY+80(%r15)
1494 ag %r3,__LC_PERCPU_OFFSET
1495 la %r4,__SF_EMPTY+16(%r15)
1504 3: # account system time going idle
1505 lg %r9,__LC_STEAL_TIMER
1506 alg %r9,__CLOCK_IDLE_ENTER(%r2)
1507 slg %r9,__LC_LAST_UPDATE_CLOCK
1508 stg %r9,__LC_STEAL_TIMER
1509 mvc __LC_LAST_UPDATE_CLOCK(8),__CLOCK_IDLE_EXIT(%r2)
1510 lg %r9,__LC_SYSTEM_TIMER
1511 alg %r9,__LC_LAST_UPDATE_TIMER
1512 slg %r9,__TIMER_IDLE_ENTER(%r2)
1513 stg %r9,__LC_SYSTEM_TIMER
1514 mvc __LC_LAST_UPDATE_TIMER(8),__TIMER_IDLE_EXIT(%r2)
1515 # prepare return psw
1516 nihh %r8,0xfcfd # clear irq & wait state bits
1517 lg %r9,48(%r11) # return from psw_idle
1519 .Lcleanup_idle_insn:
1520 .quad .Lpsw_idle_lpsw
1522 .Lcleanup_save_fpu_regs:
1523 larl %r9,save_fpu_regs
1526 .Lcleanup_load_fpu_regs:
1527 larl %r9,load_fpu_regs
1535 .quad .L__critical_start
1537 .quad .L__critical_end - .L__critical_start
1538 #if IS_ENABLED(CONFIG_KVM)
1539 .Lsie_critical_start:
1541 .Lsie_critical_length:
1542 .quad .Lsie_done - .Lsie_gmap
1543 .Lsie_crit_mcck_start:
1545 .Lsie_crit_mcck_length:
1546 .quad .Lsie_skip - .Lsie_entry
1548 .section .rodata, "a"
1549 #define SYSCALL(esame,emu) .long esame
1550 .globl sys_call_table
1552 #include "asm/syscall_table.h"
1555 #ifdef CONFIG_COMPAT
1557 #define SYSCALL(esame,emu) .long emu
1558 .globl sys_call_table_emu
1560 #include "asm/syscall_table.h"