arch/riscv/kernel/cpufeature.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copied from arch/arm64/kernel/cpufeature.c
   4  *
   5  * Copyright (C) 2015 ARM Ltd.
   6  * Copyright (C) 2017 SiFive
   7  */
   8
   9 #include <linux/acpi.h>
  10 #include <linux/bitmap.h>
  11 #include <linux/ctype.h>
  12 #include <linux/log2.h>
  13 #include <linux/memory.h>
  14 #include <linux/module.h>
  15 #include <linux/of.h>
  16 #include <linux/of_device.h>
  17 #include <asm/acpi.h>
  18 #include <asm/alternative.h>
  19 #include <asm/cacheflush.h>
  20 #include <asm/cpufeature.h>
  21 #include <asm/hwcap.h>
  22 #include <asm/patch.h>
  23 #include <asm/processor.h>
  24 #include <asm/vector.h>
  25
  26 #define NUM_ALPHA_EXTS ('z' - 'a' + 1)
  27
  28 unsigned long elf_hwcap __read_mostly;
  29
  30 /* Host ISA bitmap */
  31 static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly;
  32
  33 /* Per-cpu ISA extensions. */
  34 struct riscv_isainfo hart_isa[NR_CPUS];
  35
  36 /* Performance information */
  37 DEFINE_PER_CPU(long, misaligned_access_speed);
  38
  39 /**
  40  * riscv_isa_extension_base() - Get base extension word
  41  *
  42  * @isa_bitmap: ISA bitmap to use
  43  * Return: base extension word as unsigned long value
  44  *
  45  * NOTE: If isa_bitmap is NULL then Host ISA bitmap will be used.
  46  */
  47 unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap)
  48 {
  49         if (!isa_bitmap)
  50                 return riscv_isa[0];
  51         return isa_bitmap[0];
  52 }
  53 EXPORT_SYMBOL_GPL(riscv_isa_extension_base);
  54
  55 /**
  56  * __riscv_isa_extension_available() - Check whether given extension
  57  * is available or not
  58  *
  59  * @isa_bitmap: ISA bitmap to use
  60  * @bit: bit position of the desired extension
  61  * Return: true or false
  62  *
  63  * NOTE: If isa_bitmap is NULL then Host ISA bitmap will be used.
  64  */
  65 bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int bit)
  66 {
  67         const unsigned long *bmap = (isa_bitmap) ? isa_bitmap : riscv_isa;
  68
  69         if (bit >= RISCV_ISA_EXT_MAX)
  70                 return false;
  71
  72         return test_bit(bit, bmap) ? true : false;
  73 }
  74 EXPORT_SYMBOL_GPL(__riscv_isa_extension_available);
  75
  76 static bool riscv_isa_extension_check(int id)
  77 {
  78         switch (id) {
  79         case RISCV_ISA_EXT_ZICBOM:
  80                 if (!riscv_cbom_block_size) {
  81                         pr_err("Zicbom detected in ISA string, disabling as no cbom-block-size found\n");
  82                         return false;
  83                 } else if (!is_power_of_2(riscv_cbom_block_size)) {
  84                         pr_err("Zicbom disabled as cbom-block-size present, but is not a power-of-2\n");
  85                         return false;
  86                 }
  87                 return true;
  88         case RISCV_ISA_EXT_ZICBOZ:
  89                 if (!riscv_cboz_block_size) {
  90                         pr_err("Zicboz detected in ISA string, but no cboz-block-size found\n");
  91                         return false;
  92                 } else if (!is_power_of_2(riscv_cboz_block_size)) {
  93                         pr_err("cboz-block-size present, but is not a power-of-2\n");
  94                         return false;
  95                 }
  96                 return true;
  97         }
  98
  99         return true;
 100 }
 101
 102 void __init riscv_fill_hwcap(void)
 103 {
 104         struct device_node *node;
 105         const char *isa;
 106         char print_str[NUM_ALPHA_EXTS + 1];
 107         int i, j, rc;
 108         unsigned long isa2hwcap[26] = {0};
 109         struct acpi_table_header *rhct;
 110         acpi_status status;
 111         unsigned int cpu;
 112
 113         isa2hwcap['i' - 'a'] = COMPAT_HWCAP_ISA_I;
 114         isa2hwcap['m' - 'a'] = COMPAT_HWCAP_ISA_M;
 115         isa2hwcap['a' - 'a'] = COMPAT_HWCAP_ISA_A;
 116         isa2hwcap['f' - 'a'] = COMPAT_HWCAP_ISA_F;
 117         isa2hwcap['d' - 'a'] = COMPAT_HWCAP_ISA_D;
 118         isa2hwcap['c' - 'a'] = COMPAT_HWCAP_ISA_C;
 119         isa2hwcap['v' - 'a'] = COMPAT_HWCAP_ISA_V;
 120
 121         elf_hwcap = 0;
 122
 123         bitmap_zero(riscv_isa, RISCV_ISA_EXT_MAX);
 124
 125         if (!acpi_disabled) {
 126                 status = acpi_get_table(ACPI_SIG_RHCT, 0, &rhct);
 127                 if (ACPI_FAILURE(status))
 128                         return;
 129         }
 130
 131         for_each_possible_cpu(cpu) {
 132                 struct riscv_isainfo *isainfo = &hart_isa[cpu];
 133                 unsigned long this_hwcap = 0;
 134
 135                 if (acpi_disabled) {
 136                         node = of_cpu_device_node_get(cpu);
 137                         if (!node) {
 138                                 pr_warn("Unable to find cpu node\n");
 139                                 continue;
 140                         }
 141
 142                         rc = of_property_read_string(node, "riscv,isa", &isa);
 143                         of_node_put(node);
 144                         if (rc) {
 145                                 pr_warn("Unable to find \"riscv,isa\" devicetree entry\n");
 146                                 continue;
 147                         }
 148                 } else {
 149                         rc = acpi_get_riscv_isa(rhct, cpu, &isa);
 150                         if (rc < 0) {
 151                                 pr_warn("Unable to get ISA for the hart - %d\n", cpu);
 152                                 continue;
 153                         }
 154                 }
 155
 156                 /*
 157                  * For all possible cpus, we have already validated in
 158                  * the boot process that they at least contain "rv" and
 159                  * whichever of "32"/"64" this kernel supports, and so this
 160                  * section can be skipped.
 161                  */
 162                 isa += 4;
 163
 164                 while (*isa) {
 165                         const char *ext = isa++;
 166                         const char *ext_end = isa;
 167                         bool ext_long = false, ext_err = false;
 168
 169                         switch (*ext) {
 170                         case 's':
 171                                 /*
 172                                  * Workaround for invalid single-letter 's' & 'u'(QEMU).
 173                                  * No need to set the bit in riscv_isa as 's' & 'u' are
 174                                  * not valid ISA extensions. It works until multi-letter
 175                                  * extension starting with "Su" appears.
 176                                  */
 177                                 if (ext[-1] != '_' && ext[1] == 'u') {
 178                                         ++isa;
 179                                         ext_err = true;
 180                                         break;
 181                                 }
 182                                 fallthrough;
 183                         case 'S':
 184                         case 'x':
 185                         case 'X':
 186                         case 'z':
 187                         case 'Z':
 188                                 /*
 189                                  * Before attempting to parse the extension itself, we find its end.
 190                                  * As multi-letter extensions must be split from other multi-letter
 191                                  * extensions with an "_", the end of a multi-letter extension will
 192                                  * either be the null character or the "_" at the start of the next
 193                                  * multi-letter extension.
 194                                  *
 195                                  * Next, as the extensions version is currently ignored, we
 196                                  * eliminate that portion. This is done by parsing backwards from
 197                                  * the end of the extension, removing any numbers. This may be a
 198                                  * major or minor number however, so the process is repeated if a
 199                                  * minor number was found.
 200                                  *
 201                                  * ext_end is intended to represent the first character *after* the
 202                                  * name portion of an extension, but will be decremented to the last
 203                                  * character itself while eliminating the extensions version number.
 204                                  * A simple re-increment solves this problem.
 205                                  */
 206                                 ext_long = true;
 207                                 for (; *isa && *isa != '_'; ++isa)
 208                                         if (unlikely(!isalnum(*isa)))
 209                                                 ext_err = true;
 210
 211                                 ext_end = isa;
 212                                 if (unlikely(ext_err))
 213                                         break;
 214
 215                                 if (!isdigit(ext_end[-1]))
 216                                         break;
 217
 218                                 while (isdigit(*--ext_end))
 219                                         ;
 220
 221                                 if (tolower(ext_end[0]) != 'p' || !isdigit(ext_end[-1])) {
 222                                         ++ext_end;
 223                                         break;
 224                                 }
 225
 226                                 while (isdigit(*--ext_end))
 227                                         ;
 228
 229                                 ++ext_end;
 230                                 break;
 231                         default:
 232                                 /*
 233                                  * Things are a little easier for single-letter extensions, as they
 234                                  * are parsed forwards.
 235                                  *
 236                                  * After checking that our starting position is valid, we need to
 237                                  * ensure that, when isa was incremented at the start of the loop,
 238                                  * that it arrived at the start of the next extension.
 239                                  *
 240                                  * If we are already on a non-digit, there is nothing to do. Either
 241                                  * we have a multi-letter extension's _, or the start of an
 242                                  * extension.
 243                                  *
 244                                  * Otherwise we have found the current extension's major version
 245                                  * number. Parse past it, and a subsequent p/minor version number
 246                                  * if present. The `p` extension must not appear immediately after
 247                                  * a number, so there is no fear of missing it.
 248                                  *
 249                                  */
 250                                 if (unlikely(!isalpha(*ext))) {
 251                                         ext_err = true;
 252                                         break;
 253                                 }
 254
 255                                 if (!isdigit(*isa))
 256                                         break;
 257
 258                                 while (isdigit(*++isa))
 259                                         ;
 260
 261                                 if (tolower(*isa) != 'p')
 262                                         break;
 263
 264                                 if (!isdigit(*++isa)) {
 265                                         --isa;
 266                                         break;
 267                                 }
 268
 269                                 while (isdigit(*++isa))
 270                                         ;
 271
 272                                 break;
 273                         }
 274
 275                         /*
 276                          * The parser expects that at the start of an iteration isa points to the
 277                          * first character of the next extension. As we stop parsing an extension
 278                          * on meeting a non-alphanumeric character, an extra increment is needed
 279                          * where the succeeding extension is a multi-letter prefixed with an "_".
 280                          */
 281                         if (*isa == '_')
 282                                 ++isa;
 283
 284 #define SET_ISA_EXT_MAP(name, bit)                                                      \
 285                         do {                                                            \
 286                                 if ((ext_end - ext == sizeof(name) - 1) &&              \
 287                                      !strncasecmp(ext, name, sizeof(name) - 1) &&       \
 288                                      riscv_isa_extension_check(bit))                    \
 289                                         set_bit(bit, isainfo->isa);                     \
 290                         } while (false)                                                 \
 291
 292                         if (unlikely(ext_err))
 293                                 continue;
 294                         if (!ext_long) {
 295                                 int nr = tolower(*ext) - 'a';
 296
 297                                 if (riscv_isa_extension_check(nr)) {
 298                                         this_hwcap |= isa2hwcap[nr];
 299                                         set_bit(nr, isainfo->isa);
 300                                 }
 301                         } else {
 302                                 /* sorted alphabetically */
 303                                 SET_ISA_EXT_MAP("smaia", RISCV_ISA_EXT_SMAIA);
 304                                 SET_ISA_EXT_MAP("ssaia", RISCV_ISA_EXT_SSAIA);
 305                                 SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF);
 306                                 SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC);
 307                                 SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL);
 308                                 SET_ISA_EXT_MAP("svnapot", RISCV_ISA_EXT_SVNAPOT);
 309                                 SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT);
 310                                 SET_ISA_EXT_MAP("zba", RISCV_ISA_EXT_ZBA);
 311                                 SET_ISA_EXT_MAP("zbb", RISCV_ISA_EXT_ZBB);
 312                                 SET_ISA_EXT_MAP("zbs", RISCV_ISA_EXT_ZBS);
 313                                 SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM);
 314                                 SET_ISA_EXT_MAP("zicboz", RISCV_ISA_EXT_ZICBOZ);
 315                                 SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE);
 316                         }
 317 #undef SET_ISA_EXT_MAP
 318                 }
 319
 320                 /*
 321                  * These ones were as they were part of the base ISA when the
 322                  * port & dt-bindings were upstreamed, and so can be set
 323                  * unconditionally where `i` is in riscv,isa on DT systems.
 324                  */
 325                 if (acpi_disabled) {
 326                         set_bit(RISCV_ISA_EXT_ZICSR, isainfo->isa);
 327                         set_bit(RISCV_ISA_EXT_ZIFENCEI, isainfo->isa);
 328                         set_bit(RISCV_ISA_EXT_ZICNTR, isainfo->isa);
 329                         set_bit(RISCV_ISA_EXT_ZIHPM, isainfo->isa);
 330                 }
 331
 332                 /*
 333                  * All "okay" hart should have same isa. Set HWCAP based on
 334                  * common capabilities of every "okay" hart, in case they don't
 335                  * have.
 336                  */
 337                 if (elf_hwcap)
 338                         elf_hwcap &= this_hwcap;
 339                 else
 340                         elf_hwcap = this_hwcap;
 341
 342                 if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX))
 343                         bitmap_copy(riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX);
 344                 else
 345                         bitmap_and(riscv_isa, riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX);
 346         }
 347
 348         if (!acpi_disabled && rhct)
 349                 acpi_put_table((struct acpi_table_header *)rhct);
 350
 351         /* We don't support systems with F but without D, so mask those out
 352          * here. */
 353         if ((elf_hwcap & COMPAT_HWCAP_ISA_F) && !(elf_hwcap & COMPAT_HWCAP_ISA_D)) {
 354                 pr_info("This kernel does not support systems with F but not D\n");
 355                 elf_hwcap &= ~COMPAT_HWCAP_ISA_F;
 356         }
 357
 358         if (elf_hwcap & COMPAT_HWCAP_ISA_V) {
 359                 riscv_v_setup_vsize();
 360                 /*
 361                  * ISA string in device tree might have 'v' flag, but
 362                  * CONFIG_RISCV_ISA_V is disabled in kernel.
 363                  * Clear V flag in elf_hwcap if CONFIG_RISCV_ISA_V is disabled.
 364                  */
 365                 if (!IS_ENABLED(CONFIG_RISCV_ISA_V))
 366                         elf_hwcap &= ~COMPAT_HWCAP_ISA_V;
 367         }
 368
 369         memset(print_str, 0, sizeof(print_str));
 370         for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++)
 371                 if (riscv_isa[0] & BIT_MASK(i))
 372                         print_str[j++] = (char)('a' + i);
 373         pr_info("riscv: base ISA extensions %s\n", print_str);
 374
 375         memset(print_str, 0, sizeof(print_str));
 376         for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++)
 377                 if (elf_hwcap & BIT_MASK(i))
 378                         print_str[j++] = (char)('a' + i);
 379         pr_info("riscv: ELF capabilities %s\n", print_str);
 380 }
 381
 382 unsigned long riscv_get_elf_hwcap(void)
 383 {
 384         unsigned long hwcap;
 385
 386         hwcap = (elf_hwcap & ((1UL << RISCV_ISA_EXT_BASE) - 1));
 387
 388         if (!riscv_v_vstate_ctrl_user_allowed())
 389                 hwcap &= ~COMPAT_HWCAP_ISA_V;
 390
 391         return hwcap;
 392 }
 393
 394 #ifdef CONFIG_RISCV_ALTERNATIVE
 395 /*
 396  * Alternative patch sites consider 48 bits when determining when to patch
 397  * the old instruction sequence with the new. These bits are broken into a
 398  * 16-bit vendor ID and a 32-bit patch ID. A non-zero vendor ID means the
 399  * patch site is for an erratum, identified by the 32-bit patch ID. When
 400  * the vendor ID is zero, the patch site is for a cpufeature. cpufeatures
 401  * further break down patch ID into two 16-bit numbers. The lower 16 bits
 402  * are the cpufeature ID and the upper 16 bits are used for a value specific
 403  * to the cpufeature and patch site. If the upper 16 bits are zero, then it
 404  * implies no specific value is specified. cpufeatures that want to control
 405  * patching on a per-site basis will provide non-zero values and implement
 406  * checks here. The checks return true when patching should be done, and
 407  * false otherwise.
 408  */
 409 static bool riscv_cpufeature_patch_check(u16 id, u16 value)
 410 {
 411         if (!value)
 412                 return true;
 413
 414         switch (id) {
 415         case RISCV_ISA_EXT_ZICBOZ:
 416                 /*
 417                  * Zicboz alternative applications provide the maximum
 418                  * supported block size order, or zero when it doesn't
 419                  * matter. If the current block size exceeds the maximum,
 420                  * then the alternative cannot be applied.
 421                  */
 422                 return riscv_cboz_block_size <= (1U << value);
 423         }
 424
 425         return false;
 426 }
 427
 428 void __init_or_module riscv_cpufeature_patch_func(struct alt_entry *begin,
 429                                                   struct alt_entry *end,
 430                                                   unsigned int stage)
 431 {
 432         struct alt_entry *alt;
 433         void *oldptr, *altptr;
 434         u16 id, value;
 435
 436         if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
 437                 return;
 438
 439         for (alt = begin; alt < end; alt++) {
 440                 if (alt->vendor_id != 0)
 441                         continue;
 442
 443                 id = PATCH_ID_CPUFEATURE_ID(alt->patch_id);
 444
 445                 if (id >= RISCV_ISA_EXT_MAX) {
 446                         WARN(1, "This extension id:%d is not in ISA extension list", id);
 447                         continue;
 448                 }
 449
 450                 if (!__riscv_isa_extension_available(NULL, id))
 451                         continue;
 452
 453                 value = PATCH_ID_CPUFEATURE_VALUE(alt->patch_id);
 454                 if (!riscv_cpufeature_patch_check(id, value))
 455                         continue;
 456
 457                 oldptr = ALT_OLD_PTR(alt);
 458                 altptr = ALT_ALT_PTR(alt);
 459
 460                 mutex_lock(&text_mutex);
 461                 patch_text_nosync(oldptr, altptr, alt->alt_len);
 462                 riscv_alternative_fix_offsets(oldptr, alt->alt_len, oldptr - altptr);
 463                 mutex_unlock(&text_mutex);
 464         }
 465 }
 466 #endif