arch/riscv/boot/dts/microchip/mpfs.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
   3
   4 /dts-v1/;
   5 #include "dt-bindings/clock/microchip,mpfs-clock.h"
   6
   7 / {
   8         #address-cells = <2>;
   9         #size-cells = <2>;
  10         model = "Microchip PolarFire SoC";
  11         compatible = "microchip,mpfs";
  12
  13         cpus {
  14                 #address-cells = <1>;
  15                 #size-cells = <0>;
  16                 timebase-frequency = <1000000>;
  17
  18                 cpu0: cpu@0 {
  19                         compatible = "sifive,e51", "sifive,rocket0", "riscv";
  20                         device_type = "cpu";
  21                         i-cache-block-size = <64>;
  22                         i-cache-sets = <128>;
  23                         i-cache-size = <16384>;
  24                         reg = <0>;
  25                         riscv,isa = "rv64imac";
  26                         riscv,isa-base = "rv64i";
  27                         riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",
  28                                                "zihpm";
  29                         clocks = <&clkcfg CLK_CPU>;
  30                         status = "disabled";
  31
  32                         cpu0_intc: interrupt-controller {
  33                                 #interrupt-cells = <1>;
  34                                 compatible = "riscv,cpu-intc";
  35                                 interrupt-controller;
  36                         };
  37                 };
  38
  39                 cpu1: cpu@1 {
  40                         compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
  41                         d-cache-block-size = <64>;
  42                         d-cache-sets = <64>;
  43                         d-cache-size = <32768>;
  44                         d-tlb-sets = <1>;
  45                         d-tlb-size = <32>;
  46                         device_type = "cpu";
  47                         i-cache-block-size = <64>;
  48                         i-cache-sets = <64>;
  49                         i-cache-size = <32768>;
  50                         i-tlb-sets = <1>;
  51                         i-tlb-size = <32>;
  52                         mmu-type = "riscv,sv39";
  53                         reg = <1>;
  54                         riscv,isa = "rv64imafdc";
  55                         riscv,isa-base = "rv64i";
  56                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
  57                                                "zifencei", "zihpm";
  58                         clocks = <&clkcfg CLK_CPU>;
  59                         tlb-split;
  60                         next-level-cache = <&cctrllr>;
  61                         status = "okay";
  62
  63                         cpu1_intc: interrupt-controller {
  64                                 #interrupt-cells = <1>;
  65                                 compatible = "riscv,cpu-intc";
  66                                 interrupt-controller;
  67                         };
  68                 };
  69
  70                 cpu2: cpu@2 {
  71                         compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
  72                         d-cache-block-size = <64>;
  73                         d-cache-sets = <64>;
  74                         d-cache-size = <32768>;
  75                         d-tlb-sets = <1>;
  76                         d-tlb-size = <32>;
  77                         device_type = "cpu";
  78                         i-cache-block-size = <64>;
  79                         i-cache-sets = <64>;
  80                         i-cache-size = <32768>;
  81                         i-tlb-sets = <1>;
  82                         i-tlb-size = <32>;
  83                         mmu-type = "riscv,sv39";
  84                         reg = <2>;
  85                         riscv,isa = "rv64imafdc";
  86                         riscv,isa-base = "rv64i";
  87                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
  88                                                "zifencei", "zihpm";
  89                         clocks = <&clkcfg CLK_CPU>;
  90                         tlb-split;
  91                         next-level-cache = <&cctrllr>;
  92                         status = "okay";
  93
  94                         cpu2_intc: interrupt-controller {
  95                                 #interrupt-cells = <1>;
  96                                 compatible = "riscv,cpu-intc";
  97                                 interrupt-controller;
  98                         };
  99                 };
 100
 101                 cpu3: cpu@3 {
 102                         compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
 103                         d-cache-block-size = <64>;
 104                         d-cache-sets = <64>;
 105                         d-cache-size = <32768>;
 106                         d-tlb-sets = <1>;
 107                         d-tlb-size = <32>;
 108                         device_type = "cpu";
 109                         i-cache-block-size = <64>;
 110                         i-cache-sets = <64>;
 111                         i-cache-size = <32768>;
 112                         i-tlb-sets = <1>;
 113                         i-tlb-size = <32>;
 114                         mmu-type = "riscv,sv39";
 115                         reg = <3>;
 116                         riscv,isa = "rv64imafdc";
 117                         riscv,isa-base = "rv64i";
 118                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
 119                                                "zifencei", "zihpm";
 120                         clocks = <&clkcfg CLK_CPU>;
 121                         tlb-split;
 122                         next-level-cache = <&cctrllr>;
 123                         status = "okay";
 124
 125                         cpu3_intc: interrupt-controller {
 126                                 #interrupt-cells = <1>;
 127                                 compatible = "riscv,cpu-intc";
 128                                 interrupt-controller;
 129                         };
 130                 };
 131
 132                 cpu4: cpu@4 {
 133                         compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
 134                         d-cache-block-size = <64>;
 135                         d-cache-sets = <64>;
 136                         d-cache-size = <32768>;
 137                         d-tlb-sets = <1>;
 138                         d-tlb-size = <32>;
 139                         device_type = "cpu";
 140                         i-cache-block-size = <64>;
 141                         i-cache-sets = <64>;
 142                         i-cache-size = <32768>;
 143                         i-tlb-sets = <1>;
 144                         i-tlb-size = <32>;
 145                         mmu-type = "riscv,sv39";
 146                         reg = <4>;
 147                         riscv,isa = "rv64imafdc";
 148                         riscv,isa-base = "rv64i";
 149                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
 150                                                "zifencei", "zihpm";
 151                         clocks = <&clkcfg CLK_CPU>;
 152                         tlb-split;
 153                         next-level-cache = <&cctrllr>;
 154                         status = "okay";
 155                         cpu4_intc: interrupt-controller {
 156                                 #interrupt-cells = <1>;
 157                                 compatible = "riscv,cpu-intc";
 158                                 interrupt-controller;
 159                         };
 160                 };
 161
 162                 cpu-map {
 163                         cluster0 {
 164                                 core0 {
 165                                         cpu = <&cpu0>;
 166                                 };
 167
 168                                 core1 {
 169                                         cpu = <&cpu1>;
 170                                 };
 171
 172                                 core2 {
 173                                         cpu = <&cpu2>;
 174                                 };
 175
 176                                 core3 {
 177                                         cpu = <&cpu3>;
 178                                 };
 179
 180                                 core4 {
 181                                         cpu = <&cpu4>;
 182                                 };
 183                         };
 184                 };
 185         };
 186
 187         refclk: mssrefclk {
 188                 compatible = "fixed-clock";
 189                 #clock-cells = <0>;
 190         };
 191
 192         syscontroller: syscontroller {
 193                 compatible = "microchip,mpfs-sys-controller";
 194                 mboxes = <&mbox 0>;
 195         };
 196
 197         scbclk: mssclkclk {
 198                 compatible = "fixed-clock";
 199                 #clock-cells = <0>;
 200                 clock-frequency = <80000000>;
 201         };
 202
 203         soc {
 204                 #address-cells = <2>;
 205                 #size-cells = <2>;
 206                 compatible = "simple-bus";
 207                 ranges;
 208
 209                 cctrllr: cache-controller@2010000 {
 210                         compatible = "microchip,mpfs-ccache", "sifive,fu540-c000-ccache", "cache";
 211                         reg = <0x0 0x2010000 0x0 0x1000>;
 212                         cache-block-size = <64>;
 213                         cache-level = <2>;
 214                         cache-sets = <1024>;
 215                         cache-size = <2097152>;
 216                         cache-unified;
 217                         interrupt-parent = <&plic>;
 218                         interrupts = <1>, <3>, <4>, <2>;
 219                 };
 220
 221                 clint: clint@2000000 {
 222                         compatible = "sifive,fu540-c000-clint", "sifive,clint0";
 223                         reg = <0x0 0x2000000 0x0 0xC000>;
 224                         interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
 225                                               <&cpu1_intc 3>, <&cpu1_intc 7>,
 226                                               <&cpu2_intc 3>, <&cpu2_intc 7>,
 227                                               <&cpu3_intc 3>, <&cpu3_intc 7>,
 228                                               <&cpu4_intc 3>, <&cpu4_intc 7>;
 229                 };
 230
 231                 plic: interrupt-controller@c000000 {
 232                         compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
 233                         reg = <0x0 0xc000000 0x0 0x4000000>;
 234                         #address-cells = <0>;
 235                         #interrupt-cells = <1>;
 236                         interrupt-controller;
 237                         interrupts-extended = <&cpu0_intc 11>,
 238                                               <&cpu1_intc 11>, <&cpu1_intc 9>,
 239                                               <&cpu2_intc 11>, <&cpu2_intc 9>,
 240                                               <&cpu3_intc 11>, <&cpu3_intc 9>,
 241                                               <&cpu4_intc 11>, <&cpu4_intc 9>;
 242                         riscv,ndev = <186>;
 243                 };
 244
 245                 pdma: dma-controller@3000000 {
 246                         compatible = "sifive,fu540-c000-pdma", "sifive,pdma0";
 247                         reg = <0x0 0x3000000 0x0 0x8000>;
 248                         interrupt-parent = <&plic>;
 249                         interrupts = <5 6>, <7 8>, <9 10>, <11 12>;
 250                         dma-channels = <4>;
 251                         #dma-cells = <1>;
 252                 };
 253
 254                 clkcfg: clkcfg@20002000 {
 255                         compatible = "microchip,mpfs-clkcfg";
 256                         reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>;
 257                         clocks = <&refclk>;
 258                         #clock-cells = <1>;
 259                         #reset-cells = <1>;
 260                 };
 261
 262                 ccc_se: clock-controller@38010000 {
 263                         compatible = "microchip,mpfs-ccc";
 264                         reg = <0x0 0x38010000 0x0 0x1000>, <0x0 0x38020000 0x0 0x1000>,
 265                               <0x0 0x39010000 0x0 0x1000>, <0x0 0x39020000 0x0 0x1000>;
 266                         #clock-cells = <1>;
 267                         status = "disabled";
 268                 };
 269
 270                 ccc_ne: clock-controller@38040000 {
 271                         compatible = "microchip,mpfs-ccc";
 272                         reg = <0x0 0x38040000 0x0 0x1000>, <0x0 0x38080000 0x0 0x1000>,
 273                               <0x0 0x39040000 0x0 0x1000>, <0x0 0x39080000 0x0 0x1000>;
 274                         #clock-cells = <1>;
 275                         status = "disabled";
 276                 };
 277
 278                 ccc_nw: clock-controller@38100000 {
 279                         compatible = "microchip,mpfs-ccc";
 280                         reg = <0x0 0x38100000 0x0 0x1000>, <0x0 0x38200000 0x0 0x1000>,
 281                               <0x0 0x39100000 0x0 0x1000>, <0x0 0x39200000 0x0 0x1000>;
 282                         #clock-cells = <1>;
 283                         status = "disabled";
 284                 };
 285
 286                 ccc_sw: clock-controller@38400000 {
 287                         compatible = "microchip,mpfs-ccc";
 288                         reg = <0x0 0x38400000 0x0 0x1000>, <0x0 0x38800000 0x0 0x1000>,
 289                               <0x0 0x39400000 0x0 0x1000>, <0x0 0x39800000 0x0 0x1000>;
 290                         #clock-cells = <1>;
 291                         status = "disabled";
 292                 };
 293
 294                 mmuart0: serial@20000000 {
 295                         compatible = "ns16550a";
 296                         reg = <0x0 0x20000000 0x0 0x400>;
 297                         reg-io-width = <4>;
 298                         reg-shift = <2>;
 299                         interrupt-parent = <&plic>;
 300                         interrupts = <90>;
 301                         current-speed = <115200>;
 302                         clocks = <&clkcfg CLK_MMUART0>;
 303                         status = "disabled"; /* Reserved for the HSS */
 304                 };
 305
 306                 mmuart1: serial@20100000 {
 307                         compatible = "ns16550a";
 308                         reg = <0x0 0x20100000 0x0 0x400>;
 309                         reg-io-width = <4>;
 310                         reg-shift = <2>;
 311                         interrupt-parent = <&plic>;
 312                         interrupts = <91>;
 313                         current-speed = <115200>;
 314                         clocks = <&clkcfg CLK_MMUART1>;
 315                         status = "disabled";
 316                 };
 317
 318                 mmuart2: serial@20102000 {
 319                         compatible = "ns16550a";
 320                         reg = <0x0 0x20102000 0x0 0x400>;
 321                         reg-io-width = <4>;
 322                         reg-shift = <2>;
 323                         interrupt-parent = <&plic>;
 324                         interrupts = <92>;
 325                         current-speed = <115200>;
 326                         clocks = <&clkcfg CLK_MMUART2>;
 327                         status = "disabled";
 328                 };
 329
 330                 mmuart3: serial@20104000 {
 331                         compatible = "ns16550a";
 332                         reg = <0x0 0x20104000 0x0 0x400>;
 333                         reg-io-width = <4>;
 334                         reg-shift = <2>;
 335                         interrupt-parent = <&plic>;
 336                         interrupts = <93>;
 337                         current-speed = <115200>;
 338                         clocks = <&clkcfg CLK_MMUART3>;
 339                         status = "disabled";
 340                 };
 341
 342                 mmuart4: serial@20106000 {
 343                         compatible = "ns16550a";
 344                         reg = <0x0 0x20106000 0x0 0x400>;
 345                         reg-io-width = <4>;
 346                         reg-shift = <2>;
 347                         interrupt-parent = <&plic>;
 348                         interrupts = <94>;
 349                         clocks = <&clkcfg CLK_MMUART4>;
 350                         current-speed = <115200>;
 351                         status = "disabled";
 352                 };
 353
 354                 /* Common node entry for emmc/sd */
 355                 mmc: mmc@20008000 {
 356                         compatible = "microchip,mpfs-sd4hc", "cdns,sd4hc";
 357                         reg = <0x0 0x20008000 0x0 0x1000>;
 358                         interrupt-parent = <&plic>;
 359                         interrupts = <88>;
 360                         clocks = <&clkcfg CLK_MMC>;
 361                         max-frequency = <200000000>;
 362                         status = "disabled";
 363                 };
 364
 365                 spi0: spi@20108000 {
 366                         compatible = "microchip,mpfs-spi";
 367                         #address-cells = <1>;
 368                         #size-cells = <0>;
 369                         reg = <0x0 0x20108000 0x0 0x1000>;
 370                         interrupt-parent = <&plic>;
 371                         interrupts = <54>;
 372                         clocks = <&clkcfg CLK_SPI0>;
 373                         status = "disabled";
 374                 };
 375
 376                 spi1: spi@20109000 {
 377                         compatible = "microchip,mpfs-spi";
 378                         #address-cells = <1>;
 379                         #size-cells = <0>;
 380                         reg = <0x0 0x20109000 0x0 0x1000>;
 381                         interrupt-parent = <&plic>;
 382                         interrupts = <55>;
 383                         clocks = <&clkcfg CLK_SPI1>;
 384                         status = "disabled";
 385                 };
 386
 387                 qspi: spi@21000000 {
 388                         compatible = "microchip,mpfs-qspi", "microchip,coreqspi-rtl-v2";
 389                         #address-cells = <1>;
 390                         #size-cells = <0>;
 391                         reg = <0x0 0x21000000 0x0 0x1000>;
 392                         interrupt-parent = <&plic>;
 393                         interrupts = <85>;
 394                         clocks = <&clkcfg CLK_QSPI>;
 395                         status = "disabled";
 396                 };
 397
 398                 i2c0: i2c@2010a000 {
 399                         compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7";
 400                         reg = <0x0 0x2010a000 0x0 0x1000>;
 401                         #address-cells = <1>;
 402                         #size-cells = <0>;
 403                         interrupt-parent = <&plic>;
 404                         interrupts = <58>;
 405                         clocks = <&clkcfg CLK_I2C0>;
 406                         clock-frequency = <100000>;
 407                         status = "disabled";
 408                 };
 409
 410                 i2c1: i2c@2010b000 {
 411                         compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7";
 412                         reg = <0x0 0x2010b000 0x0 0x1000>;
 413                         #address-cells = <1>;
 414                         #size-cells = <0>;
 415                         interrupt-parent = <&plic>;
 416                         interrupts = <61>;
 417                         clocks = <&clkcfg CLK_I2C1>;
 418                         clock-frequency = <100000>;
 419                         status = "disabled";
 420                 };
 421
 422                 can0: can@2010c000 {
 423                         compatible = "microchip,mpfs-can";
 424                         reg = <0x0 0x2010c000 0x0 0x1000>;
 425                         clocks = <&clkcfg CLK_CAN0>;
 426                         interrupt-parent = <&plic>;
 427                         interrupts = <56>;
 428                         status = "disabled";
 429                 };
 430
 431                 can1: can@2010d000 {
 432                         compatible = "microchip,mpfs-can";
 433                         reg = <0x0 0x2010d000 0x0 0x1000>;
 434                         clocks = <&clkcfg CLK_CAN1>;
 435                         interrupt-parent = <&plic>;
 436                         interrupts = <57>;
 437                         status = "disabled";
 438                 };
 439
 440                 mac0: ethernet@20110000 {
 441                         compatible = "microchip,mpfs-macb", "cdns,macb";
 442                         reg = <0x0 0x20110000 0x0 0x2000>;
 443                         #address-cells = <1>;
 444                         #size-cells = <0>;
 445                         interrupt-parent = <&plic>;
 446                         interrupts = <64>, <65>, <66>, <67>, <68>, <69>;
 447                         local-mac-address = [00 00 00 00 00 00];
 448                         clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>;
 449                         clock-names = "pclk", "hclk";
 450                         resets = <&clkcfg CLK_MAC0>;
 451                         status = "disabled";
 452                 };
 453
 454                 mac1: ethernet@20112000 {
 455                         compatible = "microchip,mpfs-macb", "cdns,macb";
 456                         reg = <0x0 0x20112000 0x0 0x2000>;
 457                         #address-cells = <1>;
 458                         #size-cells = <0>;
 459                         interrupt-parent = <&plic>;
 460                         interrupts = <70>, <71>, <72>, <73>, <74>, <75>;
 461                         local-mac-address = [00 00 00 00 00 00];
 462                         clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>;
 463                         clock-names = "pclk", "hclk";
 464                         resets = <&clkcfg CLK_MAC1>;
 465                         status = "disabled";
 466                 };
 467
 468                 gpio0: gpio@20120000 {
 469                         compatible = "microchip,mpfs-gpio";
 470                         reg = <0x0 0x20120000 0x0 0x1000>;
 471                         interrupt-parent = <&plic>;
 472                         interrupt-controller;
 473                         #interrupt-cells = <1>;
 474                         clocks = <&clkcfg CLK_GPIO0>;
 475                         gpio-controller;
 476                         #gpio-cells = <2>;
 477                         status = "disabled";
 478                 };
 479
 480                 gpio1: gpio@20121000 {
 481                         compatible = "microchip,mpfs-gpio";
 482                         reg = <0x0 0x20121000 0x0 0x1000>;
 483                         interrupt-parent = <&plic>;
 484                         interrupt-controller;
 485                         #interrupt-cells = <1>;
 486                         clocks = <&clkcfg CLK_GPIO1>;
 487                         gpio-controller;
 488                         #gpio-cells = <2>;
 489                         status = "disabled";
 490                 };
 491
 492                 gpio2: gpio@20122000 {
 493                         compatible = "microchip,mpfs-gpio";
 494                         reg = <0x0 0x20122000 0x0 0x1000>;
 495                         interrupt-parent = <&plic>;
 496                         interrupt-controller;
 497                         #interrupt-cells = <1>;
 498                         clocks = <&clkcfg CLK_GPIO2>;
 499                         gpio-controller;
 500                         #gpio-cells = <2>;
 501                         status = "disabled";
 502                 };
 503
 504                 rtc: rtc@20124000 {
 505                         compatible = "microchip,mpfs-rtc";
 506                         reg = <0x0 0x20124000 0x0 0x1000>;
 507                         interrupt-parent = <&plic>;
 508                         interrupts = <80>, <81>;
 509                         clocks = <&clkcfg CLK_RTC>, <&clkcfg CLK_RTCREF>;
 510                         clock-names = "rtc", "rtcref";
 511                         status = "disabled";
 512                 };
 513
 514                 usb: usb@20201000 {
 515                         compatible = "microchip,mpfs-musb";
 516                         reg = <0x0 0x20201000 0x0 0x1000>;
 517                         interrupt-parent = <&plic>;
 518                         interrupts = <86>, <87>;
 519                         clocks = <&clkcfg CLK_USB>;
 520                         interrupt-names = "dma","mc";
 521                         status = "disabled";
 522                 };
 523
 524                 mbox: mailbox@37020000 {
 525                         compatible = "microchip,mpfs-mailbox";
 526                         reg = <0x0 0x37020000 0x0 0x58>, <0x0 0x2000318C 0x0 0x40>,
 527                               <0x0 0x37020800 0x0 0x100>;
 528                         interrupt-parent = <&plic>;
 529                         interrupts = <96>;
 530                         #mbox-cells = <1>;
 531                         status = "disabled";
 532                 };
 533
 534                 syscontroller_qspi: spi@37020100 {
 535                         compatible = "microchip,mpfs-qspi", "microchip,coreqspi-rtl-v2";
 536                         #address-cells = <1>;
 537                         #size-cells = <0>;
 538                         reg = <0x0 0x37020100 0x0 0x100>;
 539                         interrupt-parent = <&plic>;
 540                         interrupts = <110>;
 541                         clocks = <&scbclk>;
 542                         status = "disabled";
 543                 };
 544         };
 545 };