2 * STx GP3 board specific routines
4 * Dan Malek <dan@embeddededge.com>
5 * Copyright 2004 Embedded Edge, LLC
7 * Copied from mpc8560_ads.c
8 * Copyright 2002, 2003 Motorola Inc.
10 * Ported to 2.6, Matt Porter <mporter@kernel.crashing.org>
11 * Copyright 2004-2005 MontaVista Software, Inc.
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
19 #include <linux/stddef.h>
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/errno.h>
23 #include <linux/reboot.h>
24 #include <linux/pci.h>
25 #include <linux/kdev_t.h>
26 #include <linux/major.h>
27 #include <linux/blkdev.h>
28 #include <linux/console.h>
29 #include <linux/delay.h>
30 #include <linux/root_dev.h>
31 #include <linux/seq_file.h>
32 #include <linux/serial.h>
33 #include <linux/initrd.h>
34 #include <linux/module.h>
35 #include <linux/fsl_devices.h>
36 #include <linux/interrupt.h>
37 #include <linux/rio.h>
39 #include <asm/system.h>
40 #include <asm/pgtable.h>
42 #include <asm/atomic.h>
45 #include <asm/machdep.h>
46 #include <asm/open_pic.h>
47 #include <asm/bootinfo.h>
48 #include <asm/pci-bridge.h>
49 #include <asm/mpc85xx.h>
51 #include <asm/immap_85xx.h>
53 #include <asm/ppc_sys.h>
55 #include <syslib/cpm2_pic.h>
56 #include <syslib/ppc85xx_common.h>
59 unsigned char __res[sizeof(bd_t)];
62 unsigned long isa_io_base = 0;
63 unsigned long isa_mem_base = 0;
64 unsigned long pci_dram_offset = 0;
67 /* Internal interrupts are all Level Sensitive, and Positive Polarity */
68 static u8 gp3_openpic_initsenses[] __initdata = {
69 MPC85XX_INTERNAL_IRQ_SENSES,
70 0x0, /* External 0: */
71 #if defined(CONFIG_PCI)
72 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 1: PCI slot 0 */
73 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 2: PCI slot 1 */
74 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 3: PCI slot 2 */
75 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 4: PCI slot 3 */
77 0x0, /* External 1: */
78 0x0, /* External 2: */
79 0x0, /* External 3: */
80 0x0, /* External 4: */
82 0x0, /* External 5: */
83 0x0, /* External 6: */
84 0x0, /* External 7: */
85 0x0, /* External 8: */
86 0x0, /* External 9: */
87 0x0, /* External 10: */
88 0x0, /* External 11: */
92 * Setup the architecture
97 bd_t *binfo = (bd_t *) __res;
99 struct gianfar_platform_data *pdata;
100 struct gianfar_mdio_data *mdata;
104 /* get the core frequency */
105 freq = binfo->bi_intfreq;
108 ppc_md.progress("gp3_setup_arch()", 0);
110 /* Set loops_per_jiffy to a half-way reasonable value,
111 for use until calibrate_delay gets called. */
112 loops_per_jiffy = freq / HZ;
115 /* setup PCI host bridges */
116 mpc85xx_setup_hose();
119 /* setup the board related info for the MDIO bus */
120 mdata = (struct gianfar_mdio_data *) ppc_sys_get_pdata(MPC85xx_MDIO);
122 mdata->irq[2] = MPC85xx_IRQ_EXT5;
123 mdata->irq[4] = MPC85xx_IRQ_EXT5;
124 mdata->irq[31] = PHY_POLL;
126 /* setup the board related information for the enet controllers */
127 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1);
129 /* pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; */
132 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
135 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2);
137 /* pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; */
140 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
143 #ifdef CONFIG_BLK_DEV_INITRD
145 ROOT_DEV = Root_RAM0;
148 #ifdef CONFIG_ROOT_NFS
151 ROOT_DEV = Root_HDA1;
154 printk ("bi_immr_base = %8.8lx\n", binfo->bi_immr_base);
157 static irqreturn_t cpm2_cascade(int irq, void *dev_id)
159 while ((irq = cpm2_get_irq()) >= 0)
165 static struct irqaction cpm2_irqaction = {
166 .handler = cpm2_cascade,
167 .flags = IRQF_DISABLED,
168 .mask = CPU_MASK_NONE,
169 .name = "cpm2_cascade",
175 bd_t *binfo = (bd_t *) __res;
181 /* Determine the Physical Address of the OpenPIC regs */
182 phys_addr_t OpenPIC_PAddr =
183 binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET;
184 OpenPIC_Addr = ioremap(OpenPIC_PAddr, MPC85xx_OPENPIC_SIZE);
185 OpenPIC_InitSenses = gp3_openpic_initsenses;
186 OpenPIC_NumInitSenses = sizeof (gp3_openpic_initsenses);
188 /* Skip reserved space and internal sources */
189 openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);
191 /* Map PIC IRQs 0-11 */
192 openpic_set_sources(48, 12, OpenPIC_Addr + 0x10000);
195 * Let openpic interrupts starting from an offset, to
196 * leave space for cascading interrupts underneath.
198 openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET);
203 setup_irq(MPC85xx_IRQ_CPM, &cpm2_irqaction);
209 gp3_show_cpuinfo(struct seq_file *m)
211 uint pvid, svid, phid1;
212 bd_t *binfo = (bd_t *) __res;
215 extern unsigned long total_memory; /* in mm/init */
217 /* get the core frequency */
218 freq = binfo->bi_intfreq;
220 pvid = mfspr(SPRN_PVR);
221 svid = mfspr(SPRN_SVR);
223 memsize = total_memory;
225 seq_printf(m, "Vendor\t\t: RPC Electronics STx \n");
226 seq_printf(m, "Machine\t\t: GP3 - MPC%s\n", cur_ppc_sys_spec->ppc_sys_name);
227 seq_printf(m, "bus freq\t: %u.%.6u MHz\n", freq / 1000000,
229 seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
230 seq_printf(m, "SVR\t\t: 0x%x\n", svid);
232 /* Display cpu Pll setting */
233 phid1 = mfspr(SPRN_HID1);
234 seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
236 /* Display the amount of memory */
237 seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
243 int mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel,
246 static char pci_irq_table[][4] =
248 * PCI IDSEL/INTPIN->INTLINE
252 {PIRQA, PIRQB, PIRQC, PIRQD},
253 {PIRQD, PIRQA, PIRQB, PIRQC},
254 {PIRQC, PIRQD, PIRQA, PIRQB},
255 {PIRQB, PIRQC, PIRQD, PIRQA},
258 const long min_idsel = 12, max_idsel = 15, irqs_per_slot = 4;
259 return PCI_IRQ_TABLE_LOOKUP;
262 int mpc85xx_exclude_device(u_char bus, u_char devfn)
264 if (bus == 0 && PCI_SLOT(devfn) == 0)
265 return PCIBIOS_DEVICE_NOT_FOUND;
267 return PCIBIOS_SUCCESSFUL;
269 #endif /* CONFIG_PCI */
271 #ifdef CONFIG_RAPIDIO
272 extern void mpc85xx_rio_setup(int law_start, int law_size);
274 platform_rio_init(void)
277 * The STx firmware configures the RapidIO Local Access Window
278 * at 0xc0000000 with a size of 512MB.
280 mpc85xx_rio_setup(0xc0000000, 0x20000000);
282 #endif /* CONFIG_RAPIDIO */
285 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
286 unsigned long r6, unsigned long r7)
288 /* parse_bootinfo must always be called first */
289 parse_bootinfo(find_bootinfo());
292 * If we were passed in a board information, copy it into the
293 * residual data area.
296 memcpy((void *) __res, (void *) (r3 + KERNELBASE),
300 #if defined(CONFIG_BLK_DEV_INITRD)
302 * If the init RAM disk has been configured in, and there's a valid
303 * starting address for it, set it up.
306 initrd_start = r4 + KERNELBASE;
307 initrd_end = r5 + KERNELBASE;
309 #endif /* CONFIG_BLK_DEV_INITRD */
311 /* Copy the kernel command line arguments to a safe place. */
314 *(char *) (r7 + KERNELBASE) = 0;
315 strcpy(cmd_line, (char *) (r6 + KERNELBASE));
318 identify_ppc_sys_by_id(mfspr(SPRN_SVR));
320 /* setup the PowerPC module struct */
321 ppc_md.setup_arch = gp3_setup_arch;
322 ppc_md.show_cpuinfo = gp3_show_cpuinfo;
324 ppc_md.init_IRQ = gp3_init_IRQ;
325 ppc_md.get_irq = openpic_get_irq;
327 ppc_md.restart = mpc85xx_restart;
328 ppc_md.power_off = mpc85xx_power_off;
329 ppc_md.halt = mpc85xx_halt;
331 ppc_md.find_end_of_memory = mpc85xx_find_end_of_memory;
333 ppc_md.calibrate_decr = mpc85xx_calibrate_decr;
336 ppc_md.progress("platform_init(): exit", 0);