1 // SPDX-License-Identifier: GPL-2.0-only
2 #include <linux/kernel.h>
3 #include <linux/kvm_host.h>
4 #include <asm/asm-prototypes.h>
6 #include <asm/kvm_ppc.h>
7 #include <asm/ppc-opcode.h>
9 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
10 static void __start_timing(struct kvm_vcpu *vcpu, struct kvmhv_tb_accumulator *next)
12 struct kvmppc_vcore *vc = vcpu->arch.vcore;
13 u64 tb = mftb() - vc->tb_offset_applied;
15 vcpu->arch.cur_activity = next;
16 vcpu->arch.cur_tb_start = tb;
19 static void __accumulate_time(struct kvm_vcpu *vcpu, struct kvmhv_tb_accumulator *next)
21 struct kvmppc_vcore *vc = vcpu->arch.vcore;
22 struct kvmhv_tb_accumulator *curr;
23 u64 tb = mftb() - vc->tb_offset_applied;
28 curr = vcpu->arch.cur_activity;
29 vcpu->arch.cur_activity = next;
30 prev_tb = vcpu->arch.cur_tb_start;
31 vcpu->arch.cur_tb_start = tb;
39 curr->seqcount = seq + 1;
41 curr->tb_total += delta;
42 if (seq == 0 || delta < curr->tb_min)
44 if (delta > curr->tb_max)
47 curr->seqcount = seq + 2;
50 #define start_timing(vcpu, next) __start_timing(vcpu, next)
51 #define end_timing(vcpu) __start_timing(vcpu, NULL)
52 #define accumulate_time(vcpu, next) __accumulate_time(vcpu, next)
54 #define start_timing(vcpu, next) do {} while (0)
55 #define end_timing(vcpu) do {} while (0)
56 #define accumulate_time(vcpu, next) do {} while (0)
59 static inline void mfslb(unsigned int idx, u64 *slbee, u64 *slbev)
61 asm volatile("slbmfev %0,%1" : "=r" (*slbev) : "r" (idx));
62 asm volatile("slbmfee %0,%1" : "=r" (*slbee) : "r" (idx));
65 static inline void mtslb(u64 slbee, u64 slbev)
67 asm volatile("slbmte %0,%1" :: "r" (slbev), "r" (slbee));
70 static inline void clear_slb_entry(unsigned int idx)
75 static inline void slb_clear_invalidate_partition(void)
78 asm volatile(PPC_SLBIA(6));
82 * Malicious or buggy radix guests may have inserted SLB entries
83 * (only 0..3 because radix always runs with UPRT=1), so these must
84 * be cleared here to avoid side-channels. slbmte is used rather
85 * than slbia, as it won't clear cached translations.
87 static void radix_clear_slb(void)
91 for (i = 0; i < 4; i++)
95 static void switch_mmu_to_guest_radix(struct kvm *kvm, struct kvm_vcpu *vcpu, u64 lpcr)
97 struct kvm_nested_guest *nested = vcpu->arch.nested;
100 lpid = nested ? nested->shadow_lpid : kvm->arch.lpid;
103 * All the isync()s are overkill but trivially follow the ISA
104 * requirements. Some can likely be replaced with justification
105 * comment for why they are not needed.
108 mtspr(SPRN_LPID, lpid);
110 mtspr(SPRN_LPCR, lpcr);
112 mtspr(SPRN_PID, vcpu->arch.pid);
116 static void switch_mmu_to_guest_hpt(struct kvm *kvm, struct kvm_vcpu *vcpu, u64 lpcr)
121 lpid = kvm->arch.lpid;
123 mtspr(SPRN_LPID, lpid);
124 mtspr(SPRN_LPCR, lpcr);
125 mtspr(SPRN_PID, vcpu->arch.pid);
127 for (i = 0; i < vcpu->arch.slb_max; i++)
128 mtslb(vcpu->arch.slb[i].orige, vcpu->arch.slb[i].origv);
133 static void switch_mmu_to_host(struct kvm *kvm, u32 pid)
136 mtspr(SPRN_PID, pid);
138 mtspr(SPRN_LPID, kvm->arch.host_lpid);
140 mtspr(SPRN_LPCR, kvm->arch.host_lpcr);
143 if (!radix_enabled())
144 slb_restore_bolted_realmode();
147 static void save_clear_host_mmu(struct kvm *kvm)
149 if (!radix_enabled()) {
151 * Hash host could save and restore host SLB entries to
152 * reduce SLB fault overheads of VM exits, but for now the
153 * existing code clears all entries and restores just the
154 * bolted ones when switching back to host.
156 slb_clear_invalidate_partition();
160 static void save_clear_guest_mmu(struct kvm *kvm, struct kvm_vcpu *vcpu)
162 if (kvm_is_radix(kvm)) {
169 * This must run before switching to host (radix host can't
172 for (i = 0; i < vcpu->arch.slb_nr; i++) {
174 mfslb(i, &slbee, &slbev);
175 if (slbee & SLB_ESID_V) {
176 vcpu->arch.slb[nr].orige = slbee | i;
177 vcpu->arch.slb[nr].origv = slbev;
181 vcpu->arch.slb_max = nr;
182 slb_clear_invalidate_partition();
186 int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpcr)
188 struct kvm *kvm = vcpu->kvm;
189 struct kvm_nested_guest *nested = vcpu->arch.nested;
190 struct kvmppc_vcore *vc = vcpu->arch.vcore;
197 unsigned long host_hfscr;
198 unsigned long host_ciabr;
199 unsigned long host_dawr0;
200 unsigned long host_dawrx0;
201 unsigned long host_psscr;
202 unsigned long host_pidr;
203 unsigned long host_dawr1;
204 unsigned long host_dawrx1;
206 hdec = time_limit - mftb();
208 return BOOK3S_INTERRUPT_HV_DECREMENTER;
210 WARN_ON_ONCE(vcpu->arch.shregs.msr & MSR_HV);
211 WARN_ON_ONCE(!(vcpu->arch.shregs.msr & MSR_ME));
213 start_timing(vcpu, &vcpu->arch.rm_entry);
215 vcpu->arch.ceded = 0;
218 u64 new_tb = mftb() + vc->tb_offset;
219 mtspr(SPRN_TBU40, new_tb);
221 if ((tb & 0xffffff) < (new_tb & 0xffffff))
222 mtspr(SPRN_TBU40, new_tb + 0x1000000);
223 vc->tb_offset_applied = vc->tb_offset;
228 host_hfscr = mfspr(SPRN_HFSCR);
229 host_ciabr = mfspr(SPRN_CIABR);
230 host_dawr0 = mfspr(SPRN_DAWR0);
231 host_dawrx0 = mfspr(SPRN_DAWRX0);
232 host_psscr = mfspr(SPRN_PSSCR);
233 host_pidr = mfspr(SPRN_PID);
234 if (cpu_has_feature(CPU_FTR_DAWR1)) {
235 host_dawr1 = mfspr(SPRN_DAWR1);
236 host_dawrx1 = mfspr(SPRN_DAWRX1);
240 mtspr(SPRN_PCR, vc->pcr | PCR_MASK);
241 mtspr(SPRN_DPDES, vc->dpdes);
242 mtspr(SPRN_VTB, vc->vtb);
244 local_paca->kvm_hstate.host_purr = mfspr(SPRN_PURR);
245 local_paca->kvm_hstate.host_spurr = mfspr(SPRN_SPURR);
246 mtspr(SPRN_PURR, vcpu->arch.purr);
247 mtspr(SPRN_SPURR, vcpu->arch.spurr);
249 if (dawr_enabled()) {
250 mtspr(SPRN_DAWR0, vcpu->arch.dawr0);
251 mtspr(SPRN_DAWRX0, vcpu->arch.dawrx0);
252 if (cpu_has_feature(CPU_FTR_DAWR1)) {
253 mtspr(SPRN_DAWR1, vcpu->arch.dawr1);
254 mtspr(SPRN_DAWRX1, vcpu->arch.dawrx1);
257 mtspr(SPRN_CIABR, vcpu->arch.ciabr);
258 mtspr(SPRN_IC, vcpu->arch.ic);
260 mtspr(SPRN_PSSCR, vcpu->arch.psscr | PSSCR_EC |
261 (local_paca->kvm_hstate.fake_suspend << PSSCR_FAKE_SUSPEND_LG));
263 mtspr(SPRN_HFSCR, vcpu->arch.hfscr);
265 mtspr(SPRN_HSRR0, vcpu->arch.regs.nip);
266 mtspr(SPRN_HSRR1, (vcpu->arch.shregs.msr & ~MSR_HV) | MSR_ME);
269 * On POWER9 DD2.1 and below, sometimes on a Hypervisor Data Storage
270 * Interrupt (HDSI) the HDSISR is not be updated at all.
272 * To work around this we put a canary value into the HDSISR before
273 * returning to a guest and then check for this canary when we take a
274 * HDSI. If we find the canary on a HDSI, we know the hardware didn't
275 * update the HDSISR. In this case we return to the guest to retake the
276 * HDSI which should correctly update the HDSISR the second time HDSI
279 * Just do this on all p9 processors for now.
281 mtspr(SPRN_HDSISR, HDSISR_CANARY);
283 mtspr(SPRN_SPRG0, vcpu->arch.shregs.sprg0);
284 mtspr(SPRN_SPRG1, vcpu->arch.shregs.sprg1);
285 mtspr(SPRN_SPRG2, vcpu->arch.shregs.sprg2);
286 mtspr(SPRN_SPRG3, vcpu->arch.shregs.sprg3);
288 mtspr(SPRN_AMOR, ~0UL);
290 local_paca->kvm_hstate.in_guest = KVM_GUEST_MODE_HV_P9;
293 * Hash host, hash guest, or radix guest with prefetch bug, all have
294 * to disable the MMU before switching to guest MMU state.
296 if (!radix_enabled() || !kvm_is_radix(kvm) ||
297 cpu_has_feature(CPU_FTR_P9_RADIX_PREFETCH_BUG))
298 __mtmsrd(msr & ~(MSR_IR|MSR_DR|MSR_RI), 0);
300 save_clear_host_mmu(kvm);
302 if (kvm_is_radix(kvm)) {
303 switch_mmu_to_guest_radix(kvm, vcpu, lpcr);
304 if (!cpu_has_feature(CPU_FTR_P9_RADIX_PREFETCH_BUG))
305 __mtmsrd(0, 1); /* clear RI */
308 switch_mmu_to_guest_hpt(kvm, vcpu, lpcr);
311 /* TLBIEL uses LPID=LPIDR, so run this after setting guest LPID */
312 kvmppc_check_need_tlb_flush(kvm, vc->pcpu, nested);
315 * P9 suppresses the HDEC exception when LPCR[HDICE] = 0,
316 * so set guest LPCR (with HDICE) before writing HDEC.
318 mtspr(SPRN_HDEC, hdec);
320 mtspr(SPRN_DAR, vcpu->arch.shregs.dar);
321 mtspr(SPRN_DSISR, vcpu->arch.shregs.dsisr);
322 mtspr(SPRN_SRR0, vcpu->arch.shregs.srr0);
323 mtspr(SPRN_SRR1, vcpu->arch.shregs.srr1);
325 accumulate_time(vcpu, &vcpu->arch.guest_time);
327 kvmppc_p9_enter_guest(vcpu);
329 accumulate_time(vcpu, &vcpu->arch.rm_intr);
331 /* XXX: Could get these from r11/12 and paca exsave instead */
332 vcpu->arch.shregs.srr0 = mfspr(SPRN_SRR0);
333 vcpu->arch.shregs.srr1 = mfspr(SPRN_SRR1);
334 vcpu->arch.shregs.dar = mfspr(SPRN_DAR);
335 vcpu->arch.shregs.dsisr = mfspr(SPRN_DSISR);
337 /* 0x2 bit for HSRR is only used by PR and P7/8 HV paths, clear it */
338 trap = local_paca->kvm_hstate.scratch0 & ~0x2;
340 /* HSRR interrupts leave MSR[RI] unchanged, SRR interrupts clear it. */
342 if (likely(trap > BOOK3S_INTERRUPT_MACHINE_CHECK)) {
343 if (trap != BOOK3S_INTERRUPT_SYSCALL &&
344 (vcpu->arch.shregs.msr & MSR_RI))
346 exsave = local_paca->exgen;
347 } else if (trap == BOOK3S_INTERRUPT_SYSTEM_RESET) {
348 exsave = local_paca->exnmi;
349 } else { /* trap == 0x200 */
350 exsave = local_paca->exmc;
353 vcpu->arch.regs.gpr[1] = local_paca->kvm_hstate.scratch1;
354 vcpu->arch.regs.gpr[3] = local_paca->kvm_hstate.scratch2;
357 * Only set RI after reading machine check regs (DAR, DSISR, SRR0/1)
358 * and hstate scratch (which we need to move into exsave to make
359 * re-entrant vs SRESET/MCE)
362 if (unlikely(!(mfmsr() & MSR_RI))) {
367 WARN_ON_ONCE(mfmsr() & MSR_RI);
371 vcpu->arch.regs.gpr[9] = exsave[EX_R9/sizeof(u64)];
372 vcpu->arch.regs.gpr[10] = exsave[EX_R10/sizeof(u64)];
373 vcpu->arch.regs.gpr[11] = exsave[EX_R11/sizeof(u64)];
374 vcpu->arch.regs.gpr[12] = exsave[EX_R12/sizeof(u64)];
375 vcpu->arch.regs.gpr[13] = exsave[EX_R13/sizeof(u64)];
376 vcpu->arch.ppr = exsave[EX_PPR/sizeof(u64)];
377 vcpu->arch.cfar = exsave[EX_CFAR/sizeof(u64)];
378 vcpu->arch.regs.ctr = exsave[EX_CTR/sizeof(u64)];
380 vcpu->arch.last_inst = KVM_INST_FETCH_FAILED;
382 if (unlikely(trap == BOOK3S_INTERRUPT_MACHINE_CHECK)) {
383 vcpu->arch.fault_dar = exsave[EX_DAR/sizeof(u64)];
384 vcpu->arch.fault_dsisr = exsave[EX_DSISR/sizeof(u64)];
385 kvmppc_realmode_machine_check(vcpu);
387 } else if (unlikely(trap == BOOK3S_INTERRUPT_HMI)) {
388 kvmppc_realmode_hmi_handler();
390 } else if (trap == BOOK3S_INTERRUPT_H_EMUL_ASSIST) {
391 vcpu->arch.emul_inst = mfspr(SPRN_HEIR);
393 } else if (trap == BOOK3S_INTERRUPT_H_DATA_STORAGE) {
394 vcpu->arch.fault_dar = exsave[EX_DAR/sizeof(u64)];
395 vcpu->arch.fault_dsisr = exsave[EX_DSISR/sizeof(u64)];
396 vcpu->arch.fault_gpa = mfspr(SPRN_ASDR);
398 } else if (trap == BOOK3S_INTERRUPT_H_INST_STORAGE) {
399 vcpu->arch.fault_gpa = mfspr(SPRN_ASDR);
401 } else if (trap == BOOK3S_INTERRUPT_H_FAC_UNAVAIL) {
402 vcpu->arch.hfscr = mfspr(SPRN_HFSCR);
404 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
406 * Softpatch interrupt for transactional memory emulation cases
407 * on POWER9 DD2.2. This is early in the guest exit path - we
408 * haven't saved registers or done a treclaim yet.
410 } else if (trap == BOOK3S_INTERRUPT_HV_SOFTPATCH) {
411 vcpu->arch.emul_inst = mfspr(SPRN_HEIR);
414 * The cases we want to handle here are those where the guest
415 * is in real suspend mode and is trying to transition to
416 * transactional mode.
418 if (local_paca->kvm_hstate.fake_suspend &&
419 (vcpu->arch.shregs.msr & MSR_TS_S)) {
420 if (kvmhv_p9_tm_emulation_early(vcpu)) {
421 /* Prevent it being handled again. */
428 accumulate_time(vcpu, &vcpu->arch.rm_exit);
430 /* Advance host PURR/SPURR by the amount used by guest */
431 purr = mfspr(SPRN_PURR);
432 spurr = mfspr(SPRN_SPURR);
433 mtspr(SPRN_PURR, local_paca->kvm_hstate.host_purr +
434 purr - vcpu->arch.purr);
435 mtspr(SPRN_SPURR, local_paca->kvm_hstate.host_spurr +
436 spurr - vcpu->arch.spurr);
437 vcpu->arch.purr = purr;
438 vcpu->arch.spurr = spurr;
440 vcpu->arch.ic = mfspr(SPRN_IC);
441 vcpu->arch.pid = mfspr(SPRN_PID);
442 vcpu->arch.psscr = mfspr(SPRN_PSSCR) & PSSCR_GUEST_VIS;
444 vcpu->arch.shregs.sprg0 = mfspr(SPRN_SPRG0);
445 vcpu->arch.shregs.sprg1 = mfspr(SPRN_SPRG1);
446 vcpu->arch.shregs.sprg2 = mfspr(SPRN_SPRG2);
447 vcpu->arch.shregs.sprg3 = mfspr(SPRN_SPRG3);
449 /* Preserve PSSCR[FAKE_SUSPEND] until we've called kvmppc_save_tm_hv */
450 mtspr(SPRN_PSSCR, host_psscr |
451 (local_paca->kvm_hstate.fake_suspend << PSSCR_FAKE_SUSPEND_LG));
452 mtspr(SPRN_HFSCR, host_hfscr);
453 mtspr(SPRN_CIABR, host_ciabr);
454 mtspr(SPRN_DAWR0, host_dawr0);
455 mtspr(SPRN_DAWRX0, host_dawrx0);
456 if (cpu_has_feature(CPU_FTR_DAWR1)) {
457 mtspr(SPRN_DAWR1, host_dawr1);
458 mtspr(SPRN_DAWRX1, host_dawrx1);
461 if (kvm_is_radix(kvm)) {
463 * Since this is radix, do a eieio; tlbsync; ptesync sequence
464 * in case we interrupted the guest between a tlbie and a
467 asm volatile("eieio; tlbsync; ptesync");
471 * cp_abort is required if the processor supports local copy-paste
472 * to clear the copy buffer that was under control of the guest.
474 if (cpu_has_feature(CPU_FTR_ARCH_31))
475 asm volatile(PPC_CP_ABORT);
477 vc->dpdes = mfspr(SPRN_DPDES);
478 vc->vtb = mfspr(SPRN_VTB);
479 mtspr(SPRN_DPDES, 0);
481 mtspr(SPRN_PCR, PCR_MASK);
483 if (vc->tb_offset_applied) {
484 u64 new_tb = mftb() - vc->tb_offset_applied;
485 mtspr(SPRN_TBU40, new_tb);
487 if ((tb & 0xffffff) < (new_tb & 0xffffff))
488 mtspr(SPRN_TBU40, new_tb + 0x1000000);
489 vc->tb_offset_applied = 0;
492 mtspr(SPRN_HDEC, 0x7fffffff);
494 save_clear_guest_mmu(kvm, vcpu);
495 switch_mmu_to_host(kvm, host_pidr);
496 local_paca->kvm_hstate.in_guest = KVM_GUEST_MODE_NONE;
499 * If we are in real mode, only switch MMU on after the MMU is
500 * switched to host, to avoid the P9_RADIX_PREFETCH_BUG.
508 EXPORT_SYMBOL_GPL(kvmhv_vcpu_entry_p9);