2 * Common prep/pmac/chrp boot and setup code.
5 #include <linux/module.h>
6 #include <linux/string.h>
7 #include <linux/sched.h>
8 #include <linux/init.h>
9 #include <linux/kernel.h>
10 #include <linux/reboot.h>
11 #include <linux/delay.h>
12 #include <linux/initrd.h>
13 #include <linux/tty.h>
14 #include <linux/seq_file.h>
15 #include <linux/root_dev.h>
16 #include <linux/cpu.h>
17 #include <linux/console.h>
18 #include <linux/memblock.h>
19 #include <linux/export.h>
20 #include <linux/nvram.h>
24 #include <asm/processor.h>
25 #include <asm/pgtable.h>
26 #include <asm/setup.h>
29 #include <asm/cputable.h>
30 #include <asm/bootx.h>
31 #include <asm/btext.h>
32 #include <asm/machdep.h>
33 #include <linux/uaccess.h>
34 #include <asm/pmac_feature.h>
35 #include <asm/sections.h>
36 #include <asm/nvram.h>
39 #include <asm/serial.h>
41 #include <asm/code-patching.h>
42 #include <asm/cpu_has_feature.h>
43 #include <asm/asm-prototypes.h>
44 #include <asm/kdump.h>
45 #include <asm/feature-fixups.h>
51 extern void bootx_init(unsigned long r4, unsigned long phys);
54 EXPORT_SYMBOL_GPL(boot_cpuid_phys);
56 int smp_hw_index[NR_CPUS];
57 EXPORT_SYMBOL(smp_hw_index);
59 unsigned long ISA_DMA_THRESHOLD;
60 unsigned int DMA_MODE_READ;
61 unsigned int DMA_MODE_WRITE;
63 EXPORT_SYMBOL(DMA_MODE_READ);
64 EXPORT_SYMBOL(DMA_MODE_WRITE);
67 * This is run before start_kernel(), the kernel has been relocated
68 * and we are running with enough of the MMU enabled to have our
69 * proper kernel virtual addresses
71 * We do the initial parsing of the flat device-tree and prepares
72 * for the MMU to be fully initialized.
74 notrace void __init machine_init(u64 dt_ptr)
76 unsigned int *addr = (unsigned int *)patch_site_addr(&patch__memset_nocache);
79 /* Configure static keys first, now that we're relocated. */
82 /* Enable early debugging if any specified (see udbg.h) */
85 patch_instruction_site(&patch__memcpy_nocache, PPC_INST_NOP);
87 insn = create_cond_branch(addr, branch_target(addr), 0x820000);
88 patch_instruction(addr, insn); /* replace b by bne cr0 */
90 /* Do some early initialization based on the flat device tree */
91 early_init_devtree(__va(dt_ptr));
95 setup_kdump_trampoline();
98 /* Checks "l2cr=xxxx" command-line option */
99 static int __init ppc_setup_l2cr(char *str)
101 if (cpu_has_feature(CPU_FTR_L2CR)) {
102 unsigned long val = simple_strtoul(str, NULL, 0);
103 printk(KERN_INFO "l2cr set to %lx\n", val);
104 _set_L2CR(0); /* force invalidate by disable cache */
105 _set_L2CR(val); /* and enable it */
109 __setup("l2cr=", ppc_setup_l2cr);
111 /* Checks "l3cr=xxxx" command-line option */
112 static int __init ppc_setup_l3cr(char *str)
114 if (cpu_has_feature(CPU_FTR_L3CR)) {
115 unsigned long val = simple_strtoul(str, NULL, 0);
116 printk(KERN_INFO "l3cr set to %lx\n", val);
117 _set_L3CR(val); /* and enable it */
121 __setup("l3cr=", ppc_setup_l3cr);
123 static int __init ppc_init(void)
125 /* clear the progress line */
127 ppc_md.progress(" ", 0xffff);
129 /* call platform init */
130 if (ppc_md.init != NULL) {
135 arch_initcall(ppc_init);
137 static void *__init alloc_stack(void)
139 void *ptr = memblock_alloc(THREAD_SIZE, THREAD_SIZE);
142 panic("cannot allocate %d bytes for stack at %pS\n",
143 THREAD_SIZE, (void *)_RET_IP_);
148 void __init irqstack_early_init(void)
152 /* interrupt stacks must be in lowmem, we get that for free on ppc32
153 * as the memblock is limited to lowmem by default */
154 for_each_possible_cpu(i) {
155 softirq_ctx[i] = alloc_stack();
156 hardirq_ctx[i] = alloc_stack();
160 #if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
161 void __init exc_lvl_early_init(void)
163 unsigned int i, hw_cpu;
165 /* interrupt stacks must be in lowmem, we get that for free on ppc32
166 * as the memblock is limited to lowmem by MEMBLOCK_REAL_LIMIT */
167 for_each_possible_cpu(i) {
169 hw_cpu = get_hard_smp_processor_id(i);
174 critirq_ctx[hw_cpu] = alloc_stack();
176 dbgirq_ctx[hw_cpu] = alloc_stack();
177 mcheckirq_ctx[hw_cpu] = alloc_stack();
183 void __init setup_power_save(void)
185 #ifdef CONFIG_PPC_BOOK3S_32
186 if (cpu_has_feature(CPU_FTR_CAN_DOZE) ||
187 cpu_has_feature(CPU_FTR_CAN_NAP))
188 ppc_md.power_save = ppc6xx_idle;
192 if (cpu_has_feature(CPU_FTR_CAN_DOZE) ||
193 cpu_has_feature(CPU_FTR_CAN_NAP))
194 ppc_md.power_save = e500_idle;
198 __init void initialize_cache_info(void)
201 * Set cache line size based on type of cpu as a default.
202 * Systems with OF can look in the properties on the cpu node(s)
203 * for a possibly more accurate value.
205 dcache_bsize = cur_cpu_spec->dcache_bsize;
206 icache_bsize = cur_cpu_spec->icache_bsize;
208 if (cpu_has_feature(CPU_FTR_UNIFIED_ID_CACHE))
209 ucache_bsize = icache_bsize = dcache_bsize;