1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (C) 1999 Hewlett-Packard (Frank Rowand)
4 * Copyright (C) 1999 Philipp Rumpf <prumpf@tux.org>
5 * Copyright (C) 1999 SuSE GmbH
6 * Copyright (C) 2021 Helge Deller <deller@gmx.de>
9 #ifndef _PARISC_ASSEMBLY_H
10 #define _PARISC_ASSEMBLY_H
14 #define FRAME_SIZE 128
15 #define CALLEE_REG_FRAME_SIZE 144
17 #define ASM_ULONG_INSN .dword
18 #else /* CONFIG_64BIT */
21 #define CALLEE_REG_FRAME_SIZE 128
23 #define ASM_ULONG_INSN .word
26 /* Frame alignment for 32- and 64-bit */
27 #define FRAME_ALIGN 64
29 #define CALLEE_FLOAT_FRAME_SIZE 80
30 #define CALLEE_SAVE_FRAME_SIZE (CALLEE_REG_FRAME_SIZE + CALLEE_FLOAT_FRAME_SIZE)
36 # define PA_ASM_LEVEL 2.0w
38 # define PA_ASM_LEVEL 2.0
43 #define PA_ASM_LEVEL 1.1
46 /* Privilege level field in the rightmost two bits of the IA queues */
50 /* Space register used inside kernel */
67 #define COND(x) * ## x
68 #else /* CONFIG_64BIT */
81 /* the 64-bit pa gnu assembler unfortunately defaults to .level 1.1 or 2.0 so
82 * work around that for now... */
86 #include <asm/asm-offsets.h>
88 #include <asm/types.h>
90 #include <asm/asmregs.h>
94 * We provide two versions of each macro to convert from physical
95 * to virtual and vice versa. The "_r1" versions take one argument
96 * register, but trashes r1 to do the conversion. The other
97 * version takes two arguments: a src and destination register.
98 * However, the source and destination registers can not be
102 .macro tophys grvirt, grphys
103 ldil L%(__PAGE_OFFSET), \grphys
104 sub \grvirt, \grphys, \grphys
107 .macro tovirt grphys, grvirt
108 ldil L%(__PAGE_OFFSET), \grvirt
109 add \grphys, \grvirt, \grvirt
113 ldil L%(__PAGE_OFFSET), %r1
118 ldil L%(__PAGE_OFFSET), %r1
134 zdep \r, 31-(\sa), 32-(\sa), \t
137 /* And the PA 2.0W shift left */
139 depd,z \r, 63-(\sa), 64-(\sa), \t
142 /* Shift Right for 32-bit. Clobbers upper 32-bit on PA2.0. */
144 extru \r, 31-(\sa), 32-(\sa), \t
147 /* pa20w version of shift right */
149 extrd,u \r, 63-(\sa), 64-(\sa), \t
152 /* Extract unsigned for 32- and 64-bit
153 * The extru instruction leaves the most significant 32 bits of the
154 * target register in an undefined state on PA 2.0 systems. */
155 .macro extru_safe r, p, len, t
157 extrd,u \r, 32+(\p), \len, \t
159 extru \r, \p, \len, \t
163 /* The depi instruction leaves the most significant 32 bits of the
164 * target register in an undefined state on PA 2.0 systems. */
165 .macro depi_safe i, p, len, t
167 depdi \i, 32+(\p), \len, \t
169 depi \i, \p, \len, \t
173 /* The depw instruction leaves the most significant 32 bits of the
174 * target register in an undefined state on PA 2.0 systems. */
175 .macro dep_safe i, p, len, t
177 depd \i, 32+(\p), \len, \t
179 depw \i, \p, \len, \t
183 /* load 32-bit 'value' into 'reg' compensating for the ldil
184 * sign-extension when running in wide mode.
185 * WARNING!! neither 'value' nor 'reg' can be expressions
186 * containing '.'!!!! */
187 .macro load32 value, reg
189 ldo R%\value(\reg), \reg
195 ldo R%__gp(%r27), %r27
197 ldil L%$global$, %r27
198 ldo R%$global$(%r27), %r27
202 #define SAVE_SP(r, where) mfsp r, %r1 ! STREG %r1, where
203 #define REST_SP(r, where) LDREG where, %r1 ! mtsp %r1, r
204 #define SAVE_CR(r, where) mfctl r, %r1 ! STREG %r1, where
205 #define REST_CR(r, where) LDREG where, %r1 ! mtctl %r1, r
207 .macro save_general regs
208 STREG %r1, PT_GR1 (\regs)
209 STREG %r2, PT_GR2 (\regs)
210 STREG %r3, PT_GR3 (\regs)
211 STREG %r4, PT_GR4 (\regs)
212 STREG %r5, PT_GR5 (\regs)
213 STREG %r6, PT_GR6 (\regs)
214 STREG %r7, PT_GR7 (\regs)
215 STREG %r8, PT_GR8 (\regs)
216 STREG %r9, PT_GR9 (\regs)
217 STREG %r10, PT_GR10(\regs)
218 STREG %r11, PT_GR11(\regs)
219 STREG %r12, PT_GR12(\regs)
220 STREG %r13, PT_GR13(\regs)
221 STREG %r14, PT_GR14(\regs)
222 STREG %r15, PT_GR15(\regs)
223 STREG %r16, PT_GR16(\regs)
224 STREG %r17, PT_GR17(\regs)
225 STREG %r18, PT_GR18(\regs)
226 STREG %r19, PT_GR19(\regs)
227 STREG %r20, PT_GR20(\regs)
228 STREG %r21, PT_GR21(\regs)
229 STREG %r22, PT_GR22(\regs)
230 STREG %r23, PT_GR23(\regs)
231 STREG %r24, PT_GR24(\regs)
232 STREG %r25, PT_GR25(\regs)
233 /* r26 is saved in get_stack and used to preserve a value across virt_map */
234 STREG %r27, PT_GR27(\regs)
235 STREG %r28, PT_GR28(\regs)
236 /* r29 is saved in get_stack and used to point to saved registers */
237 /* r30 stack pointer saved in get_stack */
238 STREG %r31, PT_GR31(\regs)
241 .macro rest_general regs
242 /* r1 used as a temp in rest_stack and is restored there */
243 LDREG PT_GR2 (\regs), %r2
244 LDREG PT_GR3 (\regs), %r3
245 LDREG PT_GR4 (\regs), %r4
246 LDREG PT_GR5 (\regs), %r5
247 LDREG PT_GR6 (\regs), %r6
248 LDREG PT_GR7 (\regs), %r7
249 LDREG PT_GR8 (\regs), %r8
250 LDREG PT_GR9 (\regs), %r9
251 LDREG PT_GR10(\regs), %r10
252 LDREG PT_GR11(\regs), %r11
253 LDREG PT_GR12(\regs), %r12
254 LDREG PT_GR13(\regs), %r13
255 LDREG PT_GR14(\regs), %r14
256 LDREG PT_GR15(\regs), %r15
257 LDREG PT_GR16(\regs), %r16
258 LDREG PT_GR17(\regs), %r17
259 LDREG PT_GR18(\regs), %r18
260 LDREG PT_GR19(\regs), %r19
261 LDREG PT_GR20(\regs), %r20
262 LDREG PT_GR21(\regs), %r21
263 LDREG PT_GR22(\regs), %r22
264 LDREG PT_GR23(\regs), %r23
265 LDREG PT_GR24(\regs), %r24
266 LDREG PT_GR25(\regs), %r25
267 LDREG PT_GR26(\regs), %r26
268 LDREG PT_GR27(\regs), %r27
269 LDREG PT_GR28(\regs), %r28
270 /* r29 points to register save area, and is restored in rest_stack */
271 /* r30 stack pointer restored in rest_stack */
272 LDREG PT_GR31(\regs), %r31
276 fstd,ma %fr0, 8(\regs)
277 fstd,ma %fr1, 8(\regs)
278 fstd,ma %fr2, 8(\regs)
279 fstd,ma %fr3, 8(\regs)
280 fstd,ma %fr4, 8(\regs)
281 fstd,ma %fr5, 8(\regs)
282 fstd,ma %fr6, 8(\regs)
283 fstd,ma %fr7, 8(\regs)
284 fstd,ma %fr8, 8(\regs)
285 fstd,ma %fr9, 8(\regs)
286 fstd,ma %fr10, 8(\regs)
287 fstd,ma %fr11, 8(\regs)
288 fstd,ma %fr12, 8(\regs)
289 fstd,ma %fr13, 8(\regs)
290 fstd,ma %fr14, 8(\regs)
291 fstd,ma %fr15, 8(\regs)
292 fstd,ma %fr16, 8(\regs)
293 fstd,ma %fr17, 8(\regs)
294 fstd,ma %fr18, 8(\regs)
295 fstd,ma %fr19, 8(\regs)
296 fstd,ma %fr20, 8(\regs)
297 fstd,ma %fr21, 8(\regs)
298 fstd,ma %fr22, 8(\regs)
299 fstd,ma %fr23, 8(\regs)
300 fstd,ma %fr24, 8(\regs)
301 fstd,ma %fr25, 8(\regs)
302 fstd,ma %fr26, 8(\regs)
303 fstd,ma %fr27, 8(\regs)
304 fstd,ma %fr28, 8(\regs)
305 fstd,ma %fr29, 8(\regs)
306 fstd,ma %fr30, 8(\regs)
312 fldd,mb -8(\regs), %fr30
313 fldd,mb -8(\regs), %fr29
314 fldd,mb -8(\regs), %fr28
315 fldd,mb -8(\regs), %fr27
316 fldd,mb -8(\regs), %fr26
317 fldd,mb -8(\regs), %fr25
318 fldd,mb -8(\regs), %fr24
319 fldd,mb -8(\regs), %fr23
320 fldd,mb -8(\regs), %fr22
321 fldd,mb -8(\regs), %fr21
322 fldd,mb -8(\regs), %fr20
323 fldd,mb -8(\regs), %fr19
324 fldd,mb -8(\regs), %fr18
325 fldd,mb -8(\regs), %fr17
326 fldd,mb -8(\regs), %fr16
327 fldd,mb -8(\regs), %fr15
328 fldd,mb -8(\regs), %fr14
329 fldd,mb -8(\regs), %fr13
330 fldd,mb -8(\regs), %fr12
331 fldd,mb -8(\regs), %fr11
332 fldd,mb -8(\regs), %fr10
333 fldd,mb -8(\regs), %fr9
334 fldd,mb -8(\regs), %fr8
335 fldd,mb -8(\regs), %fr7
336 fldd,mb -8(\regs), %fr6
337 fldd,mb -8(\regs), %fr5
338 fldd,mb -8(\regs), %fr4
339 fldd,mb -8(\regs), %fr3
340 fldd,mb -8(\regs), %fr2
341 fldd,mb -8(\regs), %fr1
342 fldd,mb -8(\regs), %fr0
345 .macro callee_save_float
346 fstd,ma %fr12, 8(%r30)
347 fstd,ma %fr13, 8(%r30)
348 fstd,ma %fr14, 8(%r30)
349 fstd,ma %fr15, 8(%r30)
350 fstd,ma %fr16, 8(%r30)
351 fstd,ma %fr17, 8(%r30)
352 fstd,ma %fr18, 8(%r30)
353 fstd,ma %fr19, 8(%r30)
354 fstd,ma %fr20, 8(%r30)
355 fstd,ma %fr21, 8(%r30)
358 .macro callee_rest_float
359 fldd,mb -8(%r30), %fr21
360 fldd,mb -8(%r30), %fr20
361 fldd,mb -8(%r30), %fr19
362 fldd,mb -8(%r30), %fr18
363 fldd,mb -8(%r30), %fr17
364 fldd,mb -8(%r30), %fr16
365 fldd,mb -8(%r30), %fr15
366 fldd,mb -8(%r30), %fr14
367 fldd,mb -8(%r30), %fr13
368 fldd,mb -8(%r30), %fr12
373 std,ma %r3, CALLEE_REG_FRAME_SIZE(%r30)
411 ldd,mb -CALLEE_REG_FRAME_SIZE(%r30), %r3
414 #else /* ! CONFIG_64BIT */
417 stw,ma %r3, CALLEE_REG_FRAME_SIZE(%r30)
455 ldw,mb -CALLEE_REG_FRAME_SIZE(%r30), %r3
457 #endif /* ! CONFIG_64BIT */
459 .macro save_specials regs
461 SAVE_SP (%sr0, PT_SR0 (\regs))
462 SAVE_SP (%sr1, PT_SR1 (\regs))
463 SAVE_SP (%sr2, PT_SR2 (\regs))
464 SAVE_SP (%sr3, PT_SR3 (\regs))
465 SAVE_SP (%sr4, PT_SR4 (\regs))
466 SAVE_SP (%sr5, PT_SR5 (\regs))
467 SAVE_SP (%sr6, PT_SR6 (\regs))
469 SAVE_CR (%cr17, PT_IASQ0(\regs))
471 SAVE_CR (%cr17, PT_IASQ1(\regs))
473 SAVE_CR (%cr18, PT_IAOQ0(\regs))
475 SAVE_CR (%cr18, PT_IAOQ1(\regs))
478 /* cr11 (sar) is a funny one. 5 bits on PA1.1 and 6 bit on PA2.0
479 * For PA2.0 mtsar or mtctl always write 6 bits, but mfctl only
480 * reads 5 bits. Use mfctl,w to read all six bits. Otherwise
481 * we lose the 6th bit on a save/restore over interrupt.
484 STREG %r1, PT_SAR (\regs)
486 SAVE_CR (%cr11, PT_SAR (\regs))
488 SAVE_CR (%cr19, PT_IIR (\regs))
491 * Code immediately following this macro (in intr_save) relies
492 * on r8 containing ipsw.
495 STREG %r8, PT_PSW(\regs)
498 .macro rest_specials regs
500 REST_SP (%sr0, PT_SR0 (\regs))
501 REST_SP (%sr1, PT_SR1 (\regs))
502 REST_SP (%sr2, PT_SR2 (\regs))
503 REST_SP (%sr3, PT_SR3 (\regs))
504 REST_SP (%sr4, PT_SR4 (\regs))
505 REST_SP (%sr5, PT_SR5 (\regs))
506 REST_SP (%sr6, PT_SR6 (\regs))
507 REST_SP (%sr7, PT_SR7 (\regs))
509 REST_CR (%cr17, PT_IASQ0(\regs))
510 REST_CR (%cr17, PT_IASQ1(\regs))
512 REST_CR (%cr18, PT_IAOQ0(\regs))
513 REST_CR (%cr18, PT_IAOQ1(\regs))
515 REST_CR (%cr11, PT_SAR (\regs))
517 REST_CR (%cr22, PT_PSW (\regs))
521 /* First step to create a "relied upon translation"
522 * See PA 2.0 Arch. page F-4 and F-5.
524 * The ssm was originally necessary due to a "PCxT bug".
525 * But someone decided it needed to be added to the architecture
526 * and this "feature" went into rev3 of PA-RISC 1.1 Arch Manual.
527 * It's been carried forward into PA 2.0 Arch as well. :^(
529 * "ssm 0,%r0" is a NOP with side effects (prefetch barrier).
530 * rsm/ssm prevents the ifetch unit from speculatively fetching
531 * instructions past this line in the code stream.
532 * PA 2.0 processor will single step all insn in the same QUAD (4 insn).
545 /* Switch to virtual mapping, trashing only %r1 */
548 rsm PSW_SM_I, %r0 /* barrier for "Relied upon Translation */
553 load32 KERNEL_PSW, %r1
555 rsm PSW_SM_QUIET,%r0 /* second "heavy weight" ctl op */
556 mtctl %r0, %cr17 /* Clear IIASQ tail */
557 mtctl %r0, %cr17 /* Clear IIASQ head */
560 mtctl %r1, %cr18 /* Set IIAOQ tail */
562 mtctl %r1, %cr18 /* Set IIAOQ head */
570 * ASM_EXCEPTIONTABLE_ENTRY
572 * Creates an exception table entry.
573 * Do not convert to a assembler macro. This won't work.
575 #define ASM_EXCEPTIONTABLE_ENTRY(fault_addr, except_addr) \
576 .section __ex_table,"aw" ! \
578 .word (fault_addr - .), (except_addr - .) ! \
582 #endif /* __ASSEMBLY__ */