2 * linux/arch/mps/tx4938/common/irq.c
4 * Common tx4938 irq handler
5 * Copyright (C) 2000-2001 Toshiba Corporation
7 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
12 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
14 #include <linux/errno.h>
15 #include <linux/init.h>
16 #include <linux/kernel_stat.h>
17 #include <linux/module.h>
18 #include <linux/signal.h>
19 #include <linux/sched.h>
20 #include <linux/types.h>
21 #include <linux/interrupt.h>
22 #include <linux/ioport.h>
23 #include <linux/timex.h>
24 #include <linux/slab.h>
25 #include <linux/random.h>
26 #include <linux/irq.h>
27 #include <asm/bitops.h>
28 #include <asm/bootinfo.h>
31 #include <asm/mipsregs.h>
32 #include <asm/system.h>
33 #include <asm/tx4938/rbtx4938.h>
35 /**********************************************************************************/
36 /* Forwad definitions for all pic's */
37 /**********************************************************************************/
39 static unsigned int tx4938_irq_cp0_startup(unsigned int irq);
40 static void tx4938_irq_cp0_shutdown(unsigned int irq);
41 static void tx4938_irq_cp0_enable(unsigned int irq);
42 static void tx4938_irq_cp0_disable(unsigned int irq);
43 static void tx4938_irq_cp0_mask_and_ack(unsigned int irq);
44 static void tx4938_irq_cp0_end(unsigned int irq);
46 static unsigned int tx4938_irq_pic_startup(unsigned int irq);
47 static void tx4938_irq_pic_shutdown(unsigned int irq);
48 static void tx4938_irq_pic_enable(unsigned int irq);
49 static void tx4938_irq_pic_disable(unsigned int irq);
50 static void tx4938_irq_pic_mask_and_ack(unsigned int irq);
51 static void tx4938_irq_pic_end(unsigned int irq);
53 /**********************************************************************************/
54 /* Kernel structs for all pic's */
55 /**********************************************************************************/
56 DEFINE_SPINLOCK(tx4938_cp0_lock);
57 DEFINE_SPINLOCK(tx4938_pic_lock);
59 #define TX4938_CP0_NAME "TX4938-CP0"
60 static struct irq_chip tx4938_irq_cp0_type = {
61 .typename = TX4938_CP0_NAME,
62 .startup = tx4938_irq_cp0_startup,
63 .shutdown = tx4938_irq_cp0_shutdown,
64 .enable = tx4938_irq_cp0_enable,
65 .disable = tx4938_irq_cp0_disable,
66 .ack = tx4938_irq_cp0_mask_and_ack,
67 .end = tx4938_irq_cp0_end,
71 #define TX4938_PIC_NAME "TX4938-PIC"
72 static struct irq_chip tx4938_irq_pic_type = {
73 .typename = TX4938_PIC_NAME,
74 .startup = tx4938_irq_pic_startup,
75 .shutdown = tx4938_irq_pic_shutdown,
76 .enable = tx4938_irq_pic_enable,
77 .disable = tx4938_irq_pic_disable,
78 .ack = tx4938_irq_pic_mask_and_ack,
79 .end = tx4938_irq_pic_end,
83 static struct irqaction tx4938_irq_pic_action = {
86 .mask = CPU_MASK_NONE,
87 .name = TX4938_PIC_NAME
90 /**********************************************************************************/
91 /* Functions for cp0 */
92 /**********************************************************************************/
94 #define tx4938_irq_cp0_mask(irq) ( 1 << ( irq-TX4938_IRQ_CP0_BEG+8 ) )
97 tx4938_irq_cp0_init(void)
101 for (i = TX4938_IRQ_CP0_BEG; i <= TX4938_IRQ_CP0_END; i++) {
102 irq_desc[i].status = IRQ_DISABLED;
103 irq_desc[i].action = 0;
104 irq_desc[i].depth = 1;
105 irq_desc[i].chip = &tx4938_irq_cp0_type;
112 tx4938_irq_cp0_startup(unsigned int irq)
114 tx4938_irq_cp0_enable(irq);
120 tx4938_irq_cp0_shutdown(unsigned int irq)
122 tx4938_irq_cp0_disable(irq);
126 tx4938_irq_cp0_enable(unsigned int irq)
130 spin_lock_irqsave(&tx4938_cp0_lock, flags);
132 set_c0_status(tx4938_irq_cp0_mask(irq));
134 spin_unlock_irqrestore(&tx4938_cp0_lock, flags);
138 tx4938_irq_cp0_disable(unsigned int irq)
142 spin_lock_irqsave(&tx4938_cp0_lock, flags);
144 clear_c0_status(tx4938_irq_cp0_mask(irq));
146 spin_unlock_irqrestore(&tx4938_cp0_lock, flags);
152 tx4938_irq_cp0_mask_and_ack(unsigned int irq)
154 tx4938_irq_cp0_disable(irq);
160 tx4938_irq_cp0_end(unsigned int irq)
162 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
163 tx4938_irq_cp0_enable(irq);
169 /**********************************************************************************/
170 /* Functions for pic */
171 /**********************************************************************************/
174 tx4938_irq_pic_addr(int irq)
176 /* MVMCP -- need to formulize this */
177 irq -= TX4938_IRQ_PIC_BEG;
184 return (TX4938_MKA(TX4938_IRC_IRLVL0));
190 return (TX4938_MKA(TX4938_IRC_IRLVL1));
196 return (TX4938_MKA(TX4938_IRC_IRLVL2));
202 return (TX4938_MKA(TX4938_IRC_IRLVL3));
208 return (TX4938_MKA(TX4938_IRC_IRLVL4));
214 return (TX4938_MKA(TX4938_IRC_IRLVL5));
220 return (TX4938_MKA(TX4938_IRC_IRLVL6));
226 return (TX4938_MKA(TX4938_IRC_IRLVL7));
234 tx4938_irq_pic_mask(int irq)
236 /* MVMCP -- need to formulize this */
237 irq -= TX4938_IRQ_PIC_BEG;
285 tx4938_irq_pic_modify(unsigned pic_reg, unsigned clr_bits, unsigned set_bits)
287 unsigned long val = 0;
289 val = TX4938_RD(pic_reg);
292 TX4938_WR(pic_reg, val);
300 tx4938_irq_pic_init(void)
305 for (i = TX4938_IRQ_PIC_BEG; i <= TX4938_IRQ_PIC_END; i++) {
306 irq_desc[i].status = IRQ_DISABLED;
307 irq_desc[i].action = 0;
308 irq_desc[i].depth = 2;
309 irq_desc[i].chip = &tx4938_irq_pic_type;
312 setup_irq(TX4938_IRQ_NEST_PIC_ON_CP0, &tx4938_irq_pic_action);
314 spin_lock_irqsave(&tx4938_pic_lock, flags);
316 TX4938_WR(0xff1ff640, 0x6); /* irq level mask -- only accept hightest */
317 TX4938_WR(0xff1ff600, TX4938_RD(0xff1ff600) | 0x1); /* irq enable */
319 spin_unlock_irqrestore(&tx4938_pic_lock, flags);
325 tx4938_irq_pic_startup(unsigned int irq)
327 tx4938_irq_pic_enable(irq);
333 tx4938_irq_pic_shutdown(unsigned int irq)
335 tx4938_irq_pic_disable(irq);
341 tx4938_irq_pic_enable(unsigned int irq)
345 spin_lock_irqsave(&tx4938_pic_lock, flags);
347 tx4938_irq_pic_modify(tx4938_irq_pic_addr(irq), 0,
348 tx4938_irq_pic_mask(irq));
350 spin_unlock_irqrestore(&tx4938_pic_lock, flags);
356 tx4938_irq_pic_disable(unsigned int irq)
360 spin_lock_irqsave(&tx4938_pic_lock, flags);
362 tx4938_irq_pic_modify(tx4938_irq_pic_addr(irq),
363 tx4938_irq_pic_mask(irq), 0);
365 spin_unlock_irqrestore(&tx4938_pic_lock, flags);
371 tx4938_irq_pic_mask_and_ack(unsigned int irq)
373 tx4938_irq_pic_disable(irq);
379 tx4938_irq_pic_end(unsigned int irq)
381 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
382 tx4938_irq_pic_enable(irq);
388 /**********************************************************************************/
389 /* Main init functions */
390 /**********************************************************************************/
393 tx4938_irq_init(void)
395 tx4938_irq_cp0_init();
396 tx4938_irq_pic_init();
402 tx4938_irq_nested(void)
407 level2 = TX4938_RD(0xff1ff6a0);
408 if ((level2 & 0x10000) == 0) {
410 sw_irq = TX4938_IRQ_PIC_BEG + level2;
413 extern int toshiba_rbtx4938_irq_nested(int sw_irq);
414 sw_irq = toshiba_rbtx4938_irq_nested(sw_irq);
423 asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
425 unsigned int pending = read_c0_cause() & read_c0_status();
427 if (pending & STATUSF_IP7)
428 do_IRQ(TX4938_IRQ_CPU_TIMER, regs);
429 else if (pending & STATUSF_IP2) {
430 int irq = tx4938_irq_nested();
434 spurious_interrupt(regs);
435 } else if (pending & STATUSF_IP1)
436 do_IRQ(TX4938_IRQ_USER1, regs);
437 else if (pending & STATUSF_IP0)
438 do_IRQ(TX4938_IRQ_USER0, regs);