1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __iop_scrc_in_defs_h
3 #define __iop_scrc_in_defs_h
6 * This file is autogenerated from
7 * file: ../../inst/io_proc/rtl/iop_scrc_in.r
8 * id: iop_scrc_in.r,v 1.10 2005/02/16 09:13:58 niklaspa Exp
9 * last modfied: Mon Apr 11 16:08:46 2005
11 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_scrc_in_defs.h ../../inst/io_proc/rtl/iop_scrc_in.r
12 * id: $Id: iop_scrc_in_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
13 * Any changes here will be lost.
15 * -*- buffer-read-only: t -*-
17 /* Main access macros */
19 #define REG_RD( scope, inst, reg ) \
20 REG_READ( reg_##scope##_##reg, \
21 (inst) + REG_RD_ADDR_##scope##_##reg )
25 #define REG_WR( scope, inst, reg, val ) \
26 REG_WRITE( reg_##scope##_##reg, \
27 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
31 #define REG_RD_VECT( scope, inst, reg, index ) \
32 REG_READ( reg_##scope##_##reg, \
33 (inst) + REG_RD_ADDR_##scope##_##reg + \
34 (index) * STRIDE_##scope##_##reg )
38 #define REG_WR_VECT( scope, inst, reg, index, val ) \
39 REG_WRITE( reg_##scope##_##reg, \
40 (inst) + REG_WR_ADDR_##scope##_##reg + \
41 (index) * STRIDE_##scope##_##reg, (val) )
45 #define REG_RD_INT( scope, inst, reg ) \
46 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
50 #define REG_WR_INT( scope, inst, reg, val ) \
51 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
54 #ifndef REG_RD_INT_VECT
55 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
56 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
57 (index) * STRIDE_##scope##_##reg )
60 #ifndef REG_WR_INT_VECT
61 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
62 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
63 (index) * STRIDE_##scope##_##reg, (val) )
67 #define REG_TYPE_CONV( type, orgtype, val ) \
68 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
72 #define reg_page_size 8192
76 #define REG_ADDR( scope, inst, reg ) \
77 ( (inst) + REG_RD_ADDR_##scope##_##reg )
81 #define REG_ADDR_VECT( scope, inst, reg, index ) \
82 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
83 (index) * STRIDE_##scope##_##reg )
86 /* C-code for register scope iop_scrc_in */
88 /* Register rw_cfg, scope iop_scrc_in, type rw */
90 unsigned int trig : 2;
91 unsigned int dummy1 : 30;
92 } reg_iop_scrc_in_rw_cfg;
93 #define REG_RD_ADDR_iop_scrc_in_rw_cfg 0
94 #define REG_WR_ADDR_iop_scrc_in_rw_cfg 0
96 /* Register rw_ctrl, scope iop_scrc_in, type rw */
98 unsigned int dif_in_en : 1;
99 unsigned int dummy1 : 31;
100 } reg_iop_scrc_in_rw_ctrl;
101 #define REG_RD_ADDR_iop_scrc_in_rw_ctrl 4
102 #define REG_WR_ADDR_iop_scrc_in_rw_ctrl 4
104 /* Register r_stat, scope iop_scrc_in, type r */
106 unsigned int err : 1;
107 unsigned int dummy1 : 31;
108 } reg_iop_scrc_in_r_stat;
109 #define REG_RD_ADDR_iop_scrc_in_r_stat 8
111 /* Register rw_init_crc, scope iop_scrc_in, type rw */
112 typedef unsigned int reg_iop_scrc_in_rw_init_crc;
113 #define REG_RD_ADDR_iop_scrc_in_rw_init_crc 12
114 #define REG_WR_ADDR_iop_scrc_in_rw_init_crc 12
116 /* Register rs_computed_crc, scope iop_scrc_in, type rs */
117 typedef unsigned int reg_iop_scrc_in_rs_computed_crc;
118 #define REG_RD_ADDR_iop_scrc_in_rs_computed_crc 16
120 /* Register r_computed_crc, scope iop_scrc_in, type r */
121 typedef unsigned int reg_iop_scrc_in_r_computed_crc;
122 #define REG_RD_ADDR_iop_scrc_in_r_computed_crc 20
124 /* Register rw_crc, scope iop_scrc_in, type rw */
125 typedef unsigned int reg_iop_scrc_in_rw_crc;
126 #define REG_RD_ADDR_iop_scrc_in_rw_crc 24
127 #define REG_WR_ADDR_iop_scrc_in_rw_crc 24
129 /* Register rw_correct_crc, scope iop_scrc_in, type rw */
130 typedef unsigned int reg_iop_scrc_in_rw_correct_crc;
131 #define REG_RD_ADDR_iop_scrc_in_rw_correct_crc 28
132 #define REG_WR_ADDR_iop_scrc_in_rw_correct_crc 28
134 /* Register rw_wr1bit, scope iop_scrc_in, type rw */
136 unsigned int data : 2;
137 unsigned int last : 2;
138 unsigned int dummy1 : 28;
139 } reg_iop_scrc_in_rw_wr1bit;
140 #define REG_RD_ADDR_iop_scrc_in_rw_wr1bit 32
141 #define REG_WR_ADDR_iop_scrc_in_rw_wr1bit 32
146 regk_iop_scrc_in_dif_in = 0x00000002,
147 regk_iop_scrc_in_hi = 0x00000000,
148 regk_iop_scrc_in_neg = 0x00000002,
149 regk_iop_scrc_in_no = 0x00000000,
150 regk_iop_scrc_in_pos = 0x00000001,
151 regk_iop_scrc_in_pos_neg = 0x00000003,
152 regk_iop_scrc_in_r_computed_crc_default = 0x00000000,
153 regk_iop_scrc_in_rs_computed_crc_default = 0x00000000,
154 regk_iop_scrc_in_rw_cfg_default = 0x00000000,
155 regk_iop_scrc_in_rw_ctrl_default = 0x00000000,
156 regk_iop_scrc_in_rw_init_crc_default = 0x00000000,
157 regk_iop_scrc_in_set0 = 0x00000000,
158 regk_iop_scrc_in_set1 = 0x00000001,
159 regk_iop_scrc_in_yes = 0x00000001
161 #endif /* __iop_scrc_in_defs_h */