arch/blackfin/include/asm/dma.h

   1 /*
   2  * dma.h - Blackfin DMA defines/structures/etc...
   3  *
   4  * Copyright 2004-2008 Analog Devices Inc.
   5  * Licensed under the GPL-2 or later.
   6  */
   7
   8 #ifndef _BLACKFIN_DMA_H_
   9 #define _BLACKFIN_DMA_H_
  10
  11 #include <linux/interrupt.h>
  12 #include <mach/dma.h>
  13 #include <asm/atomic.h>
  14 #include <asm/blackfin.h>
  15 #include <asm/page.h>
  16
  17 #define MAX_DMA_ADDRESS PAGE_OFFSET
  18
  19 /*****************************************************************************
  20 *        Generic DMA  Declarations
  21 *
  22 ****************************************************************************/
  23
  24 /*-------------------------
  25  * config reg bits value
  26  *-------------------------*/
  27 #define DATA_SIZE_8             0
  28 #define DATA_SIZE_16            1
  29 #define DATA_SIZE_32            2
  30
  31 #define DMA_FLOW_STOP           0
  32 #define DMA_FLOW_AUTO           1
  33 #define DMA_FLOW_ARRAY          4
  34 #define DMA_FLOW_SMALL          6
  35 #define DMA_FLOW_LARGE          7
  36
  37 #define DIMENSION_LINEAR    0
  38 #define DIMENSION_2D           1
  39
  40 #define DIR_READ     0
  41 #define DIR_WRITE    1
  42
  43 #define INTR_DISABLE   0
  44 #define INTR_ON_BUF    2
  45 #define INTR_ON_ROW    3
  46
  47 #define DMA_NOSYNC_KEEP_DMA_BUF 0
  48 #define DMA_SYNC_RESTART        1
  49
  50 struct dmasg {
  51         void *next_desc_addr;
  52         unsigned long start_addr;
  53         unsigned short cfg;
  54         unsigned short x_count;
  55         short x_modify;
  56         unsigned short y_count;
  57         short y_modify;
  58 } __attribute__((packed));
  59
  60 struct dma_register {
  61         void *next_desc_ptr;    /* DMA Next Descriptor Pointer register */
  62         unsigned long start_addr;       /* DMA Start address  register */
  63
  64         unsigned short cfg;     /* DMA Configuration register */
  65         unsigned short dummy1;  /* DMA Configuration register */
  66
  67         unsigned long reserved;
  68
  69         unsigned short x_count; /* DMA x_count register */
  70         unsigned short dummy2;
  71
  72         short x_modify; /* DMA x_modify register */
  73         unsigned short dummy3;
  74
  75         unsigned short y_count; /* DMA y_count register */
  76         unsigned short dummy4;
  77
  78         short y_modify; /* DMA y_modify register */
  79         unsigned short dummy5;
  80
  81         void *curr_desc_ptr;    /* DMA Current Descriptor Pointer
  82                                            register */
  83         unsigned long curr_addr_ptr;    /* DMA Current Address Pointer
  84                                                    register */
  85         unsigned short irq_status;      /* DMA irq status register */
  86         unsigned short dummy6;
  87
  88         unsigned short peripheral_map;  /* DMA peripheral map register */
  89         unsigned short dummy7;
  90
  91         unsigned short curr_x_count;    /* DMA Current x-count register */
  92         unsigned short dummy8;
  93
  94         unsigned long reserved2;
  95
  96         unsigned short curr_y_count;    /* DMA Current y-count register */
  97         unsigned short dummy9;
  98
  99         unsigned long reserved3;
 100
 101 };
 102
 103 struct dma_channel {
 104         const char *device_id;
 105         atomic_t chan_status;
 106         volatile struct dma_register *regs;
 107         struct dmasg *sg;               /* large mode descriptor */
 108         unsigned int irq;
 109         void *data;
 110 #ifdef CONFIG_PM
 111         unsigned short saved_peripheral_map;
 112 #endif
 113 };
 114
 115 #ifdef CONFIG_PM
 116 int blackfin_dma_suspend(void);
 117 void blackfin_dma_resume(void);
 118 #endif
 119
 120 /*******************************************************************************
 121 *       DMA API's
 122 *******************************************************************************/
 123 extern struct dma_channel dma_ch[MAX_DMA_CHANNELS];
 124 extern struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS];
 125 extern int channel2irq(unsigned int channel);
 126
 127 static inline void set_dma_start_addr(unsigned int channel, unsigned long addr)
 128 {
 129         dma_ch[channel].regs->start_addr = addr;
 130 }
 131 static inline void set_dma_next_desc_addr(unsigned int channel, void *addr)
 132 {
 133         dma_ch[channel].regs->next_desc_ptr = addr;
 134 }
 135 static inline void set_dma_curr_desc_addr(unsigned int channel, void *addr)
 136 {
 137         dma_ch[channel].regs->curr_desc_ptr = addr;
 138 }
 139 static inline void set_dma_x_count(unsigned int channel, unsigned short x_count)
 140 {
 141         dma_ch[channel].regs->x_count = x_count;
 142 }
 143 static inline void set_dma_y_count(unsigned int channel, unsigned short y_count)
 144 {
 145         dma_ch[channel].regs->y_count = y_count;
 146 }
 147 static inline void set_dma_x_modify(unsigned int channel, short x_modify)
 148 {
 149         dma_ch[channel].regs->x_modify = x_modify;
 150 }
 151 static inline void set_dma_y_modify(unsigned int channel, short y_modify)
 152 {
 153         dma_ch[channel].regs->y_modify = y_modify;
 154 }
 155 static inline void set_dma_config(unsigned int channel, unsigned short config)
 156 {
 157         dma_ch[channel].regs->cfg = config;
 158 }
 159 static inline void set_dma_curr_addr(unsigned int channel, unsigned long addr)
 160 {
 161         dma_ch[channel].regs->curr_addr_ptr = addr;
 162 }
 163
 164 static inline unsigned short
 165 set_bfin_dma_config(char direction, char flow_mode,
 166                     char intr_mode, char dma_mode, char width, char syncmode)
 167 {
 168         return (direction << 1) | (width << 2) | (dma_mode << 4) |
 169                 (intr_mode << 6) | (flow_mode << 12) | (syncmode << 5);
 170 }
 171
 172 static inline unsigned short get_dma_curr_irqstat(unsigned int channel)
 173 {
 174         return dma_ch[channel].regs->irq_status;
 175 }
 176 static inline unsigned short get_dma_curr_xcount(unsigned int channel)
 177 {
 178         return dma_ch[channel].regs->curr_x_count;
 179 }
 180 static inline unsigned short get_dma_curr_ycount(unsigned int channel)
 181 {
 182         return dma_ch[channel].regs->curr_y_count;
 183 }
 184 static inline void *get_dma_next_desc_ptr(unsigned int channel)
 185 {
 186         return dma_ch[channel].regs->next_desc_ptr;
 187 }
 188 static inline void *get_dma_curr_desc_ptr(unsigned int channel)
 189 {
 190         return dma_ch[channel].regs->curr_desc_ptr;
 191 }
 192 static inline unsigned short get_dma_config(unsigned int channel)
 193 {
 194         return dma_ch[channel].regs->cfg;
 195 }
 196 static inline unsigned long get_dma_curr_addr(unsigned int channel)
 197 {
 198         return dma_ch[channel].regs->curr_addr_ptr;
 199 }
 200
 201 static inline void set_dma_sg(unsigned int channel, struct dmasg *sg, int ndsize)
 202 {
 203         /* Make sure the internal data buffers in the core are drained
 204          * so that the DMA descriptors are completely written when the
 205          * DMA engine goes to fetch them below.
 206          */
 207         SSYNC();
 208
 209         dma_ch[channel].regs->next_desc_ptr = sg;
 210         dma_ch[channel].regs->cfg =
 211                 (dma_ch[channel].regs->cfg & ~(0xf << 8)) |
 212                 ((ndsize & 0xf) << 8);
 213 }
 214
 215 static inline int dma_channel_active(unsigned int channel)
 216 {
 217         return atomic_read(&dma_ch[channel].chan_status);
 218 }
 219
 220 static inline void disable_dma(unsigned int channel)
 221 {
 222         dma_ch[channel].regs->cfg &= ~DMAEN;
 223         SSYNC();
 224 }
 225 static inline void enable_dma(unsigned int channel)
 226 {
 227         dma_ch[channel].regs->curr_x_count = 0;
 228         dma_ch[channel].regs->curr_y_count = 0;
 229         dma_ch[channel].regs->cfg |= DMAEN;
 230 }
 231 void free_dma(unsigned int channel);
 232 int request_dma(unsigned int channel, const char *device_id);
 233 int set_dma_callback(unsigned int channel, irq_handler_t callback, void *data);
 234
 235 static inline void dma_disable_irq(unsigned int channel)
 236 {
 237         disable_irq(dma_ch[channel].irq);
 238 }
 239 static inline void dma_enable_irq(unsigned int channel)
 240 {
 241         enable_irq(dma_ch[channel].irq);
 242 }
 243 static inline void clear_dma_irqstat(unsigned int channel)
 244 {
 245         dma_ch[channel].regs->irq_status = DMA_DONE | DMA_ERR;
 246 }
 247
 248 void *dma_memcpy(void *dest, const void *src, size_t count);
 249 void *safe_dma_memcpy(void *dest, const void *src, size_t count);
 250 void blackfin_dma_early_init(void);
 251 void early_dma_memcpy(void *dest, const void *src, size_t count);
 252 void early_dma_memcpy_done(void);
 253
 254 #endif