1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2012,2013 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
6 * Derived from arch/arm/include/kvm_emulate.h
7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
8 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
11 #ifndef __ARM64_KVM_EMULATE_H__
12 #define __ARM64_KVM_EMULATE_H__
14 #include <linux/kvm_host.h>
16 #include <asm/debug-monitors.h>
18 #include <asm/kvm_arm.h>
19 #include <asm/kvm_hyp.h>
20 #include <asm/kvm_nested.h>
21 #include <asm/ptrace.h>
22 #include <asm/cputype.h>
25 #define CURRENT_EL_SP_EL0_VECTOR 0x0
26 #define CURRENT_EL_SP_ELx_VECTOR 0x200
27 #define LOWER_EL_AArch64_VECTOR 0x400
28 #define LOWER_EL_AArch32_VECTOR 0x600
32 except_type_irq = 0x80,
33 except_type_fiq = 0x100,
34 except_type_serror = 0x180,
37 #define kvm_exception_type_names \
38 { except_type_sync, "SYNC" }, \
39 { except_type_irq, "IRQ" }, \
40 { except_type_fiq, "FIQ" }, \
41 { except_type_serror, "SERROR" }
43 bool kvm_condition_valid32(const struct kvm_vcpu *vcpu);
44 void kvm_skip_instr32(struct kvm_vcpu *vcpu);
46 void kvm_inject_undefined(struct kvm_vcpu *vcpu);
47 void kvm_inject_vabt(struct kvm_vcpu *vcpu);
48 void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr);
49 void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr);
50 void kvm_inject_size_fault(struct kvm_vcpu *vcpu);
52 void kvm_vcpu_wfi(struct kvm_vcpu *vcpu);
54 void kvm_emulate_nested_eret(struct kvm_vcpu *vcpu);
55 int kvm_inject_nested_sync(struct kvm_vcpu *vcpu, u64 esr_el2);
56 int kvm_inject_nested_irq(struct kvm_vcpu *vcpu);
58 #if defined(__KVM_VHE_HYPERVISOR__) || defined(__KVM_NVHE_HYPERVISOR__)
59 static __always_inline bool vcpu_el1_is_32bit(struct kvm_vcpu *vcpu)
61 return !(vcpu->arch.hcr_el2 & HCR_RW);
64 static __always_inline bool vcpu_el1_is_32bit(struct kvm_vcpu *vcpu)
66 return vcpu_has_feature(vcpu, KVM_ARM_VCPU_EL1_32BIT);
70 static inline void vcpu_reset_hcr(struct kvm_vcpu *vcpu)
72 vcpu->arch.hcr_el2 = HCR_GUEST_FLAGS;
73 if (has_vhe() || has_hvhe())
74 vcpu->arch.hcr_el2 |= HCR_E2H;
75 if (cpus_have_final_cap(ARM64_HAS_RAS_EXTN)) {
76 /* route synchronous external abort exceptions to EL2 */
77 vcpu->arch.hcr_el2 |= HCR_TEA;
78 /* trap error record accesses */
79 vcpu->arch.hcr_el2 |= HCR_TERR;
82 if (cpus_have_final_cap(ARM64_HAS_STAGE2_FWB)) {
83 vcpu->arch.hcr_el2 |= HCR_FWB;
86 * For non-FWB CPUs, we trap VM ops (HCR_EL2.TVM) until M+C
87 * get set in SCTLR_EL1 such that we can detect when the guest
88 * MMU gets turned on and do the necessary cache maintenance
91 vcpu->arch.hcr_el2 |= HCR_TVM;
94 if (cpus_have_final_cap(ARM64_HAS_EVT) &&
95 !cpus_have_final_cap(ARM64_MISMATCHED_CACHE_TYPE))
96 vcpu->arch.hcr_el2 |= HCR_TID4;
98 vcpu->arch.hcr_el2 |= HCR_TID2;
100 if (vcpu_el1_is_32bit(vcpu))
101 vcpu->arch.hcr_el2 &= ~HCR_RW;
103 if (kvm_has_mte(vcpu->kvm))
104 vcpu->arch.hcr_el2 |= HCR_ATA;
107 static inline unsigned long *vcpu_hcr(struct kvm_vcpu *vcpu)
109 return (unsigned long *)&vcpu->arch.hcr_el2;
112 static inline void vcpu_clear_wfx_traps(struct kvm_vcpu *vcpu)
114 vcpu->arch.hcr_el2 &= ~HCR_TWE;
115 if (atomic_read(&vcpu->arch.vgic_cpu.vgic_v3.its_vpe.vlpi_count) ||
116 vcpu->kvm->arch.vgic.nassgireq)
117 vcpu->arch.hcr_el2 &= ~HCR_TWI;
119 vcpu->arch.hcr_el2 |= HCR_TWI;
122 static inline void vcpu_set_wfx_traps(struct kvm_vcpu *vcpu)
124 vcpu->arch.hcr_el2 |= HCR_TWE;
125 vcpu->arch.hcr_el2 |= HCR_TWI;
128 static inline void vcpu_ptrauth_enable(struct kvm_vcpu *vcpu)
130 vcpu->arch.hcr_el2 |= (HCR_API | HCR_APK);
133 static inline void vcpu_ptrauth_disable(struct kvm_vcpu *vcpu)
135 vcpu->arch.hcr_el2 &= ~(HCR_API | HCR_APK);
138 static inline unsigned long vcpu_get_vsesr(struct kvm_vcpu *vcpu)
140 return vcpu->arch.vsesr_el2;
143 static inline void vcpu_set_vsesr(struct kvm_vcpu *vcpu, u64 vsesr)
145 vcpu->arch.vsesr_el2 = vsesr;
148 static __always_inline unsigned long *vcpu_pc(const struct kvm_vcpu *vcpu)
150 return (unsigned long *)&vcpu_gp_regs(vcpu)->pc;
153 static __always_inline unsigned long *vcpu_cpsr(const struct kvm_vcpu *vcpu)
155 return (unsigned long *)&vcpu_gp_regs(vcpu)->pstate;
158 static __always_inline bool vcpu_mode_is_32bit(const struct kvm_vcpu *vcpu)
160 return !!(*vcpu_cpsr(vcpu) & PSR_MODE32_BIT);
163 static __always_inline bool kvm_condition_valid(const struct kvm_vcpu *vcpu)
165 if (vcpu_mode_is_32bit(vcpu))
166 return kvm_condition_valid32(vcpu);
171 static inline void vcpu_set_thumb(struct kvm_vcpu *vcpu)
173 *vcpu_cpsr(vcpu) |= PSR_AA32_T_BIT;
177 * vcpu_get_reg and vcpu_set_reg should always be passed a register number
178 * coming from a read of ESR_EL2. Otherwise, it may give the wrong result on
179 * AArch32 with banked registers.
181 static __always_inline unsigned long vcpu_get_reg(const struct kvm_vcpu *vcpu,
184 return (reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs[reg_num];
187 static __always_inline void vcpu_set_reg(struct kvm_vcpu *vcpu, u8 reg_num,
191 vcpu_gp_regs(vcpu)->regs[reg_num] = val;
194 static inline bool vcpu_is_el2_ctxt(const struct kvm_cpu_context *ctxt)
196 switch (ctxt->regs.pstate & (PSR_MODE32_BIT | PSR_MODE_MASK)) {
205 static inline bool vcpu_is_el2(const struct kvm_vcpu *vcpu)
207 return vcpu_is_el2_ctxt(&vcpu->arch.ctxt);
210 static inline bool __vcpu_el2_e2h_is_set(const struct kvm_cpu_context *ctxt)
212 return (!cpus_have_final_cap(ARM64_HAS_HCR_NV1) ||
213 (ctxt_sys_reg(ctxt, HCR_EL2) & HCR_E2H));
216 static inline bool vcpu_el2_e2h_is_set(const struct kvm_vcpu *vcpu)
218 return __vcpu_el2_e2h_is_set(&vcpu->arch.ctxt);
221 static inline bool __vcpu_el2_tge_is_set(const struct kvm_cpu_context *ctxt)
223 return ctxt_sys_reg(ctxt, HCR_EL2) & HCR_TGE;
226 static inline bool vcpu_el2_tge_is_set(const struct kvm_vcpu *vcpu)
228 return __vcpu_el2_tge_is_set(&vcpu->arch.ctxt);
231 static inline bool __is_hyp_ctxt(const struct kvm_cpu_context *ctxt)
234 * We are in a hypervisor context if the vcpu mode is EL2 or
235 * E2H and TGE bits are set. The latter means we are in the user space
236 * of the VHE kernel. ARMv8.1 ARM describes this as 'InHost'
238 * Note that the HCR_EL2.{E2H,TGE}={0,1} isn't really handled in the
239 * rest of the KVM code, and will result in a misbehaving guest.
241 return vcpu_is_el2_ctxt(ctxt) ||
242 (__vcpu_el2_e2h_is_set(ctxt) && __vcpu_el2_tge_is_set(ctxt)) ||
243 __vcpu_el2_tge_is_set(ctxt);
246 static inline bool is_hyp_ctxt(const struct kvm_vcpu *vcpu)
248 return vcpu_has_nv(vcpu) && __is_hyp_ctxt(&vcpu->arch.ctxt);
252 * The layout of SPSR for an AArch32 state is different when observed from an
253 * AArch64 SPSR_ELx or an AArch32 SPSR_*. This function generates the AArch32
254 * view given an AArch64 view.
256 * In ARM DDI 0487E.a see:
258 * - The AArch64 view (SPSR_EL2) in section C5.2.18, page C5-426
259 * - The AArch32 view (SPSR_abt) in section G8.2.126, page G8-6256
260 * - The AArch32 view (SPSR_und) in section G8.2.132, page G8-6280
262 * Which show the following differences:
264 * | Bit | AA64 | AA32 | Notes |
265 * +-----+------+------+-----------------------------|
266 * | 24 | DIT | J | J is RES0 in ARMv8 |
267 * | 21 | SS | DIT | SS doesn't exist in AArch32 |
269 * ... and all other bits are (currently) common.
271 static inline unsigned long host_spsr_to_spsr32(unsigned long spsr)
273 const unsigned long overlap = BIT(24) | BIT(21);
274 unsigned long dit = !!(spsr & PSR_AA32_DIT_BIT);
283 static inline bool vcpu_mode_priv(const struct kvm_vcpu *vcpu)
287 if (vcpu_mode_is_32bit(vcpu)) {
288 mode = *vcpu_cpsr(vcpu) & PSR_AA32_MODE_MASK;
289 return mode > PSR_AA32_MODE_USR;
292 mode = *vcpu_cpsr(vcpu) & PSR_MODE_MASK;
294 return mode != PSR_MODE_EL0t;
297 static __always_inline u64 kvm_vcpu_get_esr(const struct kvm_vcpu *vcpu)
299 return vcpu->arch.fault.esr_el2;
302 static __always_inline int kvm_vcpu_get_condition(const struct kvm_vcpu *vcpu)
304 u64 esr = kvm_vcpu_get_esr(vcpu);
306 if (esr & ESR_ELx_CV)
307 return (esr & ESR_ELx_COND_MASK) >> ESR_ELx_COND_SHIFT;
312 static __always_inline unsigned long kvm_vcpu_get_hfar(const struct kvm_vcpu *vcpu)
314 return vcpu->arch.fault.far_el2;
317 static __always_inline phys_addr_t kvm_vcpu_get_fault_ipa(const struct kvm_vcpu *vcpu)
319 return ((phys_addr_t)vcpu->arch.fault.hpfar_el2 & HPFAR_MASK) << 8;
322 static inline u64 kvm_vcpu_get_disr(const struct kvm_vcpu *vcpu)
324 return vcpu->arch.fault.disr_el1;
327 static inline u32 kvm_vcpu_hvc_get_imm(const struct kvm_vcpu *vcpu)
329 return kvm_vcpu_get_esr(vcpu) & ESR_ELx_xVC_IMM_MASK;
332 static __always_inline bool kvm_vcpu_dabt_isvalid(const struct kvm_vcpu *vcpu)
334 return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_ISV);
337 static inline unsigned long kvm_vcpu_dabt_iss_nisv_sanitized(const struct kvm_vcpu *vcpu)
339 return kvm_vcpu_get_esr(vcpu) & (ESR_ELx_CM | ESR_ELx_WNR | ESR_ELx_FSC);
342 static inline bool kvm_vcpu_dabt_issext(const struct kvm_vcpu *vcpu)
344 return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_SSE);
347 static inline bool kvm_vcpu_dabt_issf(const struct kvm_vcpu *vcpu)
349 return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_SF);
352 static __always_inline int kvm_vcpu_dabt_get_rd(const struct kvm_vcpu *vcpu)
354 return (kvm_vcpu_get_esr(vcpu) & ESR_ELx_SRT_MASK) >> ESR_ELx_SRT_SHIFT;
357 static __always_inline bool kvm_vcpu_abt_iss1tw(const struct kvm_vcpu *vcpu)
359 return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_S1PTW);
362 /* Always check for S1PTW *before* using this. */
363 static __always_inline bool kvm_vcpu_dabt_iswrite(const struct kvm_vcpu *vcpu)
365 return kvm_vcpu_get_esr(vcpu) & ESR_ELx_WNR;
368 static inline bool kvm_vcpu_dabt_is_cm(const struct kvm_vcpu *vcpu)
370 return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_CM);
373 static __always_inline unsigned int kvm_vcpu_dabt_get_as(const struct kvm_vcpu *vcpu)
375 return 1 << ((kvm_vcpu_get_esr(vcpu) & ESR_ELx_SAS) >> ESR_ELx_SAS_SHIFT);
378 /* This one is not specific to Data Abort */
379 static __always_inline bool kvm_vcpu_trap_il_is32bit(const struct kvm_vcpu *vcpu)
381 return !!(kvm_vcpu_get_esr(vcpu) & ESR_ELx_IL);
384 static __always_inline u8 kvm_vcpu_trap_get_class(const struct kvm_vcpu *vcpu)
386 return ESR_ELx_EC(kvm_vcpu_get_esr(vcpu));
389 static inline bool kvm_vcpu_trap_is_iabt(const struct kvm_vcpu *vcpu)
391 return kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_IABT_LOW;
394 static inline bool kvm_vcpu_trap_is_exec_fault(const struct kvm_vcpu *vcpu)
396 return kvm_vcpu_trap_is_iabt(vcpu) && !kvm_vcpu_abt_iss1tw(vcpu);
399 static __always_inline u8 kvm_vcpu_trap_get_fault(const struct kvm_vcpu *vcpu)
401 return kvm_vcpu_get_esr(vcpu) & ESR_ELx_FSC;
405 bool kvm_vcpu_trap_is_permission_fault(const struct kvm_vcpu *vcpu)
407 return esr_fsc_is_permission_fault(kvm_vcpu_get_esr(vcpu));
411 bool kvm_vcpu_trap_is_translation_fault(const struct kvm_vcpu *vcpu)
413 return esr_fsc_is_translation_fault(kvm_vcpu_get_esr(vcpu));
417 u64 kvm_vcpu_trap_get_perm_fault_granule(const struct kvm_vcpu *vcpu)
419 unsigned long esr = kvm_vcpu_get_esr(vcpu);
421 BUG_ON(!esr_fsc_is_permission_fault(esr));
422 return BIT(ARM64_HW_PGTABLE_LEVEL_SHIFT(esr & ESR_ELx_FSC_LEVEL));
425 static __always_inline bool kvm_vcpu_abt_issea(const struct kvm_vcpu *vcpu)
427 switch (kvm_vcpu_trap_get_fault(vcpu)) {
428 case ESR_ELx_FSC_EXTABT:
429 case ESR_ELx_FSC_SEA_TTW(-1) ... ESR_ELx_FSC_SEA_TTW(3):
430 case ESR_ELx_FSC_SECC:
431 case ESR_ELx_FSC_SECC_TTW(-1) ... ESR_ELx_FSC_SECC_TTW(3):
438 static __always_inline int kvm_vcpu_sys_get_rt(struct kvm_vcpu *vcpu)
440 u64 esr = kvm_vcpu_get_esr(vcpu);
441 return ESR_ELx_SYS64_ISS_RT(esr);
444 static inline bool kvm_is_write_fault(struct kvm_vcpu *vcpu)
446 if (kvm_vcpu_abt_iss1tw(vcpu)) {
448 * Only a permission fault on a S1PTW should be
449 * considered as a write. Otherwise, page tables baked
450 * in a read-only memslot will result in an exception
451 * being delivered in the guest.
453 * The drawback is that we end-up faulting twice if the
454 * guest is using any of HW AF/DB: a translation fault
455 * to map the page containing the PT (read only at
456 * first), then a permission fault to allow the flags
459 return kvm_vcpu_trap_is_permission_fault(vcpu);
462 if (kvm_vcpu_trap_is_iabt(vcpu))
465 return kvm_vcpu_dabt_iswrite(vcpu);
468 static inline unsigned long kvm_vcpu_get_mpidr_aff(struct kvm_vcpu *vcpu)
470 return __vcpu_sys_reg(vcpu, MPIDR_EL1) & MPIDR_HWID_BITMASK;
473 static inline void kvm_vcpu_set_be(struct kvm_vcpu *vcpu)
475 if (vcpu_mode_is_32bit(vcpu)) {
476 *vcpu_cpsr(vcpu) |= PSR_AA32_E_BIT;
478 u64 sctlr = vcpu_read_sys_reg(vcpu, SCTLR_EL1);
479 sctlr |= SCTLR_ELx_EE;
480 vcpu_write_sys_reg(vcpu, sctlr, SCTLR_EL1);
484 static inline bool kvm_vcpu_is_be(struct kvm_vcpu *vcpu)
486 if (vcpu_mode_is_32bit(vcpu))
487 return !!(*vcpu_cpsr(vcpu) & PSR_AA32_E_BIT);
489 if (vcpu_mode_priv(vcpu))
490 return !!(vcpu_read_sys_reg(vcpu, SCTLR_EL1) & SCTLR_ELx_EE);
492 return !!(vcpu_read_sys_reg(vcpu, SCTLR_EL1) & SCTLR_EL1_E0E);
495 static inline unsigned long vcpu_data_guest_to_host(struct kvm_vcpu *vcpu,
499 if (kvm_vcpu_is_be(vcpu)) {
504 return be16_to_cpu(data & 0xffff);
506 return be32_to_cpu(data & 0xffffffff);
508 return be64_to_cpu(data);
515 return le16_to_cpu(data & 0xffff);
517 return le32_to_cpu(data & 0xffffffff);
519 return le64_to_cpu(data);
523 return data; /* Leave LE untouched */
526 static inline unsigned long vcpu_data_host_to_guest(struct kvm_vcpu *vcpu,
530 if (kvm_vcpu_is_be(vcpu)) {
535 return cpu_to_be16(data & 0xffff);
537 return cpu_to_be32(data & 0xffffffff);
539 return cpu_to_be64(data);
546 return cpu_to_le16(data & 0xffff);
548 return cpu_to_le32(data & 0xffffffff);
550 return cpu_to_le64(data);
554 return data; /* Leave LE untouched */
557 static __always_inline void kvm_incr_pc(struct kvm_vcpu *vcpu)
559 WARN_ON(vcpu_get_flag(vcpu, PENDING_EXCEPTION));
560 vcpu_set_flag(vcpu, INCREMENT_PC);
563 #define kvm_pend_exception(v, e) \
565 WARN_ON(vcpu_get_flag((v), INCREMENT_PC)); \
566 vcpu_set_flag((v), PENDING_EXCEPTION); \
567 vcpu_set_flag((v), e); \
570 static __always_inline void kvm_write_cptr_el2(u64 val)
572 if (has_vhe() || has_hvhe())
573 write_sysreg(val, cpacr_el1);
575 write_sysreg(val, cptr_el2);
578 static __always_inline u64 kvm_get_reset_cptr_el2(struct kvm_vcpu *vcpu)
583 val = (CPACR_EL1_FPEN_EL0EN | CPACR_EL1_FPEN_EL1EN |
584 CPACR_EL1_ZEN_EL1EN);
585 if (cpus_have_final_cap(ARM64_SME))
586 val |= CPACR_EL1_SMEN_EL1EN;
587 } else if (has_hvhe()) {
588 val = (CPACR_EL1_FPEN_EL0EN | CPACR_EL1_FPEN_EL1EN);
590 if (!vcpu_has_sve(vcpu) ||
591 (vcpu->arch.fp_state != FP_STATE_GUEST_OWNED))
592 val |= CPACR_EL1_ZEN_EL1EN | CPACR_EL1_ZEN_EL0EN;
593 if (cpus_have_final_cap(ARM64_SME))
594 val |= CPACR_EL1_SMEN_EL1EN | CPACR_EL1_SMEN_EL0EN;
596 val = CPTR_NVHE_EL2_RES1;
598 if (vcpu_has_sve(vcpu) &&
599 (vcpu->arch.fp_state == FP_STATE_GUEST_OWNED))
601 if (cpus_have_final_cap(ARM64_SME))
602 val &= ~CPTR_EL2_TSM;
608 static __always_inline void kvm_reset_cptr_el2(struct kvm_vcpu *vcpu)
610 u64 val = kvm_get_reset_cptr_el2(vcpu);
612 kvm_write_cptr_el2(val);
614 #endif /* __ARM64_KVM_EMULATE_H__ */