arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * dts file for Xilinx ZynqMP ZCU106
   4  *
   5  * (C) Copyright 2016 - 2021, Xilinx, Inc.
   6  *
   7  * Michal Simek <michal.simek@xilinx.com>
   8  */
   9
  10 /dts-v1/;
  11
  12 #include "zynqmp.dtsi"
  13 #include "zynqmp-clk-ccf.dtsi"
  14 #include <dt-bindings/input/input.h>
  15 #include <dt-bindings/gpio/gpio.h>
  16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
  17 #include <dt-bindings/phy/phy.h>
  18
  19 / {
  20         model = "ZynqMP ZCU106 RevA";
  21         compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp";
  22
  23         aliases {
  24                 ethernet0 = &gem3;
  25                 i2c0 = &i2c0;
  26                 i2c1 = &i2c1;
  27                 mmc0 = &sdhci1;
  28                 nvmem0 = &eeprom;
  29                 rtc0 = &rtc;
  30                 serial0 = &uart0;
  31                 serial1 = &uart1;
  32                 serial2 = &dcc;
  33                 spi0 = &qspi;
  34                 usb0 = &usb0;
  35         };
  36
  37         chosen {
  38                 bootargs = "earlycon";
  39                 stdout-path = "serial0:115200n8";
  40         };
  41
  42         memory@0 {
  43                 device_type = "memory";
  44                 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
  45         };
  46
  47         gpio-keys {
  48                 compatible = "gpio-keys";
  49                 autorepeat;
  50                 switch-19 {
  51                         label = "sw19";
  52                         gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
  53                         linux,code = <KEY_DOWN>;
  54                         wakeup-source;
  55                         autorepeat;
  56                 };
  57         };
  58
  59         leds {
  60                 compatible = "gpio-leds";
  61                 heartbeat-led {
  62                         label = "heartbeat";
  63                         gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
  64                         linux,default-trigger = "heartbeat";
  65                 };
  66         };
  67
  68         ina226-u76 {
  69                 compatible = "iio-hwmon";
  70                 io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;
  71         };
  72         ina226-u77 {
  73                 compatible = "iio-hwmon";
  74                 io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
  75         };
  76         ina226-u78 {
  77                 compatible = "iio-hwmon";
  78                 io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;
  79         };
  80         ina226-u87 {
  81                 compatible = "iio-hwmon";
  82                 io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;
  83         };
  84         ina226-u85 {
  85                 compatible = "iio-hwmon";
  86                 io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;
  87         };
  88         ina226-u86 {
  89                 compatible = "iio-hwmon";
  90                 io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;
  91         };
  92         ina226-u93 {
  93                 compatible = "iio-hwmon";
  94                 io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;
  95         };
  96         ina226-u88 {
  97                 compatible = "iio-hwmon";
  98                 io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;
  99         };
 100         ina226-u15 {
 101                 compatible = "iio-hwmon";
 102                 io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;
 103         };
 104         ina226-u92 {
 105                 compatible = "iio-hwmon";
 106                 io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;
 107         };
 108         ina226-u79 {
 109                 compatible = "iio-hwmon";
 110                 io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
 111         };
 112         ina226-u81 {
 113                 compatible = "iio-hwmon";
 114                 io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;
 115         };
 116         ina226-u80 {
 117                 compatible = "iio-hwmon";
 118                 io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;
 119         };
 120         ina226-u84 {
 121                 compatible = "iio-hwmon";
 122                 io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;
 123         };
 124         ina226-u16 {
 125                 compatible = "iio-hwmon";
 126                 io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;
 127         };
 128         ina226-u65 {
 129                 compatible = "iio-hwmon";
 130                 io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
 131         };
 132         ina226-u74 {
 133                 compatible = "iio-hwmon";
 134                 io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;
 135         };
 136         ina226-u75 {
 137                 compatible = "iio-hwmon";
 138                 io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
 139         };
 140
 141         /* 48MHz reference crystal */
 142         ref48: ref48M {
 143                 compatible = "fixed-clock";
 144                 #clock-cells = <0>;
 145                 clock-frequency = <48000000>;
 146         };
 147
 148         refhdmi: refhdmi {
 149                 compatible = "fixed-clock";
 150                 #clock-cells = <0>;
 151                 clock-frequency = <114285000>;
 152         };
 153 };
 154
 155 &can1 {
 156         status = "okay";
 157         pinctrl-names = "default";
 158         pinctrl-0 = <&pinctrl_can1_default>;
 159 };
 160
 161 &dcc {
 162         status = "okay";
 163 };
 164
 165 &fpd_dma_chan1 {
 166         status = "okay";
 167 };
 168
 169 &fpd_dma_chan2 {
 170         status = "okay";
 171 };
 172
 173 &fpd_dma_chan3 {
 174         status = "okay";
 175 };
 176
 177 &fpd_dma_chan4 {
 178         status = "okay";
 179 };
 180
 181 &fpd_dma_chan5 {
 182         status = "okay";
 183 };
 184
 185 &fpd_dma_chan6 {
 186         status = "okay";
 187 };
 188
 189 &fpd_dma_chan7 {
 190         status = "okay";
 191 };
 192
 193 &fpd_dma_chan8 {
 194         status = "okay";
 195 };
 196
 197 &gem3 {
 198         status = "okay";
 199         phy-handle = <&phy0>;
 200         phy-mode = "rgmii-id";
 201         pinctrl-names = "default";
 202         pinctrl-0 = <&pinctrl_gem3_default>;
 203         phy0: ethernet-phy@c {
 204                 reg = <0xc>;
 205                 ti,rx-internal-delay = <0x8>;
 206                 ti,tx-internal-delay = <0xa>;
 207                 ti,fifo-depth = <0x1>;
 208                 ti,dp83867-rxctrl-strap-quirk;
 209         };
 210 };
 211
 212 &gpio {
 213         status = "okay";
 214         pinctrl-names = "default";
 215         pinctrl-0 = <&pinctrl_gpio_default>;
 216 };
 217
 218 &i2c0 {
 219         status = "okay";
 220         clock-frequency = <400000>;
 221         pinctrl-names = "default", "gpio";
 222         pinctrl-0 = <&pinctrl_i2c0_default>;
 223         pinctrl-1 = <&pinctrl_i2c0_gpio>;
 224         scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
 225         sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
 226
 227         tca6416_u97: gpio@20 {
 228                 compatible = "ti,tca6416";
 229                 reg = <0x20>;
 230                 gpio-controller; /* interrupt not connected */
 231                 #gpio-cells = <2>;
 232                 /*
 233                  * IRQ not connected
 234                  * Lines:
 235                  * 0 - SFP_SI5328_INT_ALM
 236                  * 1 - HDMI_SI5328_INT_ALM
 237                  * 5 - IIC_MUX_RESET_B
 238                  * 6 - GEM3_EXP_RESET_B
 239                  * 10 - FMC_HPC0_PRSNT_M2C_B
 240                  * 11 - FMC_HPC1_PRSNT_M2C_B
 241                  * 2-4, 7, 12-17 - not connected
 242                  */
 243         };
 244
 245         tca6416_u61: gpio@21 {
 246                 compatible = "ti,tca6416";
 247                 reg = <0x21>;
 248                 gpio-controller;
 249                 #gpio-cells = <2>;
 250                 /*
 251                  * IRQ not connected
 252                  * Lines:
 253                  * 0 - VCCPSPLL_EN
 254                  * 1 - MGTRAVCC_EN
 255                  * 2 - MGTRAVTT_EN
 256                  * 3 - VCCPSDDRPLL_EN
 257                  * 4 - MIO26_PMU_INPUT_LS
 258                  * 5 - PL_PMBUS_ALERT
 259                  * 6 - PS_PMBUS_ALERT
 260                  * 7 - MAXIM_PMBUS_ALERT
 261                  * 10 - PL_DDR4_VTERM_EN
 262                  * 11 - PL_DDR4_VPP_2V5_EN
 263                  * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
 264                  * 13 - PS_DIMM_SUSPEND_EN
 265                  * 14 - PS_DDR4_VTERM_EN
 266                  * 15 - PS_DDR4_VPP_2V5_EN
 267                  * 16 - 17 - not connected
 268                  */
 269         };
 270
 271         i2c-mux@75 { /* u60 */
 272                 compatible = "nxp,pca9544";
 273                 #address-cells = <1>;
 274                 #size-cells = <0>;
 275                 reg = <0x75>;
 276                 i2c@0 {
 277                         #address-cells = <1>;
 278                         #size-cells = <0>;
 279                         reg = <0>;
 280                         /* PS_PMBUS */
 281                         u76: ina226@40 { /* u76 */
 282                                 compatible = "ti,ina226";
 283                                 #io-channel-cells = <1>;
 284                                 label = "ina226-u76";
 285                                 reg = <0x40>;
 286                                 shunt-resistor = <5000>;
 287                         };
 288                         u77: ina226@41 { /* u77 */
 289                                 compatible = "ti,ina226";
 290                                 #io-channel-cells = <1>;
 291                                 label = "ina226-u77";
 292                                 reg = <0x41>;
 293                                 shunt-resistor = <5000>;
 294                         };
 295                         u78: ina226@42 { /* u78 */
 296                                 compatible = "ti,ina226";
 297                                 #io-channel-cells = <1>;
 298                                 label = "ina226-u78";
 299                                 reg = <0x42>;
 300                                 shunt-resistor = <5000>;
 301                         };
 302                         u87: ina226@43 { /* u87 */
 303                                 compatible = "ti,ina226";
 304                                 #io-channel-cells = <1>;
 305                                 label = "ina226-u87";
 306                                 reg = <0x43>;
 307                                 shunt-resistor = <5000>;
 308                         };
 309                         u85: ina226@44 { /* u85 */
 310                                 compatible = "ti,ina226";
 311                                 #io-channel-cells = <1>;
 312                                 label = "ina226-u85";
 313                                 reg = <0x44>;
 314                                 shunt-resistor = <5000>;
 315                         };
 316                         u86: ina226@45 { /* u86 */
 317                                 compatible = "ti,ina226";
 318                                 #io-channel-cells = <1>;
 319                                 label = "ina226-u86";
 320                                 reg = <0x45>;
 321                                 shunt-resistor = <5000>;
 322                         };
 323                         u93: ina226@46 { /* u93 */
 324                                 compatible = "ti,ina226";
 325                                 #io-channel-cells = <1>;
 326                                 label = "ina226-u93";
 327                                 reg = <0x46>;
 328                                 shunt-resistor = <5000>;
 329                         };
 330                         u88: ina226@47 { /* u88 */
 331                                 compatible = "ti,ina226";
 332                                 #io-channel-cells = <1>;
 333                                 label = "ina226-u88";
 334                                 reg = <0x47>;
 335                                 shunt-resistor = <5000>;
 336                         };
 337                         u15: ina226@4a { /* u15 */
 338                                 compatible = "ti,ina226";
 339                                 #io-channel-cells = <1>;
 340                                 label = "ina226-u15";
 341                                 reg = <0x4a>;
 342                                 shunt-resistor = <5000>;
 343                         };
 344                         u92: ina226@4b { /* u92 */
 345                                 compatible = "ti,ina226";
 346                                 #io-channel-cells = <1>;
 347                                 label = "ina226-u92";
 348                                 reg = <0x4b>;
 349                                 shunt-resistor = <5000>;
 350                         };
 351                 };
 352                 i2c@1 {
 353                         #address-cells = <1>;
 354                         #size-cells = <0>;
 355                         reg = <1>;
 356                         /* PL_PMBUS */
 357                         u79: ina226@40 { /* u79 */
 358                                 compatible = "ti,ina226";
 359                                 #io-channel-cells = <1>;
 360                                 label = "ina226-u79";
 361                                 reg = <0x40>;
 362                                 shunt-resistor = <2000>;
 363                         };
 364                         u81: ina226@41 { /* u81 */
 365                                 compatible = "ti,ina226";
 366                                 #io-channel-cells = <1>;
 367                                 label = "ina226-u81";
 368                                 reg = <0x41>;
 369                                 shunt-resistor = <5000>;
 370                         };
 371                         u80: ina226@42 { /* u80 */
 372                                 compatible = "ti,ina226";
 373                                 #io-channel-cells = <1>;
 374                                 label = "ina226-u80";
 375                                 reg = <0x42>;
 376                                 shunt-resistor = <5000>;
 377                         };
 378                         u84: ina226@43 { /* u84 */
 379                                 compatible = "ti,ina226";
 380                                 #io-channel-cells = <1>;
 381                                 label = "ina226-u84";
 382                                 reg = <0x43>;
 383                                 shunt-resistor = <5000>;
 384                         };
 385                         u16: ina226@44 { /* u16 */
 386                                 compatible = "ti,ina226";
 387                                 #io-channel-cells = <1>;
 388                                 label = "ina226-u16";
 389                                 reg = <0x44>;
 390                                 shunt-resistor = <5000>;
 391                         };
 392                         u65: ina226@45 { /* u65 */
 393                                 compatible = "ti,ina226";
 394                                 #io-channel-cells = <1>;
 395                                 label = "ina226-u65";
 396                                 reg = <0x45>;
 397                                 shunt-resistor = <5000>;
 398                         };
 399                         u74: ina226@46 { /* u74 */
 400                                 compatible = "ti,ina226";
 401                                 #io-channel-cells = <1>;
 402                                 label = "ina226-u74";
 403                                 reg = <0x46>;
 404                                 shunt-resistor = <5000>;
 405                         };
 406                         u75: ina226@47 { /* u75 */
 407                                 compatible = "ti,ina226";
 408                                 #io-channel-cells = <1>;
 409                                 label = "ina226-u75";
 410                                 reg = <0x47>;
 411                                 shunt-resistor = <5000>;
 412                         };
 413                 };
 414                 i2c@2 {
 415                         #address-cells = <1>;
 416                         #size-cells = <0>;
 417                         reg = <2>;
 418                         /* MAXIM_PMBUS - 00 */
 419                         max15301@a { /* u46 */
 420                                 compatible = "maxim,max15301";
 421                                 reg = <0xa>;
 422                         };
 423                         max15303@b { /* u4 */
 424                                 compatible = "maxim,max15303";
 425                                 reg = <0xb>;
 426                         };
 427                         max15303@10 { /* u13 */
 428                                 compatible = "maxim,max15303";
 429                                 reg = <0x10>;
 430                         };
 431                         max15301@13 { /* u47 */
 432                                 compatible = "maxim,max15301";
 433                                 reg = <0x13>;
 434                         };
 435                         max15303@14 { /* u7 */
 436                                 compatible = "maxim,max15303";
 437                                 reg = <0x14>;
 438                         };
 439                         max15303@15 { /* u6 */
 440                                 compatible = "maxim,max15303";
 441                                 reg = <0x15>;
 442                         };
 443                         max15303@16 { /* u10 */
 444                                 compatible = "maxim,max15303";
 445                                 reg = <0x16>;
 446                         };
 447                         max15303@17 { /* u9 */
 448                                 compatible = "maxim,max15303";
 449                                 reg = <0x17>;
 450                         };
 451                         max15301@18 { /* u63 */
 452                                 compatible = "maxim,max15301";
 453                                 reg = <0x18>;
 454                         };
 455                         max15303@1a { /* u49 */
 456                                 compatible = "maxim,max15303";
 457                                 reg = <0x1a>;
 458                         };
 459                         max15303@1b { /* u8 */
 460                                 compatible = "maxim,max15303";
 461                                 reg = <0x1b>;
 462                         };
 463                         max15303@1d { /* u18 */
 464                                 compatible = "maxim,max15303";
 465                                 reg = <0x1d>;
 466                         };
 467
 468                         max20751@72 { /* u95 */
 469                                 compatible = "maxim,max20751";
 470                                 reg = <0x72>;
 471                         };
 472                         max20751@73 { /* u96 */
 473                                 compatible = "maxim,max20751";
 474                                 reg = <0x73>;
 475                         };
 476                 };
 477                 /* Bus 3 is not connected */
 478         };
 479 };
 480
 481 &i2c1 {
 482         status = "okay";
 483         clock-frequency = <400000>;
 484         pinctrl-names = "default", "gpio";
 485         pinctrl-0 = <&pinctrl_i2c1_default>;
 486         pinctrl-1 = <&pinctrl_i2c1_gpio>;
 487         scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
 488         sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
 489
 490         /* PL i2c via PCA9306 - u45 */
 491         i2c-mux@74 { /* u34 */
 492                 compatible = "nxp,pca9548";
 493                 #address-cells = <1>;
 494                 #size-cells = <0>;
 495                 reg = <0x74>;
 496                 i2c@0 {
 497                         #address-cells = <1>;
 498                         #size-cells = <0>;
 499                         reg = <0>;
 500                         /*
 501                          * IIC_EEPROM 1kB memory which uses 256B blocks
 502                          * where every block has different address.
 503                          *    0 - 256B address 0x54
 504                          * 256B - 512B address 0x55
 505                          * 512B - 768B address 0x56
 506                          * 768B - 1024B address 0x57
 507                          */
 508                         eeprom: eeprom@54 { /* u23 */
 509                                 compatible = "atmel,24c08";
 510                                 reg = <0x54>;
 511                         };
 512                 };
 513                 i2c@1 {
 514                         #address-cells = <1>;
 515                         #size-cells = <0>;
 516                         reg = <1>;
 517                         si5341: clock-generator@36 { /* SI5341 - u69 */
 518                                 compatible = "silabs,si5341";
 519                                 reg = <0x36>;
 520                                 #clock-cells = <2>;
 521                                 #address-cells = <1>;
 522                                 #size-cells = <0>;
 523                                 clocks = <&ref48>;
 524                                 clock-names = "xtal";
 525                                 clock-output-names = "si5341";
 526
 527                                 si5341_0: out@0 {
 528                                         /* refclk0 for PS-GT, used for DP */
 529                                         reg = <0>;
 530                                         always-on;
 531                                 };
 532                                 si5341_2: out@2 {
 533                                         /* refclk2 for PS-GT, used for USB3 */
 534                                         reg = <2>;
 535                                         always-on;
 536                                 };
 537                                 si5341_3: out@3 {
 538                                         /* refclk3 for PS-GT, used for SATA */
 539                                         reg = <3>;
 540                                         always-on;
 541                                 };
 542                                 si5341_6: out@6 {
 543                                         /* refclk6 PL CLK125 */
 544                                         reg = <6>;
 545                                         always-on;
 546                                 };
 547                                 si5341_7: out@7 {
 548                                         /* refclk7 PL CLK74 */
 549                                         reg = <7>;
 550                                         always-on;
 551                                 };
 552                                 si5341_9: out@9 {
 553                                         /* refclk9 used for PS_REF_CLK 33.3 MHz */
 554                                         reg = <9>;
 555                                         always-on;
 556                                 };
 557                         };
 558
 559                 };
 560                 i2c@2 {
 561                         #address-cells = <1>;
 562                         #size-cells = <0>;
 563                         reg = <2>;
 564                         si570_1: clock-generator@5d { /* USER SI570 - u42 */
 565                                 #clock-cells = <0>;
 566                                 compatible = "silabs,si570";
 567                                 reg = <0x5d>;
 568                                 temperature-stability = <50>;
 569                                 factory-fout = <300000000>;
 570                                 clock-frequency = <300000000>;
 571                                 clock-output-names = "si570_user";
 572                         };
 573                 };
 574                 i2c@3 {
 575                         #address-cells = <1>;
 576                         #size-cells = <0>;
 577                         reg = <3>;
 578                         si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */
 579                                 #clock-cells = <0>;
 580                                 compatible = "silabs,si570";
 581                                 reg = <0x5d>;
 582                                 temperature-stability = <50>; /* copy from zc702 */
 583                                 factory-fout = <156250000>;
 584                                 clock-frequency = <148500000>;
 585                                 clock-output-names = "si570_mgt";
 586                         };
 587                 };
 588                 i2c@4 {
 589                         #address-cells = <1>;
 590                         #size-cells = <0>;
 591                         reg = <4>;
 592                         /* SI5328 - u20 */
 593                 };
 594                 i2c@5 {
 595                         #address-cells = <1>;
 596                         #size-cells = <0>;
 597                         reg = <5>; /* FAN controller */
 598                         temp@4c {/* lm96163 - u128 */
 599                                 compatible = "national,lm96163";
 600                                 reg = <0x4c>;
 601                         };
 602                 };
 603                 /* 6 - 7 unconnected */
 604         };
 605
 606         i2c-mux@75 {
 607                 compatible = "nxp,pca9548"; /* u135 */
 608                 #address-cells = <1>;
 609                 #size-cells = <0>;
 610                 reg = <0x75>;
 611
 612                 i2c@0 {
 613                         #address-cells = <1>;
 614                         #size-cells = <0>;
 615                         reg = <0>;
 616                         /* HPC0_IIC */
 617                 };
 618                 i2c@1 {
 619                         #address-cells = <1>;
 620                         #size-cells = <0>;
 621                         reg = <1>;
 622                         /* HPC1_IIC */
 623                 };
 624                 i2c@2 {
 625                         #address-cells = <1>;
 626                         #size-cells = <0>;
 627                         reg = <2>;
 628                         /* SYSMON */
 629                 };
 630                 i2c@3 {
 631                         #address-cells = <1>;
 632                         #size-cells = <0>;
 633                         reg = <3>;
 634                         /* DDR4 SODIMM */
 635                 };
 636                 i2c@4 {
 637                         #address-cells = <1>;
 638                         #size-cells = <0>;
 639                         reg = <4>;
 640                         /* SEP 3 */
 641                 };
 642                 i2c@5 {
 643                         #address-cells = <1>;
 644                         #size-cells = <0>;
 645                         reg = <5>;
 646                         /* SEP 2 */
 647                 };
 648                 i2c@6 {
 649                         #address-cells = <1>;
 650                         #size-cells = <0>;
 651                         reg = <6>;
 652                         /* SEP 1 */
 653                 };
 654                 i2c@7 {
 655                         #address-cells = <1>;
 656                         #size-cells = <0>;
 657                         reg = <7>;
 658                         /* SEP 0 */
 659                 };
 660         };
 661 };
 662
 663 &pinctrl0 {
 664         status = "okay";
 665         pinctrl_i2c0_default: i2c0-default {
 666                 mux {
 667                         groups = "i2c0_3_grp";
 668                         function = "i2c0";
 669                 };
 670
 671                 conf {
 672                         groups = "i2c0_3_grp";
 673                         bias-pull-up;
 674                         slew-rate = <SLEW_RATE_SLOW>;
 675                         power-source = <IO_STANDARD_LVCMOS18>;
 676                 };
 677         };
 678
 679         pinctrl_i2c0_gpio: i2c0-gpio {
 680                 mux {
 681                         groups = "gpio0_14_grp", "gpio0_15_grp";
 682                         function = "gpio0";
 683                 };
 684
 685                 conf {
 686                         groups = "gpio0_14_grp", "gpio0_15_grp";
 687                         slew-rate = <SLEW_RATE_SLOW>;
 688                         power-source = <IO_STANDARD_LVCMOS18>;
 689                 };
 690         };
 691
 692         pinctrl_i2c1_default: i2c1-default {
 693                 mux {
 694                         groups = "i2c1_4_grp";
 695                         function = "i2c1";
 696                 };
 697
 698                 conf {
 699                         groups = "i2c1_4_grp";
 700                         bias-pull-up;
 701                         slew-rate = <SLEW_RATE_SLOW>;
 702                         power-source = <IO_STANDARD_LVCMOS18>;
 703                 };
 704         };
 705
 706         pinctrl_i2c1_gpio: i2c1-gpio {
 707                 mux {
 708                         groups = "gpio0_16_grp", "gpio0_17_grp";
 709                         function = "gpio0";
 710                 };
 711
 712                 conf {
 713                         groups = "gpio0_16_grp", "gpio0_17_grp";
 714                         slew-rate = <SLEW_RATE_SLOW>;
 715                         power-source = <IO_STANDARD_LVCMOS18>;
 716                 };
 717         };
 718
 719         pinctrl_uart0_default: uart0-default {
 720                 mux {
 721                         groups = "uart0_4_grp";
 722                         function = "uart0";
 723                 };
 724
 725                 conf {
 726                         groups = "uart0_4_grp";
 727                         slew-rate = <SLEW_RATE_SLOW>;
 728                         power-source = <IO_STANDARD_LVCMOS18>;
 729                 };
 730
 731                 conf-rx {
 732                         pins = "MIO18";
 733                         bias-high-impedance;
 734                 };
 735
 736                 conf-tx {
 737                         pins = "MIO19";
 738                         bias-disable;
 739                 };
 740         };
 741
 742         pinctrl_uart1_default: uart1-default {
 743                 mux {
 744                         groups = "uart1_5_grp";
 745                         function = "uart1";
 746                 };
 747
 748                 conf {
 749                         groups = "uart1_5_grp";
 750                         slew-rate = <SLEW_RATE_SLOW>;
 751                         power-source = <IO_STANDARD_LVCMOS18>;
 752                 };
 753
 754                 conf-rx {
 755                         pins = "MIO21";
 756                         bias-high-impedance;
 757                 };
 758
 759                 conf-tx {
 760                         pins = "MIO20";
 761                         bias-disable;
 762                 };
 763         };
 764
 765         pinctrl_usb0_default: usb0-default {
 766                 mux {
 767                         groups = "usb0_0_grp";
 768                         function = "usb0";
 769                 };
 770
 771                 conf {
 772                         groups = "usb0_0_grp";
 773                         slew-rate = <SLEW_RATE_SLOW>;
 774                         power-source = <IO_STANDARD_LVCMOS18>;
 775                 };
 776
 777                 conf-rx {
 778                         pins = "MIO52", "MIO53", "MIO55";
 779                         bias-high-impedance;
 780                 };
 781
 782                 conf-tx {
 783                         pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
 784                                "MIO60", "MIO61", "MIO62", "MIO63";
 785                         bias-disable;
 786                 };
 787         };
 788
 789         pinctrl_gem3_default: gem3-default {
 790                 mux {
 791                         function = "ethernet3";
 792                         groups = "ethernet3_0_grp";
 793                 };
 794
 795                 conf {
 796                         groups = "ethernet3_0_grp";
 797                         slew-rate = <SLEW_RATE_SLOW>;
 798                         power-source = <IO_STANDARD_LVCMOS18>;
 799                 };
 800
 801                 conf-rx {
 802                         pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
 803                                                                         "MIO75";
 804                         bias-high-impedance;
 805                         low-power-disable;
 806                 };
 807
 808                 conf-tx {
 809                         pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
 810                                                                         "MIO69";
 811                         bias-disable;
 812                         low-power-enable;
 813                 };
 814
 815                 mux-mdio {
 816                         function = "mdio3";
 817                         groups = "mdio3_0_grp";
 818                 };
 819
 820                 conf-mdio {
 821                         groups = "mdio3_0_grp";
 822                         slew-rate = <SLEW_RATE_SLOW>;
 823                         power-source = <IO_STANDARD_LVCMOS18>;
 824                         bias-disable;
 825                 };
 826         };
 827
 828         pinctrl_can1_default: can1-default {
 829                 mux {
 830                         function = "can1";
 831                         groups = "can1_6_grp";
 832                 };
 833
 834                 conf {
 835                         groups = "can1_6_grp";
 836                         slew-rate = <SLEW_RATE_SLOW>;
 837                         power-source = <IO_STANDARD_LVCMOS18>;
 838                 };
 839
 840                 conf-rx {
 841                         pins = "MIO25";
 842                         bias-high-impedance;
 843                 };
 844
 845                 conf-tx {
 846                         pins = "MIO24";
 847                         bias-disable;
 848                 };
 849         };
 850
 851         pinctrl_sdhci1_default: sdhci1-default {
 852                 mux {
 853                         groups = "sdio1_0_grp";
 854                         function = "sdio1";
 855                 };
 856
 857                 conf {
 858                         groups = "sdio1_0_grp";
 859                         slew-rate = <SLEW_RATE_SLOW>;
 860                         power-source = <IO_STANDARD_LVCMOS18>;
 861                         bias-disable;
 862                 };
 863
 864                 mux-cd {
 865                         groups = "sdio1_cd_0_grp";
 866                         function = "sdio1_cd";
 867                 };
 868
 869                 conf-cd {
 870                         groups = "sdio1_cd_0_grp";
 871                         bias-high-impedance;
 872                         bias-pull-up;
 873                         slew-rate = <SLEW_RATE_SLOW>;
 874                         power-source = <IO_STANDARD_LVCMOS18>;
 875                 };
 876
 877                 mux-wp {
 878                         groups = "sdio1_wp_0_grp";
 879                         function = "sdio1_wp";
 880                 };
 881
 882                 conf-wp {
 883                         groups = "sdio1_wp_0_grp";
 884                         bias-high-impedance;
 885                         bias-pull-up;
 886                         slew-rate = <SLEW_RATE_SLOW>;
 887                         power-source = <IO_STANDARD_LVCMOS18>;
 888                 };
 889         };
 890
 891         pinctrl_gpio_default: gpio-default {
 892                 mux {
 893                         function = "gpio0";
 894                         groups = "gpio0_22_grp", "gpio0_23_grp";
 895                 };
 896
 897                 conf {
 898                         groups = "gpio0_22_grp", "gpio0_23_grp";
 899                         slew-rate = <SLEW_RATE_SLOW>;
 900                         power-source = <IO_STANDARD_LVCMOS18>;
 901                 };
 902
 903                 mux-msp {
 904                         function = "gpio0";
 905                         groups = "gpio0_13_grp", "gpio0_38_grp";
 906                 };
 907
 908                 conf-msp {
 909                         groups = "gpio0_13_grp", "gpio0_38_grp";
 910                         slew-rate = <SLEW_RATE_SLOW>;
 911                         power-source = <IO_STANDARD_LVCMOS18>;
 912                 };
 913
 914                 conf-pull-up {
 915                         pins = "MIO22";
 916                         bias-pull-up;
 917                 };
 918
 919                 conf-pull-none {
 920                         pins = "MIO13", "MIO23", "MIO38";
 921                         bias-disable;
 922                 };
 923         };
 924 };
 925
 926 &psgtr {
 927         status = "okay";
 928         /* nc, sata, usb3, dp */
 929         clocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
 930         clock-names = "ref1", "ref2", "ref3";
 931 };
 932
 933 &qspi {
 934         status = "okay";
 935         flash@0 {
 936                 compatible = "m25p80", "jedec,spi-nor"; /* 16MB + 16MB */
 937                 #address-cells = <1>;
 938                 #size-cells = <1>;
 939                 reg = <0x0>;
 940                 spi-tx-bus-width = <1>;
 941                 spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
 942                 spi-max-frequency = <108000000>; /* Based on DC1 spec */
 943         };
 944 };
 945
 946 &rtc {
 947         status = "okay";
 948 };
 949
 950 &sata {
 951         status = "okay";
 952         /* SATA OOB timing settings */
 953         ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 954         ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 955         ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 956         ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 957         ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
 958         ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 959         ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 960         ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
 961         phy-names = "sata-phy";
 962         phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
 963 };
 964
 965 /* SD1 with level shifter */
 966 &sdhci1 {
 967         status = "okay";
 968         /*
 969          * This property should be removed for supporting UHS mode
 970          */
 971         no-1-8-v;
 972         pinctrl-names = "default";
 973         pinctrl-0 = <&pinctrl_sdhci1_default>;
 974         xlnx,mio-bank = <1>;
 975 };
 976
 977 &uart0 {
 978         status = "okay";
 979         pinctrl-names = "default";
 980         pinctrl-0 = <&pinctrl_uart0_default>;
 981 };
 982
 983 &uart1 {
 984         status = "okay";
 985         pinctrl-names = "default";
 986         pinctrl-0 = <&pinctrl_uart1_default>;
 987 };
 988
 989 /* ULPI SMSC USB3320 */
 990 &usb0 {
 991         status = "okay";
 992         pinctrl-names = "default";
 993         pinctrl-0 = <&pinctrl_usb0_default>;
 994         phy-names = "usb3-phy";
 995         phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
 996 };
 997
 998 &dwc3_0 {
 999         status = "okay";
1000         dr_mode = "host";
1001         snps,usb3_lpm_capable;
1002         maximum-speed = "super-speed";
1003 };
1004
1005 &watchdog0 {
1006         status = "okay";
1007 };
1008
1009 &zynqmp_dpdma {
1010         status = "okay";
1011 };
1012
1013 &zynqmp_dpsub {
1014         status = "okay";
1015         phy-names = "dp-phy0", "dp-phy1";
1016         phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
1017                <&psgtr 0 PHY_TYPE_DP 1 3>;
1018 };