arch/arm64/boot/dts/ti/k3-j7200-main.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for J7200 SoC Family Main Domain peripherals
   4  *
   5  * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
   6  */
   7
   8 / {
   9         serdes_refclk: serdes-refclk {
  10                 #clock-cells = <0>;
  11                 compatible = "fixed-clock";
  12         };
  13 };
  14
  15 &cbass_main {
  16         msmc_ram: sram@70000000 {
  17                 compatible = "mmio-sram";
  18                 reg = <0x00 0x70000000 0x00 0x100000>;
  19                 #address-cells = <1>;
  20                 #size-cells = <1>;
  21                 ranges = <0x00 0x00 0x70000000 0x100000>;
  22
  23                 atf-sram@0 {
  24                         reg = <0x00 0x20000>;
  25                 };
  26         };
  27
  28         scm_conf: scm-conf@100000 {
  29                 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
  30                 reg = <0x00 0x00100000 0x00 0x1c000>;
  31                 #address-cells = <1>;
  32                 #size-cells = <1>;
  33                 ranges = <0x00 0x00 0x00100000 0x1c000>;
  34
  35                 serdes_ln_ctrl: mux-controller@4080 {
  36                         compatible = "mmio-mux";
  37                         #mux-control-cells = <1>;
  38                         mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
  39                                         <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */
  40                 };
  41
  42                 cpsw0_phy_gmii_sel: phy@4044 {
  43                         compatible = "ti,j7200-cpsw5g-phy-gmii-sel";
  44                         ti,qsgmii-main-ports = <1>;
  45                         reg = <0x4044 0x10>;
  46                         #phy-cells = <1>;
  47                 };
  48
  49                 usb_serdes_mux: mux-controller@4000 {
  50                         compatible = "mmio-mux";
  51                         #mux-control-cells = <1>;
  52                         mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
  53                 };
  54         };
  55
  56         gic500: interrupt-controller@1800000 {
  57                 compatible = "arm,gic-v3";
  58                 #address-cells = <2>;
  59                 #size-cells = <2>;
  60                 ranges;
  61                 #interrupt-cells = <3>;
  62                 interrupt-controller;
  63                 reg = <0x00 0x01800000 0x00 0x10000>,   /* GICD */
  64                       <0x00 0x01900000 0x00 0x100000>,  /* GICR */
  65                       <0x00 0x6f000000 0x00 0x2000>,    /* GICC */
  66                       <0x00 0x6f010000 0x00 0x1000>,    /* GICH */
  67                       <0x00 0x6f020000 0x00 0x2000>;    /* GICV */
  68
  69                 /* vcpumntirq: virtual CPU interface maintenance interrupt */
  70                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
  71
  72                 gic_its: msi-controller@1820000 {
  73                         compatible = "arm,gic-v3-its";
  74                         reg = <0x00 0x01820000 0x00 0x10000>;
  75                         socionext,synquacer-pre-its = <0x1000000 0x400000>;
  76                         msi-controller;
  77                         #msi-cells = <1>;
  78                 };
  79         };
  80
  81         main_gpio_intr: interrupt-controller@a00000 {
  82                 compatible = "ti,sci-intr";
  83                 reg = <0x00 0x00a00000 0x00 0x800>;
  84                 ti,intr-trigger-type = <1>;
  85                 interrupt-controller;
  86                 interrupt-parent = <&gic500>;
  87                 #interrupt-cells = <1>;
  88                 ti,sci = <&dmsc>;
  89                 ti,sci-dev-id = <131>;
  90                 ti,interrupt-ranges = <8 392 56>;
  91         };
  92
  93         main_navss: bus@30000000 {
  94                 compatible = "simple-bus";
  95                 #address-cells = <2>;
  96                 #size-cells = <2>;
  97                 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
  98                 ti,sci-dev-id = <199>;
  99                 dma-coherent;
 100                 dma-ranges;
 101
 102                 main_navss_intr: interrupt-controller@310e0000 {
 103                         compatible = "ti,sci-intr";
 104                         reg = <0x00 0x310e0000 0x00 0x4000>;
 105                         ti,intr-trigger-type = <4>;
 106                         interrupt-controller;
 107                         interrupt-parent = <&gic500>;
 108                         #interrupt-cells = <1>;
 109                         ti,sci = <&dmsc>;
 110                         ti,sci-dev-id = <213>;
 111                         ti,interrupt-ranges = <0 64 64>,
 112                                               <64 448 64>,
 113                                               <128 672 64>;
 114                 };
 115
 116                 main_udmass_inta: msi-controller@33d00000 {
 117                         compatible = "ti,sci-inta";
 118                         reg = <0x00 0x33d00000 0x00 0x100000>;
 119                         interrupt-controller;
 120                         #interrupt-cells = <0>;
 121                         interrupt-parent = <&main_navss_intr>;
 122                         msi-controller;
 123                         ti,sci = <&dmsc>;
 124                         ti,sci-dev-id = <209>;
 125                         ti,interrupt-ranges = <0 0 256>;
 126                 };
 127
 128                 secure_proxy_main: mailbox@32c00000 {
 129                         compatible = "ti,am654-secure-proxy";
 130                         #mbox-cells = <1>;
 131                         reg-names = "target_data", "rt", "scfg";
 132                         reg = <0x00 0x32c00000 0x00 0x100000>,
 133                               <0x00 0x32400000 0x00 0x100000>,
 134                               <0x00 0x32800000 0x00 0x100000>;
 135                         interrupt-names = "rx_011";
 136                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 137                 };
 138
 139                 hwspinlock: spinlock@30e00000 {
 140                         compatible = "ti,am654-hwspinlock";
 141                         reg = <0x00 0x30e00000 0x00 0x1000>;
 142                         #hwlock-cells = <1>;
 143                 };
 144
 145                 mailbox0_cluster0: mailbox@31f80000 {
 146                         compatible = "ti,am654-mailbox";
 147                         reg = <0x00 0x31f80000 0x00 0x200>;
 148                         #mbox-cells = <1>;
 149                         ti,mbox-num-users = <4>;
 150                         ti,mbox-num-fifos = <16>;
 151                         interrupt-parent = <&main_navss_intr>;
 152                         status = "disabled";
 153                 };
 154
 155                 mailbox0_cluster1: mailbox@31f81000 {
 156                         compatible = "ti,am654-mailbox";
 157                         reg = <0x00 0x31f81000 0x00 0x200>;
 158                         #mbox-cells = <1>;
 159                         ti,mbox-num-users = <4>;
 160                         ti,mbox-num-fifos = <16>;
 161                         interrupt-parent = <&main_navss_intr>;
 162                         status = "disabled";
 163                 };
 164
 165                 mailbox0_cluster2: mailbox@31f82000 {
 166                         compatible = "ti,am654-mailbox";
 167                         reg = <0x00 0x31f82000 0x00 0x200>;
 168                         #mbox-cells = <1>;
 169                         ti,mbox-num-users = <4>;
 170                         ti,mbox-num-fifos = <16>;
 171                         interrupt-parent = <&main_navss_intr>;
 172                         status = "disabled";
 173                 };
 174
 175                 mailbox0_cluster3: mailbox@31f83000 {
 176                         compatible = "ti,am654-mailbox";
 177                         reg = <0x00 0x31f83000 0x00 0x200>;
 178                         #mbox-cells = <1>;
 179                         ti,mbox-num-users = <4>;
 180                         ti,mbox-num-fifos = <16>;
 181                         interrupt-parent = <&main_navss_intr>;
 182                         status = "disabled";
 183                 };
 184
 185                 mailbox0_cluster4: mailbox@31f84000 {
 186                         compatible = "ti,am654-mailbox";
 187                         reg = <0x00 0x31f84000 0x00 0x200>;
 188                         #mbox-cells = <1>;
 189                         ti,mbox-num-users = <4>;
 190                         ti,mbox-num-fifos = <16>;
 191                         interrupt-parent = <&main_navss_intr>;
 192                         status = "disabled";
 193                 };
 194
 195                 mailbox0_cluster5: mailbox@31f85000 {
 196                         compatible = "ti,am654-mailbox";
 197                         reg = <0x00 0x31f85000 0x00 0x200>;
 198                         #mbox-cells = <1>;
 199                         ti,mbox-num-users = <4>;
 200                         ti,mbox-num-fifos = <16>;
 201                         interrupt-parent = <&main_navss_intr>;
 202                         status = "disabled";
 203                 };
 204
 205                 mailbox0_cluster6: mailbox@31f86000 {
 206                         compatible = "ti,am654-mailbox";
 207                         reg = <0x00 0x31f86000 0x00 0x200>;
 208                         #mbox-cells = <1>;
 209                         ti,mbox-num-users = <4>;
 210                         ti,mbox-num-fifos = <16>;
 211                         interrupt-parent = <&main_navss_intr>;
 212                         status = "disabled";
 213                 };
 214
 215                 mailbox0_cluster7: mailbox@31f87000 {
 216                         compatible = "ti,am654-mailbox";
 217                         reg = <0x00 0x31f87000 0x00 0x200>;
 218                         #mbox-cells = <1>;
 219                         ti,mbox-num-users = <4>;
 220                         ti,mbox-num-fifos = <16>;
 221                         interrupt-parent = <&main_navss_intr>;
 222                         status = "disabled";
 223                 };
 224
 225                 mailbox0_cluster8: mailbox@31f88000 {
 226                         compatible = "ti,am654-mailbox";
 227                         reg = <0x00 0x31f88000 0x00 0x200>;
 228                         #mbox-cells = <1>;
 229                         ti,mbox-num-users = <4>;
 230                         ti,mbox-num-fifos = <16>;
 231                         interrupt-parent = <&main_navss_intr>;
 232                         status = "disabled";
 233                 };
 234
 235                 mailbox0_cluster9: mailbox@31f89000 {
 236                         compatible = "ti,am654-mailbox";
 237                         reg = <0x00 0x31f89000 0x00 0x200>;
 238                         #mbox-cells = <1>;
 239                         ti,mbox-num-users = <4>;
 240                         ti,mbox-num-fifos = <16>;
 241                         interrupt-parent = <&main_navss_intr>;
 242                         status = "disabled";
 243                 };
 244
 245                 mailbox0_cluster10: mailbox@31f8a000 {
 246                         compatible = "ti,am654-mailbox";
 247                         reg = <0x00 0x31f8a000 0x00 0x200>;
 248                         #mbox-cells = <1>;
 249                         ti,mbox-num-users = <4>;
 250                         ti,mbox-num-fifos = <16>;
 251                         interrupt-parent = <&main_navss_intr>;
 252                         status = "disabled";
 253                 };
 254
 255                 mailbox0_cluster11: mailbox@31f8b000 {
 256                         compatible = "ti,am654-mailbox";
 257                         reg = <0x00 0x31f8b000 0x00 0x200>;
 258                         #mbox-cells = <1>;
 259                         ti,mbox-num-users = <4>;
 260                         ti,mbox-num-fifos = <16>;
 261                         interrupt-parent = <&main_navss_intr>;
 262                         status = "disabled";
 263                 };
 264
 265                 main_ringacc: ringacc@3c000000 {
 266                         compatible = "ti,am654-navss-ringacc";
 267                         reg = <0x00 0x3c000000 0x00 0x400000>,
 268                               <0x00 0x38000000 0x00 0x400000>,
 269                               <0x00 0x31120000 0x00 0x100>,
 270                               <0x00 0x33000000 0x00 0x40000>,
 271                               <0x00 0x31080000 0x00 0x40000>;
 272                         reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
 273                         ti,num-rings = <1024>;
 274                         ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
 275                         ti,sci = <&dmsc>;
 276                         ti,sci-dev-id = <211>;
 277                         msi-parent = <&main_udmass_inta>;
 278                 };
 279
 280                 main_udmap: dma-controller@31150000 {
 281                         compatible = "ti,j721e-navss-main-udmap";
 282                         reg = <0x00 0x31150000 0x00 0x100>,
 283                               <0x00 0x34000000 0x00 0x100000>,
 284                               <0x00 0x35000000 0x00 0x100000>,
 285                               <0x00 0x30b00000 0x00 0x4000>,
 286                               <0x00 0x30c00000 0x00 0x4000>,
 287                               <0x00 0x30d00000 0x00 0x4000>;
 288                         reg-names = "gcfg", "rchanrt", "tchanrt",
 289                                     "tchan", "rchan", "rflow";
 290                         msi-parent = <&main_udmass_inta>;
 291                         #dma-cells = <1>;
 292
 293                         ti,sci = <&dmsc>;
 294                         ti,sci-dev-id = <212>;
 295                         ti,ringacc = <&main_ringacc>;
 296
 297                         ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
 298                                                 <0x0f>, /* TX_HCHAN */
 299                                                 <0x10>; /* TX_UHCHAN */
 300                         ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
 301                                                 <0x0b>, /* RX_HCHAN */
 302                                                 <0x0c>; /* RX_UHCHAN */
 303                         ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
 304                 };
 305
 306                 cpts@310d0000 {
 307                         compatible = "ti,j721e-cpts";
 308                         reg = <0x00 0x310d0000 0x00 0x400>;
 309                         reg-names = "cpts";
 310                         clocks = <&k3_clks 201 1>;
 311                         clock-names = "cpts";
 312                         interrupts-extended = <&main_navss_intr 391>;
 313                         interrupt-names = "cpts";
 314                         ti,cpts-periodic-outputs = <6>;
 315                         ti,cpts-ext-ts-inputs = <8>;
 316                 };
 317         };
 318
 319         cpsw0: ethernet@c000000 {
 320                 compatible = "ti,j7200-cpswxg-nuss";
 321                 #address-cells = <2>;
 322                 #size-cells = <2>;
 323                 reg = <0x00 0xc000000 0x00 0x200000>;
 324                 reg-names = "cpsw_nuss";
 325                 ranges = <0x00 0x00 0x00 0xc000000 0x00 0x200000>;
 326                 clocks = <&k3_clks 19 33>;
 327                 clock-names = "fck";
 328                 power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>;
 329
 330                 dmas = <&main_udmap 0xca00>,
 331                        <&main_udmap 0xca01>,
 332                        <&main_udmap 0xca02>,
 333                        <&main_udmap 0xca03>,
 334                        <&main_udmap 0xca04>,
 335                        <&main_udmap 0xca05>,
 336                        <&main_udmap 0xca06>,
 337                        <&main_udmap 0xca07>,
 338                        <&main_udmap 0x4a00>;
 339                 dma-names = "tx0", "tx1", "tx2", "tx3",
 340                             "tx4", "tx5", "tx6", "tx7",
 341                             "rx";
 342
 343                 status = "disabled";
 344
 345                 ethernet-ports {
 346                         #address-cells = <1>;
 347                         #size-cells = <0>;
 348                         cpsw0_port1: port@1 {
 349                                 reg = <1>;
 350                                 ti,mac-only;
 351                                 label = "port1";
 352                                 status = "disabled";
 353                         };
 354
 355                         cpsw0_port2: port@2 {
 356                                 reg = <2>;
 357                                 ti,mac-only;
 358                                 label = "port2";
 359                                 status = "disabled";
 360                         };
 361
 362                         cpsw0_port3: port@3 {
 363                                 reg = <3>;
 364                                 ti,mac-only;
 365                                 label = "port3";
 366                                 status = "disabled";
 367                         };
 368
 369                         cpsw0_port4: port@4 {
 370                                 reg = <4>;
 371                                 ti,mac-only;
 372                                 label = "port4";
 373                                 status = "disabled";
 374                         };
 375                 };
 376
 377                 cpsw5g_mdio: mdio@f00 {
 378                         compatible = "ti,cpsw-mdio","ti,davinci_mdio";
 379                         reg = <0x00 0xf00 0x00 0x100>;
 380                         #address-cells = <1>;
 381                         #size-cells = <0>;
 382                         clocks = <&k3_clks 19 33>;
 383                         clock-names = "fck";
 384                         bus_freq = <1000000>;
 385                         status = "disabled";
 386                 };
 387
 388                 cpts@3d000 {
 389                         compatible = "ti,j721e-cpts";
 390                         reg = <0x00 0x3d000 0x00 0x400>;
 391                         clocks = <&k3_clks 19 16>;
 392                         clock-names = "cpts";
 393                         interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 394                         interrupt-names = "cpts";
 395                         ti,cpts-ext-ts-inputs = <4>;
 396                         ti,cpts-periodic-outputs = <2>;
 397                 };
 398         };
 399
 400         /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */
 401         main_timerio_input: pinctrl@104200 {
 402                 compatible = "pinctrl-single";
 403                 reg = <0x0 0x104200 0x0 0x50>;
 404                 #pinctrl-cells = <1>;
 405                 pinctrl-single,register-width = <32>;
 406                 pinctrl-single,function-mask = <0x000001ff>;
 407         };
 408
 409         /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */
 410         main_timerio_output: pinctrl@104280 {
 411                 compatible = "pinctrl-single";
 412                 reg = <0x0 0x104280 0x0 0x20>;
 413                 #pinctrl-cells = <1>;
 414                 pinctrl-single,register-width = <32>;
 415                 pinctrl-single,function-mask = <0x0000001f>;
 416         };
 417
 418         main_pmx0: pinctrl@11c000 {
 419                 compatible = "pinctrl-single";
 420                 /* Proxy 0 addressing */
 421                 reg = <0x00 0x11c000 0x00 0x10c>;
 422                 #pinctrl-cells = <1>;
 423                 pinctrl-single,register-width = <32>;
 424                 pinctrl-single,function-mask = <0xffffffff>;
 425         };
 426
 427         main_pmx1: pinctrl@11c11c {
 428                 compatible = "pinctrl-single";
 429                 /* Proxy 0 addressing */
 430                 reg = <0x00 0x11c11c 0x00 0xc>;
 431                 #pinctrl-cells = <1>;
 432                 pinctrl-single,register-width = <32>;
 433                 pinctrl-single,function-mask = <0xffffffff>;
 434         };
 435
 436         main_uart0: serial@2800000 {
 437                 compatible = "ti,j721e-uart", "ti,am654-uart";
 438                 reg = <0x00 0x02800000 0x00 0x100>;
 439                 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
 440                 clock-frequency = <48000000>;
 441                 current-speed = <115200>;
 442                 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
 443                 clocks = <&k3_clks 146 2>;
 444                 clock-names = "fclk";
 445                 status = "disabled";
 446         };
 447
 448         main_uart1: serial@2810000 {
 449                 compatible = "ti,j721e-uart", "ti,am654-uart";
 450                 reg = <0x00 0x02810000 0x00 0x100>;
 451                 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
 452                 clock-frequency = <48000000>;
 453                 current-speed = <115200>;
 454                 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
 455                 clocks = <&k3_clks 278 2>;
 456                 clock-names = "fclk";
 457                 status = "disabled";
 458         };
 459
 460         main_uart2: serial@2820000 {
 461                 compatible = "ti,j721e-uart", "ti,am654-uart";
 462                 reg = <0x00 0x02820000 0x00 0x100>;
 463                 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
 464                 clock-frequency = <48000000>;
 465                 current-speed = <115200>;
 466                 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
 467                 clocks = <&k3_clks 279 2>;
 468                 clock-names = "fclk";
 469                 status = "disabled";
 470         };
 471
 472         main_uart3: serial@2830000 {
 473                 compatible = "ti,j721e-uart", "ti,am654-uart";
 474                 reg = <0x00 0x02830000 0x00 0x100>;
 475                 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
 476                 clock-frequency = <48000000>;
 477                 current-speed = <115200>;
 478                 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
 479                 clocks = <&k3_clks 280 2>;
 480                 clock-names = "fclk";
 481                 status = "disabled";
 482         };
 483
 484         main_uart4: serial@2840000 {
 485                 compatible = "ti,j721e-uart", "ti,am654-uart";
 486                 reg = <0x00 0x02840000 0x00 0x100>;
 487                 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
 488                 clock-frequency = <48000000>;
 489                 current-speed = <115200>;
 490                 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
 491                 clocks = <&k3_clks 281 2>;
 492                 clock-names = "fclk";
 493                 status = "disabled";
 494         };
 495
 496         main_uart5: serial@2850000 {
 497                 compatible = "ti,j721e-uart", "ti,am654-uart";
 498                 reg = <0x00 0x02850000 0x00 0x100>;
 499                 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
 500                 clock-frequency = <48000000>;
 501                 current-speed = <115200>;
 502                 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
 503                 clocks = <&k3_clks 282 2>;
 504                 clock-names = "fclk";
 505                 status = "disabled";
 506         };
 507
 508         main_uart6: serial@2860000 {
 509                 compatible = "ti,j721e-uart", "ti,am654-uart";
 510                 reg = <0x00 0x02860000 0x00 0x100>;
 511                 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
 512                 clock-frequency = <48000000>;
 513                 current-speed = <115200>;
 514                 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
 515                 clocks = <&k3_clks 283 2>;
 516                 clock-names = "fclk";
 517                 status = "disabled";
 518         };
 519
 520         main_uart7: serial@2870000 {
 521                 compatible = "ti,j721e-uart", "ti,am654-uart";
 522                 reg = <0x00 0x02870000 0x00 0x100>;
 523                 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
 524                 clock-frequency = <48000000>;
 525                 current-speed = <115200>;
 526                 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
 527                 clocks = <&k3_clks 284 2>;
 528                 clock-names = "fclk";
 529                 status = "disabled";
 530         };
 531
 532         main_uart8: serial@2880000 {
 533                 compatible = "ti,j721e-uart", "ti,am654-uart";
 534                 reg = <0x00 0x02880000 0x00 0x100>;
 535                 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
 536                 clock-frequency = <48000000>;
 537                 current-speed = <115200>;
 538                 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
 539                 clocks = <&k3_clks 285 2>;
 540                 clock-names = "fclk";
 541                 status = "disabled";
 542         };
 543
 544         main_uart9: serial@2890000 {
 545                 compatible = "ti,j721e-uart", "ti,am654-uart";
 546                 reg = <0x00 0x02890000 0x00 0x100>;
 547                 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
 548                 clock-frequency = <48000000>;
 549                 current-speed = <115200>;
 550                 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
 551                 clocks = <&k3_clks 286 2>;
 552                 clock-names = "fclk";
 553                 status = "disabled";
 554         };
 555
 556         main_i2c0: i2c@2000000 {
 557                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 558                 reg = <0x00 0x2000000 0x00 0x100>;
 559                 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
 560                 #address-cells = <1>;
 561                 #size-cells = <0>;
 562                 clock-names = "fck";
 563                 clocks = <&k3_clks 187 1>;
 564                 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>;
 565                 status = "disabled";
 566         };
 567
 568         main_i2c1: i2c@2010000 {
 569                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 570                 reg = <0x00 0x2010000 0x00 0x100>;
 571                 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
 572                 #address-cells = <1>;
 573                 #size-cells = <0>;
 574                 clock-names = "fck";
 575                 clocks = <&k3_clks 188 1>;
 576                 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
 577                 status = "disabled";
 578         };
 579
 580         main_i2c2: i2c@2020000 {
 581                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 582                 reg = <0x00 0x2020000 0x00 0x100>;
 583                 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
 584                 #address-cells = <1>;
 585                 #size-cells = <0>;
 586                 clock-names = "fck";
 587                 clocks = <&k3_clks 189 1>;
 588                 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
 589                 status = "disabled";
 590         };
 591
 592         main_i2c3: i2c@2030000 {
 593                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 594                 reg = <0x00 0x2030000 0x00 0x100>;
 595                 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
 596                 #address-cells = <1>;
 597                 #size-cells = <0>;
 598                 clock-names = "fck";
 599                 clocks = <&k3_clks 190 1>;
 600                 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
 601                 status = "disabled";
 602         };
 603
 604         main_i2c4: i2c@2040000 {
 605                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 606                 reg = <0x00 0x2040000 0x00 0x100>;
 607                 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
 608                 #address-cells = <1>;
 609                 #size-cells = <0>;
 610                 clock-names = "fck";
 611                 clocks = <&k3_clks 191 1>;
 612                 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
 613                 status = "disabled";
 614         };
 615
 616         main_i2c5: i2c@2050000 {
 617                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 618                 reg = <0x00 0x2050000 0x00 0x100>;
 619                 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
 620                 #address-cells = <1>;
 621                 #size-cells = <0>;
 622                 clock-names = "fck";
 623                 clocks = <&k3_clks 192 1>;
 624                 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
 625                 status = "disabled";
 626         };
 627
 628         main_i2c6: i2c@2060000 {
 629                 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
 630                 reg = <0x00 0x2060000 0x00 0x100>;
 631                 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
 632                 #address-cells = <1>;
 633                 #size-cells = <0>;
 634                 clock-names = "fck";
 635                 clocks = <&k3_clks 193 1>;
 636                 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
 637                 status = "disabled";
 638         };
 639
 640         main_sdhci0: mmc@4f80000 {
 641                 compatible = "ti,j7200-sdhci-8bit", "ti,j721e-sdhci-8bit";
 642                 reg = <0x00 0x04f80000 0x00 0x260>, <0x00 0x4f88000 0x00 0x134>;
 643                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 644                 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
 645                 clock-names = "clk_ahb", "clk_xin";
 646                 clocks = <&k3_clks 91 0>, <&k3_clks 91 3>;
 647                 ti,otap-del-sel-legacy = <0x0>;
 648                 ti,otap-del-sel-mmc-hs = <0x0>;
 649                 ti,otap-del-sel-ddr52 = <0x6>;
 650                 ti,otap-del-sel-hs200 = <0x8>;
 651                 ti,otap-del-sel-hs400 = <0x5>;
 652                 ti,itap-del-sel-legacy = <0x10>;
 653                 ti,itap-del-sel-mmc-hs = <0xa>;
 654                 ti,itap-del-sel-ddr52 = <0x3>;
 655                 ti,strobe-sel = <0x77>;
 656                 ti,clkbuf-sel = <0x7>;
 657                 ti,trm-icp = <0x8>;
 658                 bus-width = <8>;
 659                 mmc-ddr-1_8v;
 660                 mmc-hs200-1_8v;
 661                 mmc-hs400-1_8v;
 662                 dma-coherent;
 663                 status = "disabled";
 664         };
 665
 666         main_sdhci1: mmc@4fb0000 {
 667                 compatible = "ti,j7200-sdhci-4bit", "ti,j721e-sdhci-4bit";
 668                 reg = <0x00 0x04fb0000 0x00 0x260>, <0x00 0x4fb8000 0x00 0x134>;
 669                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 670                 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
 671                 clock-names = "clk_ahb", "clk_xin";
 672                 clocks = <&k3_clks 92 1>, <&k3_clks 92 2>;
 673                 ti,otap-del-sel-legacy = <0x0>;
 674                 ti,otap-del-sel-sd-hs = <0x0>;
 675                 ti,otap-del-sel-sdr12 = <0xf>;
 676                 ti,otap-del-sel-sdr25 = <0xf>;
 677                 ti,otap-del-sel-sdr50 = <0xc>;
 678                 ti,otap-del-sel-sdr104 = <0x5>;
 679                 ti,otap-del-sel-ddr50 = <0xc>;
 680                 ti,itap-del-sel-legacy = <0x0>;
 681                 ti,itap-del-sel-sd-hs = <0x0>;
 682                 ti,itap-del-sel-sdr12 = <0x0>;
 683                 ti,itap-del-sel-sdr25 = <0x0>;
 684                 ti,clkbuf-sel = <0x7>;
 685                 ti,trm-icp = <0x8>;
 686                 dma-coherent;
 687                 status = "disabled";
 688         };
 689
 690         serdes_wiz0: wiz@5060000 {
 691                 compatible = "ti,j721e-wiz-10g";
 692                 #address-cells = <1>;
 693                 #size-cells = <1>;
 694                 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
 695                 clocks = <&k3_clks 292 11>, <&k3_clks 292 85>, <&serdes_refclk>;
 696                 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
 697                 num-lanes = <4>;
 698                 #reset-cells = <1>;
 699                 ranges = <0x5060000 0x0 0x5060000 0x10000>;
 700
 701                 assigned-clocks = <&k3_clks 292 85>;
 702                 assigned-clock-parents = <&k3_clks 292 89>;
 703
 704                 wiz0_pll0_refclk: pll0-refclk {
 705                         clocks = <&k3_clks 292 85>, <&serdes_refclk>;
 706                         clock-output-names = "wiz0_pll0_refclk";
 707                         #clock-cells = <0>;
 708                         assigned-clocks = <&wiz0_pll0_refclk>;
 709                         assigned-clock-parents = <&k3_clks 292 85>;
 710                 };
 711
 712                 wiz0_pll1_refclk: pll1-refclk {
 713                         clocks = <&k3_clks 292 85>, <&serdes_refclk>;
 714                         clock-output-names = "wiz0_pll1_refclk";
 715                         #clock-cells = <0>;
 716                         assigned-clocks = <&wiz0_pll1_refclk>;
 717                         assigned-clock-parents = <&k3_clks 292 85>;
 718                 };
 719
 720                 wiz0_refclk_dig: refclk-dig {
 721                         clocks = <&k3_clks 292 85>, <&serdes_refclk>;
 722                         clock-output-names = "wiz0_refclk_dig";
 723                         #clock-cells = <0>;
 724                         assigned-clocks = <&wiz0_refclk_dig>;
 725                         assigned-clock-parents = <&k3_clks 292 85>;
 726                 };
 727
 728                 wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
 729                         clocks = <&wiz0_refclk_dig>;
 730                         #clock-cells = <0>;
 731                 };
 732
 733                 serdes0: serdes@5060000 {
 734                         compatible = "ti,j721e-serdes-10g";
 735                         reg = <0x05060000 0x00010000>;
 736                         reg-names = "torrent_phy";
 737                         resets = <&serdes_wiz0 0>;
 738                         reset-names = "torrent_reset";
 739                         clocks = <&wiz0_pll0_refclk>;
 740                         clock-names = "refclk";
 741                         #address-cells = <1>;
 742                         #size-cells = <0>;
 743                 };
 744         };
 745
 746         pcie1_rc: pcie@2910000 {
 747                 compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host";
 748                 reg = <0x00 0x02910000 0x00 0x1000>,
 749                       <0x00 0x02917000 0x00 0x400>,
 750                       <0x00 0x0d800000 0x00 0x00800000>,
 751                       <0x00 0x18000000 0x00 0x00001000>;
 752                 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
 753                 interrupt-names = "link_state";
 754                 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
 755                 device_type = "pci";
 756                 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
 757                 max-link-speed = <3>;
 758                 num-lanes = <4>;
 759                 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
 760                 clocks = <&k3_clks 240 6>;
 761                 clock-names = "fck";
 762                 #address-cells = <3>;
 763                 #size-cells = <2>;
 764                 bus-range = <0x0 0xff>;
 765                 cdns,no-bar-match-nbits = <64>;
 766                 vendor-id = <0x104c>;
 767                 device-id = <0xb00f>;
 768                 msi-map = <0x0 &gic_its 0x0 0x10000>;
 769                 dma-coherent;
 770                 ranges = <0x01000000 0x0 0x18001000  0x00 0x18001000  0x0 0x0010000>,
 771                          <0x02000000 0x0 0x18011000  0x00 0x18011000  0x0 0x7fef000>;
 772                 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
 773         };
 774
 775         pcie1_ep: pcie-ep@2910000 {
 776                 compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep";
 777                 reg = <0x00 0x02910000 0x00 0x1000>,
 778                       <0x00 0x02917000 0x00 0x400>,
 779                       <0x00 0x0d800000 0x00 0x00800000>,
 780                       <0x00 0x18000000 0x00 0x08000000>;
 781                 reg-names = "intd_cfg", "user_cfg", "reg", "mem";
 782                 interrupt-names = "link_state";
 783                 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
 784                 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
 785                 max-link-speed = <3>;
 786                 num-lanes = <4>;
 787                 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
 788                 clocks = <&k3_clks 240 6>;
 789                 clock-names = "fck";
 790                 max-functions = /bits/ 8 <6>;
 791                 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
 792                 dma-coherent;
 793         };
 794
 795         usbss0: cdns-usb@4104000 {
 796                 compatible = "ti,j721e-usb";
 797                 reg = <0x00 0x4104000 0x00 0x100>;
 798                 dma-coherent;
 799                 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
 800                 clocks = <&k3_clks 288 12>, <&k3_clks 288 3>;
 801                 clock-names = "ref", "lpm";
 802                 assigned-clocks = <&k3_clks 288 12>;    /* USB2_REFCLK */
 803                 assigned-clock-parents = <&k3_clks 288 13>; /* HFOSC0 */
 804                 #address-cells = <2>;
 805                 #size-cells = <2>;
 806                 ranges;
 807
 808                 usb0: usb@6000000 {
 809                         compatible = "cdns,usb3";
 810                         reg = <0x00 0x6000000 0x00 0x10000>,
 811                               <0x00 0x6010000 0x00 0x10000>,
 812                               <0x00 0x6020000 0x00 0x10000>;
 813                         reg-names = "otg", "xhci", "dev";
 814                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,  /* irq.0 */
 815                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
 816                                      <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
 817                         interrupt-names = "host",
 818                                           "peripheral",
 819                                           "otg";
 820                         maximum-speed = "super-speed";
 821                         dr_mode = "otg";
 822                         cdns,phyrst-a-enable;
 823                 };
 824         };
 825
 826         main_gpio0: gpio@600000 {
 827                 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
 828                 reg = <0x00 0x00600000 0x00 0x100>;
 829                 gpio-controller;
 830                 #gpio-cells = <2>;
 831                 interrupt-parent = <&main_gpio_intr>;
 832                 interrupts = <145>, <146>, <147>, <148>,
 833                              <149>;
 834                 interrupt-controller;
 835                 #interrupt-cells = <2>;
 836                 ti,ngpio = <69>;
 837                 ti,davinci-gpio-unbanked = <0>;
 838                 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
 839                 clocks = <&k3_clks 105 0>;
 840                 clock-names = "gpio";
 841                 status = "disabled";
 842         };
 843
 844         main_gpio2: gpio@610000 {
 845                 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
 846                 reg = <0x00 0x00610000 0x00 0x100>;
 847                 gpio-controller;
 848                 #gpio-cells = <2>;
 849                 interrupt-parent = <&main_gpio_intr>;
 850                 interrupts = <154>, <155>, <156>, <157>,
 851                              <158>;
 852                 interrupt-controller;
 853                 #interrupt-cells = <2>;
 854                 ti,ngpio = <69>;
 855                 ti,davinci-gpio-unbanked = <0>;
 856                 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
 857                 clocks = <&k3_clks 107 0>;
 858                 clock-names = "gpio";
 859                 status = "disabled";
 860         };
 861
 862         main_gpio4: gpio@620000 {
 863                 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
 864                 reg = <0x00 0x00620000 0x00 0x100>;
 865                 gpio-controller;
 866                 #gpio-cells = <2>;
 867                 interrupt-parent = <&main_gpio_intr>;
 868                 interrupts = <163>, <164>, <165>, <166>,
 869                              <167>;
 870                 interrupt-controller;
 871                 #interrupt-cells = <2>;
 872                 ti,ngpio = <69>;
 873                 ti,davinci-gpio-unbanked = <0>;
 874                 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
 875                 clocks = <&k3_clks 109 0>;
 876                 clock-names = "gpio";
 877                 status = "disabled";
 878         };
 879
 880         main_gpio6: gpio@630000 {
 881                 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
 882                 reg = <0x00 0x00630000 0x00 0x100>;
 883                 gpio-controller;
 884                 #gpio-cells = <2>;
 885                 interrupt-parent = <&main_gpio_intr>;
 886                 interrupts = <172>, <173>, <174>, <175>,
 887                              <176>;
 888                 interrupt-controller;
 889                 #interrupt-cells = <2>;
 890                 ti,ngpio = <69>;
 891                 ti,davinci-gpio-unbanked = <0>;
 892                 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
 893                 clocks = <&k3_clks 111 0>;
 894                 clock-names = "gpio";
 895                 status = "disabled";
 896         };
 897
 898         main_spi0: spi@2100000 {
 899                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
 900                 reg = <0x00 0x02100000 0x00 0x400>;
 901                 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 902                 #address-cells = <1>;
 903                 #size-cells = <0>;
 904                 power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>;
 905                 clocks = <&k3_clks 266 1>;
 906                 status = "disabled";
 907         };
 908
 909         main_spi1: spi@2110000 {
 910                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
 911                 reg = <0x00 0x02110000 0x00 0x400>;
 912                 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
 913                 #address-cells = <1>;
 914                 #size-cells = <0>;
 915                 power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>;
 916                 clocks = <&k3_clks 267 1>;
 917                 status = "disabled";
 918         };
 919
 920         main_spi2: spi@2120000 {
 921                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
 922                 reg = <0x00 0x02120000 0x00 0x400>;
 923                 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
 924                 #address-cells = <1>;
 925                 #size-cells = <0>;
 926                 power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>;
 927                 clocks = <&k3_clks 268 1>;
 928                 status = "disabled";
 929         };
 930
 931         main_spi3: spi@2130000 {
 932                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
 933                 reg = <0x00 0x02130000 0x00 0x400>;
 934                 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
 935                 #address-cells = <1>;
 936                 #size-cells = <0>;
 937                 power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>;
 938                 clocks = <&k3_clks 269 1>;
 939                 status = "disabled";
 940         };
 941
 942         main_spi4: spi@2140000 {
 943                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
 944                 reg = <0x00 0x02140000 0x00 0x400>;
 945                 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
 946                 #address-cells = <1>;
 947                 #size-cells = <0>;
 948                 power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>;
 949                 clocks = <&k3_clks 270 1>;
 950                 status = "disabled";
 951         };
 952
 953         main_spi5: spi@2150000 {
 954                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
 955                 reg = <0x00 0x02150000 0x00 0x400>;
 956                 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
 957                 #address-cells = <1>;
 958                 #size-cells = <0>;
 959                 power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>;
 960                 clocks = <&k3_clks 271 1>;
 961                 status = "disabled";
 962         };
 963
 964         main_spi6: spi@2160000 {
 965                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
 966                 reg = <0x00 0x02160000 0x00 0x400>;
 967                 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
 968                 #address-cells = <1>;
 969                 #size-cells = <0>;
 970                 power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>;
 971                 clocks = <&k3_clks 272 1>;
 972                 status = "disabled";
 973         };
 974
 975         main_spi7: spi@2170000 {
 976                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
 977                 reg = <0x00 0x02170000 0x00 0x400>;
 978                 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
 979                 #address-cells = <1>;
 980                 #size-cells = <0>;
 981                 power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>;
 982                 clocks = <&k3_clks 273 1>;
 983                 status = "disabled";
 984         };
 985
 986         watchdog0: watchdog@2200000 {
 987                 compatible = "ti,j7-rti-wdt";
 988                 reg = <0x0 0x2200000 0x0 0x100>;
 989                 clocks = <&k3_clks 252 1>;
 990                 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;
 991                 assigned-clocks = <&k3_clks 252 1>;
 992                 assigned-clock-parents = <&k3_clks 252 5>;
 993         };
 994
 995         watchdog1: watchdog@2210000 {
 996                 compatible = "ti,j7-rti-wdt";
 997                 reg = <0x0 0x2210000 0x0 0x100>;
 998                 clocks = <&k3_clks 253 1>;
 999                 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>;
1000                 assigned-clocks = <&k3_clks 253 1>;
1001                 assigned-clock-parents = <&k3_clks 253 5>;
1002         };
1003
1004         main_timer0: timer@2400000 {
1005                 compatible = "ti,am654-timer";
1006                 reg = <0x00 0x2400000 0x00 0x400>;
1007                 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
1008                 clocks = <&k3_clks 49 1>;
1009                 clock-names = "fck";
1010                 assigned-clocks = <&k3_clks 49 1>;
1011                 assigned-clock-parents = <&k3_clks 49 2>;
1012                 power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
1013                 ti,timer-pwm;
1014         };
1015
1016         main_timer1: timer@2410000 {
1017                 compatible = "ti,am654-timer";
1018                 reg = <0x00 0x2410000 0x00 0x400>;
1019                 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1020                 clocks = <&k3_clks 50 1>;
1021                 clock-names = "fck";
1022                 assigned-clocks = <&k3_clks 50 1>, <&k3_clks 313 0>;
1023                 assigned-clock-parents = <&k3_clks 50 2>, <&k3_clks 313 1>;
1024                 power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
1025                 ti,timer-pwm;
1026         };
1027
1028         main_timer2: timer@2420000 {
1029                 compatible = "ti,am654-timer";
1030                 reg = <0x00 0x2420000 0x00 0x400>;
1031                 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1032                 clocks = <&k3_clks 51 1>;
1033                 clock-names = "fck";
1034                 assigned-clocks = <&k3_clks 51 1>;
1035                 assigned-clock-parents = <&k3_clks 51 2>;
1036                 power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
1037                 ti,timer-pwm;
1038         };
1039
1040         main_timer3: timer@2430000 {
1041                 compatible = "ti,am654-timer";
1042                 reg = <0x00 0x2430000 0x00 0x400>;
1043                 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
1044                 clocks = <&k3_clks 52 1>;
1045                 clock-names = "fck";
1046                 assigned-clocks = <&k3_clks 52 1>, <&k3_clks 314 0>;
1047                 assigned-clock-parents = <&k3_clks 52 2>, <&k3_clks 314 1>;
1048                 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
1049                 ti,timer-pwm;
1050         };
1051
1052         main_timer4: timer@2440000 {
1053                 compatible = "ti,am654-timer";
1054                 reg = <0x00 0x2440000 0x00 0x400>;
1055                 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
1056                 clocks = <&k3_clks 53 1>;
1057                 clock-names = "fck";
1058                 assigned-clocks = <&k3_clks 53 1>;
1059                 assigned-clock-parents = <&k3_clks 53 2>;
1060                 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
1061                 ti,timer-pwm;
1062         };
1063
1064         main_timer5: timer@2450000 {
1065                 compatible = "ti,am654-timer";
1066                 reg = <0x00 0x2450000 0x00 0x400>;
1067                 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
1068                 clocks = <&k3_clks 54 1>;
1069                 clock-names = "fck";
1070                 assigned-clocks = <&k3_clks 54 1>, <&k3_clks 315 0>;
1071                 assigned-clock-parents = <&k3_clks 54 2>, <&k3_clks 315 1>;
1072                 power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>;
1073                 ti,timer-pwm;
1074         };
1075
1076         main_timer6: timer@2460000 {
1077                 compatible = "ti,am654-timer";
1078                 reg = <0x00 0x2460000 0x00 0x400>;
1079                 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
1080                 clocks = <&k3_clks 55 1>;
1081                 clock-names = "fck";
1082                 assigned-clocks = <&k3_clks 55 1>;
1083                 assigned-clock-parents = <&k3_clks 55 2>;
1084                 power-domains = <&k3_pds 55 TI_SCI_PD_EXCLUSIVE>;
1085                 ti,timer-pwm;
1086         };
1087
1088         main_timer7: timer@2470000 {
1089                 compatible = "ti,am654-timer";
1090                 reg = <0x00 0x2470000 0x00 0x400>;
1091                 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
1092                 clocks = <&k3_clks 57 1>;
1093                 clock-names = "fck";
1094                 assigned-clocks = <&k3_clks 57 1>, <&k3_clks 316 0>;
1095                 assigned-clock-parents = <&k3_clks 57 2>, <&k3_clks 316 1>;
1096                 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
1097                 ti,timer-pwm;
1098         };
1099
1100         main_timer8: timer@2480000 {
1101                 compatible = "ti,am654-timer";
1102                 reg = <0x00 0x2480000 0x00 0x400>;
1103                 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
1104                 clocks = <&k3_clks 58 1>;
1105                 clock-names = "fck";
1106                 assigned-clocks = <&k3_clks 58 1>;
1107                 assigned-clock-parents = <&k3_clks 58 2>;
1108                 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
1109                 ti,timer-pwm;
1110         };
1111
1112         main_timer9: timer@2490000 {
1113                 compatible = "ti,am654-timer";
1114                 reg = <0x00 0x2490000 0x00 0x400>;
1115                 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
1116                 clocks = <&k3_clks 59 1>;
1117                 clock-names = "fck";
1118                 assigned-clocks = <&k3_clks 59 1>, <&k3_clks 317 0>;
1119                 assigned-clock-parents = <&k3_clks 59 2>, <&k3_clks 317 1>;
1120                 power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>;
1121                 ti,timer-pwm;
1122         };
1123
1124         main_timer10: timer@24a0000 {
1125                 compatible = "ti,am654-timer";
1126                 reg = <0x00 0x24a0000 0x00 0x400>;
1127                 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
1128                 clocks = <&k3_clks 60 1>;
1129                 clock-names = "fck";
1130                 assigned-clocks = <&k3_clks 60 1>;
1131                 assigned-clock-parents = <&k3_clks 60 2>;
1132                 power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>;
1133                 ti,timer-pwm;
1134         };
1135
1136         main_timer11: timer@24b0000 {
1137                 compatible = "ti,am654-timer";
1138                 reg = <0x00 0x24b0000 0x00 0x400>;
1139                 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
1140                 clocks = <&k3_clks 62 1>;
1141                 clock-names = "fck";
1142                 assigned-clocks = <&k3_clks 62 1>, <&k3_clks 318 0>;
1143                 assigned-clock-parents = <&k3_clks 62 2>, <&k3_clks 318 1>;
1144                 power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>;
1145                 ti,timer-pwm;
1146         };
1147
1148         main_timer12: timer@24c0000 {
1149                 compatible = "ti,am654-timer";
1150                 reg = <0x00 0x24c0000 0x00 0x400>;
1151                 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
1152                 clocks = <&k3_clks 63 1>;
1153                 clock-names = "fck";
1154                 assigned-clocks = <&k3_clks 63 1>;
1155                 assigned-clock-parents = <&k3_clks 63 2>;
1156                 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
1157                 ti,timer-pwm;
1158         };
1159
1160         main_timer13: timer@24d0000 {
1161                 compatible = "ti,am654-timer";
1162                 reg = <0x00 0x24d0000 0x00 0x400>;
1163                 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
1164                 clocks = <&k3_clks 64 1>;
1165                 clock-names = "fck";
1166                 assigned-clocks = <&k3_clks 64 1>, <&k3_clks 319 0>;
1167                 assigned-clock-parents = <&k3_clks 64 2>, <&k3_clks 319 1>;
1168                 power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
1169                 ti,timer-pwm;
1170         };
1171
1172         main_timer14: timer@24e0000 {
1173                 compatible = "ti,am654-timer";
1174                 reg = <0x00 0x24e0000 0x00 0x400>;
1175                 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1176                 clocks = <&k3_clks 65 1>;
1177                 clock-names = "fck";
1178                 assigned-clocks = <&k3_clks 65 1>;
1179                 assigned-clock-parents = <&k3_clks 65 2>;
1180                 power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>;
1181                 ti,timer-pwm;
1182         };
1183
1184         main_timer15: timer@24f0000 {
1185                 compatible = "ti,am654-timer";
1186                 reg = <0x00 0x24f0000 0x00 0x400>;
1187                 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
1188                 clocks = <&k3_clks 66 1>;
1189                 clock-names = "fck";
1190                 assigned-clocks = <&k3_clks 66 1>, <&k3_clks 320 0>;
1191                 assigned-clock-parents = <&k3_clks 66 2>, <&k3_clks 320 1>;
1192                 power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>;
1193                 ti,timer-pwm;
1194         };
1195
1196         main_timer16: timer@2500000 {
1197                 compatible = "ti,am654-timer";
1198                 reg = <0x00 0x2500000 0x00 0x400>;
1199                 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
1200                 clocks = <&k3_clks 67 1>;
1201                 clock-names = "fck";
1202                 assigned-clocks = <&k3_clks 67 1>;
1203                 assigned-clock-parents = <&k3_clks 67 2>;
1204                 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
1205                 ti,timer-pwm;
1206         };
1207
1208         main_timer17: timer@2510000 {
1209                 compatible = "ti,am654-timer";
1210                 reg = <0x00 0x2510000 0x00 0x400>;
1211                 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
1212                 clocks = <&k3_clks 68 1>;
1213                 clock-names = "fck";
1214                 assigned-clocks = <&k3_clks 68 1>, <&k3_clks 321 0>;
1215                 assigned-clock-parents = <&k3_clks 68 2>, <&k3_clks 321 1>;
1216                 power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>;
1217                 ti,timer-pwm;
1218         };
1219
1220         main_timer18: timer@2520000 {
1221                 compatible = "ti,am654-timer";
1222                 reg = <0x00 0x2520000 0x00 0x400>;
1223                 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
1224                 clocks = <&k3_clks 69 1>;
1225                 clock-names = "fck";
1226                 assigned-clocks = <&k3_clks 69 1>;
1227                 assigned-clock-parents = <&k3_clks 69 2>;
1228                 power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>;
1229                 ti,timer-pwm;
1230         };
1231
1232         main_timer19: timer@2530000 {
1233                 compatible = "ti,am654-timer";
1234                 reg = <0x00 0x2530000 0x00 0x400>;
1235                 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
1236                 clocks = <&k3_clks 70 1>;
1237                 clock-names = "fck";
1238                 assigned-clocks = <&k3_clks 70 1>, <&k3_clks 322 0>;
1239                 assigned-clock-parents = <&k3_clks 70 2>, <&k3_clks 322 1>;
1240                 power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>;
1241                 ti,timer-pwm;
1242         };
1243
1244         main_r5fss0: r5fss@5c00000 {
1245                 compatible = "ti,j7200-r5fss";
1246                 ti,cluster-mode = <1>;
1247                 #address-cells = <1>;
1248                 #size-cells = <1>;
1249                 ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
1250                          <0x5d00000 0x00 0x5d00000 0x20000>;
1251                 power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>;
1252
1253                 main_r5fss0_core0: r5f@5c00000 {
1254                         compatible = "ti,j7200-r5f";
1255                         reg = <0x5c00000 0x00010000>,
1256                               <0x5c10000 0x00010000>;
1257                         reg-names = "atcm", "btcm";
1258                         ti,sci = <&dmsc>;
1259                         ti,sci-dev-id = <245>;
1260                         ti,sci-proc-ids = <0x06 0xff>;
1261                         resets = <&k3_reset 245 1>;
1262                         firmware-name = "j7200-main-r5f0_0-fw";
1263                         ti,atcm-enable = <1>;
1264                         ti,btcm-enable = <1>;
1265                         ti,loczrama = <1>;
1266                 };
1267
1268                 main_r5fss0_core1: r5f@5d00000 {
1269                         compatible = "ti,j7200-r5f";
1270                         reg = <0x5d00000 0x00008000>,
1271                               <0x5d10000 0x00008000>;
1272                         reg-names = "atcm", "btcm";
1273                         ti,sci = <&dmsc>;
1274                         ti,sci-dev-id = <246>;
1275                         ti,sci-proc-ids = <0x07 0xff>;
1276                         resets = <&k3_reset 246 1>;
1277                         firmware-name = "j7200-main-r5f0_1-fw";
1278                         ti,atcm-enable = <1>;
1279                         ti,btcm-enable = <1>;
1280                         ti,loczrama = <1>;
1281                 };
1282         };
1283
1284         main_esm: esm@700000 {
1285                 compatible = "ti,j721e-esm";
1286                 reg = <0x0 0x700000 0x0 0x1000>;
1287                 ti,esm-pins = <656>, <657>;
1288         };
1289 };