arch/arm64/boot/dts/ti/k3-am625.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
   2 /*
   3  * Device Tree Source for AM625 SoC family in Quad core configuration
   4  *
   5  * TRM: https://www.ti.com/lit/pdf/spruiv7
   6  *
   7  * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
   8  */
   9
  10 /dts-v1/;
  11
  12 #include "k3-am62.dtsi"
  13
  14 / {
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18
  19                 cpu-map {
  20                         cluster0: cluster0 {
  21                                 core0 {
  22                                         cpu = <&cpu0>;
  23                                 };
  24
  25                                 core1 {
  26                                         cpu = <&cpu1>;
  27                                 };
  28
  29                                 core2 {
  30                                         cpu = <&cpu2>;
  31                                 };
  32
  33                                 core3 {
  34                                         cpu = <&cpu3>;
  35                                 };
  36                         };
  37                 };
  38
  39                 cpu0: cpu@0 {
  40                         compatible = "arm,cortex-a53";
  41                         reg = <0x000>;
  42                         device_type = "cpu";
  43                         enable-method = "psci";
  44                         i-cache-size = <0x8000>;
  45                         i-cache-line-size = <64>;
  46                         i-cache-sets = <256>;
  47                         d-cache-size = <0x8000>;
  48                         d-cache-line-size = <64>;
  49                         d-cache-sets = <128>;
  50                         next-level-cache = <&L2_0>;
  51                         operating-points-v2 = <&a53_opp_table>;
  52                         clocks = <&k3_clks 135 0>;
  53                 };
  54
  55                 cpu1: cpu@1 {
  56                         compatible = "arm,cortex-a53";
  57                         reg = <0x001>;
  58                         device_type = "cpu";
  59                         enable-method = "psci";
  60                         i-cache-size = <0x8000>;
  61                         i-cache-line-size = <64>;
  62                         i-cache-sets = <256>;
  63                         d-cache-size = <0x8000>;
  64                         d-cache-line-size = <64>;
  65                         d-cache-sets = <128>;
  66                         next-level-cache = <&L2_0>;
  67                         operating-points-v2 = <&a53_opp_table>;
  68                         clocks = <&k3_clks 136 0>;
  69                 };
  70
  71                 cpu2: cpu@2 {
  72                         compatible = "arm,cortex-a53";
  73                         reg = <0x002>;
  74                         device_type = "cpu";
  75                         enable-method = "psci";
  76                         i-cache-size = <0x8000>;
  77                         i-cache-line-size = <64>;
  78                         i-cache-sets = <256>;
  79                         d-cache-size = <0x8000>;
  80                         d-cache-line-size = <64>;
  81                         d-cache-sets = <128>;
  82                         next-level-cache = <&L2_0>;
  83                         operating-points-v2 = <&a53_opp_table>;
  84                         clocks = <&k3_clks 137 0>;
  85                 };
  86
  87                 cpu3: cpu@3 {
  88                         compatible = "arm,cortex-a53";
  89                         reg = <0x003>;
  90                         device_type = "cpu";
  91                         enable-method = "psci";
  92                         i-cache-size = <0x8000>;
  93                         i-cache-line-size = <64>;
  94                         i-cache-sets = <256>;
  95                         d-cache-size = <0x8000>;
  96                         d-cache-line-size = <64>;
  97                         d-cache-sets = <128>;
  98                         next-level-cache = <&L2_0>;
  99                         operating-points-v2 = <&a53_opp_table>;
 100                         clocks = <&k3_clks 138 0>;
 101                 };
 102         };
 103
 104         a53_opp_table: opp-table {
 105                 compatible = "operating-points-v2-ti-cpu";
 106                 opp-shared;
 107                 syscon = <&wkup_conf>;
 108
 109                 opp-200000000 {
 110                         opp-hz = /bits/ 64 <200000000>;
 111                         opp-supported-hw = <0x01 0x0007>;
 112                         clock-latency-ns = <6000000>;
 113                 };
 114
 115                 opp-400000000 {
 116                         opp-hz = /bits/ 64 <400000000>;
 117                         opp-supported-hw = <0x01 0x0007>;
 118                         clock-latency-ns = <6000000>;
 119                 };
 120
 121                 opp-600000000 {
 122                         opp-hz = /bits/ 64 <600000000>;
 123                         opp-supported-hw = <0x01 0x0007>;
 124                         clock-latency-ns = <6000000>;
 125                 };
 126
 127                 opp-800000000 {
 128                         opp-hz = /bits/ 64 <800000000>;
 129                         opp-supported-hw = <0x01 0x0007>;
 130                         clock-latency-ns = <6000000>;
 131                 };
 132
 133                 opp-1000000000 {
 134                         opp-hz = /bits/ 64 <1000000000>;
 135                         opp-supported-hw = <0x01 0x0006>;
 136                         clock-latency-ns = <6000000>;
 137                 };
 138
 139                 opp-1250000000 {
 140                         opp-hz = /bits/ 64 <1250000000>;
 141                         opp-supported-hw = <0x01 0x0004>;
 142                         clock-latency-ns = <6000000>;
 143                         opp-suspend;
 144                 };
 145         };
 146
 147         L2_0: l2-cache0 {
 148                 compatible = "cache";
 149                 cache-unified;
 150                 cache-level = <2>;
 151                 cache-size = <0x80000>;
 152                 cache-line-size = <64>;
 153                 cache-sets = <512>;
 154         };
 155 };