arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   4  */
   5
   6 #include <dt-bindings/clock/rk3399-cru.h>
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/interrupt-controller/irq.h>
  10 #include <dt-bindings/pinctrl/rockchip.h>
  11 #include <dt-bindings/power/rk3399-power.h>
  12 #include <dt-bindings/thermal/thermal.h>
  13
  14 / {
  15         compatible = "rockchip,rk3399";
  16
  17         interrupt-parent = <&gic>;
  18         #address-cells = <2>;
  19         #size-cells = <2>;
  20
  21         aliases {
  22                 ethernet0 = &gmac;
  23                 i2c0 = &i2c0;
  24                 i2c1 = &i2c1;
  25                 i2c2 = &i2c2;
  26                 i2c3 = &i2c3;
  27                 i2c4 = &i2c4;
  28                 i2c5 = &i2c5;
  29                 i2c6 = &i2c6;
  30                 i2c7 = &i2c7;
  31                 i2c8 = &i2c8;
  32                 serial0 = &uart0;
  33                 serial1 = &uart1;
  34                 serial2 = &uart2;
  35                 serial3 = &uart3;
  36                 serial4 = &uart4;
  37         };
  38
  39         cpus {
  40                 #address-cells = <2>;
  41                 #size-cells = <0>;
  42
  43                 cpu-map {
  44                         cluster0 {
  45                                 core0 {
  46                                         cpu = <&cpu_l0>;
  47                                 };
  48                                 core1 {
  49                                         cpu = <&cpu_l1>;
  50                                 };
  51                                 core2 {
  52                                         cpu = <&cpu_l2>;
  53                                 };
  54                                 core3 {
  55                                         cpu = <&cpu_l3>;
  56                                 };
  57                         };
  58
  59                         cluster1 {
  60                                 core0 {
  61                                         cpu = <&cpu_b0>;
  62                                 };
  63                                 core1 {
  64                                         cpu = <&cpu_b1>;
  65                                 };
  66                         };
  67                 };
  68
  69                 cpu_l0: cpu@0 {
  70                         device_type = "cpu";
  71                         compatible = "arm,cortex-a53", "arm,armv8";
  72                         reg = <0x0 0x0>;
  73                         enable-method = "psci";
  74                         clocks = <&cru ARMCLKL>;
  75                         #cooling-cells = <2>; /* min followed by max */
  76                         dynamic-power-coefficient = <100>;
  77                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
  78                 };
  79
  80                 cpu_l1: cpu@1 {
  81                         device_type = "cpu";
  82                         compatible = "arm,cortex-a53", "arm,armv8";
  83                         reg = <0x0 0x1>;
  84                         enable-method = "psci";
  85                         clocks = <&cru ARMCLKL>;
  86                         #cooling-cells = <2>; /* min followed by max */
  87                         dynamic-power-coefficient = <100>;
  88                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
  89                 };
  90
  91                 cpu_l2: cpu@2 {
  92                         device_type = "cpu";
  93                         compatible = "arm,cortex-a53", "arm,armv8";
  94                         reg = <0x0 0x2>;
  95                         enable-method = "psci";
  96                         clocks = <&cru ARMCLKL>;
  97                         #cooling-cells = <2>; /* min followed by max */
  98                         dynamic-power-coefficient = <100>;
  99                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 100                 };
 101
 102                 cpu_l3: cpu@3 {
 103                         device_type = "cpu";
 104                         compatible = "arm,cortex-a53", "arm,armv8";
 105                         reg = <0x0 0x3>;
 106                         enable-method = "psci";
 107                         clocks = <&cru ARMCLKL>;
 108                         #cooling-cells = <2>; /* min followed by max */
 109                         dynamic-power-coefficient = <100>;
 110                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 111                 };
 112
 113                 cpu_b0: cpu@100 {
 114                         device_type = "cpu";
 115                         compatible = "arm,cortex-a72", "arm,armv8";
 116                         reg = <0x0 0x100>;
 117                         enable-method = "psci";
 118                         clocks = <&cru ARMCLKB>;
 119                         #cooling-cells = <2>; /* min followed by max */
 120                         dynamic-power-coefficient = <436>;
 121                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 122                 };
 123
 124                 cpu_b1: cpu@101 {
 125                         device_type = "cpu";
 126                         compatible = "arm,cortex-a72", "arm,armv8";
 127                         reg = <0x0 0x101>;
 128                         enable-method = "psci";
 129                         clocks = <&cru ARMCLKB>;
 130                         #cooling-cells = <2>; /* min followed by max */
 131                         dynamic-power-coefficient = <436>;
 132                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 133                 };
 134
 135                 idle-states {
 136                         entry-method = "psci";
 137
 138                         CPU_SLEEP: cpu-sleep {
 139                                 compatible = "arm,idle-state";
 140                                 local-timer-stop;
 141                                 arm,psci-suspend-param = <0x0010000>;
 142                                 entry-latency-us = <120>;
 143                                 exit-latency-us = <250>;
 144                                 min-residency-us = <900>;
 145                         };
 146
 147                         CLUSTER_SLEEP: cluster-sleep {
 148                                 compatible = "arm,idle-state";
 149                                 local-timer-stop;
 150                                 arm,psci-suspend-param = <0x1010000>;
 151                                 entry-latency-us = <400>;
 152                                 exit-latency-us = <500>;
 153                                 min-residency-us = <2000>;
 154                         };
 155                 };
 156         };
 157
 158         display-subsystem {
 159                 compatible = "rockchip,display-subsystem";
 160                 ports = <&vopl_out>, <&vopb_out>;
 161         };
 162
 163         pmu_a53 {
 164                 compatible = "arm,cortex-a53-pmu";
 165                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
 166         };
 167
 168         pmu_a72 {
 169                 compatible = "arm,cortex-a72-pmu";
 170                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
 171         };
 172
 173         psci {
 174                 compatible = "arm,psci-1.0";
 175                 method = "smc";
 176         };
 177
 178         timer {
 179                 compatible = "arm,armv8-timer";
 180                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
 181                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
 182                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
 183                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
 184                 arm,no-tick-in-suspend;
 185         };
 186
 187         xin24m: xin24m {
 188                 compatible = "fixed-clock";
 189                 clock-frequency = <24000000>;
 190                 clock-output-names = "xin24m";
 191                 #clock-cells = <0>;
 192         };
 193
 194         amba {
 195                 compatible = "simple-bus";
 196                 #address-cells = <2>;
 197                 #size-cells = <2>;
 198                 ranges;
 199
 200                 dmac_bus: dma-controller@ff6d0000 {
 201                         compatible = "arm,pl330", "arm,primecell";
 202                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 203                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
 204                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
 205                         #dma-cells = <1>;
 206                         clocks = <&cru ACLK_DMAC0_PERILP>;
 207                         clock-names = "apb_pclk";
 208                 };
 209
 210                 dmac_peri: dma-controller@ff6e0000 {
 211                         compatible = "arm,pl330", "arm,primecell";
 212                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 213                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
 214                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
 215                         #dma-cells = <1>;
 216                         clocks = <&cru ACLK_DMAC1_PERILP>;
 217                         clock-names = "apb_pclk";
 218                 };
 219         };
 220
 221         pcie0: pcie@f8000000 {
 222                 compatible = "rockchip,rk3399-pcie";
 223                 reg = <0x0 0xf8000000 0x0 0x2000000>,
 224                       <0x0 0xfd000000 0x0 0x1000000>;
 225                 reg-names = "axi-base", "apb-base";
 226                 #address-cells = <3>;
 227                 #size-cells = <2>;
 228                 #interrupt-cells = <1>;
 229                 aspm-no-l0s;
 230                 bus-range = <0x0 0x1f>;
 231                 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
 232                          <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
 233                 clock-names = "aclk", "aclk-perf",
 234                               "hclk", "pm";
 235                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
 236                              <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
 237                              <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
 238                 interrupt-names = "sys", "legacy", "client";
 239                 interrupt-map-mask = <0 0 0 7>;
 240                 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
 241                                 <0 0 0 2 &pcie0_intc 1>,
 242                                 <0 0 0 3 &pcie0_intc 2>,
 243                                 <0 0 0 4 &pcie0_intc 3>;
 244                 linux,pci-domain = <0>;
 245                 max-link-speed = <1>;
 246                 msi-map = <0x0 &its 0x0 0x1000>;
 247                 phys = <&pcie_phy 0>, <&pcie_phy 1>,
 248                        <&pcie_phy 2>, <&pcie_phy 3>;
 249                 phy-names = "pcie-phy-0", "pcie-phy-1",
 250                             "pcie-phy-2", "pcie-phy-3";
 251                 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000
 252                           0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>;
 253                 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
 254                          <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
 255                          <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
 256                          <&cru SRST_A_PCIE>;
 257                 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
 258                               "pm", "pclk", "aclk";
 259                 status = "disabled";
 260
 261                 pcie0_intc: interrupt-controller {
 262                         interrupt-controller;
 263                         #address-cells = <0>;
 264                         #interrupt-cells = <1>;
 265                 };
 266         };
 267
 268         gmac: ethernet@fe300000 {
 269                 compatible = "rockchip,rk3399-gmac";
 270                 reg = <0x0 0xfe300000 0x0 0x10000>;
 271                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
 272                 interrupt-names = "macirq";
 273                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 274                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 275                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 276                          <&cru PCLK_GMAC>;
 277                 clock-names = "stmmaceth", "mac_clk_rx",
 278                               "mac_clk_tx", "clk_mac_ref",
 279                               "clk_mac_refout", "aclk_mac",
 280                               "pclk_mac";
 281                 power-domains = <&power RK3399_PD_GMAC>;
 282                 resets = <&cru SRST_A_GMAC>;
 283                 reset-names = "stmmaceth";
 284                 rockchip,grf = <&grf>;
 285                 status = "disabled";
 286         };
 287
 288         sdio0: dwmmc@fe310000 {
 289                 compatible = "rockchip,rk3399-dw-mshc",
 290                              "rockchip,rk3288-dw-mshc";
 291                 reg = <0x0 0xfe310000 0x0 0x4000>;
 292                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
 293                 max-frequency = <150000000>;
 294                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 295                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 296                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 297                 fifo-depth = <0x100>;
 298                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
 299                 resets = <&cru SRST_SDIO0>;
 300                 reset-names = "reset";
 301                 status = "disabled";
 302         };
 303
 304         sdmmc: dwmmc@fe320000 {
 305                 compatible = "rockchip,rk3399-dw-mshc",
 306                              "rockchip,rk3288-dw-mshc";
 307                 reg = <0x0 0xfe320000 0x0 0x4000>;
 308                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
 309                 max-frequency = <150000000>;
 310                 assigned-clocks = <&cru HCLK_SD>;
 311                 assigned-clock-rates = <200000000>;
 312                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 313                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 314                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 315                 fifo-depth = <0x100>;
 316                 power-domains = <&power RK3399_PD_SD>;
 317                 resets = <&cru SRST_SDMMC>;
 318                 reset-names = "reset";
 319                 status = "disabled";
 320         };
 321
 322         sdhci: sdhci@fe330000 {
 323                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 324                 reg = <0x0 0xfe330000 0x0 0x10000>;
 325                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
 326                 arasan,soc-ctl-syscon = <&grf>;
 327                 assigned-clocks = <&cru SCLK_EMMC>;
 328                 assigned-clock-rates = <200000000>;
 329                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 330                 clock-names = "clk_xin", "clk_ahb";
 331                 clock-output-names = "emmc_cardclock";
 332                 #clock-cells = <0>;
 333                 phys = <&emmc_phy>;
 334                 phy-names = "phy_arasan";
 335                 power-domains = <&power RK3399_PD_EMMC>;
 336                 status = "disabled";
 337         };
 338
 339         usb_host0_ehci: usb@fe380000 {
 340                 compatible = "generic-ehci";
 341                 reg = <0x0 0xfe380000 0x0 0x20000>;
 342                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
 343                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 344                          <&u2phy0>;
 345                 clock-names = "usbhost", "arbiter",
 346                               "utmi";
 347                 phys = <&u2phy0_host>;
 348                 phy-names = "usb";
 349                 status = "disabled";
 350         };
 351
 352         usb_host0_ohci: usb@fe3a0000 {
 353                 compatible = "generic-ohci";
 354                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 355                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
 356                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 357                          <&u2phy0>;
 358                 clock-names = "usbhost", "arbiter",
 359                               "utmi";
 360                 phys = <&u2phy0_host>;
 361                 phy-names = "usb";
 362                 status = "disabled";
 363         };
 364
 365         usb_host1_ehci: usb@fe3c0000 {
 366                 compatible = "generic-ehci";
 367                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 368                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
 369                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 370                          <&u2phy1>;
 371                 clock-names = "usbhost", "arbiter",
 372                               "utmi";
 373                 phys = <&u2phy1_host>;
 374                 phy-names = "usb";
 375                 status = "disabled";
 376         };
 377
 378         usb_host1_ohci: usb@fe3e0000 {
 379                 compatible = "generic-ohci";
 380                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 381                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
 382                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 383                          <&u2phy1>;
 384                 clock-names = "usbhost", "arbiter",
 385                               "utmi";
 386                 phys = <&u2phy1_host>;
 387                 phy-names = "usb";
 388                 status = "disabled";
 389         };
 390
 391         usbdrd3_0: usb@fe800000 {
 392                 compatible = "rockchip,rk3399-dwc3";
 393                 #address-cells = <2>;
 394                 #size-cells = <2>;
 395                 ranges;
 396                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
 397                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 398                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 399                 clock-names = "ref_clk", "suspend_clk",
 400                               "bus_clk", "aclk_usb3_rksoc_axi_perf",
 401                               "aclk_usb3", "grf_clk";
 402                 resets = <&cru SRST_A_USB3_OTG0>;
 403                 reset-names = "usb3-otg";
 404                 status = "disabled";
 405
 406                 usbdrd_dwc3_0: dwc3 {
 407                         compatible = "snps,dwc3";
 408                         reg = <0x0 0xfe800000 0x0 0x100000>;
 409                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
 410                         dr_mode = "otg";
 411                         phys = <&u2phy0_otg>, <&tcphy0_usb3>;
 412                         phy-names = "usb2-phy", "usb3-phy";
 413                         phy_type = "utmi_wide";
 414                         snps,dis_enblslpm_quirk;
 415                         snps,dis-u2-freeclk-exists-quirk;
 416                         snps,dis_u2_susphy_quirk;
 417                         snps,dis-del-phy-power-chg-quirk;
 418                         snps,dis-tx-ipgap-linecheck-quirk;
 419                         power-domains = <&power RK3399_PD_USB3>;
 420                         status = "disabled";
 421                 };
 422         };
 423
 424         usbdrd3_1: usb@fe900000 {
 425                 compatible = "rockchip,rk3399-dwc3";
 426                 #address-cells = <2>;
 427                 #size-cells = <2>;
 428                 ranges;
 429                 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
 430                          <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 431                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 432                 clock-names = "ref_clk", "suspend_clk",
 433                               "bus_clk", "aclk_usb3_rksoc_axi_perf",
 434                               "aclk_usb3", "grf_clk";
 435                 resets = <&cru SRST_A_USB3_OTG1>;
 436                 reset-names = "usb3-otg";
 437                 status = "disabled";
 438
 439                 usbdrd_dwc3_1: dwc3 {
 440                         compatible = "snps,dwc3";
 441                         reg = <0x0 0xfe900000 0x0 0x100000>;
 442                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
 443                         dr_mode = "otg";
 444                         phys = <&u2phy1_otg>, <&tcphy1_usb3>;
 445                         phy-names = "usb2-phy", "usb3-phy";
 446                         phy_type = "utmi_wide";
 447                         snps,dis_enblslpm_quirk;
 448                         snps,dis-u2-freeclk-exists-quirk;
 449                         snps,dis_u2_susphy_quirk;
 450                         snps,dis-del-phy-power-chg-quirk;
 451                         snps,dis-tx-ipgap-linecheck-quirk;
 452                         power-domains = <&power RK3399_PD_USB3>;
 453                         status = "disabled";
 454                 };
 455         };
 456
 457         cdn_dp: dp@fec00000 {
 458                 compatible = "rockchip,rk3399-cdn-dp";
 459                 reg = <0x0 0xfec00000 0x0 0x100000>;
 460                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 461                 assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>;
 462                 assigned-clock-rates = <100000000>, <200000000>;
 463                 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
 464                          <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
 465                 clock-names = "core-clk", "pclk", "spdif", "grf";
 466                 phys = <&tcphy0_dp>, <&tcphy1_dp>;
 467                 power-domains = <&power RK3399_PD_HDCP>;
 468                 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
 469                          <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
 470                 reset-names = "spdif", "dptx", "apb", "core";
 471                 rockchip,grf = <&grf>;
 472                 #sound-dai-cells = <1>;
 473                 status = "disabled";
 474
 475                 ports {
 476                         dp_in: port {
 477                                 #address-cells = <1>;
 478                                 #size-cells = <0>;
 479
 480                                 dp_in_vopb: endpoint@0 {
 481                                         reg = <0>;
 482                                         remote-endpoint = <&vopb_out_dp>;
 483                                 };
 484
 485                                 dp_in_vopl: endpoint@1 {
 486                                         reg = <1>;
 487                                         remote-endpoint = <&vopl_out_dp>;
 488                                 };
 489                         };
 490                 };
 491         };
 492
 493         gic: interrupt-controller@fee00000 {
 494                 compatible = "arm,gic-v3";
 495                 #interrupt-cells = <4>;
 496                 #address-cells = <2>;
 497                 #size-cells = <2>;
 498                 ranges;
 499                 interrupt-controller;
 500
 501                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 502                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 503                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 504                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 505                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 506                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 507                 its: interrupt-controller@fee20000 {
 508                         compatible = "arm,gic-v3-its";
 509                         msi-controller;
 510                         reg = <0x0 0xfee20000 0x0 0x20000>;
 511                 };
 512
 513                 ppi-partitions {
 514                         ppi_cluster0: interrupt-partition-0 {
 515                                 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
 516                         };
 517
 518                         ppi_cluster1: interrupt-partition-1 {
 519                                 affinity = <&cpu_b0 &cpu_b1>;
 520                         };
 521                 };
 522         };
 523
 524         saradc: saradc@ff100000 {
 525                 compatible = "rockchip,rk3399-saradc";
 526                 reg = <0x0 0xff100000 0x0 0x100>;
 527                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
 528                 #io-channel-cells = <1>;
 529                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 530                 clock-names = "saradc", "apb_pclk";
 531                 resets = <&cru SRST_P_SARADC>;
 532                 reset-names = "saradc-apb";
 533                 status = "disabled";
 534         };
 535
 536         i2c1: i2c@ff110000 {
 537                 compatible = "rockchip,rk3399-i2c";
 538                 reg = <0x0 0xff110000 0x0 0x1000>;
 539                 assigned-clocks = <&cru SCLK_I2C1>;
 540                 assigned-clock-rates = <200000000>;
 541                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 542                 clock-names = "i2c", "pclk";
 543                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
 544                 pinctrl-names = "default";
 545                 pinctrl-0 = <&i2c1_xfer>;
 546                 #address-cells = <1>;
 547                 #size-cells = <0>;
 548                 status = "disabled";
 549         };
 550
 551         i2c2: i2c@ff120000 {
 552                 compatible = "rockchip,rk3399-i2c";
 553                 reg = <0x0 0xff120000 0x0 0x1000>;
 554                 assigned-clocks = <&cru SCLK_I2C2>;
 555                 assigned-clock-rates = <200000000>;
 556                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 557                 clock-names = "i2c", "pclk";
 558                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
 559                 pinctrl-names = "default";
 560                 pinctrl-0 = <&i2c2_xfer>;
 561                 #address-cells = <1>;
 562                 #size-cells = <0>;
 563                 status = "disabled";
 564         };
 565
 566         i2c3: i2c@ff130000 {
 567                 compatible = "rockchip,rk3399-i2c";
 568                 reg = <0x0 0xff130000 0x0 0x1000>;
 569                 assigned-clocks = <&cru SCLK_I2C3>;
 570                 assigned-clock-rates = <200000000>;
 571                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 572                 clock-names = "i2c", "pclk";
 573                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
 574                 pinctrl-names = "default";
 575                 pinctrl-0 = <&i2c3_xfer>;
 576                 #address-cells = <1>;
 577                 #size-cells = <0>;
 578                 status = "disabled";
 579         };
 580
 581         i2c5: i2c@ff140000 {
 582                 compatible = "rockchip,rk3399-i2c";
 583                 reg = <0x0 0xff140000 0x0 0x1000>;
 584                 assigned-clocks = <&cru SCLK_I2C5>;
 585                 assigned-clock-rates = <200000000>;
 586                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 587                 clock-names = "i2c", "pclk";
 588                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
 589                 pinctrl-names = "default";
 590                 pinctrl-0 = <&i2c5_xfer>;
 591                 #address-cells = <1>;
 592                 #size-cells = <0>;
 593                 status = "disabled";
 594         };
 595
 596         i2c6: i2c@ff150000 {
 597                 compatible = "rockchip,rk3399-i2c";
 598                 reg = <0x0 0xff150000 0x0 0x1000>;
 599                 assigned-clocks = <&cru SCLK_I2C6>;
 600                 assigned-clock-rates = <200000000>;
 601                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 602                 clock-names = "i2c", "pclk";
 603                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
 604                 pinctrl-names = "default";
 605                 pinctrl-0 = <&i2c6_xfer>;
 606                 #address-cells = <1>;
 607                 #size-cells = <0>;
 608                 status = "disabled";
 609         };
 610
 611         i2c7: i2c@ff160000 {
 612                 compatible = "rockchip,rk3399-i2c";
 613                 reg = <0x0 0xff160000 0x0 0x1000>;
 614                 assigned-clocks = <&cru SCLK_I2C7>;
 615                 assigned-clock-rates = <200000000>;
 616                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 617                 clock-names = "i2c", "pclk";
 618                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
 619                 pinctrl-names = "default";
 620                 pinctrl-0 = <&i2c7_xfer>;
 621                 #address-cells = <1>;
 622                 #size-cells = <0>;
 623                 status = "disabled";
 624         };
 625
 626         uart0: serial@ff180000 {
 627                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 628                 reg = <0x0 0xff180000 0x0 0x100>;
 629                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 630                 clock-names = "baudclk", "apb_pclk";
 631                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
 632                 reg-shift = <2>;
 633                 reg-io-width = <4>;
 634                 pinctrl-names = "default";
 635                 pinctrl-0 = <&uart0_xfer>;
 636                 status = "disabled";
 637         };
 638
 639         uart1: serial@ff190000 {
 640                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 641                 reg = <0x0 0xff190000 0x0 0x100>;
 642                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 643                 clock-names = "baudclk", "apb_pclk";
 644                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
 645                 reg-shift = <2>;
 646                 reg-io-width = <4>;
 647                 pinctrl-names = "default";
 648                 pinctrl-0 = <&uart1_xfer>;
 649                 status = "disabled";
 650         };
 651
 652         uart2: serial@ff1a0000 {
 653                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 654                 reg = <0x0 0xff1a0000 0x0 0x100>;
 655                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 656                 clock-names = "baudclk", "apb_pclk";
 657                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
 658                 reg-shift = <2>;
 659                 reg-io-width = <4>;
 660                 pinctrl-names = "default";
 661                 pinctrl-0 = <&uart2c_xfer>;
 662                 status = "disabled";
 663         };
 664
 665         uart3: serial@ff1b0000 {
 666                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 667                 reg = <0x0 0xff1b0000 0x0 0x100>;
 668                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 669                 clock-names = "baudclk", "apb_pclk";
 670                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
 671                 reg-shift = <2>;
 672                 reg-io-width = <4>;
 673                 pinctrl-names = "default";
 674                 pinctrl-0 = <&uart3_xfer>;
 675                 status = "disabled";
 676         };
 677
 678         spi0: spi@ff1c0000 {
 679                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 680                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 681                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 682                 clock-names = "spiclk", "apb_pclk";
 683                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
 684                 dmas = <&dmac_peri 10>, <&dmac_peri 11>;
 685                 dma-names = "tx", "rx";
 686                 pinctrl-names = "default";
 687                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 688                 #address-cells = <1>;
 689                 #size-cells = <0>;
 690                 status = "disabled";
 691         };
 692
 693         spi1: spi@ff1d0000 {
 694                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 695                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 696                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 697                 clock-names = "spiclk", "apb_pclk";
 698                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
 699                 dmas = <&dmac_peri 12>, <&dmac_peri 13>;
 700                 dma-names = "tx", "rx";
 701                 pinctrl-names = "default";
 702                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 703                 #address-cells = <1>;
 704                 #size-cells = <0>;
 705                 status = "disabled";
 706         };
 707
 708         spi2: spi@ff1e0000 {
 709                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 710                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 711                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 712                 clock-names = "spiclk", "apb_pclk";
 713                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
 714                 dmas = <&dmac_peri 14>, <&dmac_peri 15>;
 715                 dma-names = "tx", "rx";
 716                 pinctrl-names = "default";
 717                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 718                 #address-cells = <1>;
 719                 #size-cells = <0>;
 720                 status = "disabled";
 721         };
 722
 723         spi4: spi@ff1f0000 {
 724                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 725                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 726                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 727                 clock-names = "spiclk", "apb_pclk";
 728                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
 729                 dmas = <&dmac_peri 18>, <&dmac_peri 19>;
 730                 dma-names = "tx", "rx";
 731                 pinctrl-names = "default";
 732                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 733                 #address-cells = <1>;
 734                 #size-cells = <0>;
 735                 status = "disabled";
 736         };
 737
 738         spi5: spi@ff200000 {
 739                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 740                 reg = <0x0 0xff200000 0x0 0x1000>;
 741                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 742                 clock-names = "spiclk", "apb_pclk";
 743                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
 744                 dmas = <&dmac_bus 8>, <&dmac_bus 9>;
 745                 dma-names = "tx", "rx";
 746                 pinctrl-names = "default";
 747                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 748                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
 749                 #address-cells = <1>;
 750                 #size-cells = <0>;
 751                 status = "disabled";
 752         };
 753
 754         thermal_zones: thermal-zones {
 755                 cpu_thermal: cpu {
 756                         polling-delay-passive = <100>;
 757                         polling-delay = <1000>;
 758
 759                         thermal-sensors = <&tsadc 0>;
 760
 761                         trips {
 762                                 cpu_alert0: cpu_alert0 {
 763                                         temperature = <70000>;
 764                                         hysteresis = <2000>;
 765                                         type = "passive";
 766                                 };
 767                                 cpu_alert1: cpu_alert1 {
 768                                         temperature = <75000>;
 769                                         hysteresis = <2000>;
 770                                         type = "passive";
 771                                 };
 772                                 cpu_crit: cpu_crit {
 773                                         temperature = <95000>;
 774                                         hysteresis = <2000>;
 775                                         type = "critical";
 776                                 };
 777                         };
 778
 779                         cooling-maps {
 780                                 map0 {
 781                                         trip = <&cpu_alert0>;
 782                                         cooling-device =
 783                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 784                                                 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 785                                 };
 786                                 map1 {
 787                                         trip = <&cpu_alert1>;
 788                                         cooling-device =
 789                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 790                                                 <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 791                                                 <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 792                                                 <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 793                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 794                                                 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 795                                 };
 796                         };
 797                 };
 798
 799                 gpu_thermal: gpu {
 800                         polling-delay-passive = <100>;
 801                         polling-delay = <1000>;
 802
 803                         thermal-sensors = <&tsadc 1>;
 804
 805                         trips {
 806                                 gpu_alert0: gpu_alert0 {
 807                                         temperature = <75000>;
 808                                         hysteresis = <2000>;
 809                                         type = "passive";
 810                                 };
 811                                 gpu_crit: gpu_crit {
 812                                         temperature = <95000>;
 813                                         hysteresis = <2000>;
 814                                         type = "critical";
 815                                 };
 816                         };
 817
 818                         cooling-maps {
 819                                 map0 {
 820                                         trip = <&gpu_alert0>;
 821                                         cooling-device =
 822                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 823                                                 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 824                                 };
 825                         };
 826                 };
 827         };
 828
 829         tsadc: tsadc@ff260000 {
 830                 compatible = "rockchip,rk3399-tsadc";
 831                 reg = <0x0 0xff260000 0x0 0x100>;
 832                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
 833                 assigned-clocks = <&cru SCLK_TSADC>;
 834                 assigned-clock-rates = <750000>;
 835                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 836                 clock-names = "tsadc", "apb_pclk";
 837                 resets = <&cru SRST_TSADC>;
 838                 reset-names = "tsadc-apb";
 839                 rockchip,grf = <&grf>;
 840                 rockchip,hw-tshut-temp = <95000>;
 841                 pinctrl-names = "init", "default", "sleep";
 842                 pinctrl-0 = <&otp_gpio>;
 843                 pinctrl-1 = <&otp_out>;
 844                 pinctrl-2 = <&otp_gpio>;
 845                 #thermal-sensor-cells = <1>;
 846                 status = "disabled";
 847         };
 848
 849         qos_emmc: qos@ffa58000 {
 850                 compatible = "syscon";
 851                 reg = <0x0 0xffa58000 0x0 0x20>;
 852         };
 853
 854         qos_gmac: qos@ffa5c000 {
 855                 compatible = "syscon";
 856                 reg = <0x0 0xffa5c000 0x0 0x20>;
 857         };
 858
 859         qos_pcie: qos@ffa60080 {
 860                 compatible = "syscon";
 861                 reg = <0x0 0xffa60080 0x0 0x20>;
 862         };
 863
 864         qos_usb_host0: qos@ffa60100 {
 865                 compatible = "syscon";
 866                 reg = <0x0 0xffa60100 0x0 0x20>;
 867         };
 868
 869         qos_usb_host1: qos@ffa60180 {
 870                 compatible = "syscon";
 871                 reg = <0x0 0xffa60180 0x0 0x20>;
 872         };
 873
 874         qos_usb_otg0: qos@ffa70000 {
 875                 compatible = "syscon";
 876                 reg = <0x0 0xffa70000 0x0 0x20>;
 877         };
 878
 879         qos_usb_otg1: qos@ffa70080 {
 880                 compatible = "syscon";
 881                 reg = <0x0 0xffa70080 0x0 0x20>;
 882         };
 883
 884         qos_sd: qos@ffa74000 {
 885                 compatible = "syscon";
 886                 reg = <0x0 0xffa74000 0x0 0x20>;
 887         };
 888
 889         qos_sdioaudio: qos@ffa76000 {
 890                 compatible = "syscon";
 891                 reg = <0x0 0xffa76000 0x0 0x20>;
 892         };
 893
 894         qos_hdcp: qos@ffa90000 {
 895                 compatible = "syscon";
 896                 reg = <0x0 0xffa90000 0x0 0x20>;
 897         };
 898
 899         qos_iep: qos@ffa98000 {
 900                 compatible = "syscon";
 901                 reg = <0x0 0xffa98000 0x0 0x20>;
 902         };
 903
 904         qos_isp0_m0: qos@ffaa0000 {
 905                 compatible = "syscon";
 906                 reg = <0x0 0xffaa0000 0x0 0x20>;
 907         };
 908
 909         qos_isp0_m1: qos@ffaa0080 {
 910                 compatible = "syscon";
 911                 reg = <0x0 0xffaa0080 0x0 0x20>;
 912         };
 913
 914         qos_isp1_m0: qos@ffaa8000 {
 915                 compatible = "syscon";
 916                 reg = <0x0 0xffaa8000 0x0 0x20>;
 917         };
 918
 919         qos_isp1_m1: qos@ffaa8080 {
 920                 compatible = "syscon";
 921                 reg = <0x0 0xffaa8080 0x0 0x20>;
 922         };
 923
 924         qos_rga_r: qos@ffab0000 {
 925                 compatible = "syscon";
 926                 reg = <0x0 0xffab0000 0x0 0x20>;
 927         };
 928
 929         qos_rga_w: qos@ffab0080 {
 930                 compatible = "syscon";
 931                 reg = <0x0 0xffab0080 0x0 0x20>;
 932         };
 933
 934         qos_video_m0: qos@ffab8000 {
 935                 compatible = "syscon";
 936                 reg = <0x0 0xffab8000 0x0 0x20>;
 937         };
 938
 939         qos_video_m1_r: qos@ffac0000 {
 940                 compatible = "syscon";
 941                 reg = <0x0 0xffac0000 0x0 0x20>;
 942         };
 943
 944         qos_video_m1_w: qos@ffac0080 {
 945                 compatible = "syscon";
 946                 reg = <0x0 0xffac0080 0x0 0x20>;
 947         };
 948
 949         qos_vop_big_r: qos@ffac8000 {
 950                 compatible = "syscon";
 951                 reg = <0x0 0xffac8000 0x0 0x20>;
 952         };
 953
 954         qos_vop_big_w: qos@ffac8080 {
 955                 compatible = "syscon";
 956                 reg = <0x0 0xffac8080 0x0 0x20>;
 957         };
 958
 959         qos_vop_little: qos@ffad0000 {
 960                 compatible = "syscon";
 961                 reg = <0x0 0xffad0000 0x0 0x20>;
 962         };
 963
 964         qos_perihp: qos@ffad8080 {
 965                 compatible = "syscon";
 966                 reg = <0x0 0xffad8080 0x0 0x20>;
 967         };
 968
 969         qos_gpu: qos@ffae0000 {
 970                 compatible = "syscon";
 971                 reg = <0x0 0xffae0000 0x0 0x20>;
 972         };
 973
 974         pmu: power-management@ff310000 {
 975                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 976                 reg = <0x0 0xff310000 0x0 0x1000>;
 977
 978                 /*
 979                  * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
 980                  * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
 981                  * Some of the power domains are grouped together for every
 982                  * voltage domain.
 983                  * The detail contents as below.
 984                  */
 985                 power: power-controller {
 986                         compatible = "rockchip,rk3399-power-controller";
 987                         #power-domain-cells = <1>;
 988                         #address-cells = <1>;
 989                         #size-cells = <0>;
 990
 991                         /* These power domains are grouped by VD_CENTER */
 992                         pd_iep@RK3399_PD_IEP {
 993                                 reg = <RK3399_PD_IEP>;
 994                                 clocks = <&cru ACLK_IEP>,
 995                                          <&cru HCLK_IEP>;
 996                                 pm_qos = <&qos_iep>;
 997                         };
 998                         pd_rga@RK3399_PD_RGA {
 999                                 reg = <RK3399_PD_RGA>;
1000                                 clocks = <&cru ACLK_RGA>,
1001                                          <&cru HCLK_RGA>;
1002                                 pm_qos = <&qos_rga_r>,
1003                                          <&qos_rga_w>;
1004                         };
1005                         pd_vcodec@RK3399_PD_VCODEC {
1006                                 reg = <RK3399_PD_VCODEC>;
1007                                 clocks = <&cru ACLK_VCODEC>,
1008                                          <&cru HCLK_VCODEC>;
1009                                 pm_qos = <&qos_video_m0>;
1010                         };
1011                         pd_vdu@RK3399_PD_VDU {
1012                                 reg = <RK3399_PD_VDU>;
1013                                 clocks = <&cru ACLK_VDU>,
1014                                          <&cru HCLK_VDU>;
1015                                 pm_qos = <&qos_video_m1_r>,
1016                                          <&qos_video_m1_w>;
1017                         };
1018
1019                         /* These power domains are grouped by VD_GPU */
1020                         pd_gpu@RK3399_PD_GPU {
1021                                 reg = <RK3399_PD_GPU>;
1022                                 clocks = <&cru ACLK_GPU>;
1023                                 pm_qos = <&qos_gpu>;
1024                         };
1025
1026                         /* These power domains are grouped by VD_LOGIC */
1027                         pd_edp@RK3399_PD_EDP {
1028                                 reg = <RK3399_PD_EDP>;
1029                                 clocks = <&cru PCLK_EDP_CTRL>;
1030                         };
1031                         pd_emmc@RK3399_PD_EMMC {
1032                                 reg = <RK3399_PD_EMMC>;
1033                                 clocks = <&cru ACLK_EMMC>;
1034                                 pm_qos = <&qos_emmc>;
1035                         };
1036                         pd_gmac@RK3399_PD_GMAC {
1037                                 reg = <RK3399_PD_GMAC>;
1038                                 clocks = <&cru ACLK_GMAC>,
1039                                          <&cru PCLK_GMAC>;
1040                                 pm_qos = <&qos_gmac>;
1041                         };
1042                         pd_sd@RK3399_PD_SD {
1043                                 reg = <RK3399_PD_SD>;
1044                                 clocks = <&cru HCLK_SDMMC>,
1045                                          <&cru SCLK_SDMMC>;
1046                                 pm_qos = <&qos_sd>;
1047                         };
1048                         pd_sdioaudio@RK3399_PD_SDIOAUDIO {
1049                                 reg = <RK3399_PD_SDIOAUDIO>;
1050                                 clocks = <&cru HCLK_SDIO>;
1051                                 pm_qos = <&qos_sdioaudio>;
1052                         };
1053                         pd_usb3@RK3399_PD_USB3 {
1054                                 reg = <RK3399_PD_USB3>;
1055                                 clocks = <&cru ACLK_USB3>;
1056                                 pm_qos = <&qos_usb_otg0>,
1057                                          <&qos_usb_otg1>;
1058                         };
1059                         pd_vio@RK3399_PD_VIO {
1060                                 reg = <RK3399_PD_VIO>;
1061                                 #address-cells = <1>;
1062                                 #size-cells = <0>;
1063
1064                                 pd_hdcp@RK3399_PD_HDCP {
1065                                         reg = <RK3399_PD_HDCP>;
1066                                         clocks = <&cru ACLK_HDCP>,
1067                                                  <&cru HCLK_HDCP>,
1068                                                  <&cru PCLK_HDCP>;
1069                                         pm_qos = <&qos_hdcp>;
1070                                 };
1071                                 pd_isp0@RK3399_PD_ISP0 {
1072                                         reg = <RK3399_PD_ISP0>;
1073                                         clocks = <&cru ACLK_ISP0>,
1074                                                  <&cru HCLK_ISP0>;
1075                                         pm_qos = <&qos_isp0_m0>,
1076                                                  <&qos_isp0_m1>;
1077                                 };
1078                                 pd_isp1@RK3399_PD_ISP1 {
1079                                         reg = <RK3399_PD_ISP1>;
1080                                         clocks = <&cru ACLK_ISP1>,
1081                                                  <&cru HCLK_ISP1>;
1082                                         pm_qos = <&qos_isp1_m0>,
1083                                                  <&qos_isp1_m1>;
1084                                 };
1085                                 pd_tcpc0@RK3399_PD_TCPC0 {
1086                                         reg = <RK3399_PD_TCPD0>;
1087                                         clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1088                                                  <&cru SCLK_UPHY0_TCPDPHY_REF>;
1089                                 };
1090                                 pd_tcpc1@RK3399_PD_TCPC1 {
1091                                         reg = <RK3399_PD_TCPD1>;
1092                                         clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1093                                                  <&cru SCLK_UPHY1_TCPDPHY_REF>;
1094                                 };
1095                                 pd_vo@RK3399_PD_VO {
1096                                         reg = <RK3399_PD_VO>;
1097                                         #address-cells = <1>;
1098                                         #size-cells = <0>;
1099
1100                                         pd_vopb@RK3399_PD_VOPB {
1101                                                 reg = <RK3399_PD_VOPB>;
1102                                                 clocks = <&cru ACLK_VOP0>,
1103                                                          <&cru HCLK_VOP0>;
1104                                                 pm_qos = <&qos_vop_big_r>,
1105                                                          <&qos_vop_big_w>;
1106                                         };
1107                                         pd_vopl@RK3399_PD_VOPL {
1108                                                 reg = <RK3399_PD_VOPL>;
1109                                                 clocks = <&cru ACLK_VOP1>,
1110                                                          <&cru HCLK_VOP1>;
1111                                                 pm_qos = <&qos_vop_little>;
1112                                         };
1113                                 };
1114                         };
1115                 };
1116         };
1117
1118         pmugrf: syscon@ff320000 {
1119                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1120                 reg = <0x0 0xff320000 0x0 0x1000>;
1121                 #address-cells = <1>;
1122                 #size-cells = <1>;
1123
1124                 pmu_io_domains: io-domains {
1125                         compatible = "rockchip,rk3399-pmu-io-voltage-domain";
1126                         status = "disabled";
1127                 };
1128         };
1129
1130         spi3: spi@ff350000 {
1131                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1132                 reg = <0x0 0xff350000 0x0 0x1000>;
1133                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1134                 clock-names = "spiclk", "apb_pclk";
1135                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1136                 pinctrl-names = "default";
1137                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1138                 #address-cells = <1>;
1139                 #size-cells = <0>;
1140                 status = "disabled";
1141         };
1142
1143         uart4: serial@ff370000 {
1144                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1145                 reg = <0x0 0xff370000 0x0 0x100>;
1146                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1147                 clock-names = "baudclk", "apb_pclk";
1148                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1149                 reg-shift = <2>;
1150                 reg-io-width = <4>;
1151                 pinctrl-names = "default";
1152                 pinctrl-0 = <&uart4_xfer>;
1153                 status = "disabled";
1154         };
1155
1156         i2c0: i2c@ff3c0000 {
1157                 compatible = "rockchip,rk3399-i2c";
1158                 reg = <0x0 0xff3c0000 0x0 0x1000>;
1159                 assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
1160                 assigned-clock-rates = <200000000>;
1161                 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
1162                 clock-names = "i2c", "pclk";
1163                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
1164                 pinctrl-names = "default";
1165                 pinctrl-0 = <&i2c0_xfer>;
1166                 #address-cells = <1>;
1167                 #size-cells = <0>;
1168                 status = "disabled";
1169         };
1170
1171         i2c4: i2c@ff3d0000 {
1172                 compatible = "rockchip,rk3399-i2c";
1173                 reg = <0x0 0xff3d0000 0x0 0x1000>;
1174                 assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
1175                 assigned-clock-rates = <200000000>;
1176                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1177                 clock-names = "i2c", "pclk";
1178                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1179                 pinctrl-names = "default";
1180                 pinctrl-0 = <&i2c4_xfer>;
1181                 #address-cells = <1>;
1182                 #size-cells = <0>;
1183                 status = "disabled";
1184         };
1185
1186         i2c8: i2c@ff3e0000 {
1187                 compatible = "rockchip,rk3399-i2c";
1188                 reg = <0x0 0xff3e0000 0x0 0x1000>;
1189                 assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
1190                 assigned-clock-rates = <200000000>;
1191                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1192                 clock-names = "i2c", "pclk";
1193                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1194                 pinctrl-names = "default";
1195                 pinctrl-0 = <&i2c8_xfer>;
1196                 #address-cells = <1>;
1197                 #size-cells = <0>;
1198                 status = "disabled";
1199         };
1200
1201         pwm0: pwm@ff420000 {
1202                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1203                 reg = <0x0 0xff420000 0x0 0x10>;
1204                 #pwm-cells = <3>;
1205                 pinctrl-names = "default";
1206                 pinctrl-0 = <&pwm0_pin>;
1207                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1208                 clock-names = "pwm";
1209                 status = "disabled";
1210         };
1211
1212         pwm1: pwm@ff420010 {
1213                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1214                 reg = <0x0 0xff420010 0x0 0x10>;
1215                 #pwm-cells = <3>;
1216                 pinctrl-names = "default";
1217                 pinctrl-0 = <&pwm1_pin>;
1218                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1219                 clock-names = "pwm";
1220                 status = "disabled";
1221         };
1222
1223         pwm2: pwm@ff420020 {
1224                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1225                 reg = <0x0 0xff420020 0x0 0x10>;
1226                 #pwm-cells = <3>;
1227                 pinctrl-names = "default";
1228                 pinctrl-0 = <&pwm2_pin>;
1229                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1230                 clock-names = "pwm";
1231                 status = "disabled";
1232         };
1233
1234         pwm3: pwm@ff420030 {
1235                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1236                 reg = <0x0 0xff420030 0x0 0x10>;
1237                 #pwm-cells = <3>;
1238                 pinctrl-names = "default";
1239                 pinctrl-0 = <&pwm3a_pin>;
1240                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1241                 clock-names = "pwm";
1242                 status = "disabled";
1243         };
1244
1245         vpu: video-codec@ff650000 {
1246                 compatible = "rockchip,rk3399-vpu";
1247                 reg = <0x0 0xff650000 0x0 0x800>;
1248                 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>,
1249                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>;
1250                 interrupt-names = "vepu", "vdpu";
1251                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1252                 clock-names = "aclk", "hclk";
1253                 iommus = <&vpu_mmu>;
1254                 power-domains = <&power RK3399_PD_VCODEC>;
1255         };
1256
1257         vpu_mmu: iommu@ff650800 {
1258                 compatible = "rockchip,iommu";
1259                 reg = <0x0 0xff650800 0x0 0x40>;
1260                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
1261                 interrupt-names = "vpu_mmu";
1262                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1263                 clock-names = "aclk", "iface";
1264                 #iommu-cells = <0>;
1265                 power-domains = <&power RK3399_PD_VCODEC>;
1266         };
1267
1268         vdec_mmu: iommu@ff660480 {
1269                 compatible = "rockchip,iommu";
1270                 reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
1271                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
1272                 interrupt-names = "vdec_mmu";
1273                 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>;
1274                 clock-names = "aclk", "iface";
1275                 #iommu-cells = <0>;
1276                 status = "disabled";
1277         };
1278
1279         iep_mmu: iommu@ff670800 {
1280                 compatible = "rockchip,iommu";
1281                 reg = <0x0 0xff670800 0x0 0x40>;
1282                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
1283                 interrupt-names = "iep_mmu";
1284                 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1285                 clock-names = "aclk", "iface";
1286                 #iommu-cells = <0>;
1287                 status = "disabled";
1288         };
1289
1290         rga: rga@ff680000 {
1291                 compatible = "rockchip,rk3399-rga";
1292                 reg = <0x0 0xff680000 0x0 0x10000>;
1293                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1294                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1295                 clock-names = "aclk", "hclk", "sclk";
1296                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1297                 reset-names = "core", "axi", "ahb";
1298                 power-domains = <&power RK3399_PD_RGA>;
1299         };
1300
1301         efuse0: efuse@ff690000 {
1302                 compatible = "rockchip,rk3399-efuse";
1303                 reg = <0x0 0xff690000 0x0 0x80>;
1304                 #address-cells = <1>;
1305                 #size-cells = <1>;
1306                 clocks = <&cru PCLK_EFUSE1024NS>;
1307                 clock-names = "pclk_efuse";
1308
1309                 /* Data cells */
1310                 cpu_id: cpu-id@7 {
1311                         reg = <0x07 0x10>;
1312                 };
1313                 cpub_leakage: cpu-leakage@17 {
1314                         reg = <0x17 0x1>;
1315                 };
1316                 gpu_leakage: gpu-leakage@18 {
1317                         reg = <0x18 0x1>;
1318                 };
1319                 center_leakage: center-leakage@19 {
1320                         reg = <0x19 0x1>;
1321                 };
1322                 cpul_leakage: cpu-leakage@1a {
1323                         reg = <0x1a 0x1>;
1324                 };
1325                 logic_leakage: logic-leakage@1b {
1326                         reg = <0x1b 0x1>;
1327                 };
1328                 wafer_info: wafer-info@1c {
1329                         reg = <0x1c 0x1>;
1330                 };
1331         };
1332
1333         pmucru: pmu-clock-controller@ff750000 {
1334                 compatible = "rockchip,rk3399-pmucru";
1335                 reg = <0x0 0xff750000 0x0 0x1000>;
1336                 rockchip,grf = <&pmugrf>;
1337                 #clock-cells = <1>;
1338                 #reset-cells = <1>;
1339                 assigned-clocks = <&pmucru PLL_PPLL>;
1340                 assigned-clock-rates = <676000000>;
1341         };
1342
1343         cru: clock-controller@ff760000 {
1344                 compatible = "rockchip,rk3399-cru";
1345                 reg = <0x0 0xff760000 0x0 0x1000>;
1346                 rockchip,grf = <&grf>;
1347                 #clock-cells = <1>;
1348                 #reset-cells = <1>;
1349                 assigned-clocks =
1350                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1351                         <&cru PLL_NPLL>,
1352                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1353                         <&cru PCLK_PERIHP>,
1354                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1355                         <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
1356                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
1357                         <&cru ACLK_VIO>, <&cru ACLK_HDCP>,
1358                         <&cru ACLK_GIC_PRE>,
1359                         <&cru PCLK_DDR>;
1360                 assigned-clock-rates =
1361                          <594000000>,  <800000000>,
1362                         <1000000000>,
1363                          <150000000>,   <75000000>,
1364                           <37500000>,
1365                          <100000000>,  <100000000>,
1366                           <50000000>, <600000000>,
1367                          <100000000>,   <50000000>,
1368                          <400000000>, <400000000>,
1369                          <200000000>,
1370                          <200000000>;
1371         };
1372
1373         grf: syscon@ff770000 {
1374                 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1375                 reg = <0x0 0xff770000 0x0 0x10000>;
1376                 #address-cells = <1>;
1377                 #size-cells = <1>;
1378
1379                 io_domains: io-domains {
1380                         compatible = "rockchip,rk3399-io-voltage-domain";
1381                         status = "disabled";
1382                 };
1383
1384                 u2phy0: usb2-phy@e450 {
1385                         compatible = "rockchip,rk3399-usb2phy";
1386                         reg = <0xe450 0x10>;
1387                         clocks = <&cru SCLK_USB2PHY0_REF>;
1388                         clock-names = "phyclk";
1389                         #clock-cells = <0>;
1390                         clock-output-names = "clk_usbphy0_480m";
1391                         status = "disabled";
1392
1393                         u2phy0_host: host-port {
1394                                 #phy-cells = <0>;
1395                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1396                                 interrupt-names = "linestate";
1397                                 status = "disabled";
1398                         };
1399
1400                         u2phy0_otg: otg-port {
1401                                 #phy-cells = <0>;
1402                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1403                                              <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1404                                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1405                                 interrupt-names = "otg-bvalid", "otg-id",
1406                                                   "linestate";
1407                                 status = "disabled";
1408                         };
1409                 };
1410
1411                 u2phy1: usb2-phy@e460 {
1412                         compatible = "rockchip,rk3399-usb2phy";
1413                         reg = <0xe460 0x10>;
1414                         clocks = <&cru SCLK_USB2PHY1_REF>;
1415                         clock-names = "phyclk";
1416                         #clock-cells = <0>;
1417                         clock-output-names = "clk_usbphy1_480m";
1418                         status = "disabled";
1419
1420                         u2phy1_host: host-port {
1421                                 #phy-cells = <0>;
1422                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1423                                 interrupt-names = "linestate";
1424                                 status = "disabled";
1425                         };
1426
1427                         u2phy1_otg: otg-port {
1428                                 #phy-cells = <0>;
1429                                 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
1430                                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
1431                                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
1432                                 interrupt-names = "otg-bvalid", "otg-id",
1433                                                   "linestate";
1434                                 status = "disabled";
1435                         };
1436                 };
1437
1438                 emmc_phy: phy@f780 {
1439                         compatible = "rockchip,rk3399-emmc-phy";
1440                         reg = <0xf780 0x24>;
1441                         clocks = <&sdhci>;
1442                         clock-names = "emmcclk";
1443                         #phy-cells = <0>;
1444                         status = "disabled";
1445                 };
1446
1447                 pcie_phy: pcie-phy {
1448                         compatible = "rockchip,rk3399-pcie-phy";
1449                         clocks = <&cru SCLK_PCIEPHY_REF>;
1450                         clock-names = "refclk";
1451                         #phy-cells = <1>;
1452                         resets = <&cru SRST_PCIEPHY>;
1453                         reset-names = "phy";
1454                         status = "disabled";
1455                 };
1456         };
1457
1458         tcphy0: phy@ff7c0000 {
1459                 compatible = "rockchip,rk3399-typec-phy";
1460                 reg = <0x0 0xff7c0000 0x0 0x40000>;
1461                 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1462                          <&cru SCLK_UPHY0_TCPDPHY_REF>;
1463                 clock-names = "tcpdcore", "tcpdphy-ref";
1464                 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1465                 assigned-clock-rates = <50000000>;
1466                 power-domains = <&power RK3399_PD_TCPD0>;
1467                 resets = <&cru SRST_UPHY0>,
1468                          <&cru SRST_UPHY0_PIPE_L00>,
1469                          <&cru SRST_P_UPHY0_TCPHY>;
1470                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1471                 rockchip,grf = <&grf>;
1472                 status = "disabled";
1473
1474                 tcphy0_dp: dp-port {
1475                         #phy-cells = <0>;
1476                 };
1477
1478                 tcphy0_usb3: usb3-port {
1479                         #phy-cells = <0>;
1480                 };
1481         };
1482
1483         tcphy1: phy@ff800000 {
1484                 compatible = "rockchip,rk3399-typec-phy";
1485                 reg = <0x0 0xff800000 0x0 0x40000>;
1486                 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1487                          <&cru SCLK_UPHY1_TCPDPHY_REF>;
1488                 clock-names = "tcpdcore", "tcpdphy-ref";
1489                 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1490                 assigned-clock-rates = <50000000>;
1491                 power-domains = <&power RK3399_PD_TCPD1>;
1492                 resets = <&cru SRST_UPHY1>,
1493                          <&cru SRST_UPHY1_PIPE_L00>,
1494                          <&cru SRST_P_UPHY1_TCPHY>;
1495                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1496                 rockchip,grf = <&grf>;
1497                 status = "disabled";
1498
1499                 tcphy1_dp: dp-port {
1500                         #phy-cells = <0>;
1501                 };
1502
1503                 tcphy1_usb3: usb3-port {
1504                         #phy-cells = <0>;
1505                 };
1506         };
1507
1508         watchdog@ff848000 {
1509                 compatible = "snps,dw-wdt";
1510                 reg = <0x0 0xff848000 0x0 0x100>;
1511                 clocks = <&cru PCLK_WDT>;
1512                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1513         };
1514
1515         rktimer: rktimer@ff850000 {
1516                 compatible = "rockchip,rk3399-timer";
1517                 reg = <0x0 0xff850000 0x0 0x1000>;
1518                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1519                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1520                 clock-names = "pclk", "timer";
1521         };
1522
1523         spdif: spdif@ff870000 {
1524                 compatible = "rockchip,rk3399-spdif";
1525                 reg = <0x0 0xff870000 0x0 0x1000>;
1526                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1527                 dmas = <&dmac_bus 7>;
1528                 dma-names = "tx";
1529                 clock-names = "mclk", "hclk";
1530                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1531                 pinctrl-names = "default";
1532                 pinctrl-0 = <&spdif_bus>;
1533                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1534                 #sound-dai-cells = <0>;
1535                 status = "disabled";
1536         };
1537
1538         i2s0: i2s@ff880000 {
1539                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1540                 reg = <0x0 0xff880000 0x0 0x1000>;
1541                 rockchip,grf = <&grf>;
1542                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1543                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1544                 dma-names = "tx", "rx";
1545                 clock-names = "i2s_clk", "i2s_hclk";
1546                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1547                 pinctrl-names = "default";
1548                 pinctrl-0 = <&i2s0_8ch_bus>;
1549                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1550                 #sound-dai-cells = <0>;
1551                 status = "disabled";
1552         };
1553
1554         i2s1: i2s@ff890000 {
1555                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1556                 reg = <0x0 0xff890000 0x0 0x1000>;
1557                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1558                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1559                 dma-names = "tx", "rx";
1560                 clock-names = "i2s_clk", "i2s_hclk";
1561                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1562                 pinctrl-names = "default";
1563                 pinctrl-0 = <&i2s1_2ch_bus>;
1564                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1565                 #sound-dai-cells = <0>;
1566                 status = "disabled";
1567         };
1568
1569         i2s2: i2s@ff8a0000 {
1570                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1571                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1572                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1573                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1574                 dma-names = "tx", "rx";
1575                 clock-names = "i2s_clk", "i2s_hclk";
1576                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1577                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1578                 #sound-dai-cells = <0>;
1579                 status = "disabled";
1580         };
1581
1582         vopl: vop@ff8f0000 {
1583                 compatible = "rockchip,rk3399-vop-lit";
1584                 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1585                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1586                 assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1587                 assigned-clock-rates = <400000000>, <100000000>;
1588                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1589                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1590                 iommus = <&vopl_mmu>;
1591                 power-domains = <&power RK3399_PD_VOPL>;
1592                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1593                 reset-names = "axi", "ahb", "dclk";
1594                 status = "disabled";
1595
1596                 vopl_out: port {
1597                         #address-cells = <1>;
1598                         #size-cells = <0>;
1599
1600                         vopl_out_mipi: endpoint@0 {
1601                                 reg = <0>;
1602                                 remote-endpoint = <&mipi_in_vopl>;
1603                         };
1604
1605                         vopl_out_edp: endpoint@1 {
1606                                 reg = <1>;
1607                                 remote-endpoint = <&edp_in_vopl>;
1608                         };
1609
1610                         vopl_out_hdmi: endpoint@2 {
1611                                 reg = <2>;
1612                                 remote-endpoint = <&hdmi_in_vopl>;
1613                         };
1614
1615                         vopl_out_mipi1: endpoint@3 {
1616                                 reg = <3>;
1617                                 remote-endpoint = <&mipi1_in_vopl>;
1618                         };
1619
1620                         vopl_out_dp: endpoint@4 {
1621                                 reg = <4>;
1622                                 remote-endpoint = <&dp_in_vopl>;
1623                         };
1624                 };
1625         };
1626
1627         vopl_mmu: iommu@ff8f3f00 {
1628                 compatible = "rockchip,iommu";
1629                 reg = <0x0 0xff8f3f00 0x0 0x100>;
1630                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1631                 interrupt-names = "vopl_mmu";
1632                 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1633                 clock-names = "aclk", "iface";
1634                 power-domains = <&power RK3399_PD_VOPL>;
1635                 #iommu-cells = <0>;
1636                 status = "disabled";
1637         };
1638
1639         vopb: vop@ff900000 {
1640                 compatible = "rockchip,rk3399-vop-big";
1641                 reg = <0x0 0xff900000 0x0 0x3efc>;
1642                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1643                 assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1644                 assigned-clock-rates = <400000000>, <100000000>;
1645                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1646                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1647                 iommus = <&vopb_mmu>;
1648                 power-domains = <&power RK3399_PD_VOPB>;
1649                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1650                 reset-names = "axi", "ahb", "dclk";
1651                 status = "disabled";
1652
1653                 vopb_out: port {
1654                         #address-cells = <1>;
1655                         #size-cells = <0>;
1656
1657                         vopb_out_edp: endpoint@0 {
1658                                 reg = <0>;
1659                                 remote-endpoint = <&edp_in_vopb>;
1660                         };
1661
1662                         vopb_out_mipi: endpoint@1 {
1663                                 reg = <1>;
1664                                 remote-endpoint = <&mipi_in_vopb>;
1665                         };
1666
1667                         vopb_out_hdmi: endpoint@2 {
1668                                 reg = <2>;
1669                                 remote-endpoint = <&hdmi_in_vopb>;
1670                         };
1671
1672                         vopb_out_mipi1: endpoint@3 {
1673                                 reg = <3>;
1674                                 remote-endpoint = <&mipi1_in_vopb>;
1675                         };
1676
1677                         vopb_out_dp: endpoint@4 {
1678                                 reg = <4>;
1679                                 remote-endpoint = <&dp_in_vopb>;
1680                         };
1681                 };
1682         };
1683
1684         vopb_mmu: iommu@ff903f00 {
1685                 compatible = "rockchip,iommu";
1686                 reg = <0x0 0xff903f00 0x0 0x100>;
1687                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1688                 interrupt-names = "vopb_mmu";
1689                 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1690                 clock-names = "aclk", "iface";
1691                 power-domains = <&power RK3399_PD_VOPB>;
1692                 #iommu-cells = <0>;
1693                 status = "disabled";
1694         };
1695
1696         isp0_mmu: iommu@ff914000 {
1697                 compatible = "rockchip,iommu";
1698                 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
1699                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
1700                 interrupt-names = "isp0_mmu";
1701                 clocks = <&cru ACLK_ISP0_NOC>, <&cru HCLK_ISP0_NOC>;
1702                 clock-names = "aclk", "iface";
1703                 #iommu-cells = <0>;
1704                 rockchip,disable-mmu-reset;
1705                 status = "disabled";
1706         };
1707
1708         isp1_mmu: iommu@ff924000 {
1709                 compatible = "rockchip,iommu";
1710                 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
1711                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
1712                 interrupt-names = "isp1_mmu";
1713                 clocks = <&cru ACLK_ISP1_NOC>, <&cru HCLK_ISP1_NOC>;
1714                 clock-names = "aclk", "iface";
1715                 #iommu-cells = <0>;
1716                 rockchip,disable-mmu-reset;
1717                 status = "disabled";
1718         };
1719
1720         hdmi_sound: hdmi-sound {
1721                 compatible = "simple-audio-card";
1722                 simple-audio-card,format = "i2s";
1723                 simple-audio-card,mclk-fs = <256>;
1724                 simple-audio-card,name = "hdmi-sound";
1725                 status = "disabled";
1726
1727                 simple-audio-card,cpu {
1728                         sound-dai = <&i2s2>;
1729                 };
1730                 simple-audio-card,codec {
1731                         sound-dai = <&hdmi>;
1732                 };
1733         };
1734
1735         hdmi: hdmi@ff940000 {
1736                 compatible = "rockchip,rk3399-dw-hdmi";
1737                 reg = <0x0 0xff940000 0x0 0x20000>;
1738                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1739                 clocks = <&cru PCLK_HDMI_CTRL>,
1740                          <&cru SCLK_HDMI_SFR>,
1741                          <&cru PLL_VPLL>,
1742                          <&cru PCLK_VIO_GRF>,
1743                          <&cru SCLK_HDMI_CEC>;
1744                 clock-names = "iahb", "isfr", "vpll", "grf", "cec";
1745                 power-domains = <&power RK3399_PD_HDCP>;
1746                 reg-io-width = <4>;
1747                 rockchip,grf = <&grf>;
1748                 #sound-dai-cells = <0>;
1749                 status = "disabled";
1750
1751                 ports {
1752                         hdmi_in: port {
1753                                 #address-cells = <1>;
1754                                 #size-cells = <0>;
1755
1756                                 hdmi_in_vopb: endpoint@0 {
1757                                         reg = <0>;
1758                                         remote-endpoint = <&vopb_out_hdmi>;
1759                                 };
1760                                 hdmi_in_vopl: endpoint@1 {
1761                                         reg = <1>;
1762                                         remote-endpoint = <&vopl_out_hdmi>;
1763                                 };
1764                         };
1765                 };
1766         };
1767
1768         mipi_dsi: mipi@ff960000 {
1769                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1770                 reg = <0x0 0xff960000 0x0 0x8000>;
1771                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1772                 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>,
1773                          <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>;
1774                 clock-names = "ref", "pclk", "phy_cfg", "grf";
1775                 power-domains = <&power RK3399_PD_VIO>;
1776                 resets = <&cru SRST_P_MIPI_DSI0>;
1777                 reset-names = "apb";
1778                 rockchip,grf = <&grf>;
1779                 #address-cells = <1>;
1780                 #size-cells = <0>;
1781                 status = "disabled";
1782
1783                 ports {
1784                         #address-cells = <1>;
1785                         #size-cells = <0>;
1786
1787                         mipi_in: port@0 {
1788                                 reg = <0>;
1789                                 #address-cells = <1>;
1790                                 #size-cells = <0>;
1791
1792                                 mipi_in_vopb: endpoint@0 {
1793                                         reg = <0>;
1794                                         remote-endpoint = <&vopb_out_mipi>;
1795                                 };
1796                                 mipi_in_vopl: endpoint@1 {
1797                                         reg = <1>;
1798                                         remote-endpoint = <&vopl_out_mipi>;
1799                                 };
1800                         };
1801                 };
1802         };
1803
1804         mipi_dsi1: mipi@ff968000 {
1805                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1806                 reg = <0x0 0xff968000 0x0 0x8000>;
1807                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>;
1808                 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>,
1809                          <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>;
1810                 clock-names = "ref", "pclk", "phy_cfg", "grf";
1811                 power-domains = <&power RK3399_PD_VIO>;
1812                 resets = <&cru SRST_P_MIPI_DSI1>;
1813                 reset-names = "apb";
1814                 rockchip,grf = <&grf>;
1815                 #address-cells = <1>;
1816                 #size-cells = <0>;
1817                 status = "disabled";
1818
1819                 ports {
1820                         #address-cells = <1>;
1821                         #size-cells = <0>;
1822
1823                         mipi1_in: port@0 {
1824                                 reg = <0>;
1825                                 #address-cells = <1>;
1826                                 #size-cells = <0>;
1827
1828                                 mipi1_in_vopb: endpoint@0 {
1829                                         reg = <0>;
1830                                         remote-endpoint = <&vopb_out_mipi1>;
1831                                 };
1832
1833                                 mipi1_in_vopl: endpoint@1 {
1834                                         reg = <1>;
1835                                         remote-endpoint = <&vopl_out_mipi1>;
1836                                 };
1837                         };
1838                 };
1839         };
1840
1841         edp: edp@ff970000 {
1842                 compatible = "rockchip,rk3399-edp";
1843                 reg = <0x0 0xff970000 0x0 0x8000>;
1844                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
1845                 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>;
1846                 clock-names = "dp", "pclk", "grf";
1847                 pinctrl-names = "default";
1848                 pinctrl-0 = <&edp_hpd>;
1849                 power-domains = <&power RK3399_PD_EDP>;
1850                 resets = <&cru SRST_P_EDP_CTRL>;
1851                 reset-names = "dp";
1852                 rockchip,grf = <&grf>;
1853                 status = "disabled";
1854
1855                 ports {
1856                         #address-cells = <1>;
1857                         #size-cells = <0>;
1858                         edp_in: port@0 {
1859                                 reg = <0>;
1860                                 #address-cells = <1>;
1861                                 #size-cells = <0>;
1862
1863                                 edp_in_vopb: endpoint@0 {
1864                                         reg = <0>;
1865                                         remote-endpoint = <&vopb_out_edp>;
1866                                 };
1867
1868                                 edp_in_vopl: endpoint@1 {
1869                                         reg = <1>;
1870                                         remote-endpoint = <&vopl_out_edp>;
1871                                 };
1872                         };
1873                 };
1874         };
1875
1876         gpu: gpu@ff9a0000 {
1877                 compatible = "rockchip,rk3399-mali", "arm,mali-t860";
1878                 reg = <0x0 0xff9a0000 0x0 0x10000>;
1879                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
1880                              <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1881                              <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
1882                 interrupt-names = "gpu", "job", "mmu";
1883                 clocks = <&cru ACLK_GPU>;
1884                 power-domains = <&power RK3399_PD_GPU>;
1885                 status = "disabled";
1886         };
1887
1888         pinctrl: pinctrl {
1889                 compatible = "rockchip,rk3399-pinctrl";
1890                 rockchip,grf = <&grf>;
1891                 rockchip,pmu = <&pmugrf>;
1892                 #address-cells = <2>;
1893                 #size-cells = <2>;
1894                 ranges;
1895
1896                 gpio0: gpio0@ff720000 {
1897                         compatible = "rockchip,gpio-bank";
1898                         reg = <0x0 0xff720000 0x0 0x100>;
1899                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1900                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1901
1902                         gpio-controller;
1903                         #gpio-cells = <0x2>;
1904
1905                         interrupt-controller;
1906                         #interrupt-cells = <0x2>;
1907                 };
1908
1909                 gpio1: gpio1@ff730000 {
1910                         compatible = "rockchip,gpio-bank";
1911                         reg = <0x0 0xff730000 0x0 0x100>;
1912                         clocks = <&pmucru PCLK_GPIO1_PMU>;
1913                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1914
1915                         gpio-controller;
1916                         #gpio-cells = <0x2>;
1917
1918                         interrupt-controller;
1919                         #interrupt-cells = <0x2>;
1920                 };
1921
1922                 gpio2: gpio2@ff780000 {
1923                         compatible = "rockchip,gpio-bank";
1924                         reg = <0x0 0xff780000 0x0 0x100>;
1925                         clocks = <&cru PCLK_GPIO2>;
1926                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
1927
1928                         gpio-controller;
1929                         #gpio-cells = <0x2>;
1930
1931                         interrupt-controller;
1932                         #interrupt-cells = <0x2>;
1933                 };
1934
1935                 gpio3: gpio3@ff788000 {
1936                         compatible = "rockchip,gpio-bank";
1937                         reg = <0x0 0xff788000 0x0 0x100>;
1938                         clocks = <&cru PCLK_GPIO3>;
1939                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1940
1941                         gpio-controller;
1942                         #gpio-cells = <0x2>;
1943
1944                         interrupt-controller;
1945                         #interrupt-cells = <0x2>;
1946                 };
1947
1948                 gpio4: gpio4@ff790000 {
1949                         compatible = "rockchip,gpio-bank";
1950                         reg = <0x0 0xff790000 0x0 0x100>;
1951                         clocks = <&cru PCLK_GPIO4>;
1952                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
1953
1954                         gpio-controller;
1955                         #gpio-cells = <0x2>;
1956
1957                         interrupt-controller;
1958                         #interrupt-cells = <0x2>;
1959                 };
1960
1961                 pcfg_pull_up: pcfg-pull-up {
1962                         bias-pull-up;
1963                 };
1964
1965                 pcfg_pull_down: pcfg-pull-down {
1966                         bias-pull-down;
1967                 };
1968
1969                 pcfg_pull_none: pcfg-pull-none {
1970                         bias-disable;
1971                 };
1972
1973                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1974                         bias-disable;
1975                         drive-strength = <12>;
1976                 };
1977
1978                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1979                         bias-disable;
1980                         drive-strength = <13>;
1981                 };
1982
1983                 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
1984                         bias-disable;
1985                         drive-strength = <18>;
1986                 };
1987
1988                 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
1989                         bias-disable;
1990                         drive-strength = <20>;
1991                 };
1992
1993                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1994                         bias-pull-up;
1995                         drive-strength = <2>;
1996                 };
1997
1998                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1999                         bias-pull-up;
2000                         drive-strength = <8>;
2001                 };
2002
2003                 pcfg_pull_up_18ma: pcfg-pull-up-18ma {
2004                         bias-pull-up;
2005                         drive-strength = <18>;
2006                 };
2007
2008                 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
2009                         bias-pull-up;
2010                         drive-strength = <20>;
2011                 };
2012
2013                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
2014                         bias-pull-down;
2015                         drive-strength = <4>;
2016                 };
2017
2018                 pcfg_pull_down_8ma: pcfg-pull-down-8ma {
2019                         bias-pull-down;
2020                         drive-strength = <8>;
2021                 };
2022
2023                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
2024                         bias-pull-down;
2025                         drive-strength = <12>;
2026                 };
2027
2028                 pcfg_pull_down_18ma: pcfg-pull-down-18ma {
2029                         bias-pull-down;
2030                         drive-strength = <18>;
2031                 };
2032
2033                 pcfg_pull_down_20ma: pcfg-pull-down-20ma {
2034                         bias-pull-down;
2035                         drive-strength = <20>;
2036                 };
2037
2038                 pcfg_output_high: pcfg-output-high {
2039                         output-high;
2040                 };
2041
2042                 pcfg_output_low: pcfg-output-low {
2043                         output-low;
2044                 };
2045
2046                 clock {
2047                         clk_32k: clk-32k {
2048                                 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
2049                         };
2050                 };
2051
2052                 edp {
2053                         edp_hpd: edp-hpd {
2054                                 rockchip,pins =
2055                                         <4 23 RK_FUNC_2 &pcfg_pull_none>;
2056                         };
2057                 };
2058
2059                 gmac {
2060                         rgmii_pins: rgmii-pins {
2061                                 rockchip,pins =
2062                                         /* mac_txclk */
2063                                         <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
2064                                         /* mac_rxclk */
2065                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
2066                                         /* mac_mdio */
2067                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
2068                                         /* mac_txen */
2069                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
2070                                         /* mac_clk */
2071                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
2072                                         /* mac_rxdv */
2073                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
2074                                         /* mac_mdc */
2075                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
2076                                         /* mac_rxd1 */
2077                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
2078                                         /* mac_rxd0 */
2079                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
2080                                         /* mac_txd1 */
2081                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
2082                                         /* mac_txd0 */
2083                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
2084                                         /* mac_rxd3 */
2085                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
2086                                         /* mac_rxd2 */
2087                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
2088                                         /* mac_txd3 */
2089                                         <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
2090                                         /* mac_txd2 */
2091                                         <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
2092                         };
2093
2094                         rmii_pins: rmii-pins {
2095                                 rockchip,pins =
2096                                         /* mac_mdio */
2097                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
2098                                         /* mac_txen */
2099                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
2100                                         /* mac_clk */
2101                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
2102                                         /* mac_rxer */
2103                                         <3 10 RK_FUNC_1 &pcfg_pull_none>,
2104                                         /* mac_rxdv */
2105                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
2106                                         /* mac_mdc */
2107                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
2108                                         /* mac_rxd1 */
2109                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
2110                                         /* mac_rxd0 */
2111                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
2112                                         /* mac_txd1 */
2113                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
2114                                         /* mac_txd0 */
2115                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
2116                         };
2117                 };
2118
2119                 i2c0 {
2120                         i2c0_xfer: i2c0-xfer {
2121                                 rockchip,pins =
2122                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
2123                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
2124                         };
2125                 };
2126
2127                 i2c1 {
2128                         i2c1_xfer: i2c1-xfer {
2129                                 rockchip,pins =
2130                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
2131                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
2132                         };
2133                 };
2134
2135                 i2c2 {
2136                         i2c2_xfer: i2c2-xfer {
2137                                 rockchip,pins =
2138                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
2139                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
2140                         };
2141                 };
2142
2143                 i2c3 {
2144                         i2c3_xfer: i2c3-xfer {
2145                                 rockchip,pins =
2146                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
2147                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
2148                         };
2149                 };
2150
2151                 i2c4 {
2152                         i2c4_xfer: i2c4-xfer {
2153                                 rockchip,pins =
2154                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
2155                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
2156                         };
2157                 };
2158
2159                 i2c5 {
2160                         i2c5_xfer: i2c5-xfer {
2161                                 rockchip,pins =
2162                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
2163                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
2164                         };
2165                 };
2166
2167                 i2c6 {
2168                         i2c6_xfer: i2c6-xfer {
2169                                 rockchip,pins =
2170                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
2171                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
2172                         };
2173                 };
2174
2175                 i2c7 {
2176                         i2c7_xfer: i2c7-xfer {
2177                                 rockchip,pins =
2178                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
2179                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
2180                         };
2181                 };
2182
2183                 i2c8 {
2184                         i2c8_xfer: i2c8-xfer {
2185                                 rockchip,pins =
2186                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
2187                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
2188                         };
2189                 };
2190
2191                 i2s0 {
2192                         i2s0_2ch_bus: i2s0-2ch-bus {
2193                                 rockchip,pins =
2194                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
2195                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
2196                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
2197                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
2198                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
2199                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
2200                         };
2201
2202                         i2s0_8ch_bus: i2s0-8ch-bus {
2203                                 rockchip,pins =
2204                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
2205                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
2206                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
2207                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
2208                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
2209                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
2210                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
2211                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
2212                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
2213                         };
2214                 };
2215
2216                 i2s1 {
2217                         i2s1_2ch_bus: i2s1-2ch-bus {
2218                                 rockchip,pins =
2219                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
2220                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
2221                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
2222                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
2223                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
2224                         };
2225                 };
2226
2227                 sdio0 {
2228                         sdio0_bus1: sdio0-bus1 {
2229                                 rockchip,pins =
2230                                         <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>;
2231                         };
2232
2233                         sdio0_bus4: sdio0-bus4 {
2234                                 rockchip,pins =
2235                                         <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>,
2236                                         <2 RK_PC5 RK_FUNC_1 &pcfg_pull_up>,
2237                                         <2 RK_PC6 RK_FUNC_1 &pcfg_pull_up>,
2238                                         <2 RK_PC7 RK_FUNC_1 &pcfg_pull_up>;
2239                         };
2240
2241                         sdio0_cmd: sdio0-cmd {
2242                                 rockchip,pins =
2243                                         <2 RK_PD0 RK_FUNC_1 &pcfg_pull_up>;
2244                         };
2245
2246                         sdio0_clk: sdio0-clk {
2247                                 rockchip,pins =
2248                                         <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
2249                         };
2250
2251                         sdio0_cd: sdio0-cd {
2252                                 rockchip,pins =
2253                                         <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>;
2254                         };
2255
2256                         sdio0_pwr: sdio0-pwr {
2257                                 rockchip,pins =
2258                                         <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>;
2259                         };
2260
2261                         sdio0_bkpwr: sdio0-bkpwr {
2262                                 rockchip,pins =
2263                                         <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>;
2264                         };
2265
2266                         sdio0_wp: sdio0-wp {
2267                                 rockchip,pins =
2268                                         <0 RK_PA3 RK_FUNC_1 &pcfg_pull_up>;
2269                         };
2270
2271                         sdio0_int: sdio0-int {
2272                                 rockchip,pins =
2273                                         <0 RK_PA4 RK_FUNC_1 &pcfg_pull_up>;
2274                         };
2275                 };
2276
2277                 sdmmc {
2278                         sdmmc_bus1: sdmmc-bus1 {
2279                                 rockchip,pins =
2280                                         <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>;
2281                         };
2282
2283                         sdmmc_bus4: sdmmc-bus4 {
2284                                 rockchip,pins =
2285                                         <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>,
2286                                         <4 RK_PB1 RK_FUNC_1 &pcfg_pull_up>,
2287                                         <4 RK_PB2 RK_FUNC_1 &pcfg_pull_up>,
2288                                         <4 RK_PB3 RK_FUNC_1 &pcfg_pull_up>;
2289                         };
2290
2291                         sdmmc_clk: sdmmc-clk {
2292                                 rockchip,pins =
2293                                         <4 RK_PB4 RK_FUNC_1 &pcfg_pull_none>;
2294                         };
2295
2296                         sdmmc_cmd: sdmmc-cmd {
2297                                 rockchip,pins =
2298                                         <4 RK_PB5 RK_FUNC_1 &pcfg_pull_up>;
2299                         };
2300
2301                         sdmmc_cd: sdmmc-cd {
2302                                 rockchip,pins =
2303                                         <0 RK_PA7 RK_FUNC_1 &pcfg_pull_up>;
2304                         };
2305
2306                         sdmmc_wp: sdmmc-wp {
2307                                 rockchip,pins =
2308                                         <0 RK_PB0 RK_FUNC_1 &pcfg_pull_up>;
2309                         };
2310                 };
2311
2312                 sleep {
2313                         ap_pwroff: ap-pwroff {
2314                                 rockchip,pins = <1 5 RK_FUNC_1 &pcfg_pull_none>;
2315                         };
2316
2317                         ddrio_pwroff: ddrio-pwroff {
2318                                 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
2319                         };
2320                 };
2321
2322                 spdif {
2323                         spdif_bus: spdif-bus {
2324                                 rockchip,pins =
2325                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
2326                         };
2327
2328                         spdif_bus_1: spdif-bus-1 {
2329                                 rockchip,pins =
2330                                         <3 RK_PC0 RK_FUNC_3 &pcfg_pull_none>;
2331                         };
2332                 };
2333
2334                 spi0 {
2335                         spi0_clk: spi0-clk {
2336                                 rockchip,pins =
2337                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
2338                         };
2339                         spi0_cs0: spi0-cs0 {
2340                                 rockchip,pins =
2341                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
2342                         };
2343                         spi0_cs1: spi0-cs1 {
2344                                 rockchip,pins =
2345                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
2346                         };
2347                         spi0_tx: spi0-tx {
2348                                 rockchip,pins =
2349                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
2350                         };
2351                         spi0_rx: spi0-rx {
2352                                 rockchip,pins =
2353                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
2354                         };
2355                 };
2356
2357                 spi1 {
2358                         spi1_clk: spi1-clk {
2359                                 rockchip,pins =
2360                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
2361                         };
2362                         spi1_cs0: spi1-cs0 {
2363                                 rockchip,pins =
2364                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
2365                         };
2366                         spi1_rx: spi1-rx {
2367                                 rockchip,pins =
2368                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
2369                         };
2370                         spi1_tx: spi1-tx {
2371                                 rockchip,pins =
2372                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
2373                         };
2374                 };
2375
2376                 spi2 {
2377                         spi2_clk: spi2-clk {
2378                                 rockchip,pins =
2379                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
2380                         };
2381                         spi2_cs0: spi2-cs0 {
2382                                 rockchip,pins =
2383                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
2384                         };
2385                         spi2_rx: spi2-rx {
2386                                 rockchip,pins =
2387                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
2388                         };
2389                         spi2_tx: spi2-tx {
2390                                 rockchip,pins =
2391                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
2392                         };
2393                 };
2394
2395                 spi3 {
2396                         spi3_clk: spi3-clk {
2397                                 rockchip,pins =
2398                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
2399                         };
2400                         spi3_cs0: spi3-cs0 {
2401                                 rockchip,pins =
2402                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
2403                         };
2404                         spi3_rx: spi3-rx {
2405                                 rockchip,pins =
2406                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
2407                         };
2408                         spi3_tx: spi3-tx {
2409                                 rockchip,pins =
2410                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
2411                         };
2412                 };
2413
2414                 spi4 {
2415                         spi4_clk: spi4-clk {
2416                                 rockchip,pins =
2417                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
2418                         };
2419                         spi4_cs0: spi4-cs0 {
2420                                 rockchip,pins =
2421                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
2422                         };
2423                         spi4_rx: spi4-rx {
2424                                 rockchip,pins =
2425                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
2426                         };
2427                         spi4_tx: spi4-tx {
2428                                 rockchip,pins =
2429                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
2430                         };
2431                 };
2432
2433                 spi5 {
2434                         spi5_clk: spi5-clk {
2435                                 rockchip,pins =
2436                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
2437                         };
2438                         spi5_cs0: spi5-cs0 {
2439                                 rockchip,pins =
2440                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
2441                         };
2442                         spi5_rx: spi5-rx {
2443                                 rockchip,pins =
2444                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
2445                         };
2446                         spi5_tx: spi5-tx {
2447                                 rockchip,pins =
2448                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
2449                         };
2450                 };
2451
2452                 testclk {
2453                         test_clkout0: test-clkout0 {
2454                                 rockchip,pins =
2455                                         <0 0 RK_FUNC_1 &pcfg_pull_none>;
2456                         };
2457
2458                         test_clkout1: test-clkout1 {
2459                                 rockchip,pins =
2460                                         <2 25 RK_FUNC_2 &pcfg_pull_none>;
2461                         };
2462
2463                         test_clkout2: test-clkout2 {
2464                                 rockchip,pins =
2465                                         <0 8 RK_FUNC_3 &pcfg_pull_none>;
2466                         };
2467                 };
2468
2469                 tsadc {
2470                         otp_gpio: otp-gpio {
2471                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
2472                         };
2473
2474                         otp_out: otp-out {
2475                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
2476                         };
2477                 };
2478
2479                 uart0 {
2480                         uart0_xfer: uart0-xfer {
2481                                 rockchip,pins =
2482                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
2483                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
2484                         };
2485
2486                         uart0_cts: uart0-cts {
2487                                 rockchip,pins =
2488                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
2489                         };
2490
2491                         uart0_rts: uart0-rts {
2492                                 rockchip,pins =
2493                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
2494                         };
2495                 };
2496
2497                 uart1 {
2498                         uart1_xfer: uart1-xfer {
2499                                 rockchip,pins =
2500                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
2501                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
2502                         };
2503                 };
2504
2505                 uart2a {
2506                         uart2a_xfer: uart2a-xfer {
2507                                 rockchip,pins =
2508                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
2509                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
2510                         };
2511                 };
2512
2513                 uart2b {
2514                         uart2b_xfer: uart2b-xfer {
2515                                 rockchip,pins =
2516                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
2517                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
2518                         };
2519                 };
2520
2521                 uart2c {
2522                         uart2c_xfer: uart2c-xfer {
2523                                 rockchip,pins =
2524                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
2525                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
2526                         };
2527                 };
2528
2529                 uart3 {
2530                         uart3_xfer: uart3-xfer {
2531                                 rockchip,pins =
2532                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
2533                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
2534                         };
2535
2536                         uart3_cts: uart3-cts {
2537                                 rockchip,pins =
2538                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
2539                         };
2540
2541                         uart3_rts: uart3-rts {
2542                                 rockchip,pins =
2543                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
2544                         };
2545                 };
2546
2547                 uart4 {
2548                         uart4_xfer: uart4-xfer {
2549                                 rockchip,pins =
2550                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
2551                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
2552                         };
2553                 };
2554
2555                 uarthdcp {
2556                         uarthdcp_xfer: uarthdcp-xfer {
2557                                 rockchip,pins =
2558                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
2559                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
2560                         };
2561                 };
2562
2563                 pwm0 {
2564                         pwm0_pin: pwm0-pin {
2565                                 rockchip,pins =
2566                                         <4 RK_PC2 RK_FUNC_1 &pcfg_pull_none>;
2567                         };
2568
2569                         pwm0_pin_pull_down: pwm0-pin-pull-down {
2570                                 rockchip,pins =
2571                                         <4 RK_PC2 RK_FUNC_1 &pcfg_pull_down>;
2572                         };
2573
2574                         vop0_pwm_pin: vop0-pwm-pin {
2575                                 rockchip,pins =
2576                                         <4 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
2577                         };
2578
2579                         vop1_pwm_pin: vop1-pwm-pin {
2580                                 rockchip,pins =
2581                                         <4 RK_PC2 RK_FUNC_3 &pcfg_pull_none>;
2582                         };
2583                 };
2584
2585                 pwm1 {
2586                         pwm1_pin: pwm1-pin {
2587                                 rockchip,pins =
2588                                         <4 RK_PC6 RK_FUNC_1 &pcfg_pull_none>;
2589                         };
2590
2591                         pwm1_pin_pull_down: pwm1-pin-pull-down {
2592                                 rockchip,pins =
2593                                         <4 RK_PC6 RK_FUNC_1 &pcfg_pull_down>;
2594                         };
2595                 };
2596
2597                 pwm2 {
2598                         pwm2_pin: pwm2-pin {
2599                                 rockchip,pins =
2600                                         <1 RK_PC3 RK_FUNC_1 &pcfg_pull_none>;
2601                         };
2602
2603                         pwm2_pin_pull_down: pwm2-pin-pull-down {
2604                                 rockchip,pins =
2605                                         <1 RK_PC3 RK_FUNC_1 &pcfg_pull_down>;
2606                         };
2607                 };
2608
2609                 pwm3a {
2610                         pwm3a_pin: pwm3a-pin {
2611                                 rockchip,pins =
2612                                         <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>;
2613                         };
2614                 };
2615
2616                 pwm3b {
2617                         pwm3b_pin: pwm3b-pin {
2618                                 rockchip,pins =
2619                                         <1 RK_PB6 RK_FUNC_1 &pcfg_pull_none>;
2620                         };
2621                 };
2622
2623                 hdmi {
2624                         hdmi_i2c_xfer: hdmi-i2c-xfer {
2625                                 rockchip,pins =
2626                                         <4 RK_PC1 RK_FUNC_3 &pcfg_pull_none>,
2627                                         <4 RK_PC0 RK_FUNC_3 &pcfg_pull_none>;
2628                         };
2629
2630                         hdmi_cec: hdmi-cec {
2631                                 rockchip,pins =
2632                                         <4 RK_PC7 RK_FUNC_1 &pcfg_pull_none>;
2633                         };
2634                 };
2635
2636                 pcie {
2637                         pcie_clkreqn_cpm: pci-clkreqn-cpm {
2638                                 rockchip,pins =
2639                                         <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
2640                         };
2641
2642                         pcie_clkreqnb_cpm: pci-clkreqnb-cpm {
2643                                 rockchip,pins =
2644                                         <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
2645                         };
2646                 };
2647
2648         };
2649 };