arch/arm64/boot/dts/rockchip/rk3328.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
   4  */
   5
   6 #include <dt-bindings/clock/rk3328-cru.h>
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/interrupt-controller/irq.h>
  10 #include <dt-bindings/pinctrl/rockchip.h>
  11 #include <dt-bindings/power/rk3328-power.h>
  12 #include <dt-bindings/soc/rockchip,boot-mode.h>
  13 #include <dt-bindings/thermal/thermal.h>
  14
  15 / {
  16         compatible = "rockchip,rk3328";
  17
  18         interrupt-parent = <&gic>;
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         aliases {
  23                 serial0 = &uart0;
  24                 serial1 = &uart1;
  25                 serial2 = &uart2;
  26                 i2c0 = &i2c0;
  27                 i2c1 = &i2c1;
  28                 i2c2 = &i2c2;
  29                 i2c3 = &i2c3;
  30                 ethernet0 = &gmac2io;
  31                 ethernet1 = &gmac2phy;
  32         };
  33
  34         cpus {
  35                 #address-cells = <2>;
  36                 #size-cells = <0>;
  37
  38                 cpu0: cpu@0 {
  39                         device_type = "cpu";
  40                         compatible = "arm,cortex-a53", "arm,armv8";
  41                         reg = <0x0 0x0>;
  42                         clocks = <&cru ARMCLK>;
  43                         #cooling-cells = <2>;
  44                         dynamic-power-coefficient = <120>;
  45                         enable-method = "psci";
  46                         next-level-cache = <&l2>;
  47                         operating-points-v2 = <&cpu0_opp_table>;
  48                 };
  49
  50                 cpu1: cpu@1 {
  51                         device_type = "cpu";
  52                         compatible = "arm,cortex-a53", "arm,armv8";
  53                         reg = <0x0 0x1>;
  54                         clocks = <&cru ARMCLK>;
  55                         #cooling-cells = <2>;
  56                         dynamic-power-coefficient = <120>;
  57                         enable-method = "psci";
  58                         next-level-cache = <&l2>;
  59                         operating-points-v2 = <&cpu0_opp_table>;
  60                 };
  61
  62                 cpu2: cpu@2 {
  63                         device_type = "cpu";
  64                         compatible = "arm,cortex-a53", "arm,armv8";
  65                         reg = <0x0 0x2>;
  66                         clocks = <&cru ARMCLK>;
  67                         #cooling-cells = <2>;
  68                         dynamic-power-coefficient = <120>;
  69                         enable-method = "psci";
  70                         next-level-cache = <&l2>;
  71                         operating-points-v2 = <&cpu0_opp_table>;
  72                 };
  73
  74                 cpu3: cpu@3 {
  75                         device_type = "cpu";
  76                         compatible = "arm,cortex-a53", "arm,armv8";
  77                         reg = <0x0 0x3>;
  78                         clocks = <&cru ARMCLK>;
  79                         #cooling-cells = <2>;
  80                         dynamic-power-coefficient = <120>;
  81                         enable-method = "psci";
  82                         next-level-cache = <&l2>;
  83                         operating-points-v2 = <&cpu0_opp_table>;
  84                 };
  85
  86                 l2: l2-cache0 {
  87                         compatible = "cache";
  88                 };
  89         };
  90
  91         cpu0_opp_table: opp_table0 {
  92                 compatible = "operating-points-v2";
  93                 opp-shared;
  94
  95                 opp-408000000 {
  96                         opp-hz = /bits/ 64 <408000000>;
  97                         opp-microvolt = <950000>;
  98                         clock-latency-ns = <40000>;
  99                         opp-suspend;
 100                 };
 101                 opp-600000000 {
 102                         opp-hz = /bits/ 64 <600000000>;
 103                         opp-microvolt = <950000>;
 104                         clock-latency-ns = <40000>;
 105                 };
 106                 opp-816000000 {
 107                         opp-hz = /bits/ 64 <816000000>;
 108                         opp-microvolt = <1000000>;
 109                         clock-latency-ns = <40000>;
 110                 };
 111                 opp-1008000000 {
 112                         opp-hz = /bits/ 64 <1008000000>;
 113                         opp-microvolt = <1100000>;
 114                         clock-latency-ns = <40000>;
 115                 };
 116                 opp-1200000000 {
 117                         opp-hz = /bits/ 64 <1200000000>;
 118                         opp-microvolt = <1225000>;
 119                         clock-latency-ns = <40000>;
 120                 };
 121                 opp-1296000000 {
 122                         opp-hz = /bits/ 64 <1296000000>;
 123                         opp-microvolt = <1300000>;
 124                         clock-latency-ns = <40000>;
 125                 };
 126         };
 127
 128         amba {
 129                 compatible = "simple-bus";
 130                 #address-cells = <2>;
 131                 #size-cells = <2>;
 132                 ranges;
 133
 134                 dmac: dmac@ff1f0000 {
 135                         compatible = "arm,pl330", "arm,primecell";
 136                         reg = <0x0 0xff1f0000 0x0 0x4000>;
 137                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 138                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 139                         clocks = <&cru ACLK_DMAC>;
 140                         clock-names = "apb_pclk";
 141                         #dma-cells = <1>;
 142                 };
 143         };
 144
 145         arm-pmu {
 146                 compatible = "arm,cortex-a53-pmu";
 147                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 148                              <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 149                              <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 150                              <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 151                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 152         };
 153
 154         display_subsystem: display-subsystem {
 155                 compatible = "rockchip,display-subsystem";
 156                 ports = <&vop_out>;
 157         };
 158
 159         psci {
 160                 compatible = "arm,psci-1.0", "arm,psci-0.2";
 161                 method = "smc";
 162         };
 163
 164         timer {
 165                 compatible = "arm,armv8-timer";
 166                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 167                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 168                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 169                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 170         };
 171
 172         xin24m: xin24m {
 173                 compatible = "fixed-clock";
 174                 #clock-cells = <0>;
 175                 clock-frequency = <24000000>;
 176                 clock-output-names = "xin24m";
 177         };
 178
 179         i2s0: i2s@ff000000 {
 180                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 181                 reg = <0x0 0xff000000 0x0 0x1000>;
 182                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 183                 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
 184                 clock-names = "i2s_clk", "i2s_hclk";
 185                 dmas = <&dmac 11>, <&dmac 12>;
 186                 dma-names = "tx", "rx";
 187                 status = "disabled";
 188         };
 189
 190         i2s1: i2s@ff010000 {
 191                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 192                 reg = <0x0 0xff010000 0x0 0x1000>;
 193                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 194                 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
 195                 clock-names = "i2s_clk", "i2s_hclk";
 196                 dmas = <&dmac 14>, <&dmac 15>;
 197                 dma-names = "tx", "rx";
 198                 status = "disabled";
 199         };
 200
 201         i2s2: i2s@ff020000 {
 202                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 203                 reg = <0x0 0xff020000 0x0 0x1000>;
 204                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 205                 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
 206                 clock-names = "i2s_clk", "i2s_hclk";
 207                 dmas = <&dmac 0>, <&dmac 1>;
 208                 dma-names = "tx", "rx";
 209                 status = "disabled";
 210         };
 211
 212         spdif: spdif@ff030000 {
 213                 compatible = "rockchip,rk3328-spdif";
 214                 reg = <0x0 0xff030000 0x0 0x1000>;
 215                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 216                 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
 217                 clock-names = "mclk", "hclk";
 218                 dmas = <&dmac 10>;
 219                 dma-names = "tx";
 220                 pinctrl-names = "default";
 221                 pinctrl-0 = <&spdifm2_tx>;
 222                 status = "disabled";
 223         };
 224
 225         pdm: pdm@ff040000 {
 226                 compatible = "rockchip,pdm";
 227                 reg = <0x0 0xff040000 0x0 0x1000>;
 228                 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>;
 229                 clock-names = "pdm_clk", "pdm_hclk";
 230                 dmas = <&dmac 16>;
 231                 dma-names = "rx";
 232                 pinctrl-names = "default", "sleep";
 233                 pinctrl-0 = <&pdmm0_clk
 234                              &pdmm0_sdi0
 235                              &pdmm0_sdi1
 236                              &pdmm0_sdi2
 237                              &pdmm0_sdi3>;
 238                 pinctrl-1 = <&pdmm0_clk_sleep
 239                              &pdmm0_sdi0_sleep
 240                              &pdmm0_sdi1_sleep
 241                              &pdmm0_sdi2_sleep
 242                              &pdmm0_sdi3_sleep>;
 243                 status = "disabled";
 244         };
 245
 246         grf: syscon@ff100000 {
 247                 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
 248                 reg = <0x0 0xff100000 0x0 0x1000>;
 249                 #address-cells = <1>;
 250                 #size-cells = <1>;
 251
 252                 io_domains: io-domains {
 253                         compatible = "rockchip,rk3328-io-voltage-domain";
 254                         status = "disabled";
 255                 };
 256
 257                 grf_gpio: grf-gpio {
 258                         compatible = "rockchip,rk3328-grf-gpio";
 259                         gpio-controller;
 260                         #gpio-cells = <2>;
 261                 };
 262
 263                 power: power-controller {
 264                         compatible = "rockchip,rk3328-power-controller";
 265                         #power-domain-cells = <1>;
 266                         #address-cells = <1>;
 267                         #size-cells = <0>;
 268
 269                         pd_hevc@RK3328_PD_HEVC {
 270                                 reg = <RK3328_PD_HEVC>;
 271                         };
 272                         pd_video@RK3328_PD_VIDEO {
 273                                 reg = <RK3328_PD_VIDEO>;
 274                         };
 275                         pd_vpu@RK3328_PD_VPU {
 276                                 reg = <RK3328_PD_VPU>;
 277                         };
 278                 };
 279
 280                 reboot-mode {
 281                         compatible = "syscon-reboot-mode";
 282                         offset = <0x5c8>;
 283                         mode-normal = <BOOT_NORMAL>;
 284                         mode-recovery = <BOOT_RECOVERY>;
 285                         mode-bootloader = <BOOT_FASTBOOT>;
 286                         mode-loader = <BOOT_BL_DOWNLOAD>;
 287                 };
 288         };
 289
 290         uart0: serial@ff110000 {
 291                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 292                 reg = <0x0 0xff110000 0x0 0x100>;
 293                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 294                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 295                 clock-names = "baudclk", "apb_pclk";
 296                 dmas = <&dmac 2>, <&dmac 3>;
 297                 dma-names = "tx", "rx";
 298                 pinctrl-names = "default";
 299                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 300                 reg-io-width = <4>;
 301                 reg-shift = <2>;
 302                 status = "disabled";
 303         };
 304
 305         uart1: serial@ff120000 {
 306                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 307                 reg = <0x0 0xff120000 0x0 0x100>;
 308                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 309                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 310                 clock-names = "baudclk", "apb_pclk";
 311                 dmas = <&dmac 4>, <&dmac 5>;
 312                 dma-names = "tx", "rx";
 313                 pinctrl-names = "default";
 314                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 315                 reg-io-width = <4>;
 316                 reg-shift = <2>;
 317                 status = "disabled";
 318         };
 319
 320         uart2: serial@ff130000 {
 321                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 322                 reg = <0x0 0xff130000 0x0 0x100>;
 323                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 324                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 325                 clock-names = "baudclk", "apb_pclk";
 326                 dmas = <&dmac 6>, <&dmac 7>;
 327                 dma-names = "tx", "rx";
 328                 pinctrl-names = "default";
 329                 pinctrl-0 = <&uart2m1_xfer>;
 330                 reg-io-width = <4>;
 331                 reg-shift = <2>;
 332                 status = "disabled";
 333         };
 334
 335         i2c0: i2c@ff150000 {
 336                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 337                 reg = <0x0 0xff150000 0x0 0x1000>;
 338                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 339                 #address-cells = <1>;
 340                 #size-cells = <0>;
 341                 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
 342                 clock-names = "i2c", "pclk";
 343                 pinctrl-names = "default";
 344                 pinctrl-0 = <&i2c0_xfer>;
 345                 status = "disabled";
 346         };
 347
 348         i2c1: i2c@ff160000 {
 349                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 350                 reg = <0x0 0xff160000 0x0 0x1000>;
 351                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 352                 #address-cells = <1>;
 353                 #size-cells = <0>;
 354                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 355                 clock-names = "i2c", "pclk";
 356                 pinctrl-names = "default";
 357                 pinctrl-0 = <&i2c1_xfer>;
 358                 status = "disabled";
 359         };
 360
 361         i2c2: i2c@ff170000 {
 362                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 363                 reg = <0x0 0xff170000 0x0 0x1000>;
 364                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 365                 #address-cells = <1>;
 366                 #size-cells = <0>;
 367                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 368                 clock-names = "i2c", "pclk";
 369                 pinctrl-names = "default";
 370                 pinctrl-0 = <&i2c2_xfer>;
 371                 status = "disabled";
 372         };
 373
 374         i2c3: i2c@ff180000 {
 375                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 376                 reg = <0x0 0xff180000 0x0 0x1000>;
 377                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 378                 #address-cells = <1>;
 379                 #size-cells = <0>;
 380                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 381                 clock-names = "i2c", "pclk";
 382                 pinctrl-names = "default";
 383                 pinctrl-0 = <&i2c3_xfer>;
 384                 status = "disabled";
 385         };
 386
 387         spi0: spi@ff190000 {
 388                 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
 389                 reg = <0x0 0xff190000 0x0 0x1000>;
 390                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 391                 #address-cells = <1>;
 392                 #size-cells = <0>;
 393                 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
 394                 clock-names = "spiclk", "apb_pclk";
 395                 dmas = <&dmac 8>, <&dmac 9>;
 396                 dma-names = "tx", "rx";
 397                 pinctrl-names = "default";
 398                 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
 399                 status = "disabled";
 400         };
 401
 402         wdt: watchdog@ff1a0000 {
 403                 compatible = "snps,dw-wdt";
 404                 reg = <0x0 0xff1a0000 0x0 0x100>;
 405                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 406         };
 407
 408         pwm0: pwm@ff1b0000 {
 409                 compatible = "rockchip,rk3328-pwm";
 410                 reg = <0x0 0xff1b0000 0x0 0x10>;
 411                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 412                 clock-names = "pwm", "pclk";
 413                 pinctrl-names = "default";
 414                 pinctrl-0 = <&pwm0_pin>;
 415                 #pwm-cells = <3>;
 416                 status = "disabled";
 417         };
 418
 419         pwm1: pwm@ff1b0010 {
 420                 compatible = "rockchip,rk3328-pwm";
 421                 reg = <0x0 0xff1b0010 0x0 0x10>;
 422                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 423                 clock-names = "pwm", "pclk";
 424                 pinctrl-names = "default";
 425                 pinctrl-0 = <&pwm1_pin>;
 426                 #pwm-cells = <3>;
 427                 status = "disabled";
 428         };
 429
 430         pwm2: pwm@ff1b0020 {
 431                 compatible = "rockchip,rk3328-pwm";
 432                 reg = <0x0 0xff1b0020 0x0 0x10>;
 433                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 434                 clock-names = "pwm", "pclk";
 435                 pinctrl-names = "default";
 436                 pinctrl-0 = <&pwm2_pin>;
 437                 #pwm-cells = <3>;
 438                 status = "disabled";
 439         };
 440
 441         pwm3: pwm@ff1b0030 {
 442                 compatible = "rockchip,rk3328-pwm";
 443                 reg = <0x0 0xff1b0030 0x0 0x10>;
 444                 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 445                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 446                 clock-names = "pwm", "pclk";
 447                 pinctrl-names = "default";
 448                 pinctrl-0 = <&pwmir_pin>;
 449                 #pwm-cells = <3>;
 450                 status = "disabled";
 451         };
 452
 453         thermal-zones {
 454                 soc_thermal: soc-thermal {
 455                         polling-delay-passive = <20>;
 456                         polling-delay = <1000>;
 457                         sustainable-power = <1000>;
 458
 459                         thermal-sensors = <&tsadc 0>;
 460
 461                         trips {
 462                                 threshold: trip-point0 {
 463                                         temperature = <70000>;
 464                                         hysteresis = <2000>;
 465                                         type = "passive";
 466                                 };
 467                                 target: trip-point1 {
 468                                         temperature = <85000>;
 469                                         hysteresis = <2000>;
 470                                         type = "passive";
 471                                 };
 472                                 soc_crit: soc-crit {
 473                                         temperature = <95000>;
 474                                         hysteresis = <2000>;
 475                                         type = "critical";
 476                                 };
 477                         };
 478
 479                         cooling-maps {
 480                                 map0 {
 481                                         trip = <&target>;
 482                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 483                                                          <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 484                                                          <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 485                                                          <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 486                                         contribution = <4096>;
 487                                 };
 488                         };
 489                 };
 490
 491         };
 492
 493         tsadc: tsadc@ff250000 {
 494                 compatible = "rockchip,rk3328-tsadc";
 495                 reg = <0x0 0xff250000 0x0 0x100>;
 496                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 497                 assigned-clocks = <&cru SCLK_TSADC>;
 498                 assigned-clock-rates = <50000>;
 499                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 500                 clock-names = "tsadc", "apb_pclk";
 501                 pinctrl-names = "init", "default", "sleep";
 502                 pinctrl-0 = <&otp_gpio>;
 503                 pinctrl-1 = <&otp_out>;
 504                 pinctrl-2 = <&otp_gpio>;
 505                 resets = <&cru SRST_TSADC>;
 506                 reset-names = "tsadc-apb";
 507                 rockchip,grf = <&grf>;
 508                 rockchip,hw-tshut-temp = <100000>;
 509                 #thermal-sensor-cells = <1>;
 510                 status = "disabled";
 511         };
 512
 513         efuse: efuse@ff260000 {
 514                 compatible = "rockchip,rk3328-efuse";
 515                 reg = <0x0 0xff260000 0x0 0x50>;
 516                 #address-cells = <1>;
 517                 #size-cells = <1>;
 518                 clocks = <&cru SCLK_EFUSE>;
 519                 clock-names = "pclk_efuse";
 520                 rockchip,efuse-size = <0x20>;
 521
 522                 /* Data cells */
 523                 efuse_id: id@7 {
 524                         reg = <0x07 0x10>;
 525                 };
 526                 cpu_leakage: cpu-leakage@17 {
 527                         reg = <0x17 0x1>;
 528                 };
 529                 logic_leakage: logic-leakage@19 {
 530                         reg = <0x19 0x1>;
 531                 };
 532                 efuse_cpu_version: cpu-version@1a {
 533                         reg = <0x1a 0x1>;
 534                         bits = <3 3>;
 535                 };
 536         };
 537
 538         saradc: adc@ff280000 {
 539                 compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc";
 540                 reg = <0x0 0xff280000 0x0 0x100>;
 541                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 542                 #io-channel-cells = <1>;
 543                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 544                 clock-names = "saradc", "apb_pclk";
 545                 resets = <&cru SRST_SARADC_P>;
 546                 reset-names = "saradc-apb";
 547                 status = "disabled";
 548         };
 549
 550         gpu: gpu@ff300000 {
 551                 compatible = "rockchip,rk3328-mali", "arm,mali-450";
 552                 reg = <0x0 0xff300000 0x0 0x40000>;
 553                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
 554                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 555                              <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
 556                              <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
 557                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 558                              <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
 559                              <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 560                 interrupt-names = "gp",
 561                                   "gpmmu",
 562                                   "pp",
 563                                   "pp0",
 564                                   "ppmmu0",
 565                                   "pp1",
 566                                   "ppmmu1";
 567                 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
 568                 clock-names = "bus", "core";
 569                 resets = <&cru SRST_GPU_A>;
 570         };
 571
 572         h265e_mmu: iommu@ff330200 {
 573                 compatible = "rockchip,iommu";
 574                 reg = <0x0 0xff330200 0 0x100>;
 575                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 576                 interrupt-names = "h265e_mmu";
 577                 clocks = <&cru ACLK_H265>, <&cru PCLK_H265>;
 578                 clock-names = "aclk", "iface";
 579                 #iommu-cells = <0>;
 580                 status = "disabled";
 581         };
 582
 583         vepu_mmu: iommu@ff340800 {
 584                 compatible = "rockchip,iommu";
 585                 reg = <0x0 0xff340800 0x0 0x40>;
 586                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 587                 interrupt-names = "vepu_mmu";
 588                 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
 589                 clock-names = "aclk", "iface";
 590                 #iommu-cells = <0>;
 591                 status = "disabled";
 592         };
 593
 594         vpu_mmu: iommu@ff350800 {
 595                 compatible = "rockchip,iommu";
 596                 reg = <0x0 0xff350800 0x0 0x40>;
 597                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 598                 interrupt-names = "vpu_mmu";
 599                 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
 600                 clock-names = "aclk", "iface";
 601                 #iommu-cells = <0>;
 602                 status = "disabled";
 603         };
 604
 605         rkvdec_mmu: iommu@ff360480 {
 606                 compatible = "rockchip,iommu";
 607                 reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>;
 608                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 609                 interrupt-names = "rkvdec_mmu";
 610                 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
 611                 clock-names = "aclk", "iface";
 612                 #iommu-cells = <0>;
 613                 status = "disabled";
 614         };
 615
 616         vop: vop@ff370000 {
 617                 compatible = "rockchip,rk3328-vop";
 618                 reg = <0x0 0xff370000 0x0 0x3efc>;
 619                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 620                 clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>;
 621                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 622                 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
 623                 reset-names = "axi", "ahb", "dclk";
 624                 iommus = <&vop_mmu>;
 625                 status = "disabled";
 626
 627                 vop_out: port {
 628                         #address-cells = <1>;
 629                         #size-cells = <0>;
 630
 631                         vop_out_hdmi: endpoint@0 {
 632                                 reg = <0>;
 633                                 remote-endpoint = <&hdmi_in_vop>;
 634                         };
 635                 };
 636         };
 637
 638         vop_mmu: iommu@ff373f00 {
 639                 compatible = "rockchip,iommu";
 640                 reg = <0x0 0xff373f00 0x0 0x100>;
 641                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 642                 interrupt-names = "vop_mmu";
 643                 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
 644                 clock-names = "aclk", "iface";
 645                 #iommu-cells = <0>;
 646                 status = "disabled";
 647         };
 648
 649         hdmi: hdmi@ff3c0000 {
 650                 compatible = "rockchip,rk3328-dw-hdmi";
 651                 reg = <0x0 0xff3c0000 0x0 0x20000>;
 652                 reg-io-width = <4>;
 653                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 654                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 655                 clocks = <&cru PCLK_HDMI>,
 656                          <&cru SCLK_HDMI_SFC>;
 657                 clock-names = "iahb",
 658                               "isfr";
 659                 phys = <&hdmiphy>;
 660                 phy-names = "hdmi";
 661                 pinctrl-names = "default";
 662                 pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>;
 663                 rockchip,grf = <&grf>;
 664                 status = "disabled";
 665
 666                 ports {
 667                         hdmi_in: port {
 668                                 hdmi_in_vop: endpoint {
 669                                         remote-endpoint = <&vop_out_hdmi>;
 670                                 };
 671                         };
 672                 };
 673         };
 674
 675         hdmiphy: phy@ff430000 {
 676                 compatible = "rockchip,rk3328-hdmi-phy";
 677                 reg = <0x0 0xff430000 0x0 0x10000>;
 678                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 679                 clocks = <&cru PCLK_HDMIPHY>, <&xin24m>, <&cru DCLK_HDMIPHY>;
 680                 clock-names = "sysclk", "refoclk", "refpclk";
 681                 clock-output-names = "hdmi_phy";
 682                 #clock-cells = <0>;
 683                 nvmem-cells = <&efuse_cpu_version>;
 684                 nvmem-cell-names = "cpu-version";
 685                 #phy-cells = <0>;
 686                 status = "disabled";
 687         };
 688
 689         cru: clock-controller@ff440000 {
 690                 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
 691                 reg = <0x0 0xff440000 0x0 0x1000>;
 692                 rockchip,grf = <&grf>;
 693                 #clock-cells = <1>;
 694                 #reset-cells = <1>;
 695                 assigned-clocks =
 696                         /*
 697                          * CPLL should run at 1200, but that is to high for
 698                          * the initial dividers of most of its children.
 699                          * We need set cpll child clk div first,
 700                          * and then set the cpll frequency.
 701                          */
 702                         <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
 703                         <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
 704                         <&cru SCLK_UART1>, <&cru SCLK_UART2>,
 705                         <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 706                         <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
 707                         <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
 708                         <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
 709                         <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
 710                         <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
 711                         <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
 712                         <&cru SCLK_WIFI>, <&cru ARMCLK>,
 713                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 714                         <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
 715                         <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 716                         <&cru HCLK_PERI>, <&cru PCLK_PERI>,
 717                         <&cru SCLK_RTC32K>;
 718                 assigned-clock-parents =
 719                         <&cru HDMIPHY>, <&cru PLL_APLL>,
 720                         <&cru PLL_GPLL>, <&xin24m>,
 721                         <&xin24m>, <&xin24m>;
 722                 assigned-clock-rates =
 723                         <0>, <61440000>,
 724                         <0>, <24000000>,
 725                         <24000000>, <24000000>,
 726                         <15000000>, <15000000>,
 727                         <100000000>, <100000000>,
 728                         <100000000>, <100000000>,
 729                         <50000000>, <100000000>,
 730                         <100000000>, <100000000>,
 731                         <50000000>, <50000000>,
 732                         <50000000>, <50000000>,
 733                         <24000000>, <600000000>,
 734                         <491520000>, <1200000000>,
 735                         <150000000>, <75000000>,
 736                         <75000000>, <150000000>,
 737                         <75000000>, <75000000>,
 738                         <32768>;
 739         };
 740
 741         usb2phy_grf: syscon@ff450000 {
 742                 compatible = "rockchip,rk3328-usb2phy-grf", "syscon",
 743                              "simple-mfd";
 744                 reg = <0x0 0xff450000 0x0 0x10000>;
 745                 #address-cells = <1>;
 746                 #size-cells = <1>;
 747
 748                 u2phy: usb2-phy@100 {
 749                         compatible = "rockchip,rk3328-usb2phy";
 750                         reg = <0x100 0x10>;
 751                         clocks = <&xin24m>;
 752                         clock-names = "phyclk";
 753                         clock-output-names = "usb480m_phy";
 754                         #clock-cells = <0>;
 755                         assigned-clocks = <&cru USB480M>;
 756                         assigned-clock-parents = <&u2phy>;
 757                         status = "disabled";
 758
 759                         u2phy_otg: otg-port {
 760                                 #phy-cells = <0>;
 761                                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 762                                              <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 763                                              <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 764                                 interrupt-names = "otg-bvalid", "otg-id",
 765                                                   "linestate";
 766                                 status = "disabled";
 767                         };
 768
 769                         u2phy_host: host-port {
 770                                 #phy-cells = <0>;
 771                                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 772                                 interrupt-names = "linestate";
 773                                 status = "disabled";
 774                         };
 775                 };
 776         };
 777
 778         sdmmc: dwmmc@ff500000 {
 779                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 780                 reg = <0x0 0xff500000 0x0 0x4000>;
 781                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 782                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 783                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 784                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 785                 fifo-depth = <0x100>;
 786                 status = "disabled";
 787         };
 788
 789         sdio: dwmmc@ff510000 {
 790                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 791                 reg = <0x0 0xff510000 0x0 0x4000>;
 792                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 793                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 794                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 795                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 796                 fifo-depth = <0x100>;
 797                 status = "disabled";
 798         };
 799
 800         emmc: dwmmc@ff520000 {
 801                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 802                 reg = <0x0 0xff520000 0x0 0x4000>;
 803                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 804                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 805                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 806                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 807                 fifo-depth = <0x100>;
 808                 status = "disabled";
 809         };
 810
 811         gmac2io: ethernet@ff540000 {
 812                 compatible = "rockchip,rk3328-gmac";
 813                 reg = <0x0 0xff540000 0x0 0x10000>;
 814                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 815                 interrupt-names = "macirq";
 816                 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
 817                          <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
 818                          <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
 819                          <&cru PCLK_MAC2IO>;
 820                 clock-names = "stmmaceth", "mac_clk_rx",
 821                               "mac_clk_tx", "clk_mac_ref",
 822                               "clk_mac_refout", "aclk_mac",
 823                               "pclk_mac";
 824                 resets = <&cru SRST_GMAC2IO_A>;
 825                 reset-names = "stmmaceth";
 826                 rockchip,grf = <&grf>;
 827                 status = "disabled";
 828         };
 829
 830         gmac2phy: ethernet@ff550000 {
 831                 compatible = "rockchip,rk3328-gmac";
 832                 reg = <0x0 0xff550000 0x0 0x10000>;
 833                 rockchip,grf = <&grf>;
 834                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 835                 interrupt-names = "macirq";
 836                 clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>,
 837                          <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>,
 838                          <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>,
 839                          <&cru SCLK_MAC2PHY_OUT>;
 840                 clock-names = "stmmaceth", "mac_clk_rx",
 841                               "mac_clk_tx", "clk_mac_ref",
 842                               "aclk_mac", "pclk_mac",
 843                               "clk_macphy";
 844                 resets = <&cru SRST_GMAC2PHY_A>, <&cru SRST_MACPHY>;
 845                 reset-names = "stmmaceth", "mac-phy";
 846                 phy-mode = "rmii";
 847                 phy-handle = <&phy>;
 848                 status = "disabled";
 849
 850                 mdio {
 851                         compatible = "snps,dwmac-mdio";
 852                         #address-cells = <1>;
 853                         #size-cells = <0>;
 854
 855                         phy: phy@0 {
 856                                 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
 857                                 reg = <0>;
 858                                 clocks = <&cru SCLK_MAC2PHY_OUT>;
 859                                 resets = <&cru SRST_MACPHY>;
 860                                 pinctrl-names = "default";
 861                                 pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>;
 862                                 phy-is-integrated;
 863                         };
 864                 };
 865         };
 866
 867         usb20_otg: usb@ff580000 {
 868                 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
 869                              "snps,dwc2";
 870                 reg = <0x0 0xff580000 0x0 0x40000>;
 871                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 872                 clocks = <&cru HCLK_OTG>;
 873                 clock-names = "otg";
 874                 dr_mode = "otg";
 875                 g-np-tx-fifo-size = <16>;
 876                 g-rx-fifo-size = <280>;
 877                 g-tx-fifo-size = <256 128 128 64 32 16>;
 878                 g-use-dma;
 879                 phys = <&u2phy_otg>;
 880                 phy-names = "usb2-phy";
 881                 status = "disabled";
 882         };
 883
 884         usb_host0_ehci: usb@ff5c0000 {
 885                 compatible = "generic-ehci";
 886                 reg = <0x0 0xff5c0000 0x0 0x10000>;
 887                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 888                 clocks = <&cru HCLK_HOST0>, <&u2phy>;
 889                 clock-names = "usbhost", "utmi";
 890                 phys = <&u2phy_host>;
 891                 phy-names = "usb";
 892                 status = "disabled";
 893         };
 894
 895         usb_host0_ohci: usb@ff5d0000 {
 896                 compatible = "generic-ohci";
 897                 reg = <0x0 0xff5d0000 0x0 0x10000>;
 898                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 899                 clocks = <&cru HCLK_HOST0>, <&u2phy>;
 900                 clock-names = "usbhost", "utmi";
 901                 phys = <&u2phy_host>;
 902                 phy-names = "usb";
 903                 status = "disabled";
 904         };
 905
 906         gic: interrupt-controller@ff811000 {
 907                 compatible = "arm,gic-400";
 908                 #interrupt-cells = <3>;
 909                 #address-cells = <0>;
 910                 interrupt-controller;
 911                 reg = <0x0 0xff811000 0 0x1000>,
 912                       <0x0 0xff812000 0 0x2000>,
 913                       <0x0 0xff814000 0 0x2000>,
 914                       <0x0 0xff816000 0 0x2000>;
 915                 interrupts = <GIC_PPI 9
 916                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 917         };
 918
 919         pinctrl: pinctrl {
 920                 compatible = "rockchip,rk3328-pinctrl";
 921                 rockchip,grf = <&grf>;
 922                 #address-cells = <2>;
 923                 #size-cells = <2>;
 924                 ranges;
 925
 926                 gpio0: gpio0@ff210000 {
 927                         compatible = "rockchip,gpio-bank";
 928                         reg = <0x0 0xff210000 0x0 0x100>;
 929                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 930                         clocks = <&cru PCLK_GPIO0>;
 931
 932                         gpio-controller;
 933                         #gpio-cells = <2>;
 934
 935                         interrupt-controller;
 936                         #interrupt-cells = <2>;
 937                 };
 938
 939                 gpio1: gpio1@ff220000 {
 940                         compatible = "rockchip,gpio-bank";
 941                         reg = <0x0 0xff220000 0x0 0x100>;
 942                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 943                         clocks = <&cru PCLK_GPIO1>;
 944
 945                         gpio-controller;
 946                         #gpio-cells = <2>;
 947
 948                         interrupt-controller;
 949                         #interrupt-cells = <2>;
 950                 };
 951
 952                 gpio2: gpio2@ff230000 {
 953                         compatible = "rockchip,gpio-bank";
 954                         reg = <0x0 0xff230000 0x0 0x100>;
 955                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 956                         clocks = <&cru PCLK_GPIO2>;
 957
 958                         gpio-controller;
 959                         #gpio-cells = <2>;
 960
 961                         interrupt-controller;
 962                         #interrupt-cells = <2>;
 963                 };
 964
 965                 gpio3: gpio3@ff240000 {
 966                         compatible = "rockchip,gpio-bank";
 967                         reg = <0x0 0xff240000 0x0 0x100>;
 968                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 969                         clocks = <&cru PCLK_GPIO3>;
 970
 971                         gpio-controller;
 972                         #gpio-cells = <2>;
 973
 974                         interrupt-controller;
 975                         #interrupt-cells = <2>;
 976                 };
 977
 978                 pcfg_pull_up: pcfg-pull-up {
 979                         bias-pull-up;
 980                 };
 981
 982                 pcfg_pull_down: pcfg-pull-down {
 983                         bias-pull-down;
 984                 };
 985
 986                 pcfg_pull_none: pcfg-pull-none {
 987                         bias-disable;
 988                 };
 989
 990                 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
 991                         bias-disable;
 992                         drive-strength = <2>;
 993                 };
 994
 995                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
 996                         bias-pull-up;
 997                         drive-strength = <2>;
 998                 };
 999
1000                 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
1001                         bias-pull-up;
1002                         drive-strength = <4>;
1003                 };
1004
1005                 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
1006                         bias-disable;
1007                         drive-strength = <4>;
1008                 };
1009
1010                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1011                         bias-pull-down;
1012                         drive-strength = <4>;
1013                 };
1014
1015                 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
1016                         bias-disable;
1017                         drive-strength = <8>;
1018                 };
1019
1020                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1021                         bias-pull-up;
1022                         drive-strength = <8>;
1023                 };
1024
1025                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1026                         bias-disable;
1027                         drive-strength = <12>;
1028                 };
1029
1030                 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
1031                         bias-pull-up;
1032                         drive-strength = <12>;
1033                 };
1034
1035                 pcfg_output_high: pcfg-output-high {
1036                         output-high;
1037                 };
1038
1039                 pcfg_output_low: pcfg-output-low {
1040                         output-low;
1041                 };
1042
1043                 pcfg_input_high: pcfg-input-high {
1044                         bias-pull-up;
1045                         input-enable;
1046                 };
1047
1048                 pcfg_input: pcfg-input {
1049                         input-enable;
1050                 };
1051
1052                 i2c0 {
1053                         i2c0_xfer: i2c0-xfer {
1054                                 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>,
1055                                                 <2 RK_PD1 1 &pcfg_pull_none>;
1056                         };
1057                 };
1058
1059                 i2c1 {
1060                         i2c1_xfer: i2c1-xfer {
1061                                 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>,
1062                                                 <2 RK_PA5 2 &pcfg_pull_none>;
1063                         };
1064                 };
1065
1066                 i2c2 {
1067                         i2c2_xfer: i2c2-xfer {
1068                                 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>,
1069                                                 <2 RK_PB6 1 &pcfg_pull_none>;
1070                         };
1071                 };
1072
1073                 i2c3 {
1074                         i2c3_xfer: i2c3-xfer {
1075                                 rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>,
1076                                                 <0 RK_PA6 2 &pcfg_pull_none>;
1077                         };
1078                         i2c3_gpio: i2c3-gpio {
1079                                 rockchip,pins =
1080                                         <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>,
1081                                         <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1082                         };
1083                 };
1084
1085                 hdmi_i2c {
1086                         hdmii2c_xfer: hdmii2c-xfer {
1087                                 rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>,
1088                                                 <0 RK_PA6 1 &pcfg_pull_none>;
1089                         };
1090                 };
1091
1092                 pdm-0 {
1093                         pdmm0_clk: pdmm0-clk {
1094                                 rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>;
1095                         };
1096
1097                         pdmm0_fsync: pdmm0-fsync {
1098                                 rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>;
1099                         };
1100
1101                         pdmm0_sdi0: pdmm0-sdi0 {
1102                                 rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>;
1103                         };
1104
1105                         pdmm0_sdi1: pdmm0-sdi1 {
1106                                 rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>;
1107                         };
1108
1109                         pdmm0_sdi2: pdmm0-sdi2 {
1110                                 rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>;
1111                         };
1112
1113                         pdmm0_sdi3: pdmm0-sdi3 {
1114                                 rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>;
1115                         };
1116
1117                         pdmm0_clk_sleep: pdmm0-clk-sleep {
1118                                 rockchip,pins =
1119                                         <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>;
1120                         };
1121
1122                         pdmm0_sdi0_sleep: pdmm0-sdi0-sleep {
1123                                 rockchip,pins =
1124                                         <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>;
1125                         };
1126
1127                         pdmm0_sdi1_sleep: pdmm0-sdi1-sleep {
1128                                 rockchip,pins =
1129                                         <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>;
1130                         };
1131
1132                         pdmm0_sdi2_sleep: pdmm0-sdi2-sleep {
1133                                 rockchip,pins =
1134                                         <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>;
1135                         };
1136
1137                         pdmm0_sdi3_sleep: pdmm0-sdi3-sleep {
1138                                 rockchip,pins =
1139                                         <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1140                         };
1141
1142                         pdmm0_fsync_sleep: pdmm0-fsync-sleep {
1143                                 rockchip,pins =
1144                                         <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1145                         };
1146                 };
1147
1148                 tsadc {
1149                         otp_gpio: otp-gpio {
1150                                 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1151                         };
1152
1153                         otp_out: otp-out {
1154                                 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>;
1155                         };
1156                 };
1157
1158                 uart0 {
1159                         uart0_xfer: uart0-xfer {
1160                                 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_up>,
1161                                                 <1 RK_PB0 1 &pcfg_pull_none>;
1162                         };
1163
1164                         uart0_cts: uart0-cts {
1165                                 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;
1166                         };
1167
1168                         uart0_rts: uart0-rts {
1169                                 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>;
1170                         };
1171
1172                         uart0_rts_gpio: uart0-rts-gpio {
1173                                 rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
1174                         };
1175                 };
1176
1177                 uart1 {
1178                         uart1_xfer: uart1-xfer {
1179                                 rockchip,pins = <3 RK_PA4 4 &pcfg_pull_up>,
1180                                                 <3 RK_PA6 4 &pcfg_pull_none>;
1181                         };
1182
1183                         uart1_cts: uart1-cts {
1184                                 rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>;
1185                         };
1186
1187                         uart1_rts: uart1-rts {
1188                                 rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>;
1189                         };
1190
1191                         uart1_rts_gpio: uart1-rts-gpio {
1192                                 rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
1193                         };
1194                 };
1195
1196                 uart2-0 {
1197                         uart2m0_xfer: uart2m0-xfer {
1198                                 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_up>,
1199                                                 <1 RK_PA1 2 &pcfg_pull_none>;
1200                         };
1201                 };
1202
1203                 uart2-1 {
1204                         uart2m1_xfer: uart2m1-xfer {
1205                                 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_up>,
1206                                                 <2 RK_PA1 1 &pcfg_pull_none>;
1207                         };
1208                 };
1209
1210                 spi0-0 {
1211                         spi0m0_clk: spi0m0-clk {
1212                                 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>;
1213                         };
1214
1215                         spi0m0_cs0: spi0m0-cs0 {
1216                                 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>;
1217                         };
1218
1219                         spi0m0_tx: spi0m0-tx {
1220                                 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>;
1221                         };
1222
1223                         spi0m0_rx: spi0m0-rx {
1224                                 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>;
1225                         };
1226
1227                         spi0m0_cs1: spi0m0-cs1 {
1228                                 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>;
1229                         };
1230                 };
1231
1232                 spi0-1 {
1233                         spi0m1_clk: spi0m1-clk {
1234                                 rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>;
1235                         };
1236
1237                         spi0m1_cs0: spi0m1-cs0 {
1238                                 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>;
1239                         };
1240
1241                         spi0m1_tx: spi0m1-tx {
1242                                 rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>;
1243                         };
1244
1245                         spi0m1_rx: spi0m1-rx {
1246                                 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>;
1247                         };
1248
1249                         spi0m1_cs1: spi0m1-cs1 {
1250                                 rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>;
1251                         };
1252                 };
1253
1254                 spi0-2 {
1255                         spi0m2_clk: spi0m2-clk {
1256                                 rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>;
1257                         };
1258
1259                         spi0m2_cs0: spi0m2-cs0 {
1260                                 rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>;
1261                         };
1262
1263                         spi0m2_tx: spi0m2-tx {
1264                                 rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>;
1265                         };
1266
1267                         spi0m2_rx: spi0m2-rx {
1268                                 rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>;
1269                         };
1270                 };
1271
1272                 i2s1 {
1273                         i2s1_mclk: i2s1-mclk {
1274                                 rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>;
1275                         };
1276
1277                         i2s1_sclk: i2s1-sclk {
1278                                 rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>;
1279                         };
1280
1281                         i2s1_lrckrx: i2s1-lrckrx {
1282                                 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>;
1283                         };
1284
1285                         i2s1_lrcktx: i2s1-lrcktx {
1286                                 rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>;
1287                         };
1288
1289                         i2s1_sdi: i2s1-sdi {
1290                                 rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>;
1291                         };
1292
1293                         i2s1_sdo: i2s1-sdo {
1294                                 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>;
1295                         };
1296
1297                         i2s1_sdio1: i2s1-sdio1 {
1298                                 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>;
1299                         };
1300
1301                         i2s1_sdio2: i2s1-sdio2 {
1302                                 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>;
1303                         };
1304
1305                         i2s1_sdio3: i2s1-sdio3 {
1306                                 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>;
1307                         };
1308
1309                         i2s1_sleep: i2s1-sleep {
1310                                 rockchip,pins =
1311                                         <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>,
1312                                         <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>,
1313                                         <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>,
1314                                         <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>,
1315                                         <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>,
1316                                         <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>,
1317                                         <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1318                                         <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1319                                         <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1320                         };
1321                 };
1322
1323                 i2s2-0 {
1324                         i2s2m0_mclk: i2s2m0-mclk {
1325                                 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
1326                         };
1327
1328                         i2s2m0_sclk: i2s2m0-sclk {
1329                                 rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>;
1330                         };
1331
1332                         i2s2m0_lrckrx: i2s2m0-lrckrx {
1333                                 rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>;
1334                         };
1335
1336                         i2s2m0_lrcktx: i2s2m0-lrcktx {
1337                                 rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>;
1338                         };
1339
1340                         i2s2m0_sdi: i2s2m0-sdi {
1341                                 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>;
1342                         };
1343
1344                         i2s2m0_sdo: i2s2m0-sdo {
1345                                 rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>;
1346                         };
1347
1348                         i2s2m0_sleep: i2s2m0-sleep {
1349                                 rockchip,pins =
1350                                         <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1351                                         <1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1352                                         <1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>,
1353                                         <1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>,
1354                                         <1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>,
1355                                         <1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>;
1356                         };
1357                 };
1358
1359                 i2s2-1 {
1360                         i2s2m1_mclk: i2s2m1-mclk {
1361                                 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
1362                         };
1363
1364                         i2s2m1_sclk: i2s2m1-sclk {
1365                                 rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>;
1366                         };
1367
1368                         i2s2m1_lrckrx: i2sm1-lrckrx {
1369                                 rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>;
1370                         };
1371
1372                         i2s2m1_lrcktx: i2s2m1-lrcktx {
1373                                 rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>;
1374                         };
1375
1376                         i2s2m1_sdi: i2s2m1-sdi {
1377                                 rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>;
1378                         };
1379
1380                         i2s2m1_sdo: i2s2m1-sdo {
1381                                 rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>;
1382                         };
1383
1384                         i2s2m1_sleep: i2s2m1-sleep {
1385                                 rockchip,pins =
1386                                         <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1387                                         <3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>,
1388                                         <3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>,
1389                                         <3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>,
1390                                         <3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>;
1391                         };
1392                 };
1393
1394                 spdif-0 {
1395                         spdifm0_tx: spdifm0-tx {
1396                                 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
1397                         };
1398                 };
1399
1400                 spdif-1 {
1401                         spdifm1_tx: spdifm1-tx {
1402                                 rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>;
1403                         };
1404                 };
1405
1406                 spdif-2 {
1407                         spdifm2_tx: spdifm2-tx {
1408                                 rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>;
1409                         };
1410                 };
1411
1412                 sdmmc0-0 {
1413                         sdmmc0m0_pwren: sdmmc0m0-pwren {
1414                                 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>;
1415                         };
1416
1417                         sdmmc0m0_gpio: sdmmc0m0-gpio {
1418                                 rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1419                         };
1420                 };
1421
1422                 sdmmc0-1 {
1423                         sdmmc0m1_pwren: sdmmc0m1-pwren {
1424                                 rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>;
1425                         };
1426
1427                         sdmmc0m1_gpio: sdmmc0m1-gpio {
1428                                 rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1429                         };
1430                 };
1431
1432                 sdmmc0 {
1433                         sdmmc0_clk: sdmmc0-clk {
1434                                 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_4ma>;
1435                         };
1436
1437                         sdmmc0_cmd: sdmmc0-cmd {
1438                                 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_4ma>;
1439                         };
1440
1441                         sdmmc0_dectn: sdmmc0-dectn {
1442                                 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>;
1443                         };
1444
1445                         sdmmc0_wrprt: sdmmc0-wrprt {
1446                                 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>;
1447                         };
1448
1449                         sdmmc0_bus1: sdmmc0-bus1 {
1450                                 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_4ma>;
1451                         };
1452
1453                         sdmmc0_bus4: sdmmc0-bus4 {
1454                                 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_4ma>,
1455                                                 <1 RK_PA1 1 &pcfg_pull_up_4ma>,
1456                                                 <1 RK_PA2 1 &pcfg_pull_up_4ma>,
1457                                                 <1 RK_PA3 1 &pcfg_pull_up_4ma>;
1458                         };
1459
1460                         sdmmc0_gpio: sdmmc0-gpio {
1461                                 rockchip,pins =
1462                                         <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1463                                         <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1464                                         <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1465                                         <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1466                                         <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1467                                         <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1468                                         <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1469                                         <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1470                         };
1471                 };
1472
1473                 sdmmc0ext {
1474                         sdmmc0ext_clk: sdmmc0ext-clk {
1475                                 rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_4ma>;
1476                         };
1477
1478                         sdmmc0ext_cmd: sdmmc0ext-cmd {
1479                                 rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>;
1480                         };
1481
1482                         sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1483                                 rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>;
1484                         };
1485
1486                         sdmmc0ext_dectn: sdmmc0ext-dectn {
1487                                 rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>;
1488                         };
1489
1490                         sdmmc0ext_bus1: sdmmc0ext-bus1 {
1491                                 rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>;
1492                         };
1493
1494                         sdmmc0ext_bus4: sdmmc0ext-bus4 {
1495                                 rockchip,pins =
1496                                         <3 RK_PA4 3 &pcfg_pull_up_4ma>,
1497                                         <3 RK_PA5 3 &pcfg_pull_up_4ma>,
1498                                         <3 RK_PA6 3 &pcfg_pull_up_4ma>,
1499                                         <3 RK_PA7 3 &pcfg_pull_up_4ma>;
1500                         };
1501
1502                         sdmmc0ext_gpio: sdmmc0ext-gpio {
1503                                 rockchip,pins =
1504                                         <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1505                                         <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1506                                         <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1507                                         <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1508                                         <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1509                                         <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1510                                         <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1511                                         <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1512                         };
1513                 };
1514
1515                 sdmmc1 {
1516                         sdmmc1_clk: sdmmc1-clk {
1517                                 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none_8ma>;
1518                         };
1519
1520                         sdmmc1_cmd: sdmmc1-cmd {
1521                                 rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>;
1522                         };
1523
1524                         sdmmc1_pwren: sdmmc1-pwren {
1525                                 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>;
1526                         };
1527
1528                         sdmmc1_wrprt: sdmmc1-wrprt {
1529                                 rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>;
1530                         };
1531
1532                         sdmmc1_dectn: sdmmc1-dectn {
1533                                 rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>;
1534                         };
1535
1536                         sdmmc1_bus1: sdmmc1-bus1 {
1537                                 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>;
1538                         };
1539
1540                         sdmmc1_bus4: sdmmc1-bus4 {
1541                                 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>,
1542                                                 <1 RK_PB7 1 &pcfg_pull_up_8ma>,
1543                                                 <1 RK_PC0 1 &pcfg_pull_up_8ma>,
1544                                                 <1 RK_PC1 1 &pcfg_pull_up_8ma>;
1545                         };
1546
1547                         sdmmc1_gpio: sdmmc1-gpio {
1548                                 rockchip,pins =
1549                                         <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1550                                         <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1551                                         <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1552                                         <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1553                                         <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1554                                         <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1555                                         <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1556                                         <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1557                                         <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1558                         };
1559                 };
1560
1561                 emmc {
1562                         emmc_clk: emmc-clk {
1563                                 rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none_12ma>;
1564                         };
1565
1566                         emmc_cmd: emmc-cmd {
1567                                 rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>;
1568                         };
1569
1570                         emmc_pwren: emmc-pwren {
1571                                 rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>;
1572                         };
1573
1574                         emmc_rstnout: emmc-rstnout {
1575                                 rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>;
1576                         };
1577
1578                         emmc_bus1: emmc-bus1 {
1579                                 rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>;
1580                         };
1581
1582                         emmc_bus4: emmc-bus4 {
1583                                 rockchip,pins =
1584                                         <0 RK_PA7 2 &pcfg_pull_up_12ma>,
1585                                         <2 RK_PD4 2 &pcfg_pull_up_12ma>,
1586                                         <2 RK_PD5 2 &pcfg_pull_up_12ma>,
1587                                         <2 RK_PD6 2 &pcfg_pull_up_12ma>;
1588                         };
1589
1590                         emmc_bus8: emmc-bus8 {
1591                                 rockchip,pins =
1592                                         <0 RK_PA7 2 &pcfg_pull_up_12ma>,
1593                                         <2 RK_PD4 2 &pcfg_pull_up_12ma>,
1594                                         <2 RK_PD5 2 &pcfg_pull_up_12ma>,
1595                                         <2 RK_PD6 2 &pcfg_pull_up_12ma>,
1596                                         <2 RK_PD7 2 &pcfg_pull_up_12ma>,
1597                                         <3 RK_PC0 2 &pcfg_pull_up_12ma>,
1598                                         <3 RK_PC1 2 &pcfg_pull_up_12ma>,
1599                                         <3 RK_PC2 2 &pcfg_pull_up_12ma>;
1600                         };
1601                 };
1602
1603                 pwm0 {
1604                         pwm0_pin: pwm0-pin {
1605                                 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>;
1606                         };
1607                 };
1608
1609                 pwm1 {
1610                         pwm1_pin: pwm1-pin {
1611                                 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>;
1612                         };
1613                 };
1614
1615                 pwm2 {
1616                         pwm2_pin: pwm2-pin {
1617                                 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>;
1618                         };
1619                 };
1620
1621                 pwmir {
1622                         pwmir_pin: pwmir-pin {
1623                                 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>;
1624                         };
1625                 };
1626
1627                 gmac-1 {
1628                         rgmiim1_pins: rgmiim1-pins {
1629                                 rockchip,pins =
1630                                         /* mac_txclk */
1631                                         <1 RK_PB4 2 &pcfg_pull_none_12ma>,
1632                                         /* mac_rxclk */
1633                                         <1 RK_PB5 2 &pcfg_pull_none_2ma>,
1634                                         /* mac_mdio */
1635                                         <1 RK_PC3 2 &pcfg_pull_none_2ma>,
1636                                         /* mac_txen */
1637                                         <1 RK_PD1 2 &pcfg_pull_none_12ma>,
1638                                         /* mac_clk */
1639                                         <1 RK_PC5 2 &pcfg_pull_none_2ma>,
1640                                         /* mac_rxdv */
1641                                         <1 RK_PC6 2 &pcfg_pull_none_2ma>,
1642                                         /* mac_mdc */
1643                                         <1 RK_PC7 2 &pcfg_pull_none_2ma>,
1644                                         /* mac_rxd1 */
1645                                         <1 RK_PB2 2 &pcfg_pull_none_2ma>,
1646                                         /* mac_rxd0 */
1647                                         <1 RK_PB3 2 &pcfg_pull_none_2ma>,
1648                                         /* mac_txd1 */
1649                                         <1 RK_PB0 2 &pcfg_pull_none_12ma>,
1650                                         /* mac_txd0 */
1651                                         <1 RK_PB1 2 &pcfg_pull_none_12ma>,
1652                                         /* mac_rxd3 */
1653                                         <1 RK_PB6 2 &pcfg_pull_none_2ma>,
1654                                         /* mac_rxd2 */
1655                                         <1 RK_PB7 2 &pcfg_pull_none_2ma>,
1656                                         /* mac_txd3 */
1657                                         <1 RK_PC0 2 &pcfg_pull_none_12ma>,
1658                                         /* mac_txd2 */
1659                                         <1 RK_PC1 2 &pcfg_pull_none_12ma>,
1660
1661                                         /* mac_txclk */
1662                                         <0 RK_PB0 1 &pcfg_pull_none>,
1663                                         /* mac_txen */
1664                                         <0 RK_PB4 1 &pcfg_pull_none>,
1665                                         /* mac_clk */
1666                                         <0 RK_PD0 1 &pcfg_pull_none>,
1667                                         /* mac_txd1 */
1668                                         <0 RK_PC0 1 &pcfg_pull_none>,
1669                                         /* mac_txd0 */
1670                                         <0 RK_PC1 1 &pcfg_pull_none>,
1671                                         /* mac_txd3 */
1672                                         <0 RK_PC7 1 &pcfg_pull_none>,
1673                                         /* mac_txd2 */
1674                                         <0 RK_PC6 1 &pcfg_pull_none>;
1675                         };
1676
1677                         rmiim1_pins: rmiim1-pins {
1678                                 rockchip,pins =
1679                                         /* mac_mdio */
1680                                         <1 RK_PC3 2 &pcfg_pull_none_2ma>,
1681                                         /* mac_txen */
1682                                         <1 RK_PD1 2 &pcfg_pull_none_12ma>,
1683                                         /* mac_clk */
1684                                         <1 RK_PC5 2 &pcfg_pull_none_2ma>,
1685                                         /* mac_rxer */
1686                                         <1 RK_PD0 2 &pcfg_pull_none_2ma>,
1687                                         /* mac_rxdv */
1688                                         <1 RK_PC6 2 &pcfg_pull_none_2ma>,
1689                                         /* mac_mdc */
1690                                         <1 RK_PC7 2 &pcfg_pull_none_2ma>,
1691                                         /* mac_rxd1 */
1692                                         <1 RK_PB2 2 &pcfg_pull_none_2ma>,
1693                                         /* mac_rxd0 */
1694                                         <1 RK_PB3 2 &pcfg_pull_none_2ma>,
1695                                         /* mac_txd1 */
1696                                         <1 RK_PB0 2 &pcfg_pull_none_12ma>,
1697                                         /* mac_txd0 */
1698                                         <1 RK_PB1 2 &pcfg_pull_none_12ma>,
1699
1700                                         /* mac_mdio */
1701                                         <0 RK_PB3 1 &pcfg_pull_none>,
1702                                         /* mac_txen */
1703                                         <0 RK_PB4 1 &pcfg_pull_none>,
1704                                         /* mac_clk */
1705                                         <0 RK_PD0 1 &pcfg_pull_none>,
1706                                         /* mac_mdc */
1707                                         <0 RK_PC3 1 &pcfg_pull_none>,
1708                                         /* mac_txd1 */
1709                                         <0 RK_PC0 1 &pcfg_pull_none>,
1710                                         /* mac_txd0 */
1711                                         <0 RK_PC1 1 &pcfg_pull_none>;
1712                         };
1713                 };
1714
1715                 gmac2phy {
1716                         fephyled_speed100: fephyled-speed100 {
1717                                 rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>;
1718                         };
1719
1720                         fephyled_speed10: fephyled-speed10 {
1721                                 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>;
1722                         };
1723
1724                         fephyled_duplex: fephyled-duplex {
1725                                 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
1726                         };
1727
1728                         fephyled_rxm0: fephyled-rxm0 {
1729                                 rockchip,pins = <0 RK_PD5 1 &pcfg_pull_none>;
1730                         };
1731
1732                         fephyled_txm0: fephyled-txm0 {
1733                                 rockchip,pins = <0 RK_PD5 2 &pcfg_pull_none>;
1734                         };
1735
1736                         fephyled_linkm0: fephyled-linkm0 {
1737                                 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>;
1738                         };
1739
1740                         fephyled_rxm1: fephyled-rxm1 {
1741                                 rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>;
1742                         };
1743
1744                         fephyled_txm1: fephyled-txm1 {
1745                                 rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>;
1746                         };
1747
1748                         fephyled_linkm1: fephyled-linkm1 {
1749                                 rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>;
1750                         };
1751                 };
1752
1753                 tsadc_pin {
1754                         tsadc_int: tsadc-int {
1755                                 rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>;
1756                         };
1757                         tsadc_gpio: tsadc-gpio {
1758                                 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1759                         };
1760                 };
1761
1762                 hdmi_pin {
1763                         hdmi_cec: hdmi-cec {
1764                                 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
1765                         };
1766
1767                         hdmi_hpd: hdmi-hpd {
1768                                 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>;
1769                         };
1770                 };
1771
1772                 cif-0 {
1773                         dvp_d2d9_m0:dvp-d2d9-m0 {
1774                                 rockchip,pins =
1775                                         /* cif_d0 */
1776                                         <3 RK_PA4 2 &pcfg_pull_none>,
1777                                         /* cif_d1 */
1778                                         <3 RK_PA5 2 &pcfg_pull_none>,
1779                                         /* cif_d2 */
1780                                         <3 RK_PA6 2 &pcfg_pull_none>,
1781                                         /* cif_d3 */
1782                                         <3 RK_PA7 2 &pcfg_pull_none>,
1783                                         /* cif_d4 */
1784                                         <3 RK_PB0 2 &pcfg_pull_none>,
1785                                         /* cif_d5m0 */
1786                                         <3 RK_PB1 2 &pcfg_pull_none>,
1787                                         /* cif_d6m0 */
1788                                         <3 RK_PB2 2 &pcfg_pull_none>,
1789                                         /* cif_d7m0 */
1790                                         <3 RK_PB3 2 &pcfg_pull_none>,
1791                                         /* cif_href */
1792                                         <3 RK_PA1 2 &pcfg_pull_none>,
1793                                         /* cif_vsync */
1794                                         <3 RK_PA0 2 &pcfg_pull_none>,
1795                                         /* cif_clkoutm0 */
1796                                         <3 RK_PA3 2 &pcfg_pull_none>,
1797                                         /* cif_clkin */
1798                                         <3 RK_PA2 2 &pcfg_pull_none>;
1799                         };
1800                 };
1801
1802                 cif-1 {
1803                         dvp_d2d9_m1:dvp-d2d9-m1 {
1804                                 rockchip,pins =
1805                                         /* cif_d0 */
1806                                         <3 RK_PA4 2 &pcfg_pull_none>,
1807                                         /* cif_d1 */
1808                                         <3 RK_PA5 2 &pcfg_pull_none>,
1809                                         /* cif_d2 */
1810                                         <3 RK_PA6 2 &pcfg_pull_none>,
1811                                         /* cif_d3 */
1812                                         <3 RK_PA7 2 &pcfg_pull_none>,
1813                                         /* cif_d4 */
1814                                         <3 RK_PB0 2 &pcfg_pull_none>,
1815                                         /* cif_d5m1 */
1816                                         <2 RK_PC0 4 &pcfg_pull_none>,
1817                                         /* cif_d6m1 */
1818                                         <2 RK_PC1 4 &pcfg_pull_none>,
1819                                         /* cif_d7m1 */
1820                                         <2 RK_PC2 4 &pcfg_pull_none>,
1821                                         /* cif_href */
1822                                         <3 RK_PA1 2 &pcfg_pull_none>,
1823                                         /* cif_vsync */
1824                                         <3 RK_PA0 2 &pcfg_pull_none>,
1825                                         /* cif_clkoutm1 */
1826                                         <2 RK_PB7 4 &pcfg_pull_none>,
1827                                         /* cif_clkin */
1828                                         <3 RK_PA2 2 &pcfg_pull_none>;
1829                         };
1830                 };
1831         };
1832 };