arch/arm64/boot/dts/qcom/sm8550.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * Copyright (c) 2022, Linaro Limited
   4  */
   5
   6 #include <dt-bindings/clock/qcom,rpmh.h>
   7 #include <dt-bindings/clock/qcom,sm8450-videocc.h>
   8 #include <dt-bindings/clock/qcom,sm8550-camcc.h>
   9 #include <dt-bindings/clock/qcom,sm8550-gcc.h>
  10 #include <dt-bindings/clock/qcom,sm8550-gpucc.h>
  11 #include <dt-bindings/clock/qcom,sm8550-tcsr.h>
  12 #include <dt-bindings/clock/qcom,sm8550-dispcc.h>
  13 #include <dt-bindings/dma/qcom-gpi.h>
  14 #include <dt-bindings/firmware/qcom,scm.h>
  15 #include <dt-bindings/gpio/gpio.h>
  16 #include <dt-bindings/interrupt-controller/arm-gic.h>
  17 #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
  18 #include <dt-bindings/mailbox/qcom-ipcc.h>
  19 #include <dt-bindings/power/qcom-rpmpd.h>
  20 #include <dt-bindings/power/qcom,rpmhpd.h>
  21 #include <dt-bindings/soc/qcom,gpr.h>
  22 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  23 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
  24 #include <dt-bindings/phy/phy-qcom-qmp.h>
  25 #include <dt-bindings/thermal/thermal.h>
  26
  27 / {
  28         interrupt-parent = <&intc>;
  29
  30         #address-cells = <2>;
  31         #size-cells = <2>;
  32
  33         chosen { };
  34
  35         clocks {
  36                 xo_board: xo-board {
  37                         compatible = "fixed-clock";
  38                         #clock-cells = <0>;
  39                 };
  40
  41                 sleep_clk: sleep-clk {
  42                         compatible = "fixed-clock";
  43                         #clock-cells = <0>;
  44                 };
  45
  46                 bi_tcxo_div2: bi-tcxo-div2-clk {
  47                         #clock-cells = <0>;
  48                         compatible = "fixed-factor-clock";
  49                         clocks = <&rpmhcc RPMH_CXO_CLK>;
  50                         clock-mult = <1>;
  51                         clock-div = <2>;
  52                 };
  53
  54                 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
  55                         #clock-cells = <0>;
  56                         compatible = "fixed-factor-clock";
  57                         clocks = <&rpmhcc RPMH_CXO_CLK_A>;
  58                         clock-mult = <1>;
  59                         clock-div = <2>;
  60                 };
  61
  62                 pcie_1_phy_aux_clk: pcie-1-phy-aux-clk {
  63                         compatible = "fixed-clock";
  64                         #clock-cells = <0>;
  65                 };
  66         };
  67
  68         cpus {
  69                 #address-cells = <2>;
  70                 #size-cells = <0>;
  71
  72                 CPU0: cpu@0 {
  73                         device_type = "cpu";
  74                         compatible = "arm,cortex-a510";
  75                         reg = <0 0>;
  76                         clocks = <&cpufreq_hw 0>;
  77                         enable-method = "psci";
  78                         next-level-cache = <&L2_0>;
  79                         power-domains = <&CPU_PD0>;
  80                         power-domain-names = "psci";
  81                         qcom,freq-domain = <&cpufreq_hw 0>;
  82                         capacity-dmips-mhz = <1024>;
  83                         dynamic-power-coefficient = <100>;
  84                         #cooling-cells = <2>;
  85                         L2_0: l2-cache {
  86                                 compatible = "cache";
  87                                 cache-level = <2>;
  88                                 cache-unified;
  89                                 next-level-cache = <&L3_0>;
  90                                 L3_0: l3-cache {
  91                                         compatible = "cache";
  92                                         cache-level = <3>;
  93                                         cache-unified;
  94                                 };
  95                         };
  96                 };
  97
  98                 CPU1: cpu@100 {
  99                         device_type = "cpu";
 100                         compatible = "arm,cortex-a510";
 101                         reg = <0 0x100>;
 102                         clocks = <&cpufreq_hw 0>;
 103                         enable-method = "psci";
 104                         next-level-cache = <&L2_100>;
 105                         power-domains = <&CPU_PD1>;
 106                         power-domain-names = "psci";
 107                         qcom,freq-domain = <&cpufreq_hw 0>;
 108                         capacity-dmips-mhz = <1024>;
 109                         dynamic-power-coefficient = <100>;
 110                         #cooling-cells = <2>;
 111                         L2_100: l2-cache {
 112                                 compatible = "cache";
 113                                 cache-level = <2>;
 114                                 cache-unified;
 115                                 next-level-cache = <&L3_0>;
 116                         };
 117                 };
 118
 119                 CPU2: cpu@200 {
 120                         device_type = "cpu";
 121                         compatible = "arm,cortex-a510";
 122                         reg = <0 0x200>;
 123                         clocks = <&cpufreq_hw 0>;
 124                         enable-method = "psci";
 125                         next-level-cache = <&L2_200>;
 126                         power-domains = <&CPU_PD2>;
 127                         power-domain-names = "psci";
 128                         qcom,freq-domain = <&cpufreq_hw 0>;
 129                         capacity-dmips-mhz = <1024>;
 130                         dynamic-power-coefficient = <100>;
 131                         #cooling-cells = <2>;
 132                         L2_200: l2-cache {
 133                                 compatible = "cache";
 134                                 cache-level = <2>;
 135                                 cache-unified;
 136                                 next-level-cache = <&L3_0>;
 137                         };
 138                 };
 139
 140                 CPU3: cpu@300 {
 141                         device_type = "cpu";
 142                         compatible = "arm,cortex-a715";
 143                         reg = <0 0x300>;
 144                         clocks = <&cpufreq_hw 1>;
 145                         enable-method = "psci";
 146                         next-level-cache = <&L2_300>;
 147                         power-domains = <&CPU_PD3>;
 148                         power-domain-names = "psci";
 149                         qcom,freq-domain = <&cpufreq_hw 1>;
 150                         capacity-dmips-mhz = <1792>;
 151                         dynamic-power-coefficient = <270>;
 152                         #cooling-cells = <2>;
 153                         L2_300: l2-cache {
 154                                 compatible = "cache";
 155                                 cache-level = <2>;
 156                                 cache-unified;
 157                                 next-level-cache = <&L3_0>;
 158                         };
 159                 };
 160
 161                 CPU4: cpu@400 {
 162                         device_type = "cpu";
 163                         compatible = "arm,cortex-a715";
 164                         reg = <0 0x400>;
 165                         clocks = <&cpufreq_hw 1>;
 166                         enable-method = "psci";
 167                         next-level-cache = <&L2_400>;
 168                         power-domains = <&CPU_PD4>;
 169                         power-domain-names = "psci";
 170                         qcom,freq-domain = <&cpufreq_hw 1>;
 171                         capacity-dmips-mhz = <1792>;
 172                         dynamic-power-coefficient = <270>;
 173                         #cooling-cells = <2>;
 174                         L2_400: l2-cache {
 175                                 compatible = "cache";
 176                                 cache-level = <2>;
 177                                 cache-unified;
 178                                 next-level-cache = <&L3_0>;
 179                         };
 180                 };
 181
 182                 CPU5: cpu@500 {
 183                         device_type = "cpu";
 184                         compatible = "arm,cortex-a710";
 185                         reg = <0 0x500>;
 186                         clocks = <&cpufreq_hw 1>;
 187                         enable-method = "psci";
 188                         next-level-cache = <&L2_500>;
 189                         power-domains = <&CPU_PD5>;
 190                         power-domain-names = "psci";
 191                         qcom,freq-domain = <&cpufreq_hw 1>;
 192                         capacity-dmips-mhz = <1792>;
 193                         dynamic-power-coefficient = <270>;
 194                         #cooling-cells = <2>;
 195                         L2_500: l2-cache {
 196                                 compatible = "cache";
 197                                 cache-level = <2>;
 198                                 cache-unified;
 199                                 next-level-cache = <&L3_0>;
 200                         };
 201                 };
 202
 203                 CPU6: cpu@600 {
 204                         device_type = "cpu";
 205                         compatible = "arm,cortex-a710";
 206                         reg = <0 0x600>;
 207                         clocks = <&cpufreq_hw 1>;
 208                         enable-method = "psci";
 209                         next-level-cache = <&L2_600>;
 210                         power-domains = <&CPU_PD6>;
 211                         power-domain-names = "psci";
 212                         qcom,freq-domain = <&cpufreq_hw 1>;
 213                         capacity-dmips-mhz = <1792>;
 214                         dynamic-power-coefficient = <270>;
 215                         #cooling-cells = <2>;
 216                         L2_600: l2-cache {
 217                                 compatible = "cache";
 218                                 cache-level = <2>;
 219                                 cache-unified;
 220                                 next-level-cache = <&L3_0>;
 221                         };
 222                 };
 223
 224                 CPU7: cpu@700 {
 225                         device_type = "cpu";
 226                         compatible = "arm,cortex-x3";
 227                         reg = <0 0x700>;
 228                         clocks = <&cpufreq_hw 2>;
 229                         enable-method = "psci";
 230                         next-level-cache = <&L2_700>;
 231                         power-domains = <&CPU_PD7>;
 232                         power-domain-names = "psci";
 233                         qcom,freq-domain = <&cpufreq_hw 2>;
 234                         capacity-dmips-mhz = <1894>;
 235                         dynamic-power-coefficient = <588>;
 236                         #cooling-cells = <2>;
 237                         L2_700: l2-cache {
 238                                 compatible = "cache";
 239                                 cache-level = <2>;
 240                                 cache-unified;
 241                                 next-level-cache = <&L3_0>;
 242                         };
 243                 };
 244
 245                 cpu-map {
 246                         cluster0 {
 247                                 core0 {
 248                                         cpu = <&CPU0>;
 249                                 };
 250
 251                                 core1 {
 252                                         cpu = <&CPU1>;
 253                                 };
 254
 255                                 core2 {
 256                                         cpu = <&CPU2>;
 257                                 };
 258
 259                                 core3 {
 260                                         cpu = <&CPU3>;
 261                                 };
 262
 263                                 core4 {
 264                                         cpu = <&CPU4>;
 265                                 };
 266
 267                                 core5 {
 268                                         cpu = <&CPU5>;
 269                                 };
 270
 271                                 core6 {
 272                                         cpu = <&CPU6>;
 273                                 };
 274
 275                                 core7 {
 276                                         cpu = <&CPU7>;
 277                                 };
 278                         };
 279                 };
 280
 281                 idle-states {
 282                         entry-method = "psci";
 283
 284                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 285                                 compatible = "arm,idle-state";
 286                                 idle-state-name = "silver-rail-power-collapse";
 287                                 arm,psci-suspend-param = <0x40000004>;
 288                                 entry-latency-us = <550>;
 289                                 exit-latency-us = <750>;
 290                                 min-residency-us = <6700>;
 291                                 local-timer-stop;
 292                         };
 293
 294                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 295                                 compatible = "arm,idle-state";
 296                                 idle-state-name = "gold-rail-power-collapse";
 297                                 arm,psci-suspend-param = <0x40000004>;
 298                                 entry-latency-us = <600>;
 299                                 exit-latency-us = <1300>;
 300                                 min-residency-us = <8136>;
 301                                 local-timer-stop;
 302                         };
 303
 304                         PRIME_CPU_SLEEP_0: cpu-sleep-2-0 {
 305                                 compatible = "arm,idle-state";
 306                                 idle-state-name = "goldplus-rail-power-collapse";
 307                                 arm,psci-suspend-param = <0x40000004>;
 308                                 entry-latency-us = <500>;
 309                                 exit-latency-us = <1350>;
 310                                 min-residency-us = <7480>;
 311                                 local-timer-stop;
 312                         };
 313                 };
 314
 315                 domain-idle-states {
 316                         CLUSTER_SLEEP_0: cluster-sleep-0 {
 317                                 compatible = "domain-idle-state";
 318                                 arm,psci-suspend-param = <0x41000044>;
 319                                 entry-latency-us = <750>;
 320                                 exit-latency-us = <2350>;
 321                                 min-residency-us = <9144>;
 322                         };
 323
 324                         CLUSTER_SLEEP_1: cluster-sleep-1 {
 325                                 compatible = "domain-idle-state";
 326                                 arm,psci-suspend-param = <0x4100c344>;
 327                                 entry-latency-us = <2800>;
 328                                 exit-latency-us = <4400>;
 329                                 min-residency-us = <10150>;
 330                         };
 331                 };
 332         };
 333
 334         firmware {
 335                 scm: scm {
 336                         compatible = "qcom,scm-sm8550", "qcom,scm";
 337                         qcom,dload-mode = <&tcsr 0x19000>;
 338                         interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
 339                 };
 340         };
 341
 342         clk_virt: interconnect-0 {
 343                 compatible = "qcom,sm8550-clk-virt";
 344                 #interconnect-cells = <2>;
 345                 qcom,bcm-voters = <&apps_bcm_voter>;
 346         };
 347
 348         mc_virt: interconnect-1 {
 349                 compatible = "qcom,sm8550-mc-virt";
 350                 #interconnect-cells = <2>;
 351                 qcom,bcm-voters = <&apps_bcm_voter>;
 352         };
 353
 354         memory@a0000000 {
 355                 device_type = "memory";
 356                 /* We expect the bootloader to fill in the size */
 357                 reg = <0 0xa0000000 0 0>;
 358         };
 359
 360         pmu {
 361                 compatible = "arm,armv8-pmuv3";
 362                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 363         };
 364
 365         psci {
 366                 compatible = "arm,psci-1.0";
 367                 method = "smc";
 368
 369                 CPU_PD0: power-domain-cpu0 {
 370                         #power-domain-cells = <0>;
 371                         power-domains = <&CLUSTER_PD>;
 372                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 373                 };
 374
 375                 CPU_PD1: power-domain-cpu1 {
 376                         #power-domain-cells = <0>;
 377                         power-domains = <&CLUSTER_PD>;
 378                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 379                 };
 380
 381                 CPU_PD2: power-domain-cpu2 {
 382                         #power-domain-cells = <0>;
 383                         power-domains = <&CLUSTER_PD>;
 384                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 385                 };
 386
 387                 CPU_PD3: power-domain-cpu3 {
 388                         #power-domain-cells = <0>;
 389                         power-domains = <&CLUSTER_PD>;
 390                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 391                 };
 392
 393                 CPU_PD4: power-domain-cpu4 {
 394                         #power-domain-cells = <0>;
 395                         power-domains = <&CLUSTER_PD>;
 396                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 397                 };
 398
 399                 CPU_PD5: power-domain-cpu5 {
 400                         #power-domain-cells = <0>;
 401                         power-domains = <&CLUSTER_PD>;
 402                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 403                 };
 404
 405                 CPU_PD6: power-domain-cpu6 {
 406                         #power-domain-cells = <0>;
 407                         power-domains = <&CLUSTER_PD>;
 408                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 409                 };
 410
 411                 CPU_PD7: power-domain-cpu7 {
 412                         #power-domain-cells = <0>;
 413                         power-domains = <&CLUSTER_PD>;
 414                         domain-idle-states = <&PRIME_CPU_SLEEP_0>;
 415                 };
 416
 417                 CLUSTER_PD: power-domain-cluster {
 418                         #power-domain-cells = <0>;
 419                         domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>;
 420                 };
 421         };
 422
 423         reserved_memory: reserved-memory {
 424                 #address-cells = <2>;
 425                 #size-cells = <2>;
 426                 ranges;
 427
 428                 hyp_mem: hyp-region@80000000 {
 429                         reg = <0 0x80000000 0 0xa00000>;
 430                         no-map;
 431                 };
 432
 433                 cpusys_vm_mem: cpusys-vm-region@80a00000 {
 434                         reg = <0 0x80a00000 0 0x400000>;
 435                         no-map;
 436                 };
 437
 438                 hyp_tags_mem: hyp-tags-region@80e00000 {
 439                         reg = <0 0x80e00000 0 0x3d0000>;
 440                         no-map;
 441                 };
 442
 443                 xbl_sc_mem: xbl-sc-region@d8100000 {
 444                         reg = <0 0xd8100000 0 0x40000>;
 445                         no-map;
 446                 };
 447
 448                 hyp_tags_reserved_mem: hyp-tags-reserved-region@811d0000 {
 449                         reg = <0 0x811d0000 0 0x30000>;
 450                         no-map;
 451                 };
 452
 453                 /* merged xbl_dt_log, xbl_ramdump, aop_image */
 454                 xbl_dt_log_merged_mem: xbl-dt-log-merged-region@81a00000 {
 455                         reg = <0 0x81a00000 0 0x260000>;
 456                         no-map;
 457                 };
 458
 459                 aop_cmd_db_mem: aop-cmd-db-region@81c60000 {
 460                         compatible = "qcom,cmd-db";
 461                         reg = <0 0x81c60000 0 0x20000>;
 462                         no-map;
 463                 };
 464
 465                 /* merged aop_config, tme_crash_dump, tme_log, uefi_log */
 466                 aop_config_merged_mem: aop-config-merged-region@81c80000 {
 467                         reg = <0 0x81c80000 0 0x74000>;
 468                         no-map;
 469                 };
 470
 471                 /* secdata region can be reused by apps */
 472                 smem: smem@81d00000 {
 473                         compatible = "qcom,smem";
 474                         reg = <0 0x81d00000 0 0x200000>;
 475                         hwlocks = <&tcsr_mutex 3>;
 476                         no-map;
 477                 };
 478
 479                 adsp_mhi_mem: adsp-mhi-region@81f00000 {
 480                         reg = <0 0x81f00000 0 0x20000>;
 481                         no-map;
 482                 };
 483
 484                 global_sync_mem: global-sync-region@82600000 {
 485                         reg = <0 0x82600000 0 0x100000>;
 486                         no-map;
 487                 };
 488
 489                 tz_stat_mem: tz-stat-region@82700000 {
 490                         reg = <0 0x82700000 0 0x100000>;
 491                         no-map;
 492                 };
 493
 494                 cdsp_secure_heap_mem: cdsp-secure-heap-region@82800000 {
 495                         reg = <0 0x82800000 0 0x4600000>;
 496                         no-map;
 497                 };
 498
 499                 mpss_mem: mpss-region@8a800000 {
 500                         reg = <0 0x8a800000 0 0x10800000>;
 501                         no-map;
 502                 };
 503
 504                 q6_mpss_dtb_mem: q6-mpss-dtb-region@9b000000 {
 505                         reg = <0 0x9b000000 0 0x80000>;
 506                         no-map;
 507                 };
 508
 509                 ipa_fw_mem: ipa-fw-region@9b080000 {
 510                         reg = <0 0x9b080000 0 0x10000>;
 511                         no-map;
 512                 };
 513
 514                 ipa_gsi_mem: ipa-gsi-region@9b090000 {
 515                         reg = <0 0x9b090000 0 0xa000>;
 516                         no-map;
 517                 };
 518
 519                 gpu_micro_code_mem: gpu-micro-code-region@9b09a000 {
 520                         reg = <0 0x9b09a000 0 0x2000>;
 521                         no-map;
 522                 };
 523
 524                 spss_region_mem: spss-region@9b100000 {
 525                         reg = <0 0x9b100000 0 0x180000>;
 526                         no-map;
 527                 };
 528
 529                 /* First part of the "SPU secure shared memory" region */
 530                 spu_tz_shared_mem: spu-tz-shared-region@9b280000 {
 531                         reg = <0 0x9b280000 0 0x60000>;
 532                         no-map;
 533                 };
 534
 535                 /* Second part of the "SPU secure shared memory" region */
 536                 spu_modem_shared_mem: spu-modem-shared-region@9b2e0000 {
 537                         reg = <0 0x9b2e0000 0 0x20000>;
 538                         no-map;
 539                 };
 540
 541                 camera_mem: camera-region@9b300000 {
 542                         reg = <0 0x9b300000 0 0x800000>;
 543                         no-map;
 544                 };
 545
 546                 video_mem: video-region@9bb00000 {
 547                         reg = <0 0x9bb00000 0 0x700000>;
 548                         no-map;
 549                 };
 550
 551                 cvp_mem: cvp-region@9c200000 {
 552                         reg = <0 0x9c200000 0 0x700000>;
 553                         no-map;
 554                 };
 555
 556                 cdsp_mem: cdsp-region@9c900000 {
 557                         reg = <0 0x9c900000 0 0x2000000>;
 558                         no-map;
 559                 };
 560
 561                 q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9e900000 {
 562                         reg = <0 0x9e900000 0 0x80000>;
 563                         no-map;
 564                 };
 565
 566                 q6_adsp_dtb_mem: q6-adsp-dtb-region@9e980000 {
 567                         reg = <0 0x9e980000 0 0x80000>;
 568                         no-map;
 569                 };
 570
 571                 adspslpi_mem: adspslpi-region@9ea00000 {
 572                         reg = <0 0x9ea00000 0 0x4080000>;
 573                         no-map;
 574                 };
 575
 576                 /* uefi region can be reused by apps */
 577
 578                 /* Linux kernel image is loaded at 0xa8000000 */
 579
 580                 rmtfs_mem: rmtfs-region@d4a80000 {
 581                         compatible = "qcom,rmtfs-mem";
 582                         reg = <0x0 0xd4a80000 0x0 0x280000>;
 583                         no-map;
 584
 585                         qcom,client-id = <1>;
 586                         qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
 587                 };
 588
 589                 mpss_dsm_mem: mpss-dsm-region@d4d00000 {
 590                         reg = <0 0xd4d00000 0 0x3300000>;
 591                         no-map;
 592                 };
 593
 594                 tz_reserved_mem: tz-reserved-region@d8000000 {
 595                         reg = <0 0xd8000000 0 0x100000>;
 596                         no-map;
 597                 };
 598
 599                 cpucp_fw_mem: cpucp-fw-region@d8140000 {
 600                         reg = <0 0xd8140000 0 0x1c0000>;
 601                         no-map;
 602                 };
 603
 604                 qtee_mem: qtee-region@d8300000 {
 605                         reg = <0 0xd8300000 0 0x500000>;
 606                         no-map;
 607                 };
 608
 609                 ta_mem: ta-region@d8800000 {
 610                         reg = <0 0xd8800000 0 0x8a00000>;
 611                         no-map;
 612                 };
 613
 614                 tz_tags_mem: tz-tags-region@e1200000 {
 615                         reg = <0 0xe1200000 0 0x2740000>;
 616                         no-map;
 617                 };
 618
 619                 hwfence_shbuf: hwfence-shbuf-region@e6440000 {
 620                         reg = <0 0xe6440000 0 0x279000>;
 621                         no-map;
 622                 };
 623
 624                 trust_ui_vm_mem: trust-ui-vm-region@f3600000 {
 625                         reg = <0 0xf3600000 0 0x4aee000>;
 626                         no-map;
 627                 };
 628
 629                 trust_ui_vm_dump: trust-ui-vm-dump-region@f80ee000 {
 630                         reg = <0 0xf80ee000 0 0x1000>;
 631                         no-map;
 632                 };
 633
 634                 trust_ui_vm_qrtr: trust-ui-vm-qrt-region@f80ef000 {
 635                         reg = <0 0xf80ef000 0 0x9000>;
 636                         no-map;
 637                 };
 638
 639                 trust_ui_vm_vblk0_ring: trust-ui-vm-vblk0-ring-region@f80f8000 {
 640                         reg = <0 0xf80f8000 0 0x4000>;
 641                         no-map;
 642                 };
 643
 644                 trust_ui_vm_vblk1_ring: trust-ui-vm-vblk1-ring-region@f80fc000 {
 645                         reg = <0 0xf80fc000 0 0x4000>;
 646                         no-map;
 647                 };
 648
 649                 trust_ui_vm_swiotlb: trust-ui-vm-swiotlb-region@f8100000 {
 650                         reg = <0 0xf8100000 0 0x100000>;
 651                         no-map;
 652                 };
 653
 654                 oem_vm_mem: oem-vm-region@f8400000 {
 655                         reg = <0 0xf8400000 0 0x4800000>;
 656                         no-map;
 657                 };
 658
 659                 oem_vm_vblk0_ring: oem-vm-vblk0-ring-region@fcc00000 {
 660                         reg = <0 0xfcc00000 0 0x4000>;
 661                         no-map;
 662                 };
 663
 664                 oem_vm_swiotlb: oem-vm-swiotlb-region@fcc04000 {
 665                         reg = <0 0xfcc04000 0 0x100000>;
 666                         no-map;
 667                 };
 668
 669                 hyp_ext_tags_mem: hyp-ext-tags-region@fce00000 {
 670                         reg = <0 0xfce00000 0 0x2900000>;
 671                         no-map;
 672                 };
 673
 674                 hyp_ext_reserved_mem: hyp-ext-reserved-region@ff700000 {
 675                         reg = <0 0xff700000 0 0x100000>;
 676                         no-map;
 677                 };
 678         };
 679
 680         smp2p-adsp {
 681                 compatible = "qcom,smp2p";
 682                 qcom,smem = <443>, <429>;
 683                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
 684                                              IPCC_MPROC_SIGNAL_SMP2P
 685                                              IRQ_TYPE_EDGE_RISING>;
 686                 mboxes = <&ipcc IPCC_CLIENT_LPASS
 687                                 IPCC_MPROC_SIGNAL_SMP2P>;
 688
 689                 qcom,local-pid = <0>;
 690                 qcom,remote-pid = <2>;
 691
 692                 smp2p_adsp_out: master-kernel {
 693                         qcom,entry-name = "master-kernel";
 694                         #qcom,smem-state-cells = <1>;
 695                 };
 696
 697                 smp2p_adsp_in: slave-kernel {
 698                         qcom,entry-name = "slave-kernel";
 699                         interrupt-controller;
 700                         #interrupt-cells = <2>;
 701                 };
 702         };
 703
 704         smp2p-cdsp {
 705                 compatible = "qcom,smp2p";
 706                 qcom,smem = <94>, <432>;
 707                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
 708                                              IPCC_MPROC_SIGNAL_SMP2P
 709                                              IRQ_TYPE_EDGE_RISING>;
 710                 mboxes = <&ipcc IPCC_CLIENT_CDSP
 711                                 IPCC_MPROC_SIGNAL_SMP2P>;
 712
 713                 qcom,local-pid = <0>;
 714                 qcom,remote-pid = <5>;
 715
 716                 smp2p_cdsp_out: master-kernel {
 717                         qcom,entry-name = "master-kernel";
 718                         #qcom,smem-state-cells = <1>;
 719                 };
 720
 721                 smp2p_cdsp_in: slave-kernel {
 722                         qcom,entry-name = "slave-kernel";
 723                         interrupt-controller;
 724                         #interrupt-cells = <2>;
 725                 };
 726         };
 727
 728         smp2p-modem {
 729                 compatible = "qcom,smp2p";
 730                 qcom,smem = <435>, <428>;
 731                 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
 732                                              IPCC_MPROC_SIGNAL_SMP2P
 733                                              IRQ_TYPE_EDGE_RISING>;
 734                 mboxes = <&ipcc IPCC_CLIENT_MPSS
 735                                 IPCC_MPROC_SIGNAL_SMP2P>;
 736
 737                 qcom,local-pid = <0>;
 738                 qcom,remote-pid = <1>;
 739
 740                 smp2p_modem_out: master-kernel {
 741                         qcom,entry-name = "master-kernel";
 742                         #qcom,smem-state-cells = <1>;
 743                 };
 744
 745                 smp2p_modem_in: slave-kernel {
 746                         qcom,entry-name = "slave-kernel";
 747                         interrupt-controller;
 748                         #interrupt-cells = <2>;
 749                 };
 750
 751                 ipa_smp2p_out: ipa-ap-to-modem {
 752                         qcom,entry-name = "ipa";
 753                         #qcom,smem-state-cells = <1>;
 754                 };
 755
 756                 ipa_smp2p_in: ipa-modem-to-ap {
 757                         qcom,entry-name = "ipa";
 758                         interrupt-controller;
 759                         #interrupt-cells = <2>;
 760                 };
 761         };
 762
 763         soc: soc@0 {
 764                 compatible = "simple-bus";
 765                 ranges = <0 0 0 0 0x10 0>;
 766                 dma-ranges = <0 0 0 0 0x10 0>;
 767
 768                 #address-cells = <2>;
 769                 #size-cells = <2>;
 770
 771                 gcc: clock-controller@100000 {
 772                         compatible = "qcom,sm8550-gcc";
 773                         reg = <0 0x00100000 0 0x1f4200>;
 774                         #clock-cells = <1>;
 775                         #reset-cells = <1>;
 776                         #power-domain-cells = <1>;
 777                         clocks = <&bi_tcxo_div2>, <&sleep_clk>,
 778                                  <&pcie0_phy>,
 779                                  <&pcie1_phy>,
 780                                  <&pcie_1_phy_aux_clk>,
 781                                  <&ufs_mem_phy 0>,
 782                                  <&ufs_mem_phy 1>,
 783                                  <&ufs_mem_phy 2>,
 784                                  <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
 785                 };
 786
 787                 ipcc: mailbox@408000 {
 788                         compatible = "qcom,sm8550-ipcc", "qcom,ipcc";
 789                         reg = <0 0x00408000 0 0x1000>;
 790                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
 791                         interrupt-controller;
 792                         #interrupt-cells = <3>;
 793                         #mbox-cells = <2>;
 794                 };
 795
 796                 gpi_dma2: dma-controller@800000 {
 797                         compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma";
 798                         #dma-cells = <3>;
 799                         reg = <0 0x00800000 0 0x60000>;
 800                         interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
 801                                      <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
 802                                      <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
 803                                      <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
 804                                      <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
 805                                      <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
 806                                      <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
 807                                      <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
 808                                      <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
 809                                      <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
 810                                      <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
 811                                      <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
 812                         dma-channels = <12>;
 813                         dma-channel-mask = <0x3e>;
 814                         iommus = <&apps_smmu 0x436 0>;
 815                         status = "disabled";
 816                 };
 817
 818                 qupv3_id_1: geniqup@8c0000 {
 819                         compatible = "qcom,geni-se-qup";
 820                         reg = <0 0x008c0000 0 0x2000>;
 821                         ranges;
 822                         clock-names = "m-ahb", "s-ahb";
 823                         clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
 824                                  <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
 825                         iommus = <&apps_smmu 0x423 0>;
 826                         #address-cells = <2>;
 827                         #size-cells = <2>;
 828                         status = "disabled";
 829
 830                         i2c8: i2c@880000 {
 831                                 compatible = "qcom,geni-i2c";
 832                                 reg = <0 0x00880000 0 0x4000>;
 833                                 clock-names = "se";
 834                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
 835                                 pinctrl-names = "default";
 836                                 pinctrl-0 = <&qup_i2c8_data_clk>;
 837                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
 838                                 #address-cells = <1>;
 839                                 #size-cells = <0>;
 840                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 841                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
 842                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
 843                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 844                                 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
 845                                        <&gpi_dma2 1 0 QCOM_GPI_I2C>;
 846                                 dma-names = "tx", "rx";
 847                                 status = "disabled";
 848                         };
 849
 850                         spi8: spi@880000 {
 851                                 compatible = "qcom,geni-spi";
 852                                 reg = <0 0x00880000 0 0x4000>;
 853                                 clock-names = "se";
 854                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
 855                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
 856                                 pinctrl-names = "default";
 857                                 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
 858                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 859                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
 860                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
 861                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 862                                 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
 863                                        <&gpi_dma2 1 0 QCOM_GPI_SPI>;
 864                                 dma-names = "tx", "rx";
 865                                 #address-cells = <1>;
 866                                 #size-cells = <0>;
 867                                 status = "disabled";
 868                         };
 869
 870                         i2c9: i2c@884000 {
 871                                 compatible = "qcom,geni-i2c";
 872                                 reg = <0 0x00884000 0 0x4000>;
 873                                 clock-names = "se";
 874                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
 875                                 pinctrl-names = "default";
 876                                 pinctrl-0 = <&qup_i2c9_data_clk>;
 877                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
 878                                 #address-cells = <1>;
 879                                 #size-cells = <0>;
 880                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 881                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
 882                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
 883                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 884                                 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
 885                                        <&gpi_dma2 1 1 QCOM_GPI_I2C>;
 886                                 dma-names = "tx", "rx";
 887                                 status = "disabled";
 888                         };
 889
 890                         spi9: spi@884000 {
 891                                 compatible = "qcom,geni-spi";
 892                                 reg = <0 0x00884000 0 0x4000>;
 893                                 clock-names = "se";
 894                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
 895                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
 896                                 pinctrl-names = "default";
 897                                 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
 898                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 899                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
 900                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
 901                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 902                                 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
 903                                        <&gpi_dma2 1 1 QCOM_GPI_SPI>;
 904                                 dma-names = "tx", "rx";
 905                                 #address-cells = <1>;
 906                                 #size-cells = <0>;
 907                                 status = "disabled";
 908                         };
 909
 910                         i2c10: i2c@888000 {
 911                                 compatible = "qcom,geni-i2c";
 912                                 reg = <0 0x00888000 0 0x4000>;
 913                                 clock-names = "se";
 914                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
 915                                 pinctrl-names = "default";
 916                                 pinctrl-0 = <&qup_i2c10_data_clk>;
 917                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
 918                                 #address-cells = <1>;
 919                                 #size-cells = <0>;
 920                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 921                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
 922                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
 923                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 924                                 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
 925                                        <&gpi_dma2 1 2 QCOM_GPI_I2C>;
 926                                 dma-names = "tx", "rx";
 927                                 status = "disabled";
 928                         };
 929
 930                         spi10: spi@888000 {
 931                                 compatible = "qcom,geni-spi";
 932                                 reg = <0 0x00888000 0 0x4000>;
 933                                 clock-names = "se";
 934                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
 935                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
 936                                 pinctrl-names = "default";
 937                                 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
 938                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 939                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
 940                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
 941                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 942                                 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
 943                                        <&gpi_dma2 1 2 QCOM_GPI_SPI>;
 944                                 dma-names = "tx", "rx";
 945                                 #address-cells = <1>;
 946                                 #size-cells = <0>;
 947                                 status = "disabled";
 948                         };
 949
 950                         i2c11: i2c@88c000 {
 951                                 compatible = "qcom,geni-i2c";
 952                                 reg = <0 0x0088c000 0 0x4000>;
 953                                 clock-names = "se";
 954                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
 955                                 pinctrl-names = "default";
 956                                 pinctrl-0 = <&qup_i2c11_data_clk>;
 957                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
 958                                 #address-cells = <1>;
 959                                 #size-cells = <0>;
 960                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 961                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
 962                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
 963                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 964                                 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
 965                                        <&gpi_dma2 1 3 QCOM_GPI_I2C>;
 966                                 dma-names = "tx", "rx";
 967                                 status = "disabled";
 968                         };
 969
 970                         spi11: spi@88c000 {
 971                                 compatible = "qcom,geni-spi";
 972                                 reg = <0 0x0088c000 0 0x4000>;
 973                                 clock-names = "se";
 974                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
 975                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
 976                                 pinctrl-names = "default";
 977                                 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
 978                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 979                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
 980                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
 981                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 982                                 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
 983                                        <&gpi_dma2 1 3 QCOM_GPI_I2C>;
 984                                 dma-names = "tx", "rx";
 985                                 #address-cells = <1>;
 986                                 #size-cells = <0>;
 987                                 status = "disabled";
 988                         };
 989
 990                         i2c12: i2c@890000 {
 991                                 compatible = "qcom,geni-i2c";
 992                                 reg = <0 0x00890000 0 0x4000>;
 993                                 clock-names = "se";
 994                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
 995                                 pinctrl-names = "default";
 996                                 pinctrl-0 = <&qup_i2c12_data_clk>;
 997                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
 998                                 #address-cells = <1>;
 999                                 #size-cells = <0>;
1000                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1001                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1002                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
1003                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1004                                 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1005                                        <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1006                                 dma-names = "tx", "rx";
1007                                 status = "disabled";
1008                         };
1009
1010                         spi12: spi@890000 {
1011                                 compatible = "qcom,geni-spi";
1012                                 reg = <0 0x00890000 0 0x4000>;
1013                                 clock-names = "se";
1014                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1015                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1016                                 pinctrl-names = "default";
1017                                 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1018                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1019                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1020                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
1021                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1022                                 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1023                                        <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1024                                 dma-names = "tx", "rx";
1025                                 #address-cells = <1>;
1026                                 #size-cells = <0>;
1027                                 status = "disabled";
1028                         };
1029
1030                         i2c13: i2c@894000 {
1031                                 compatible = "qcom,geni-i2c";
1032                                 reg = <0 0x00894000 0 0x4000>;
1033                                 clock-names = "se";
1034                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1035                                 pinctrl-names = "default";
1036                                 pinctrl-0 = <&qup_i2c13_data_clk>;
1037                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1038                                 #address-cells = <1>;
1039                                 #size-cells = <0>;
1040                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1041                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1042                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
1043                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1044                                 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1045                                        <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1046                                 dma-names = "tx", "rx";
1047                                 status = "disabled";
1048                         };
1049
1050                         spi13: spi@894000 {
1051                                 compatible = "qcom,geni-spi";
1052                                 reg = <0 0x00894000 0 0x4000>;
1053                                 clock-names = "se";
1054                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1055                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1056                                 pinctrl-names = "default";
1057                                 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1058                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1059                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1060                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
1061                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1062                                 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1063                                        <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1064                                 dma-names = "tx", "rx";
1065                                 #address-cells = <1>;
1066                                 #size-cells = <0>;
1067                                 status = "disabled";
1068                         };
1069
1070                         uart14: serial@898000 {
1071                                 compatible = "qcom,geni-uart";
1072                                 reg = <0 0x898000 0 0x4000>;
1073                                 clock-names = "se";
1074                                 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1075                                 pinctrl-names = "default";
1076                                 pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>;
1077                                 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
1078                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1079                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>;
1080                                 interconnect-names = "qup-core", "qup-config";
1081                                 status = "disabled";
1082                         };
1083
1084                         i2c15: i2c@89c000 {
1085                                 compatible = "qcom,geni-i2c";
1086                                 reg = <0 0x0089c000 0 0x4000>;
1087                                 clock-names = "se";
1088                                 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1089                                 pinctrl-names = "default";
1090                                 pinctrl-0 = <&qup_i2c15_data_clk>;
1091                                 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
1092                                 #address-cells = <1>;
1093                                 #size-cells = <0>;
1094                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1095                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1096                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
1097                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1098                                 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>,
1099                                        <&gpi_dma2 1 7 QCOM_GPI_I2C>;
1100                                 dma-names = "tx", "rx";
1101                                 status = "disabled";
1102                         };
1103
1104                         spi15: spi@89c000 {
1105                                 compatible = "qcom,geni-spi";
1106                                 reg = <0 0x0089c000 0 0x4000>;
1107                                 clock-names = "se";
1108                                 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1109                                 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
1110                                 pinctrl-names = "default";
1111                                 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
1112                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1113                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1114                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt  SLAVE_EBI1 0>;
1115                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1116                                 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>,
1117                                        <&gpi_dma2 1 7 QCOM_GPI_SPI>;
1118                                 dma-names = "tx", "rx";
1119                                 #address-cells = <1>;
1120                                 #size-cells = <0>;
1121                                 status = "disabled";
1122                         };
1123                 };
1124
1125                 i2c_master_hub_0: geniqup@9c0000 {
1126                         compatible = "qcom,geni-se-i2c-master-hub";
1127                         reg = <0x0 0x009c0000 0x0 0x2000>;
1128                         clock-names = "s-ahb";
1129                         clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>;
1130                         #address-cells = <2>;
1131                         #size-cells = <2>;
1132                         ranges;
1133                         status = "disabled";
1134
1135                         i2c_hub_0: i2c@980000 {
1136                                 compatible = "qcom,geni-i2c-master-hub";
1137                                 reg = <0x0 0x00980000 0x0 0x4000>;
1138                                 clock-names = "se", "core";
1139                                 clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>,
1140                                          <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1141                                 pinctrl-names = "default";
1142                                 pinctrl-0 = <&hub_i2c0_data_clk>;
1143                                 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>;
1144                                 #address-cells = <1>;
1145                                 #size-cells = <0>;
1146                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1147                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1148                                 interconnect-names = "qup-core", "qup-config";
1149                                 status = "disabled";
1150                         };
1151
1152                         i2c_hub_1: i2c@984000 {
1153                                 compatible = "qcom,geni-i2c-master-hub";
1154                                 reg = <0x0 0x00984000 0x0 0x4000>;
1155                                 clock-names = "se", "core";
1156                                 clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>,
1157                                          <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1158                                 pinctrl-names = "default";
1159                                 pinctrl-0 = <&hub_i2c1_data_clk>;
1160                                 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
1161                                 #address-cells = <1>;
1162                                 #size-cells = <0>;
1163                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1164                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1165                                 interconnect-names = "qup-core", "qup-config";
1166                                 status = "disabled";
1167                         };
1168
1169                         i2c_hub_2: i2c@988000 {
1170                                 compatible = "qcom,geni-i2c-master-hub";
1171                                 reg = <0x0 0x00988000 0x0 0x4000>;
1172                                 clock-names = "se", "core";
1173                                 clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>,
1174                                          <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1175                                 pinctrl-names = "default";
1176                                 pinctrl-0 = <&hub_i2c2_data_clk>;
1177                                 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
1178                                 #address-cells = <1>;
1179                                 #size-cells = <0>;
1180                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1181                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1182                                 interconnect-names = "qup-core", "qup-config";
1183                                 status = "disabled";
1184                         };
1185
1186                         i2c_hub_3: i2c@98c000 {
1187                                 compatible = "qcom,geni-i2c-master-hub";
1188                                 reg = <0x0 0x0098c000 0x0 0x4000>;
1189                                 clock-names = "se", "core";
1190                                 clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>,
1191                                          <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1192                                 pinctrl-names = "default";
1193                                 pinctrl-0 = <&hub_i2c3_data_clk>;
1194                                 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
1195                                 #address-cells = <1>;
1196                                 #size-cells = <0>;
1197                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1198                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1199                                 interconnect-names = "qup-core", "qup-config";
1200                                 status = "disabled";
1201                         };
1202
1203                         i2c_hub_4: i2c@990000 {
1204                                 compatible = "qcom,geni-i2c-master-hub";
1205                                 reg = <0x0 0x00990000 0x0 0x4000>;
1206                                 clock-names = "se", "core";
1207                                 clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>,
1208                                          <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1209                                 pinctrl-names = "default";
1210                                 pinctrl-0 = <&hub_i2c4_data_clk>;
1211                                 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
1212                                 #address-cells = <1>;
1213                                 #size-cells = <0>;
1214                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1215                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1216                                 interconnect-names = "qup-core", "qup-config";
1217                                 status = "disabled";
1218                         };
1219
1220                         i2c_hub_5: i2c@994000 {
1221                                 compatible = "qcom,geni-i2c-master-hub";
1222                                 reg = <0 0x00994000 0 0x4000>;
1223                                 clock-names = "se", "core";
1224                                 clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>,
1225                                          <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1226                                 pinctrl-names = "default";
1227                                 pinctrl-0 = <&hub_i2c5_data_clk>;
1228                                 interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
1229                                 #address-cells = <1>;
1230                                 #size-cells = <0>;
1231                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1232                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1233                                 interconnect-names = "qup-core", "qup-config";
1234                                 status = "disabled";
1235                         };
1236
1237                         i2c_hub_6: i2c@998000 {
1238                                 compatible = "qcom,geni-i2c-master-hub";
1239                                 reg = <0 0x00998000 0 0x4000>;
1240                                 clock-names = "se", "core";
1241                                 clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>,
1242                                          <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1243                                 pinctrl-names = "default";
1244                                 pinctrl-0 = <&hub_i2c6_data_clk>;
1245                                 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>;
1246                                 #address-cells = <1>;
1247                                 #size-cells = <0>;
1248                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1249                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1250                                 interconnect-names = "qup-core", "qup-config";
1251                                 status = "disabled";
1252                         };
1253
1254                         i2c_hub_7: i2c@99c000 {
1255                                 compatible = "qcom,geni-i2c-master-hub";
1256                                 reg = <0 0x0099c000 0 0x4000>;
1257                                 clock-names = "se", "core";
1258                                 clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>,
1259                                          <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1260                                 pinctrl-names = "default";
1261                                 pinctrl-0 = <&hub_i2c7_data_clk>;
1262                                 interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>;
1263                                 #address-cells = <1>;
1264                                 #size-cells = <0>;
1265                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1266                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1267                                 interconnect-names = "qup-core", "qup-config";
1268                                 status = "disabled";
1269                         };
1270
1271                         i2c_hub_8: i2c@9a0000 {
1272                                 compatible = "qcom,geni-i2c-master-hub";
1273                                 reg = <0 0x009a0000 0 0x4000>;
1274                                 clock-names = "se", "core";
1275                                 clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>,
1276                                          <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1277                                 pinctrl-names = "default";
1278                                 pinctrl-0 = <&hub_i2c8_data_clk>;
1279                                 interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>;
1280                                 #address-cells = <1>;
1281                                 #size-cells = <0>;
1282                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1283                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1284                                 interconnect-names = "qup-core", "qup-config";
1285                                 status = "disabled";
1286                         };
1287
1288                         i2c_hub_9: i2c@9a4000 {
1289                                 compatible = "qcom,geni-i2c-master-hub";
1290                                 reg = <0 0x009a4000 0 0x4000>;
1291                                 clock-names = "se", "core";
1292                                 clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>,
1293                                          <&gcc GCC_QUPV3_I2C_CORE_CLK>;
1294                                 pinctrl-names = "default";
1295                                 pinctrl-0 = <&hub_i2c9_data_clk>;
1296                                 interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
1297                                 #address-cells = <1>;
1298                                 #size-cells = <0>;
1299                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1300                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>;
1301                                 interconnect-names = "qup-core", "qup-config";
1302                                 status = "disabled";
1303                         };
1304                 };
1305
1306                 gpi_dma1: dma-controller@a00000 {
1307                         compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma";
1308                         #dma-cells = <3>;
1309                         reg = <0 0x00a00000 0 0x60000>;
1310                         interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1311                                      <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1312                                      <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1313                                      <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1314                                      <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1315                                      <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1316                                      <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1317                                      <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1318                                      <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1319                                      <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1320                                      <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1321                                      <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
1322                         dma-channels = <12>;
1323                         dma-channel-mask = <0x1e>;
1324                         iommus = <&apps_smmu 0xb6 0>;
1325                         status = "disabled";
1326                 };
1327
1328                 qupv3_id_0: geniqup@ac0000 {
1329                         compatible = "qcom,geni-se-qup";
1330                         reg = <0 0x00ac0000 0 0x2000>;
1331                         ranges;
1332                         clock-names = "m-ahb", "s-ahb";
1333                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1334                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1335                         iommus = <&apps_smmu 0xa3 0>;
1336                         interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>;
1337                         interconnect-names = "qup-core";
1338                         #address-cells = <2>;
1339                         #size-cells = <2>;
1340                         status = "disabled";
1341
1342                         i2c0: i2c@a80000 {
1343                                 compatible = "qcom,geni-i2c";
1344                                 reg = <0 0x00a80000 0 0x4000>;
1345                                 clock-names = "se";
1346                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1347                                 pinctrl-names = "default";
1348                                 pinctrl-0 = <&qup_i2c0_data_clk>;
1349                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1350                                 #address-cells = <1>;
1351                                 #size-cells = <0>;
1352                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1353                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1354                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1355                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1356                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1357                                        <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1358                                 dma-names = "tx", "rx";
1359                                 status = "disabled";
1360                         };
1361
1362                         spi0: spi@a80000 {
1363                                 compatible = "qcom,geni-spi";
1364                                 reg = <0 0x00a80000 0 0x4000>;
1365                                 clock-names = "se";
1366                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1367                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1368                                 pinctrl-names = "default";
1369                                 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1370                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1371                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1372                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1373                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1374                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1375                                        <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1376                                 dma-names = "tx", "rx";
1377                                 #address-cells = <1>;
1378                                 #size-cells = <0>;
1379                                 status = "disabled";
1380                         };
1381
1382                         i2c1: i2c@a84000 {
1383                                 compatible = "qcom,geni-i2c";
1384                                 reg = <0 0x00a84000 0 0x4000>;
1385                                 clock-names = "se";
1386                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1387                                 pinctrl-names = "default";
1388                                 pinctrl-0 = <&qup_i2c1_data_clk>;
1389                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1390                                 #address-cells = <1>;
1391                                 #size-cells = <0>;
1392                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1393                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1394                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1395                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1396                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1397                                        <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1398                                 dma-names = "tx", "rx";
1399                                 status = "disabled";
1400                         };
1401
1402                         spi1: spi@a84000 {
1403                                 compatible = "qcom,geni-spi";
1404                                 reg = <0 0x00a84000 0 0x4000>;
1405                                 clock-names = "se";
1406                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1407                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1408                                 pinctrl-names = "default";
1409                                 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1410                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1411                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1412                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1413                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1414                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1415                                        <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1416                                 dma-names = "tx", "rx";
1417                                 #address-cells = <1>;
1418                                 #size-cells = <0>;
1419                                 status = "disabled";
1420                         };
1421
1422                         i2c2: i2c@a88000 {
1423                                 compatible = "qcom,geni-i2c";
1424                                 reg = <0 0x00a88000 0 0x4000>;
1425                                 clock-names = "se";
1426                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1427                                 pinctrl-names = "default";
1428                                 pinctrl-0 = <&qup_i2c2_data_clk>;
1429                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1430                                 #address-cells = <1>;
1431                                 #size-cells = <0>;
1432                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1433                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1434                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1435                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1436                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1437                                        <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1438                                 dma-names = "tx", "rx";
1439                                 status = "disabled";
1440                         };
1441
1442                         spi2: spi@a88000 {
1443                                 compatible = "qcom,geni-spi";
1444                                 reg = <0 0x00a88000 0 0x4000>;
1445                                 clock-names = "se";
1446                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1447                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1448                                 pinctrl-names = "default";
1449                                 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1450                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1451                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1452                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1453                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1454                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1455                                        <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1456                                 dma-names = "tx", "rx";
1457                                 #address-cells = <1>;
1458                                 #size-cells = <0>;
1459                                 status = "disabled";
1460                         };
1461
1462                         i2c3: i2c@a8c000 {
1463                                 compatible = "qcom,geni-i2c";
1464                                 reg = <0 0x00a8c000 0 0x4000>;
1465                                 clock-names = "se";
1466                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1467                                 pinctrl-names = "default";
1468                                 pinctrl-0 = <&qup_i2c3_data_clk>;
1469                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1470                                 #address-cells = <1>;
1471                                 #size-cells = <0>;
1472                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1473                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1474                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1475                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1476                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1477                                        <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1478                                 dma-names = "tx", "rx";
1479                                 status = "disabled";
1480                         };
1481
1482                         spi3: spi@a8c000 {
1483                                 compatible = "qcom,geni-spi";
1484                                 reg = <0 0x00a8c000 0 0x4000>;
1485                                 clock-names = "se";
1486                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1487                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1488                                 pinctrl-names = "default";
1489                                 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1490                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1491                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1492                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1493                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1494                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1495                                        <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1496                                 dma-names = "tx", "rx";
1497                                 #address-cells = <1>;
1498                                 #size-cells = <0>;
1499                                 status = "disabled";
1500                         };
1501
1502                         i2c4: i2c@a90000 {
1503                                 compatible = "qcom,geni-i2c";
1504                                 reg = <0 0x00a90000 0 0x4000>;
1505                                 clock-names = "se";
1506                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1507                                 pinctrl-names = "default";
1508                                 pinctrl-0 = <&qup_i2c4_data_clk>;
1509                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1510                                 #address-cells = <1>;
1511                                 #size-cells = <0>;
1512                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1513                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1514                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1515                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1516                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1517                                        <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1518                                 dma-names = "tx", "rx";
1519                                 status = "disabled";
1520                         };
1521
1522                         spi4: spi@a90000 {
1523                                 compatible = "qcom,geni-spi";
1524                                 reg = <0 0x00a90000 0 0x4000>;
1525                                 clock-names = "se";
1526                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1527                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1528                                 pinctrl-names = "default";
1529                                 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1530                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1531                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1532                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1533                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1534                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1535                                        <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1536                                 dma-names = "tx", "rx";
1537                                 #address-cells = <1>;
1538                                 #size-cells = <0>;
1539                                 status = "disabled";
1540                         };
1541
1542                         i2c5: i2c@a94000 {
1543                                 compatible = "qcom,geni-i2c";
1544                                 reg = <0 0x00a94000 0 0x4000>;
1545                                 clock-names = "se";
1546                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1547                                 pinctrl-names = "default";
1548                                 pinctrl-0 = <&qup_i2c5_data_clk>;
1549                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1550                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1551                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1552                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1553                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1554                                 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1555                                        <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1556                                 dma-names = "tx", "rx";
1557                                 #address-cells = <1>;
1558                                 #size-cells = <0>;
1559                                 status = "disabled";
1560                         };
1561
1562                         spi5: spi@a94000 {
1563                                 compatible = "qcom,geni-spi";
1564                                 reg = <0 0x00a94000 0 0x4000>;
1565                                 clock-names = "se";
1566                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1567                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1568                                 pinctrl-names = "default";
1569                                 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1570                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1571                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1572                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1573                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1574                                 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1575                                        <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1576                                 dma-names = "tx", "rx";
1577                                 #address-cells = <1>;
1578                                 #size-cells = <0>;
1579                                 status = "disabled";
1580                         };
1581
1582                         i2c6: i2c@a98000 {
1583                                 compatible = "qcom,geni-i2c";
1584                                 reg = <0 0x00a98000 0 0x4000>;
1585                                 clock-names = "se";
1586                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1587                                 pinctrl-names = "default";
1588                                 pinctrl-0 = <&qup_i2c6_data_clk>;
1589                                 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
1590                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1591                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1592                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1593                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1594                                 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1595                                        <&gpi_dma1 1 6 QCOM_GPI_I2C>;
1596                                 dma-names = "tx", "rx";
1597                                 #address-cells = <1>;
1598                                 #size-cells = <0>;
1599                                 status = "disabled";
1600                         };
1601
1602                         spi6: spi@a98000 {
1603                                 compatible = "qcom,geni-spi";
1604                                 reg = <0 0x00a98000 0 0x4000>;
1605                                 clock-names = "se";
1606                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1607                                 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
1608                                 pinctrl-names = "default";
1609                                 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1610                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1611                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1612                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt  SLAVE_EBI1 0>;
1613                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1614                                 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
1615                                        <&gpi_dma1 1 6 QCOM_GPI_SPI>;
1616                                 dma-names = "tx", "rx";
1617                                 #address-cells = <1>;
1618                                 #size-cells = <0>;
1619                                 status = "disabled";
1620                         };
1621
1622                         uart7: serial@a9c000 {
1623                                 compatible = "qcom,geni-debug-uart";
1624                                 reg = <0 0x00a9c000 0 0x4000>;
1625                                 clock-names = "se";
1626                                 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1627                                 pinctrl-names = "default";
1628                                 pinctrl-0 = <&qup_uart7_default>;
1629                                 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>;
1630                                 interconnect-names = "qup-core", "qup-config";
1631                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1632                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1633                                 status = "disabled";
1634                         };
1635                 };
1636
1637                 cnoc_main: interconnect@1500000 {
1638                         compatible = "qcom,sm8550-cnoc-main";
1639                         reg = <0 0x01500000 0 0x13080>;
1640                         #interconnect-cells = <2>;
1641                         qcom,bcm-voters = <&apps_bcm_voter>;
1642                 };
1643
1644                 config_noc: interconnect@1600000 {
1645                         compatible = "qcom,sm8550-config-noc";
1646                         reg = <0 0x01600000 0 0x6200>;
1647                         #interconnect-cells = <2>;
1648                         qcom,bcm-voters = <&apps_bcm_voter>;
1649                 };
1650
1651                 system_noc: interconnect@1680000 {
1652                         compatible = "qcom,sm8550-system-noc";
1653                         reg = <0 0x01680000 0 0x1d080>;
1654                         #interconnect-cells = <2>;
1655                         qcom,bcm-voters = <&apps_bcm_voter>;
1656                 };
1657
1658                 pcie_noc: interconnect@16c0000 {
1659                         compatible = "qcom,sm8550-pcie-anoc";
1660                         reg = <0 0x016c0000 0 0x12200>;
1661                         #interconnect-cells = <2>;
1662                         clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
1663                                  <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>;
1664                         qcom,bcm-voters = <&apps_bcm_voter>;
1665                 };
1666
1667                 aggre1_noc: interconnect@16e0000 {
1668                         compatible = "qcom,sm8550-aggre1-noc";
1669                         reg = <0 0x016e0000 0 0x14400>;
1670                         #interconnect-cells = <2>;
1671                         clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1672                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
1673                         qcom,bcm-voters = <&apps_bcm_voter>;
1674                 };
1675
1676                 aggre2_noc: interconnect@1700000 {
1677                         compatible = "qcom,sm8550-aggre2-noc";
1678                         reg = <0 0x01700000 0 0x1e400>;
1679                         #interconnect-cells = <2>;
1680                         clocks = <&rpmhcc RPMH_IPA_CLK>;
1681                         qcom,bcm-voters = <&apps_bcm_voter>;
1682                 };
1683
1684                 mmss_noc: interconnect@1780000 {
1685                         compatible = "qcom,sm8550-mmss-noc";
1686                         reg = <0 0x01780000 0 0x5b800>;
1687                         #interconnect-cells = <2>;
1688                         qcom,bcm-voters = <&apps_bcm_voter>;
1689                 };
1690
1691                 rng: rng@10c3000 {
1692                         compatible = "qcom,sm8550-trng", "qcom,trng";
1693                         reg = <0 0x010c3000 0 0x1000>;
1694                 };
1695
1696                 pcie0: pcie@1c00000 {
1697                         device_type = "pci";
1698                         compatible = "qcom,pcie-sm8550";
1699                         reg = <0 0x01c00000 0 0x3000>,
1700                               <0 0x60000000 0 0xf1d>,
1701                               <0 0x60000f20 0 0xa8>,
1702                               <0 0x60001000 0 0x1000>,
1703                               <0 0x60100000 0 0x100000>;
1704                         reg-names = "parf", "dbi", "elbi", "atu", "config";
1705                         #address-cells = <3>;
1706                         #size-cells = <2>;
1707                         ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1708                                  <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1709                         bus-range = <0x00 0xff>;
1710
1711                         dma-coherent;
1712
1713                         linux,pci-domain = <0>;
1714                         num-lanes = <2>;
1715
1716                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
1717                         interrupt-names = "msi";
1718
1719                         #interrupt-cells = <1>;
1720                         interrupt-map-mask = <0 0 0 0x7>;
1721                         interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1722                                         <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1723                                         <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1724                                         <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1725
1726                         clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
1727                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1728                                  <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1729                                  <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1730                                  <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1731                                  <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
1732                                  <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>;
1733                         clock-names = "aux",
1734                                       "cfg",
1735                                       "bus_master",
1736                                       "bus_slave",
1737                                       "slave_q2a",
1738                                       "ddrss_sf_tbu",
1739                                       "noc_aggr";
1740
1741                         interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
1742                                         <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_0 0>;
1743                         interconnect-names = "pcie-mem", "cpu-pcie";
1744
1745                         iommu-map = <0x0   &apps_smmu 0x1400 0x1>,
1746                                     <0x100 &apps_smmu 0x1401 0x1>;
1747
1748                         resets = <&gcc GCC_PCIE_0_BCR>;
1749                         reset-names = "pci";
1750
1751                         power-domains = <&gcc PCIE_0_GDSC>;
1752
1753                         phys = <&pcie0_phy>;
1754                         phy-names = "pciephy";
1755
1756                         status = "disabled";
1757                 };
1758
1759                 pcie0_phy: phy@1c06000 {
1760                         compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy";
1761                         reg = <0 0x01c06000 0 0x2000>;
1762
1763                         clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
1764                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1765                                  <&tcsr TCSR_PCIE_0_CLKREF_EN>,
1766                                  <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
1767                                  <&gcc GCC_PCIE_0_PIPE_CLK>;
1768                         clock-names = "aux", "cfg_ahb", "ref", "rchng",
1769                                       "pipe";
1770
1771                         resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1772                         reset-names = "phy";
1773
1774                         assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
1775                         assigned-clock-rates = <100000000>;
1776
1777                         power-domains = <&gcc PCIE_0_PHY_GDSC>;
1778
1779                         #clock-cells = <0>;
1780                         clock-output-names = "pcie0_pipe_clk";
1781
1782                         #phy-cells = <0>;
1783
1784                         status = "disabled";
1785                 };
1786
1787                 pcie1: pcie@1c08000 {
1788                         device_type = "pci";
1789                         compatible = "qcom,pcie-sm8550";
1790                         reg = <0x0 0x01c08000 0x0 0x3000>,
1791                               <0x0 0x40000000 0x0 0xf1d>,
1792                               <0x0 0x40000f20 0x0 0xa8>,
1793                               <0x0 0x40001000 0x0 0x1000>,
1794                               <0x0 0x40100000 0x0 0x100000>;
1795                         reg-names = "parf", "dbi", "elbi", "atu", "config";
1796                         #address-cells = <3>;
1797                         #size-cells = <2>;
1798                         ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1799                                  <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1800                         bus-range = <0x00 0xff>;
1801
1802                         dma-coherent;
1803
1804                         linux,pci-domain = <1>;
1805                         num-lanes = <2>;
1806
1807                         interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
1808                         interrupt-names = "msi";
1809
1810                         #interrupt-cells = <1>;
1811                         interrupt-map-mask = <0 0 0 0x7>;
1812                         interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1813                                         <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1814                                         <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1815                                         <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1816
1817                         clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
1818                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1819                                  <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1820                                  <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1821                                  <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1822                                  <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
1823                                  <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
1824                                  <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>;
1825                         clock-names = "aux",
1826                                       "cfg",
1827                                       "bus_master",
1828                                       "bus_slave",
1829                                       "slave_q2a",
1830                                       "ddrss_sf_tbu",
1831                                       "noc_aggr",
1832                                       "cnoc_sf_axi";
1833
1834                         assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
1835                         assigned-clock-rates = <19200000>;
1836
1837                         interconnects = <&pcie_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>,
1838                                         <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_1 0>;
1839                         interconnect-names = "pcie-mem", "cpu-pcie";
1840
1841                         iommu-map = <0x0   &apps_smmu 0x1480 0x1>,
1842                                     <0x100 &apps_smmu 0x1481 0x1>;
1843
1844                         resets = <&gcc GCC_PCIE_1_BCR>,
1845                                 <&gcc GCC_PCIE_1_LINK_DOWN_BCR>;
1846                         reset-names = "pci", "link_down";
1847
1848                         power-domains = <&gcc PCIE_1_GDSC>;
1849
1850                         phys = <&pcie1_phy>;
1851                         phy-names = "pciephy";
1852
1853                         status = "disabled";
1854                 };
1855
1856                 pcie1_phy: phy@1c0e000 {
1857                         compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy";
1858                         reg = <0x0 0x01c0e000 0x0 0x2000>;
1859
1860                         clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>,
1861                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1862                                  <&tcsr TCSR_PCIE_1_CLKREF_EN>,
1863                                  <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
1864                                  <&gcc GCC_PCIE_1_PIPE_CLK>;
1865                         clock-names = "aux", "cfg_ahb", "ref", "rchng",
1866                                       "pipe";
1867
1868                         resets = <&gcc GCC_PCIE_1_PHY_BCR>,
1869                                  <&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>;
1870                         reset-names = "phy", "phy_nocsr";
1871
1872                         assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
1873                         assigned-clock-rates = <100000000>;
1874
1875                         power-domains = <&gcc PCIE_1_PHY_GDSC>;
1876
1877                         #clock-cells = <0>;
1878                         clock-output-names = "pcie1_pipe_clk";
1879
1880                         #phy-cells = <0>;
1881
1882                         status = "disabled";
1883                 };
1884
1885                 cryptobam: dma-controller@1dc4000 {
1886                         compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
1887                         reg = <0x0 0x01dc4000 0x0 0x28000>;
1888                         interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
1889                         #dma-cells = <1>;
1890                         qcom,ee = <0>;
1891                         qcom,controlled-remotely;
1892                         iommus = <&apps_smmu 0x480 0x0>,
1893                                  <&apps_smmu 0x481 0x0>;
1894                 };
1895
1896                 crypto: crypto@1dfa000 {
1897                         compatible = "qcom,sm8550-qce", "qcom,sm8150-qce", "qcom,qce";
1898                         reg = <0x0 0x01dfa000 0x0 0x6000>;
1899                         dmas = <&cryptobam 4>, <&cryptobam 5>;
1900                         dma-names = "rx", "tx";
1901                         iommus = <&apps_smmu 0x480 0x0>,
1902                                  <&apps_smmu 0x481 0x0>;
1903                         interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
1904                         interconnect-names = "memory";
1905                 };
1906
1907                 ufs_mem_phy: phy@1d80000 {
1908                         compatible = "qcom,sm8550-qmp-ufs-phy";
1909                         reg = <0x0 0x01d80000 0x0 0x2000>;
1910                         clocks = <&tcsr TCSR_UFS_CLKREF_EN>,
1911                                  <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
1912                         clock-names = "ref", "ref_aux";
1913
1914                         power-domains = <&gcc UFS_MEM_PHY_GDSC>;
1915
1916                         resets = <&ufs_mem_hc 0>;
1917                         reset-names = "ufsphy";
1918
1919                         #clock-cells = <1>;
1920                         #phy-cells = <0>;
1921
1922                         status = "disabled";
1923                 };
1924
1925                 ufs_mem_hc: ufs@1d84000 {
1926                         compatible = "qcom,sm8550-ufshc", "qcom,ufshc",
1927                                      "jedec,ufs-2.0";
1928                         reg = <0x0 0x01d84000 0x0 0x3000>;
1929                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1930                         phys = <&ufs_mem_phy>;
1931                         phy-names = "ufsphy";
1932                         lanes-per-direction = <2>;
1933                         #reset-cells = <1>;
1934                         resets = <&gcc GCC_UFS_PHY_BCR>;
1935                         reset-names = "rst";
1936
1937                         power-domains = <&gcc UFS_PHY_GDSC>;
1938                         required-opps = <&rpmhpd_opp_nom>;
1939
1940                         iommus = <&apps_smmu 0x60 0x0>;
1941                         dma-coherent;
1942
1943                         interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
1944                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
1945
1946                         interconnect-names = "ufs-ddr", "cpu-ufs";
1947                         clock-names = "core_clk",
1948                                       "bus_aggr_clk",
1949                                       "iface_clk",
1950                                       "core_clk_unipro",
1951                                       "ref_clk",
1952                                       "tx_lane0_sync_clk",
1953                                       "rx_lane0_sync_clk",
1954                                       "rx_lane1_sync_clk";
1955                         clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
1956                                  <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1957                                  <&gcc GCC_UFS_PHY_AHB_CLK>,
1958                                  <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1959                                  <&tcsr TCSR_UFS_PAD_CLKREF_EN>,
1960                                  <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1961                                  <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
1962                                  <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
1963                         freq-table-hz =
1964                                 <75000000 300000000>,
1965                                 <0 0>,
1966                                 <0 0>,
1967                                 <75000000 300000000>,
1968                                 <100000000 403000000>,
1969                                 <0 0>,
1970                                 <0 0>,
1971                                 <0 0>;
1972                         qcom,ice = <&ice>;
1973
1974                         status = "disabled";
1975                 };
1976
1977                 ice: crypto@1d88000 {
1978                         compatible = "qcom,sm8550-inline-crypto-engine",
1979                                      "qcom,inline-crypto-engine";
1980                         reg = <0 0x01d88000 0 0x8000>;
1981                         clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
1982                 };
1983
1984                 tcsr_mutex: hwlock@1f40000 {
1985                         compatible = "qcom,tcsr-mutex";
1986                         reg = <0 0x01f40000 0 0x20000>;
1987                         #hwlock-cells = <1>;
1988                 };
1989
1990                 tcsr: clock-controller@1fc0000 {
1991                         compatible = "qcom,sm8550-tcsr", "syscon";
1992                         reg = <0 0x01fc0000 0 0x30000>;
1993                         clocks = <&rpmhcc RPMH_CXO_CLK>;
1994                         #clock-cells = <1>;
1995                         #reset-cells = <1>;
1996                 };
1997
1998                 gpu: gpu@3d00000 {
1999                         compatible = "qcom,adreno-43050a01", "qcom,adreno";
2000                         reg = <0x0 0x03d00000 0x0 0x40000>,
2001                               <0x0 0x03d9e000 0x0 0x1000>,
2002                               <0x0 0x03d61000 0x0 0x800>;
2003                         reg-names = "kgsl_3d0_reg_memory",
2004                                     "cx_mem",
2005                                     "cx_dbgc";
2006
2007                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2008
2009                         iommus = <&adreno_smmu 0 0x0>,
2010                                  <&adreno_smmu 1 0x0>;
2011
2012                         operating-points-v2 = <&gpu_opp_table>;
2013
2014                         qcom,gmu = <&gmu>;
2015
2016                         status = "disabled";
2017
2018                         zap-shader {
2019                                 memory-region = <&gpu_micro_code_mem>;
2020                         };
2021
2022                         /* Speedbin needs more work on A740+, keep only lower freqs */
2023                         gpu_opp_table: opp-table {
2024                                 compatible = "operating-points-v2";
2025
2026                                 opp-680000000 {
2027                                         opp-hz = /bits/ 64 <680000000>;
2028                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2029                                 };
2030
2031                                 opp-615000000 {
2032                                         opp-hz = /bits/ 64 <615000000>;
2033                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
2034                                 };
2035
2036                                 opp-550000000 {
2037                                         opp-hz = /bits/ 64 <550000000>;
2038                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2039                                 };
2040
2041                                 opp-475000000 {
2042                                         opp-hz = /bits/ 64 <475000000>;
2043                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
2044                                 };
2045
2046                                 opp-401000000 {
2047                                         opp-hz = /bits/ 64 <401000000>;
2048                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2049                                 };
2050
2051                                 opp-348000000 {
2052                                         opp-hz = /bits/ 64 <348000000>;
2053                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
2054                                 };
2055
2056                                 opp-295000000 {
2057                                         opp-hz = /bits/ 64 <295000000>;
2058                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
2059                                 };
2060
2061                                 opp-220000000 {
2062                                         opp-hz = /bits/ 64 <220000000>;
2063                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
2064                                 };
2065                         };
2066                 };
2067
2068                 gmu: gmu@3d6a000 {
2069                         compatible = "qcom,adreno-gmu-740.1", "qcom,adreno-gmu";
2070                         reg = <0x0 0x03d6a000 0x0 0x35000>,
2071                               <0x0 0x03d50000 0x0 0x10000>,
2072                               <0x0 0x0b280000 0x0 0x10000>;
2073                         reg-names = "gmu", "rscc", "gmu_pdc";
2074
2075                         interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2076                                      <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2077                         interrupt-names = "hfi", "gmu";
2078
2079                         clocks = <&gpucc GPU_CC_AHB_CLK>,
2080                                  <&gpucc GPU_CC_CX_GMU_CLK>,
2081                                  <&gpucc GPU_CC_CXO_CLK>,
2082                                  <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2083                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2084                                  <&gpucc GPU_CC_HUB_CX_INT_CLK>,
2085                                  <&gpucc GPU_CC_DEMET_CLK>;
2086                         clock-names = "ahb",
2087                                       "gmu",
2088                                       "cxo",
2089                                       "axi",
2090                                       "memnoc",
2091                                       "hub",
2092                                       "demet";
2093
2094                         power-domains = <&gpucc GPU_CC_CX_GDSC>,
2095                                         <&gpucc GPU_CC_GX_GDSC>;
2096                         power-domain-names = "cx",
2097                                              "gx";
2098
2099                         iommus = <&adreno_smmu 5 0x0>;
2100
2101                         qcom,qmp = <&aoss_qmp>;
2102
2103                         operating-points-v2 = <&gmu_opp_table>;
2104
2105                         gmu_opp_table: opp-table {
2106                                 compatible = "operating-points-v2";
2107
2108                                 opp-500000000 {
2109                                         opp-hz = /bits/ 64 <500000000>;
2110                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2111                                 };
2112
2113                                 opp-200000000 {
2114                                         opp-hz = /bits/ 64 <200000000>;
2115                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2116                                 };
2117                         };
2118                 };
2119
2120                 gpucc: clock-controller@3d90000 {
2121                         compatible = "qcom,sm8550-gpucc";
2122                         reg = <0 0x03d90000 0 0xa000>;
2123                         clocks = <&bi_tcxo_div2>,
2124                                  <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2125                                  <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2126                         #clock-cells = <1>;
2127                         #reset-cells = <1>;
2128                         #power-domain-cells = <1>;
2129                 };
2130
2131                 adreno_smmu: iommu@3da0000 {
2132                         compatible = "qcom,sm8550-smmu-500", "qcom,adreno-smmu",
2133                                      "qcom,smmu-500", "arm,mmu-500";
2134                         reg = <0x0 0x03da0000 0x0 0x40000>;
2135                         #iommu-cells = <2>;
2136                         #global-interrupts = <1>;
2137                         interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
2138                                      <GIC_SPI 677 IRQ_TYPE_LEVEL_HIGH>,
2139                                      <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
2140                                      <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
2141                                      <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
2142                                      <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
2143                                      <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
2144                                      <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
2145                                      <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
2146                                      <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
2147                                      <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
2148                                      <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
2149                                      <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
2150                                      <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
2151                                      <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>,
2152                                      <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>,
2153                                      <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
2154                                      <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>,
2155                                      <GIC_SPI 659 IRQ_TYPE_LEVEL_HIGH>,
2156                                      <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH>,
2157                                      <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH>,
2158                                      <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>,
2159                                      <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>,
2160                                      <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH>,
2161                                      <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>,
2162                                      <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>;
2163                         clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
2164                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2165                                  <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
2166                                  <&gpucc GPU_CC_AHB_CLK>;
2167                         clock-names = "hlos",
2168                                       "bus",
2169                                       "iface",
2170                                       "ahb";
2171                         power-domains = <&gpucc GPU_CC_CX_GDSC>;
2172                         dma-coherent;
2173                 };
2174
2175                 ipa: ipa@3f40000 {
2176                         compatible = "qcom,sm8550-ipa";
2177
2178                         iommus = <&apps_smmu 0x4a0 0x0>,
2179                                  <&apps_smmu 0x4a2 0x0>;
2180                         reg = <0 0x3f40000 0 0x10000>,
2181                               <0 0x3f50000 0 0x5000>,
2182                               <0 0x3e04000 0 0xfc000>;
2183                         reg-names = "ipa-reg",
2184                                     "ipa-shared",
2185                                     "gsi";
2186
2187                         interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>,
2188                                               <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
2189                                               <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2190                                               <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
2191                         interrupt-names = "ipa",
2192                                           "gsi",
2193                                           "ipa-clock-query",
2194                                           "ipa-setup-ready";
2195
2196                         clocks = <&rpmhcc RPMH_IPA_CLK>;
2197                         clock-names = "core";
2198
2199                         interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
2200                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
2201                         interconnect-names = "memory",
2202                                              "config";
2203
2204                         qcom,qmp = <&aoss_qmp>;
2205
2206                         qcom,smem-states = <&ipa_smp2p_out 0>,
2207                                            <&ipa_smp2p_out 1>;
2208                         qcom,smem-state-names = "ipa-clock-enabled-valid",
2209                                                 "ipa-clock-enabled";
2210
2211                         status = "disabled";
2212                 };
2213
2214                 remoteproc_mpss: remoteproc@4080000 {
2215                         compatible = "qcom,sm8550-mpss-pas";
2216                         reg = <0x0 0x04080000 0x0 0x4040>;
2217
2218                         interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
2219                                               <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
2220                                               <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
2221                                               <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
2222                                               <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
2223                                               <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
2224                         interrupt-names = "wdog", "fatal", "ready", "handover",
2225                                           "stop-ack", "shutdown-ack";
2226
2227                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2228                         clock-names = "xo";
2229
2230                         power-domains = <&rpmhpd RPMHPD_CX>,
2231                                         <&rpmhpd RPMHPD_MSS>;
2232                         power-domain-names = "cx", "mss";
2233
2234                         interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
2235
2236                         memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, <&mpss_dsm_mem>;
2237
2238                         qcom,qmp = <&aoss_qmp>;
2239
2240                         qcom,smem-states = <&smp2p_modem_out 0>;
2241                         qcom,smem-state-names = "stop";
2242
2243                         status = "disabled";
2244
2245                         glink-edge {
2246                                 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2247                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
2248                                                              IRQ_TYPE_EDGE_RISING>;
2249                                 mboxes = <&ipcc IPCC_CLIENT_MPSS
2250                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2251                                 label = "mpss";
2252                                 qcom,remote-pid = <1>;
2253                         };
2254                 };
2255
2256                 lpass_wsa2macro: codec@6aa0000 {
2257                         compatible = "qcom,sm8550-lpass-wsa-macro";
2258                         reg = <0 0x06aa0000 0 0x1000>;
2259                         clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2260                                  <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2261                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2262                                  <&lpass_vamacro>;
2263                         clock-names = "mclk", "macro", "dcodec", "fsgen";
2264
2265                         #clock-cells = <0>;
2266                         clock-output-names = "wsa2-mclk";
2267                         #sound-dai-cells = <1>;
2268                 };
2269
2270                 swr3: soundwire@6ab0000 {
2271                         compatible = "qcom,soundwire-v2.0.0";
2272                         reg = <0 0x06ab0000 0 0x10000>;
2273                         interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
2274                         clocks = <&lpass_wsa2macro>;
2275                         clock-names = "iface";
2276                         label = "WSA2";
2277
2278                         pinctrl-0 = <&wsa2_swr_active>;
2279                         pinctrl-names = "default";
2280
2281                         qcom,din-ports = <4>;
2282                         qcom,dout-ports = <9>;
2283
2284                         qcom,ports-sinterval =          /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>;
2285                         qcom,ports-offset1 =            /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
2286                         qcom,ports-offset2 =            /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2287                         qcom,ports-hstart =             /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2288                         qcom,ports-hstop =              /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2289                         qcom,ports-word-length =        /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>;
2290                         qcom,ports-block-pack-mode =    /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>;
2291                         qcom,ports-block-group-count =  /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2292                         qcom,ports-lane-control =       /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2293
2294                         #address-cells = <2>;
2295                         #size-cells = <0>;
2296                         #sound-dai-cells = <1>;
2297                         status = "disabled";
2298                 };
2299
2300                 lpass_rxmacro: codec@6ac0000 {
2301                         compatible = "qcom,sm8550-lpass-rx-macro";
2302                         reg = <0 0x06ac0000 0 0x1000>;
2303                         clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2304                                  <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2305                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2306                                  <&lpass_vamacro>;
2307                         clock-names = "mclk", "macro", "dcodec", "fsgen";
2308
2309                         #clock-cells = <0>;
2310                         clock-output-names = "mclk";
2311                         #sound-dai-cells = <1>;
2312                 };
2313
2314                 swr1: soundwire@6ad0000 {
2315                         compatible = "qcom,soundwire-v2.0.0";
2316                         reg = <0 0x06ad0000 0 0x10000>;
2317                         interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
2318                         clocks = <&lpass_rxmacro>;
2319                         clock-names = "iface";
2320                         label = "RX";
2321
2322                         pinctrl-0 = <&rx_swr_active>;
2323                         pinctrl-names = "default";
2324
2325                         qcom,din-ports = <1>;
2326                         qcom,dout-ports = <11>;
2327
2328                         qcom,ports-sinterval =          /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0xff 0xff 0xff 0xff>;
2329                         qcom,ports-offset1 =            /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
2330                         qcom,ports-offset2 =            /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
2331                         qcom,ports-hstart =             /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff>;
2332                         qcom,ports-hstop =              /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff>;
2333                         qcom,ports-word-length =        /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff 0xff 0xff 0xff 0xff 0xff>;
2334                         qcom,ports-block-pack-mode =    /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
2335                         qcom,ports-block-group-count =  /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
2336                         qcom,ports-lane-control =       /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
2337
2338                         #address-cells = <2>;
2339                         #size-cells = <0>;
2340                         #sound-dai-cells = <1>;
2341                         status = "disabled";
2342                 };
2343
2344                 lpass_txmacro: codec@6ae0000 {
2345                         compatible = "qcom,sm8550-lpass-tx-macro";
2346                         reg = <0 0x06ae0000 0 0x1000>;
2347                         clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2348                                  <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2349                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2350                                  <&lpass_vamacro>;
2351                         clock-names = "mclk", "macro", "dcodec", "fsgen";
2352
2353                         #clock-cells = <0>;
2354                         clock-output-names = "mclk";
2355                         #sound-dai-cells = <1>;
2356                 };
2357
2358                 lpass_wsamacro: codec@6b00000 {
2359                         compatible = "qcom,sm8550-lpass-wsa-macro";
2360                         reg = <0 0x06b00000 0 0x1000>;
2361                         clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2362                                  <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2363                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2364                                  <&lpass_vamacro>;
2365                         clock-names = "mclk", "macro", "dcodec", "fsgen";
2366
2367                         #clock-cells = <0>;
2368                         clock-output-names = "mclk";
2369                         #sound-dai-cells = <1>;
2370                 };
2371
2372                 swr0: soundwire@6b10000 {
2373                         compatible = "qcom,soundwire-v2.0.0";
2374                         reg = <0 0x06b10000 0 0x10000>;
2375                         interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
2376                         clocks = <&lpass_wsamacro>;
2377                         clock-names = "iface";
2378                         label = "WSA";
2379
2380                         pinctrl-0 = <&wsa_swr_active>;
2381                         pinctrl-names = "default";
2382
2383                         qcom,din-ports = <4>;
2384                         qcom,dout-ports = <9>;
2385
2386                         qcom,ports-sinterval =          /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>;
2387                         qcom,ports-offset1 =            /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
2388                         qcom,ports-offset2 =            /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2389                         qcom,ports-hstart =             /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2390                         qcom,ports-hstop =              /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
2391                         qcom,ports-word-length =        /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>;
2392                         qcom,ports-block-pack-mode =    /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>;
2393                         qcom,ports-block-group-count =  /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2394                         qcom,ports-lane-control =       /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2395
2396                         #address-cells = <2>;
2397                         #size-cells = <0>;
2398                         #sound-dai-cells = <1>;
2399                         status = "disabled";
2400                 };
2401
2402                 swr2: soundwire@6d30000 {
2403                         compatible = "qcom,soundwire-v2.0.0";
2404                         reg = <0 0x06d30000 0 0x10000>;
2405                         interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
2406                                      <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
2407                         interrupt-names = "core", "wakeup";
2408                         clocks = <&lpass_txmacro>;
2409                         clock-names = "iface";
2410                         label = "TX";
2411
2412                         pinctrl-0 = <&tx_swr_active>;
2413                         pinctrl-names = "default";
2414
2415                         qcom,din-ports = <4>;
2416                         qcom,dout-ports = <0>;
2417                         qcom,ports-sinterval-low =      /bits/ 8 <0x01 0x01 0x03 0x03>;
2418                         qcom,ports-offset1 =            /bits/ 8 <0x00 0x00 0x01 0x01>;
2419                         qcom,ports-offset2 =            /bits/ 8 <0x00 0x00 0x00 0x00>;
2420                         qcom,ports-hstart =             /bits/ 8 <0xff 0xff 0xff 0xff>;
2421                         qcom,ports-hstop =              /bits/ 8 <0xff 0xff 0xff 0xff>;
2422                         qcom,ports-word-length =        /bits/ 8 <0xff 0xff 0xff 0xff>;
2423                         qcom,ports-block-pack-mode =    /bits/ 8 <0xff 0xff 0xff 0xff>;
2424                         qcom,ports-block-group-count =  /bits/ 8 <0xff 0xff 0xff 0xff>;
2425                         qcom,ports-lane-control =       /bits/ 8 <0x01 0x02 0x00 0x00>;
2426
2427                         #address-cells = <2>;
2428                         #size-cells = <0>;
2429                         #sound-dai-cells = <1>;
2430                         status = "disabled";
2431                 };
2432
2433                 lpass_vamacro: codec@6d44000 {
2434                         compatible = "qcom,sm8550-lpass-va-macro";
2435                         reg = <0 0x06d44000 0 0x1000>;
2436                         clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2437                                  <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2438                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2439                         clock-names = "mclk", "macro", "dcodec";
2440
2441                         #clock-cells = <0>;
2442                         clock-output-names = "fsgen";
2443                         #sound-dai-cells = <1>;
2444                 };
2445
2446                 lpass_tlmm: pinctrl@6e80000 {
2447                         compatible = "qcom,sm8550-lpass-lpi-pinctrl";
2448                         reg = <0 0x06e80000 0 0x20000>,
2449                               <0 0x07250000 0 0x10000>;
2450                         gpio-controller;
2451                         #gpio-cells = <2>;
2452                         gpio-ranges = <&lpass_tlmm 0 0 23>;
2453
2454                         clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2455                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2456                         clock-names = "core", "audio";
2457
2458                         tx_swr_active: tx-swr-active-state {
2459                                 clk-pins {
2460                                         pins = "gpio0";
2461                                         function = "swr_tx_clk";
2462                                         drive-strength = <2>;
2463                                         slew-rate = <1>;
2464                                         bias-disable;
2465                                 };
2466
2467                                 data-pins {
2468                                         pins = "gpio1", "gpio2", "gpio14";
2469                                         function = "swr_tx_data";
2470                                         drive-strength = <2>;
2471                                         slew-rate = <1>;
2472                                         bias-bus-hold;
2473                                 };
2474                         };
2475
2476                         rx_swr_active: rx-swr-active-state {
2477                                 clk-pins {
2478                                         pins = "gpio3";
2479                                         function = "swr_rx_clk";
2480                                         drive-strength = <2>;
2481                                         slew-rate = <1>;
2482                                         bias-disable;
2483                                 };
2484
2485                                 data-pins {
2486                                         pins = "gpio4", "gpio5";
2487                                         function = "swr_rx_data";
2488                                         drive-strength = <2>;
2489                                         slew-rate = <1>;
2490                                         bias-bus-hold;
2491                                 };
2492                         };
2493
2494                         dmic01_default: dmic01-default-state {
2495                                 clk-pins {
2496                                         pins = "gpio6";
2497                                         function = "dmic1_clk";
2498                                         drive-strength = <8>;
2499                                         output-high;
2500                                 };
2501
2502                                 data-pins {
2503                                         pins = "gpio7";
2504                                         function = "dmic1_data";
2505                                         drive-strength = <8>;
2506                                         input-enable;
2507                                 };
2508                         };
2509
2510                         dmic02_default: dmic02-default-state {
2511                                 clk-pins {
2512                                         pins = "gpio8";
2513                                         function = "dmic2_clk";
2514                                         drive-strength = <8>;
2515                                         output-high;
2516                                 };
2517
2518                                 data-pins {
2519                                         pins = "gpio9";
2520                                         function = "dmic2_data";
2521                                         drive-strength = <8>;
2522                                         input-enable;
2523                                 };
2524                         };
2525
2526                         wsa_swr_active: wsa-swr-active-state {
2527                                 clk-pins {
2528                                         pins = "gpio10";
2529                                         function = "wsa_swr_clk";
2530                                         drive-strength = <2>;
2531                                         slew-rate = <1>;
2532                                         bias-disable;
2533                                 };
2534
2535                                 data-pins {
2536                                         pins = "gpio11";
2537                                         function = "wsa_swr_data";
2538                                         drive-strength = <2>;
2539                                         slew-rate = <1>;
2540                                         bias-bus-hold;
2541                                 };
2542                         };
2543
2544                         wsa2_swr_active: wsa2-swr-active-state {
2545                                 clk-pins {
2546                                         pins = "gpio15";
2547                                         function = "wsa2_swr_clk";
2548                                         drive-strength = <2>;
2549                                         slew-rate = <1>;
2550                                         bias-disable;
2551                                 };
2552
2553                                 data-pins {
2554                                         pins = "gpio16";
2555                                         function = "wsa2_swr_data";
2556                                         drive-strength = <2>;
2557                                         slew-rate = <1>;
2558                                         bias-bus-hold;
2559                                 };
2560                         };
2561                 };
2562
2563                 lpass_lpiaon_noc: interconnect@7400000 {
2564                         compatible = "qcom,sm8550-lpass-lpiaon-noc";
2565                         reg = <0 0x07400000 0 0x19080>;
2566                         #interconnect-cells = <2>;
2567                         qcom,bcm-voters = <&apps_bcm_voter>;
2568                 };
2569
2570                 lpass_lpicx_noc: interconnect@7430000 {
2571                         compatible = "qcom,sm8550-lpass-lpicx-noc";
2572                         reg = <0 0x07430000 0 0x3a200>;
2573                         #interconnect-cells = <2>;
2574                         qcom,bcm-voters = <&apps_bcm_voter>;
2575                 };
2576
2577                 lpass_ag_noc: interconnect@7e40000 {
2578                         compatible = "qcom,sm8550-lpass-ag-noc";
2579                         reg = <0 0x07e40000 0 0xe080>;
2580                         #interconnect-cells = <2>;
2581                         qcom,bcm-voters = <&apps_bcm_voter>;
2582                 };
2583
2584                 sdhc_2: mmc@8804000 {
2585                         compatible = "qcom,sm8550-sdhci", "qcom,sdhci-msm-v5";
2586                         reg = <0 0x08804000 0 0x1000>;
2587
2588                         interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
2589                                      <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
2590                         interrupt-names = "hc_irq", "pwr_irq";
2591
2592                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2593                                  <&gcc GCC_SDCC2_APPS_CLK>,
2594                                  <&rpmhcc RPMH_CXO_CLK>;
2595                         clock-names = "iface", "core", "xo";
2596                         iommus = <&apps_smmu 0x540 0>;
2597                         qcom,dll-config = <0x0007642c>;
2598                         qcom,ddr-config = <0x80040868>;
2599                         power-domains = <&rpmhpd RPMHPD_CX>;
2600                         operating-points-v2 = <&sdhc2_opp_table>;
2601
2602                         interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
2603                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
2604                         interconnect-names = "sdhc-ddr", "cpu-sdhc";
2605                         bus-width = <4>;
2606                         dma-coherent;
2607
2608                         /* Forbid SDR104/SDR50 - broken hw! */
2609                         sdhci-caps-mask = <0x3 0>;
2610
2611                         status = "disabled";
2612
2613                         sdhc2_opp_table: opp-table {
2614                                 compatible = "operating-points-v2";
2615
2616                                 opp-19200000 {
2617                                         opp-hz = /bits/ 64 <19200000>;
2618                                         required-opps = <&rpmhpd_opp_min_svs>;
2619                                 };
2620
2621                                 opp-50000000 {
2622                                         opp-hz = /bits/ 64 <50000000>;
2623                                         required-opps = <&rpmhpd_opp_low_svs>;
2624                                 };
2625
2626                                 opp-100000000 {
2627                                         opp-hz = /bits/ 64 <100000000>;
2628                                         required-opps = <&rpmhpd_opp_svs>;
2629                                 };
2630
2631                                 opp-202000000 {
2632                                         opp-hz = /bits/ 64 <202000000>;
2633                                         required-opps = <&rpmhpd_opp_svs_l1>;
2634                                 };
2635                         };
2636                 };
2637
2638                 videocc: clock-controller@aaf0000 {
2639                         compatible = "qcom,sm8550-videocc";
2640                         reg = <0 0x0aaf0000 0 0x10000>;
2641                         clocks = <&bi_tcxo_div2>,
2642                                  <&gcc GCC_VIDEO_AHB_CLK>;
2643                         power-domains = <&rpmhpd RPMHPD_MMCX>;
2644                         required-opps = <&rpmhpd_opp_low_svs>;
2645                         #clock-cells = <1>;
2646                         #reset-cells = <1>;
2647                         #power-domain-cells = <1>;
2648                 };
2649
2650                 camcc: clock-controller@ade0000 {
2651                         compatible = "qcom,sm8550-camcc";
2652                         reg = <0 0x0ade0000 0 0x20000>;
2653                         clocks = <&gcc GCC_CAMERA_AHB_CLK>,
2654                                  <&bi_tcxo_div2>,
2655                                  <&bi_tcxo_ao_div2>,
2656                                  <&sleep_clk>;
2657                         power-domains = <&rpmhpd SM8550_MMCX>;
2658                         required-opps = <&rpmhpd_opp_low_svs>;
2659                         #clock-cells = <1>;
2660                         #reset-cells = <1>;
2661                         #power-domain-cells = <1>;
2662                 };
2663
2664                 mdss: display-subsystem@ae00000 {
2665                         compatible = "qcom,sm8550-mdss";
2666                         reg = <0 0x0ae00000 0 0x1000>;
2667                         reg-names = "mdss";
2668
2669                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
2670                         interrupt-controller;
2671                         #interrupt-cells = <1>;
2672
2673                         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2674                                  <&gcc GCC_DISP_AHB_CLK>,
2675                                  <&gcc GCC_DISP_HF_AXI_CLK>,
2676                                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
2677
2678                         resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
2679
2680                         power-domains = <&dispcc MDSS_GDSC>;
2681
2682                         interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>,
2683                                         <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
2684                         interconnect-names = "mdp0-mem", "mdp1-mem";
2685
2686                         iommus = <&apps_smmu 0x1c00 0x2>;
2687
2688                         #address-cells = <2>;
2689                         #size-cells = <2>;
2690                         ranges;
2691
2692                         status = "disabled";
2693
2694                         mdss_mdp: display-controller@ae01000 {
2695                                 compatible = "qcom,sm8550-dpu";
2696                                 reg = <0 0x0ae01000 0 0x8f000>,
2697                                       <0 0x0aeb0000 0 0x2008>;
2698                                 reg-names = "mdp", "vbif";
2699
2700                                 interrupt-parent = <&mdss>;
2701                                 interrupts = <0>;
2702
2703                                 clocks = <&gcc GCC_DISP_AHB_CLK>,
2704                                          <&gcc GCC_DISP_HF_AXI_CLK>,
2705                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
2706                                          <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
2707                                          <&dispcc DISP_CC_MDSS_MDP_CLK>,
2708                                          <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2709                                 clock-names = "bus",
2710                                               "nrt_bus",
2711                                               "iface",
2712                                               "lut",
2713                                               "core",
2714                                               "vsync";
2715
2716                                 power-domains = <&rpmhpd RPMHPD_MMCX>;
2717
2718                                 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2719                                 assigned-clock-rates = <19200000>;
2720
2721                                 operating-points-v2 = <&mdp_opp_table>;
2722
2723                                 ports {
2724                                         #address-cells = <1>;
2725                                         #size-cells = <0>;
2726
2727                                         port@0 {
2728                                                 reg = <0>;
2729                                                 dpu_intf1_out: endpoint {
2730                                                         remote-endpoint = <&mdss_dsi0_in>;
2731                                                 };
2732                                         };
2733
2734                                         port@1 {
2735                                                 reg = <1>;
2736                                                 dpu_intf2_out: endpoint {
2737                                                         remote-endpoint = <&mdss_dsi1_in>;
2738                                                 };
2739                                         };
2740
2741                                         port@2 {
2742                                                 reg = <2>;
2743                                                 dpu_intf0_out: endpoint {
2744                                                         remote-endpoint = <&mdss_dp0_in>;
2745                                                 };
2746                                         };
2747                                 };
2748
2749                                 mdp_opp_table: opp-table {
2750                                         compatible = "operating-points-v2";
2751
2752                                         opp-200000000 {
2753                                                 opp-hz = /bits/ 64 <200000000>;
2754                                                 required-opps = <&rpmhpd_opp_low_svs>;
2755                                         };
2756
2757                                         opp-325000000 {
2758                                                 opp-hz = /bits/ 64 <325000000>;
2759                                                 required-opps = <&rpmhpd_opp_svs>;
2760                                         };
2761
2762                                         opp-375000000 {
2763                                                 opp-hz = /bits/ 64 <375000000>;
2764                                                 required-opps = <&rpmhpd_opp_svs_l1>;
2765                                         };
2766
2767                                         opp-514000000 {
2768                                                 opp-hz = /bits/ 64 <514000000>;
2769                                                 required-opps = <&rpmhpd_opp_nom>;
2770                                         };
2771                                 };
2772                         };
2773
2774                         mdss_dp0: displayport-controller@ae90000 {
2775                                 compatible = "qcom,sm8550-dp", "qcom,sm8350-dp";
2776                                 reg = <0 0xae90000 0 0x200>,
2777                                       <0 0xae90200 0 0x200>,
2778                                       <0 0xae90400 0 0xc00>,
2779                                       <0 0xae91000 0 0x400>,
2780                                       <0 0xae91400 0 0x400>;
2781                                 interrupt-parent = <&mdss>;
2782                                 interrupts = <12>;
2783                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2784                                          <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
2785                                          <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
2786                                          <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
2787                                          <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
2788                                 clock-names = "core_iface",
2789                                               "core_aux",
2790                                               "ctrl_link",
2791                                               "ctrl_link_iface",
2792                                               "stream_pixel";
2793
2794                                 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
2795                                                   <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
2796                                 assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
2797                                                          <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
2798
2799                                 phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>;
2800                                 phy-names = "dp";
2801
2802                                 #sound-dai-cells = <0>;
2803
2804                                 operating-points-v2 = <&dp_opp_table>;
2805                                 power-domains = <&rpmhpd RPMHPD_MMCX>;
2806
2807                                 status = "disabled";
2808
2809                                 ports {
2810                                         #address-cells = <1>;
2811                                         #size-cells = <0>;
2812
2813                                         port@0 {
2814                                                 reg = <0>;
2815                                                 mdss_dp0_in: endpoint {
2816                                                         remote-endpoint = <&dpu_intf0_out>;
2817                                                 };
2818                                         };
2819
2820                                         port@1 {
2821                                                 reg = <1>;
2822                                                 mdss_dp0_out: endpoint {
2823                                                 };
2824                                         };
2825                                 };
2826
2827                                 dp_opp_table: opp-table {
2828                                         compatible = "operating-points-v2";
2829
2830                                         opp-162000000 {
2831                                                 opp-hz = /bits/ 64 <162000000>;
2832                                                 required-opps = <&rpmhpd_opp_low_svs_d1>;
2833                                         };
2834
2835                                         opp-270000000 {
2836                                                 opp-hz = /bits/ 64 <270000000>;
2837                                                 required-opps = <&rpmhpd_opp_low_svs>;
2838                                         };
2839
2840                                         opp-540000000 {
2841                                                 opp-hz = /bits/ 64 <540000000>;
2842                                                 required-opps = <&rpmhpd_opp_svs_l1>;
2843                                         };
2844
2845                                         opp-810000000 {
2846                                                 opp-hz = /bits/ 64 <810000000>;
2847                                                 required-opps = <&rpmhpd_opp_nom>;
2848                                         };
2849                                 };
2850                         };
2851
2852                         mdss_dsi0: dsi@ae94000 {
2853                                 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2854                                 reg = <0 0x0ae94000 0 0x400>;
2855                                 reg-names = "dsi_ctrl";
2856
2857                                 interrupt-parent = <&mdss>;
2858                                 interrupts = <4>;
2859
2860                                 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
2861                                          <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
2862                                          <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
2863                                          <&dispcc DISP_CC_MDSS_ESC0_CLK>,
2864                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
2865                                          <&gcc GCC_DISP_HF_AXI_CLK>;
2866                                 clock-names = "byte",
2867                                               "byte_intf",
2868                                               "pixel",
2869                                               "core",
2870                                               "iface",
2871                                               "bus";
2872
2873                                 power-domains = <&rpmhpd RPMHPD_MMCX>;
2874
2875                                 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
2876                                                   <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
2877                                 assigned-clock-parents = <&mdss_dsi0_phy 0>,
2878                                                          <&mdss_dsi0_phy 1>;
2879
2880                                 operating-points-v2 = <&mdss_dsi_opp_table>;
2881
2882                                 phys = <&mdss_dsi0_phy>;
2883                                 phy-names = "dsi";
2884
2885                                 #address-cells = <1>;
2886                                 #size-cells = <0>;
2887
2888                                 status = "disabled";
2889
2890                                 ports {
2891                                         #address-cells = <1>;
2892                                         #size-cells = <0>;
2893
2894                                         port@0 {
2895                                                 reg = <0>;
2896                                                 mdss_dsi0_in: endpoint {
2897                                                         remote-endpoint = <&dpu_intf1_out>;
2898                                                 };
2899                                         };
2900
2901                                         port@1 {
2902                                                 reg = <1>;
2903                                                 mdss_dsi0_out: endpoint {
2904                                                 };
2905                                         };
2906                                 };
2907
2908                                 mdss_dsi_opp_table: opp-table {
2909                                         compatible = "operating-points-v2";
2910
2911                                         opp-187500000 {
2912                                                 opp-hz = /bits/ 64 <187500000>;
2913                                                 required-opps = <&rpmhpd_opp_low_svs>;
2914                                         };
2915
2916                                         opp-300000000 {
2917                                                 opp-hz = /bits/ 64 <300000000>;
2918                                                 required-opps = <&rpmhpd_opp_svs>;
2919                                         };
2920
2921                                         opp-358000000 {
2922                                                 opp-hz = /bits/ 64 <358000000>;
2923                                                 required-opps = <&rpmhpd_opp_svs_l1>;
2924                                         };
2925                                 };
2926                         };
2927
2928                         mdss_dsi0_phy: phy@ae95000 {
2929                                 compatible = "qcom,sm8550-dsi-phy-4nm";
2930                                 reg = <0 0x0ae95000 0 0x200>,
2931                                       <0 0x0ae95200 0 0x280>,
2932                                       <0 0x0ae95500 0 0x400>;
2933                                 reg-names = "dsi_phy",
2934                                             "dsi_phy_lane",
2935                                             "dsi_pll";
2936
2937                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2938                                          <&rpmhcc RPMH_CXO_CLK>;
2939                                 clock-names = "iface", "ref";
2940
2941                                 #clock-cells = <1>;
2942                                 #phy-cells = <0>;
2943
2944                                 status = "disabled";
2945                         };
2946
2947                         mdss_dsi1: dsi@ae96000 {
2948                                 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2949                                 reg = <0 0x0ae96000 0 0x400>;
2950                                 reg-names = "dsi_ctrl";
2951
2952                                 interrupt-parent = <&mdss>;
2953                                 interrupts = <5>;
2954
2955                                 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
2956                                          <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
2957                                          <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
2958                                          <&dispcc DISP_CC_MDSS_ESC1_CLK>,
2959                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
2960                                          <&gcc GCC_DISP_HF_AXI_CLK>;
2961                                 clock-names = "byte",
2962                                               "byte_intf",
2963                                               "pixel",
2964                                               "core",
2965                                               "iface",
2966                                               "bus";
2967
2968                                 power-domains = <&rpmhpd RPMHPD_MMCX>;
2969
2970                                 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
2971                                                   <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
2972                                 assigned-clock-parents = <&mdss_dsi1_phy 0>,
2973                                                          <&mdss_dsi1_phy 1>;
2974
2975                                 operating-points-v2 = <&mdss_dsi_opp_table>;
2976
2977                                 phys = <&mdss_dsi1_phy>;
2978                                 phy-names = "dsi";
2979
2980                                 #address-cells = <1>;
2981                                 #size-cells = <0>;
2982
2983                                 status = "disabled";
2984
2985                                 ports {
2986                                         #address-cells = <1>;
2987                                         #size-cells = <0>;
2988
2989                                         port@0 {
2990                                                 reg = <0>;
2991                                                 mdss_dsi1_in: endpoint {
2992                                                         remote-endpoint = <&dpu_intf2_out>;
2993                                                 };
2994                                         };
2995
2996                                         port@1 {
2997                                                 reg = <1>;
2998                                                 mdss_dsi1_out: endpoint {
2999                                                 };
3000                                         };
3001                                 };
3002                         };
3003
3004                         mdss_dsi1_phy: phy@ae97000 {
3005                                 compatible = "qcom,sm8550-dsi-phy-4nm";
3006                                 reg = <0 0x0ae97000 0 0x200>,
3007                                       <0 0x0ae97200 0 0x280>,
3008                                       <0 0x0ae97500 0 0x400>;
3009                                 reg-names = "dsi_phy",
3010                                             "dsi_phy_lane",
3011                                             "dsi_pll";
3012
3013                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3014                                          <&rpmhcc RPMH_CXO_CLK>;
3015                                 clock-names = "iface", "ref";
3016
3017                                 #clock-cells = <1>;
3018                                 #phy-cells = <0>;
3019
3020                                 status = "disabled";
3021                         };
3022                 };
3023
3024                 dispcc: clock-controller@af00000 {
3025                         compatible = "qcom,sm8550-dispcc";
3026                         reg = <0 0x0af00000 0 0x20000>;
3027                         clocks = <&bi_tcxo_div2>,
3028                                  <&bi_tcxo_ao_div2>,
3029                                  <&gcc GCC_DISP_AHB_CLK>,
3030                                  <&sleep_clk>,
3031                                  <&mdss_dsi0_phy 0>,
3032                                  <&mdss_dsi0_phy 1>,
3033                                  <&mdss_dsi1_phy 0>,
3034                                  <&mdss_dsi1_phy 1>,
3035                                  <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3036                                  <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
3037                                  <0>, /* dp1 */
3038                                  <0>,
3039                                  <0>, /* dp2 */
3040                                  <0>,
3041                                  <0>, /* dp3 */
3042                                  <0>;
3043                         power-domains = <&rpmhpd RPMHPD_MMCX>;
3044                         required-opps = <&rpmhpd_opp_low_svs>;
3045                         #clock-cells = <1>;
3046                         #reset-cells = <1>;
3047                         #power-domain-cells = <1>;
3048                 };
3049
3050                 usb_1_hsphy: phy@88e3000 {
3051                         compatible = "qcom,sm8550-snps-eusb2-phy";
3052                         reg = <0x0 0x088e3000 0x0 0x154>;
3053                         #phy-cells = <0>;
3054
3055                         clocks = <&tcsr TCSR_USB2_CLKREF_EN>;
3056                         clock-names = "ref";
3057
3058                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3059
3060                         status = "disabled";
3061                 };
3062
3063                 usb_dp_qmpphy: phy@88e8000 {
3064                         compatible = "qcom,sm8550-qmp-usb3-dp-phy";
3065                         reg = <0x0 0x088e8000 0x0 0x3000>;
3066
3067                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3068                                  <&rpmhcc RPMH_CXO_CLK>,
3069                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
3070                                  <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3071                         clock-names = "aux", "ref", "com_aux", "usb3_pipe";
3072
3073                         power-domains = <&gcc USB3_PHY_GDSC>;
3074
3075                         resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
3076                                  <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
3077                         reset-names = "phy", "common";
3078
3079                         #clock-cells = <1>;
3080                         #phy-cells = <1>;
3081
3082                         status = "disabled";
3083
3084                         ports {
3085                                 #address-cells = <1>;
3086                                 #size-cells = <0>;
3087
3088                                 port@0 {
3089                                         reg = <0>;
3090
3091                                         usb_dp_qmpphy_out: endpoint {
3092                                         };
3093                                 };
3094
3095                                 port@1 {
3096                                         reg = <1>;
3097
3098                                         usb_dp_qmpphy_usb_ss_in: endpoint {
3099                                         };
3100                                 };
3101
3102                                 port@2 {
3103                                         reg = <2>;
3104
3105                                         usb_dp_qmpphy_dp_in: endpoint {
3106                                         };
3107                                 };
3108                         };
3109                 };
3110
3111                 usb_1: usb@a6f8800 {
3112                         compatible = "qcom,sm8550-dwc3", "qcom,dwc3";
3113                         reg = <0x0 0x0a6f8800 0x0 0x400>;
3114                         #address-cells = <2>;
3115                         #size-cells = <2>;
3116                         ranges;
3117
3118                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3119                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3120                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3121                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
3122                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3123                                  <&tcsr TCSR_USB3_CLKREF_EN>;
3124                         clock-names = "cfg_noc",
3125                                       "core",
3126                                       "iface",
3127                                       "sleep",
3128                                       "mock_utmi",
3129                                       "xo";
3130
3131                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3132                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3133                         assigned-clock-rates = <19200000>, <200000000>;
3134
3135                         interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
3136                                               <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
3137                                               <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
3138                                               <&pdc 14 IRQ_TYPE_EDGE_BOTH>;
3139                         interrupt-names = "hs_phy_irq",
3140                                           "ss_phy_irq",
3141                                           "dm_hs_phy_irq",
3142                                           "dp_hs_phy_irq";
3143
3144                         power-domains = <&gcc USB30_PRIM_GDSC>;
3145                         required-opps = <&rpmhpd_opp_nom>;
3146
3147                         resets = <&gcc GCC_USB30_PRIM_BCR>;
3148
3149                         interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
3150                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
3151                         interconnect-names = "usb-ddr", "apps-usb";
3152
3153                         status = "disabled";
3154
3155                         usb_1_dwc3: usb@a600000 {
3156                                 compatible = "snps,dwc3";
3157                                 reg = <0x0 0x0a600000 0x0 0xcd00>;
3158                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3159                                 iommus = <&apps_smmu 0x40 0x0>;
3160                                 snps,dis_u2_susphy_quirk;
3161                                 snps,dis_enblslpm_quirk;
3162                                 snps,usb3_lpm_capable;
3163                                 phys = <&usb_1_hsphy>,
3164                                        <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>;
3165                                 phy-names = "usb2-phy", "usb3-phy";
3166
3167                                 ports {
3168                                         #address-cells = <1>;
3169                                         #size-cells = <0>;
3170
3171                                         port@0 {
3172                                                 reg = <0>;
3173
3174                                                 usb_1_dwc3_hs: endpoint {
3175                                                 };
3176                                         };
3177
3178                                         port@1 {
3179                                                 reg = <1>;
3180
3181                                                 usb_1_dwc3_ss: endpoint {
3182                                                 };
3183                                         };
3184                                 };
3185                         };
3186                 };
3187
3188                 pdc: interrupt-controller@b220000 {
3189                         compatible = "qcom,sm8550-pdc", "qcom,pdc";
3190                         reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
3191                         qcom,pdc-ranges = <0 480 94>, <94 609 31>,
3192                                           <125 63 1>, <126 716 12>,
3193                                           <138 251 5>;
3194                         #interrupt-cells = <2>;
3195                         interrupt-parent = <&intc>;
3196                         interrupt-controller;
3197                 };
3198
3199                 tsens0: thermal-sensor@c271000 {
3200                         compatible = "qcom,sm8550-tsens", "qcom,tsens-v2";
3201                         reg = <0 0x0c271000 0 0x1000>, /* TM */
3202                               <0 0x0c222000 0 0x1000>; /* SROT */
3203                         #qcom,sensors = <16>;
3204                         interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3205                                      <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>;
3206                         interrupt-names = "uplow", "critical";
3207                         #thermal-sensor-cells = <1>;
3208                 };
3209
3210                 tsens1: thermal-sensor@c272000 {
3211                         compatible = "qcom,sm8550-tsens", "qcom,tsens-v2";
3212                         reg = <0 0x0c272000 0 0x1000>, /* TM */
3213                               <0 0x0c223000 0 0x1000>; /* SROT */
3214                         #qcom,sensors = <16>;
3215                         interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
3216                                      <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>;
3217                         interrupt-names = "uplow", "critical";
3218                         #thermal-sensor-cells = <1>;
3219                 };
3220
3221                 tsens2: thermal-sensor@c273000 {
3222                         compatible = "qcom,sm8550-tsens", "qcom,tsens-v2";
3223                         reg = <0 0x0c273000 0 0x1000>, /* TM */
3224                               <0 0x0c224000 0 0x1000>; /* SROT */
3225                         #qcom,sensors = <16>;
3226                         interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>,
3227                                      <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>;
3228                         interrupt-names = "uplow", "critical";
3229                         #thermal-sensor-cells = <1>;
3230                 };
3231
3232                 aoss_qmp: power-management@c300000 {
3233                         compatible = "qcom,sm8550-aoss-qmp", "qcom,aoss-qmp";
3234                         reg = <0 0x0c300000 0 0x400>;
3235                         interrupt-parent = <&ipcc>;
3236                         interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
3237                                                      IRQ_TYPE_EDGE_RISING>;
3238                         mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
3239
3240                         #clock-cells = <0>;
3241                 };
3242
3243                 sram@c3f0000 {
3244                         compatible = "qcom,rpmh-stats";
3245                         reg = <0 0x0c3f0000 0 0x400>;
3246                 };
3247
3248                 spmi_bus: spmi@c400000 {
3249                         compatible = "qcom,spmi-pmic-arb";
3250                         reg = <0 0x0c400000 0 0x3000>,
3251                               <0 0x0c500000 0 0x4000000>,
3252                               <0 0x0c440000 0 0x80000>,
3253                               <0 0x0c4c0000 0 0x20000>,
3254                               <0 0x0c42d000 0 0x4000>;
3255                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3256                         interrupt-names = "periph_irq";
3257                         interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3258                         qcom,ee = <0>;
3259                         qcom,channel = <0>;
3260                         qcom,bus-id = <0>;
3261                         #address-cells = <2>;
3262                         #size-cells = <0>;
3263                         interrupt-controller;
3264                         #interrupt-cells = <4>;
3265                 };
3266
3267                 tlmm: pinctrl@f100000 {
3268                         compatible = "qcom,sm8550-tlmm";
3269                         reg = <0 0x0f100000 0 0x300000>;
3270                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
3271                         gpio-controller;
3272                         #gpio-cells = <2>;
3273                         interrupt-controller;
3274                         #interrupt-cells = <2>;
3275                         gpio-ranges = <&tlmm 0 0 211>;
3276                         wakeup-parent = <&pdc>;
3277
3278                         hub_i2c0_data_clk: hub-i2c0-data-clk-state {
3279                                 /* SDA, SCL */
3280                                 pins = "gpio16", "gpio17";
3281                                 function = "i2chub0_se0";
3282                                 drive-strength = <2>;
3283                                 bias-pull-up;
3284                         };
3285
3286                         hub_i2c1_data_clk: hub-i2c1-data-clk-state {
3287                                 /* SDA, SCL */
3288                                 pins = "gpio18", "gpio19";
3289                                 function = "i2chub0_se1";
3290                                 drive-strength = <2>;
3291                                 bias-pull-up;
3292                         };
3293
3294                         hub_i2c2_data_clk: hub-i2c2-data-clk-state {
3295                                 /* SDA, SCL */
3296                                 pins = "gpio20", "gpio21";
3297                                 function = "i2chub0_se2";
3298                                 drive-strength = <2>;
3299                                 bias-pull-up;
3300                         };
3301
3302                         hub_i2c3_data_clk: hub-i2c3-data-clk-state {
3303                                 /* SDA, SCL */
3304                                 pins = "gpio22", "gpio23";
3305                                 function = "i2chub0_se3";
3306                                 drive-strength = <2>;
3307                                 bias-pull-up;
3308                         };
3309
3310                         hub_i2c4_data_clk: hub-i2c4-data-clk-state {
3311                                 /* SDA, SCL */
3312                                 pins = "gpio4", "gpio5";
3313                                 function = "i2chub0_se4";
3314                                 drive-strength = <2>;
3315                                 bias-pull-up;
3316                         };
3317
3318                         hub_i2c5_data_clk: hub-i2c5-data-clk-state {
3319                                 /* SDA, SCL */
3320                                 pins = "gpio6", "gpio7";
3321                                 function = "i2chub0_se5";
3322                                 drive-strength = <2>;
3323                                 bias-pull-up;
3324                         };
3325
3326                         hub_i2c6_data_clk: hub-i2c6-data-clk-state {
3327                                 /* SDA, SCL */
3328                                 pins = "gpio8", "gpio9";
3329                                 function = "i2chub0_se6";
3330                                 drive-strength = <2>;
3331                                 bias-pull-up;
3332                         };
3333
3334                         hub_i2c7_data_clk: hub-i2c7-data-clk-state {
3335                                 /* SDA, SCL */
3336                                 pins = "gpio10", "gpio11";
3337                                 function = "i2chub0_se7";
3338                                 drive-strength = <2>;
3339                                 bias-pull-up;
3340                         };
3341
3342                         hub_i2c8_data_clk: hub-i2c8-data-clk-state {
3343                                 /* SDA, SCL */
3344                                 pins = "gpio206", "gpio207";
3345                                 function = "i2chub0_se8";
3346                                 drive-strength = <2>;
3347                                 bias-pull-up;
3348                         };
3349
3350                         hub_i2c9_data_clk: hub-i2c9-data-clk-state {
3351                                 /* SDA, SCL */
3352                                 pins = "gpio84", "gpio85";
3353                                 function = "i2chub0_se9";
3354                                 drive-strength = <2>;
3355                                 bias-pull-up;
3356                         };
3357
3358                         pcie0_default_state: pcie0-default-state {
3359                                 perst-pins {
3360                                         pins = "gpio94";
3361                                         function = "gpio";
3362                                         drive-strength = <2>;
3363                                         bias-pull-down;
3364                                 };
3365
3366                                 clkreq-pins {
3367                                         pins = "gpio95";
3368                                         function = "pcie0_clk_req_n";
3369                                         drive-strength = <2>;
3370                                         bias-pull-up;
3371                                 };
3372
3373                                 wake-pins {
3374                                         pins = "gpio96";
3375                                         function = "gpio";
3376                                         drive-strength = <2>;
3377                                         bias-pull-up;
3378                                 };
3379                         };
3380
3381                         pcie1_default_state: pcie1-default-state {
3382                                 perst-pins {
3383                                         pins = "gpio97";
3384                                         function = "gpio";
3385                                         drive-strength = <2>;
3386                                         bias-pull-down;
3387                                 };
3388
3389                                 clkreq-pins {
3390                                         pins = "gpio98";
3391                                         function = "pcie1_clk_req_n";
3392                                         drive-strength = <2>;
3393                                         bias-pull-up;
3394                                 };
3395
3396                                 wake-pins {
3397                                         pins = "gpio99";
3398                                         function = "gpio";
3399                                         drive-strength = <2>;
3400                                         bias-pull-up;
3401                                 };
3402                         };
3403
3404                         qup_i2c0_data_clk: qup-i2c0-data-clk-state {
3405                                 /* SDA, SCL */
3406                                 pins = "gpio28", "gpio29";
3407                                 function = "qup1_se0";
3408                                 drive-strength = <2>;
3409                                 bias-pull-up = <2200>;
3410                         };
3411
3412                         qup_i2c1_data_clk: qup-i2c1-data-clk-state {
3413                                 /* SDA, SCL */
3414                                 pins = "gpio32", "gpio33";
3415                                 function = "qup1_se1";
3416                                 drive-strength = <2>;
3417                                 bias-pull-up = <2200>;
3418                         };
3419
3420                         qup_i2c2_data_clk: qup-i2c2-data-clk-state {
3421                                 /* SDA, SCL */
3422                                 pins = "gpio36", "gpio37";
3423                                 function = "qup1_se2";
3424                                 drive-strength = <2>;
3425                                 bias-pull-up = <2200>;
3426                         };
3427
3428                         qup_i2c3_data_clk: qup-i2c3-data-clk-state {
3429                                 /* SDA, SCL */
3430                                 pins = "gpio40", "gpio41";
3431                                 function = "qup1_se3";
3432                                 drive-strength = <2>;
3433                                 bias-pull-up = <2200>;
3434                         };
3435
3436                         qup_i2c4_data_clk: qup-i2c4-data-clk-state {
3437                                 /* SDA, SCL */
3438                                 pins = "gpio44", "gpio45";
3439                                 function = "qup1_se4";
3440                                 drive-strength = <2>;
3441                                 bias-pull-up = <2200>;
3442                         };
3443
3444                         qup_i2c5_data_clk: qup-i2c5-data-clk-state {
3445                                 /* SDA, SCL */
3446                                 pins = "gpio52", "gpio53";
3447                                 function = "qup1_se5";
3448                                 drive-strength = <2>;
3449                                 bias-pull-up = <2200>;
3450                         };
3451
3452                         qup_i2c6_data_clk: qup-i2c6-data-clk-state {
3453                                 /* SDA, SCL */
3454                                 pins = "gpio48", "gpio49";
3455                                 function = "qup1_se6";
3456                                 drive-strength = <2>;
3457                                 bias-pull-up = <2200>;
3458                         };
3459
3460                         qup_i2c8_data_clk: qup-i2c8-data-clk-state {
3461                                 scl-pins {
3462                                         pins = "gpio57";
3463                                         function = "qup2_se0_l1_mira";
3464                                         drive-strength = <2>;
3465                                         bias-pull-up = <2200>;
3466                                 };
3467
3468                                 sda-pins {
3469                                         pins = "gpio56";
3470                                         function = "qup2_se0_l0_mira";
3471                                         drive-strength = <2>;
3472                                         bias-pull-up = <2200>;
3473                                 };
3474                         };
3475
3476                         qup_i2c9_data_clk: qup-i2c9-data-clk-state {
3477                                 /* SDA, SCL */
3478                                 pins = "gpio60", "gpio61";
3479                                 function = "qup2_se1";
3480                                 drive-strength = <2>;
3481                                 bias-pull-up = <2200>;
3482                         };
3483
3484                         qup_i2c10_data_clk: qup-i2c10-data-clk-state {
3485                                 /* SDA, SCL */
3486                                 pins = "gpio64", "gpio65";
3487                                 function = "qup2_se2";
3488                                 drive-strength = <2>;
3489                                 bias-pull-up = <2200>;
3490                         };
3491
3492                         qup_i2c11_data_clk: qup-i2c11-data-clk-state {
3493                                 /* SDA, SCL */
3494                                 pins = "gpio68", "gpio69";
3495                                 function = "qup2_se3";
3496                                 drive-strength = <2>;
3497                                 bias-pull-up = <2200>;
3498                         };
3499
3500                         qup_i2c12_data_clk: qup-i2c12-data-clk-state {
3501                                 /* SDA, SCL */
3502                                 pins = "gpio2", "gpio3";
3503                                 function = "qup2_se4";
3504                                 drive-strength = <2>;
3505                                 bias-pull-up = <2200>;
3506                         };
3507
3508                         qup_i2c13_data_clk: qup-i2c13-data-clk-state {
3509                                 /* SDA, SCL */
3510                                 pins = "gpio80", "gpio81";
3511                                 function = "qup2_se5";
3512                                 drive-strength = <2>;
3513                                 bias-pull-up = <2200>;
3514                         };
3515
3516                         qup_i2c15_data_clk: qup-i2c15-data-clk-state {
3517                                 /* SDA, SCL */
3518                                 pins = "gpio72", "gpio106";
3519                                 function = "qup2_se7";
3520                                 drive-strength = <2>;
3521                                 bias-pull-up = <2200>;
3522                         };
3523
3524                         qup_spi0_cs: qup-spi0-cs-state {
3525                                 pins = "gpio31";
3526                                 function = "qup1_se0";
3527                                 drive-strength = <6>;
3528                                 bias-disable;
3529                         };
3530
3531                         qup_spi0_data_clk: qup-spi0-data-clk-state {
3532                                 /* MISO, MOSI, CLK */
3533                                 pins = "gpio28", "gpio29", "gpio30";
3534                                 function = "qup1_se0";
3535                                 drive-strength = <6>;
3536                                 bias-disable;
3537                         };
3538
3539                         qup_spi1_cs: qup-spi1-cs-state {
3540                                 pins = "gpio35";
3541                                 function = "qup1_se1";
3542                                 drive-strength = <6>;
3543                                 bias-disable;
3544                         };
3545
3546                         qup_spi1_data_clk: qup-spi1-data-clk-state {
3547                                 /* MISO, MOSI, CLK */
3548                                 pins = "gpio32", "gpio33", "gpio34";
3549                                 function = "qup1_se1";
3550                                 drive-strength = <6>;
3551                                 bias-disable;
3552                         };
3553
3554                         qup_spi2_cs: qup-spi2-cs-state {
3555                                 pins = "gpio39";
3556                                 function = "qup1_se2";
3557                                 drive-strength = <6>;
3558                                 bias-disable;
3559                         };
3560
3561                         qup_spi2_data_clk: qup-spi2-data-clk-state {
3562                                 /* MISO, MOSI, CLK */
3563                                 pins = "gpio36", "gpio37", "gpio38";
3564                                 function = "qup1_se2";
3565                                 drive-strength = <6>;
3566                                 bias-disable;
3567                         };
3568
3569                         qup_spi3_cs: qup-spi3-cs-state {
3570                                 pins = "gpio43";
3571                                 function = "qup1_se3";
3572                                 drive-strength = <6>;
3573                                 bias-disable;
3574                         };
3575
3576                         qup_spi3_data_clk: qup-spi3-data-clk-state {
3577                                 /* MISO, MOSI, CLK */
3578                                 pins = "gpio40", "gpio41", "gpio42";
3579                                 function = "qup1_se3";
3580                                 drive-strength = <6>;
3581                                 bias-disable;
3582                         };
3583
3584                         qup_spi4_cs: qup-spi4-cs-state {
3585                                 pins = "gpio47";
3586                                 function = "qup1_se4";
3587                                 drive-strength = <6>;
3588                                 bias-disable;
3589                         };
3590
3591                         qup_spi4_data_clk: qup-spi4-data-clk-state {
3592                                 /* MISO, MOSI, CLK */
3593                                 pins = "gpio44", "gpio45", "gpio46";
3594                                 function = "qup1_se4";
3595                                 drive-strength = <6>;
3596                                 bias-disable;
3597                         };
3598
3599                         qup_spi5_cs: qup-spi5-cs-state {
3600                                 pins = "gpio55";
3601                                 function = "qup1_se5";
3602                                 drive-strength = <6>;
3603                                 bias-disable;
3604                         };
3605
3606                         qup_spi5_data_clk: qup-spi5-data-clk-state {
3607                                 /* MISO, MOSI, CLK */
3608                                 pins = "gpio52", "gpio53", "gpio54";
3609                                 function = "qup1_se5";
3610                                 drive-strength = <6>;
3611                                 bias-disable;
3612                         };
3613
3614                         qup_spi6_cs: qup-spi6-cs-state {
3615                                 pins = "gpio51";
3616                                 function = "qup1_se6";
3617                                 drive-strength = <6>;
3618                                 bias-disable;
3619                         };
3620
3621                         qup_spi6_data_clk: qup-spi6-data-clk-state {
3622                                 /* MISO, MOSI, CLK */
3623                                 pins = "gpio48", "gpio49", "gpio50";
3624                                 function = "qup1_se6";
3625                                 drive-strength = <6>;
3626                                 bias-disable;
3627                         };
3628
3629                         qup_spi8_cs: qup-spi8-cs-state {
3630                                 pins = "gpio59";
3631                                 function = "qup2_se0_l3_mira";
3632                                 drive-strength = <6>;
3633                                 bias-disable;
3634                         };
3635
3636                         qup_spi8_data_clk: qup-spi8-data-clk-state {
3637                                 /* MISO, MOSI, CLK */
3638                                 pins = "gpio56", "gpio57", "gpio58";
3639                                 function = "qup2_se0_l2_mira";
3640                                 drive-strength = <6>;
3641                                 bias-disable;
3642                         };
3643
3644                         qup_spi9_cs: qup-spi9-cs-state {
3645                                 pins = "gpio63";
3646                                 function = "qup2_se1";
3647                                 drive-strength = <6>;
3648                                 bias-disable;
3649                         };
3650
3651                         qup_spi9_data_clk: qup-spi9-data-clk-state {
3652                                 /* MISO, MOSI, CLK */
3653                                 pins = "gpio60", "gpio61", "gpio62";
3654                                 function = "qup2_se1";
3655                                 drive-strength = <6>;
3656                                 bias-disable;
3657                         };
3658
3659                         qup_spi10_cs: qup-spi10-cs-state {
3660                                 pins = "gpio67";
3661                                 function = "qup2_se2";
3662                                 drive-strength = <6>;
3663                                 bias-disable;
3664                         };
3665
3666                         qup_spi10_data_clk: qup-spi10-data-clk-state {
3667                                 /* MISO, MOSI, CLK */
3668                                 pins = "gpio64", "gpio65", "gpio66";
3669                                 function = "qup2_se2";
3670                                 drive-strength = <6>;
3671                                 bias-disable;
3672                         };
3673
3674                         qup_spi11_cs: qup-spi11-cs-state {
3675                                 pins = "gpio71";
3676                                 function = "qup2_se3";
3677                                 drive-strength = <6>;
3678                                 bias-disable;
3679                         };
3680
3681                         qup_spi11_data_clk: qup-spi11-data-clk-state {
3682                                 /* MISO, MOSI, CLK */
3683                                 pins = "gpio68", "gpio69", "gpio70";
3684                                 function = "qup2_se3";
3685                                 drive-strength = <6>;
3686                                 bias-disable;
3687                         };
3688
3689                         qup_spi12_cs: qup-spi12-cs-state {
3690                                 pins = "gpio119";
3691                                 function = "qup2_se4";
3692                                 drive-strength = <6>;
3693                                 bias-disable;
3694                         };
3695
3696                         qup_spi12_data_clk: qup-spi12-data-clk-state {
3697                                 /* MISO, MOSI, CLK */
3698                                 pins = "gpio2", "gpio3", "gpio118";
3699                                 function = "qup2_se4";
3700                                 drive-strength = <6>;
3701                                 bias-disable;
3702                         };
3703
3704                         qup_spi13_cs: qup-spi13-cs-state {
3705                                 pins = "gpio83";
3706                                 function = "qup2_se5";
3707                                 drive-strength = <6>;
3708                                 bias-disable;
3709                         };
3710
3711                         qup_spi13_data_clk: qup-spi13-data-clk-state {
3712                                 /* MISO, MOSI, CLK */
3713                                 pins = "gpio80", "gpio81", "gpio82";
3714                                 function = "qup2_se5";
3715                                 drive-strength = <6>;
3716                                 bias-disable;
3717                         };
3718
3719                         qup_spi15_cs: qup-spi15-cs-state {
3720                                 pins = "gpio75";
3721                                 function = "qup2_se7";
3722                                 drive-strength = <6>;
3723                                 bias-disable;
3724                         };
3725
3726                         qup_spi15_data_clk: qup-spi15-data-clk-state {
3727                                 /* MISO, MOSI, CLK */
3728                                 pins = "gpio72", "gpio106", "gpio74";
3729                                 function = "qup2_se7";
3730                                 drive-strength = <6>;
3731                                 bias-disable;
3732                         };
3733
3734                         qup_uart7_default: qup-uart7-default-state {
3735                                 /* TX, RX */
3736                                 pins = "gpio26", "gpio27";
3737                                 function = "qup1_se7";
3738                                 drive-strength = <2>;
3739                                 bias-disable;
3740                         };
3741
3742                         qup_uart14_default: qup-uart14-default-state {
3743                                 /* TX, RX */
3744                                 pins = "gpio78", "gpio79";
3745                                 function = "qup2_se6";
3746                                 drive-strength = <2>;
3747                                 bias-pull-up;
3748                         };
3749
3750                         qup_uart14_cts_rts: qup-uart14-cts-rts-state {
3751                                 /* CTS, RTS */
3752                                 pins = "gpio76", "gpio77";
3753                                 function = "qup2_se6";
3754                                 drive-strength = <2>;
3755                                 bias-pull-down;
3756                         };
3757
3758                         sdc2_sleep: sdc2-sleep-state {
3759                                 clk-pins {
3760                                         pins = "sdc2_clk";
3761                                         bias-disable;
3762                                         drive-strength = <2>;
3763                                 };
3764
3765                                 cmd-pins {
3766                                         pins = "sdc2_cmd";
3767                                         bias-pull-up;
3768                                         drive-strength = <2>;
3769                                 };
3770
3771                                 data-pins {
3772                                         pins = "sdc2_data";
3773                                         bias-pull-up;
3774                                         drive-strength = <2>;
3775                                 };
3776                         };
3777
3778                         sdc2_default: sdc2-default-state {
3779                                 clk-pins {
3780                                         pins = "sdc2_clk";
3781                                         bias-disable;
3782                                         drive-strength = <16>;
3783                                 };
3784
3785                                 cmd-pins {
3786                                         pins = "sdc2_cmd";
3787                                         bias-pull-up;
3788                                         drive-strength = <10>;
3789                                 };
3790
3791                                 data-pins {
3792                                         pins = "sdc2_data";
3793                                         bias-pull-up;
3794                                         drive-strength = <10>;
3795                                 };
3796                         };
3797                 };
3798
3799                 apps_smmu: iommu@15000000 {
3800                         compatible = "qcom,sm8550-smmu-500", "qcom,smmu-500", "arm,mmu-500";
3801                         reg = <0 0x15000000 0 0x100000>;
3802                         #iommu-cells = <2>;
3803                         #global-interrupts = <1>;
3804                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
3805                                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
3806                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
3807                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
3808                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
3809                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
3810                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3811                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3812                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3813                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3814                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3815                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3816                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3817                                      <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3818                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3819                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3820                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3821                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3822                                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3823                                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3824                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3825                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3826                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3827                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3828                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3829                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3830                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3831                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3832                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3833                                      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3834                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3835                                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3836                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3837                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3838                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3839                                      <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3840                                      <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3841                                      <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3842                                      <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3843                                      <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3844                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3845                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3846                                      <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3847                                      <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3848                                      <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3849                                      <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3850                                      <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3851                                      <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3852                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3853                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3854                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3855                                      <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3856                                      <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3857                                      <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3858                                      <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3859                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3860                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3861                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3862                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3863                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3864                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3865                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3866                                      <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3867                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
3868                                      <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
3869                                      <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
3870                                      <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
3871                                      <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
3872                                      <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
3873                                      <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
3874                                      <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
3875                                      <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
3876                                      <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
3877                                      <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
3878                                      <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
3879                                      <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
3880                                      <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
3881                                      <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
3882                                      <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
3883                                      <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
3884                                      <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
3885                                      <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
3886                                      <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
3887                                      <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
3888                                      <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
3889                                      <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
3890                                      <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
3891                                      <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
3892                                      <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
3893                                      <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
3894                                      <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
3895                                      <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
3896                                      <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
3897                                      <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
3898                                      <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
3899                                      <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
3900                                      <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>;
3901                 };
3902
3903                 intc: interrupt-controller@17100000 {
3904                         compatible = "arm,gic-v3";
3905                         reg = <0 0x17100000 0 0x10000>,         /* GICD */
3906                               <0 0x17180000 0 0x200000>;        /* GICR * 8 */
3907                         ranges;
3908                         #interrupt-cells = <3>;
3909                         interrupt-controller;
3910                         #redistributor-regions = <1>;
3911                         redistributor-stride = <0 0x40000>;
3912                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
3913                         #address-cells = <2>;
3914                         #size-cells = <2>;
3915
3916                         gic_its: msi-controller@17140000 {
3917                                 compatible = "arm,gic-v3-its";
3918                                 reg = <0 0x17140000 0 0x20000>;
3919                                 msi-controller;
3920                                 #msi-cells = <1>;
3921                         };
3922                 };
3923
3924                 timer@17420000 {
3925                         compatible = "arm,armv7-timer-mem";
3926                         reg = <0 0x17420000 0 0x1000>;
3927                         ranges = <0 0 0 0x20000000>;
3928                         #address-cells = <1>;
3929                         #size-cells = <1>;
3930
3931                         frame@17421000 {
3932                                 reg = <0x17421000 0x1000>,
3933                                       <0x17422000 0x1000>;
3934                                 frame-number = <0>;
3935                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3936                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
3937                         };
3938
3939                         frame@17423000 {
3940                                 reg = <0x17423000 0x1000>;
3941                                 frame-number = <1>;
3942                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3943                                 status = "disabled";
3944                         };
3945
3946                         frame@17425000 {
3947                                 reg = <0x17425000 0x1000>;
3948                                 frame-number = <2>;
3949                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3950                                 status = "disabled";
3951                         };
3952
3953                         frame@17427000 {
3954                                 reg = <0x17427000 0x1000>;
3955                                 frame-number = <3>;
3956                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3957                                 status = "disabled";
3958                         };
3959
3960                         frame@17429000 {
3961                                 reg = <0x17429000 0x1000>;
3962                                 frame-number = <4>;
3963                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3964                                 status = "disabled";
3965                         };
3966
3967                         frame@1742b000 {
3968                                 reg = <0x1742b000 0x1000>;
3969                                 frame-number = <5>;
3970                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3971                                 status = "disabled";
3972                         };
3973
3974                         frame@1742d000 {
3975                                 reg = <0x1742d000 0x1000>;
3976                                 frame-number = <6>;
3977                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3978                                 status = "disabled";
3979                         };
3980                 };
3981
3982                 apps_rsc: rsc@17a00000 {
3983                         label = "apps_rsc";
3984                         compatible = "qcom,rpmh-rsc";
3985                         reg = <0 0x17a00000 0 0x10000>,
3986                               <0 0x17a10000 0 0x10000>,
3987                               <0 0x17a20000 0 0x10000>,
3988                               <0 0x17a30000 0 0x10000>;
3989                         reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
3990                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
3991                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
3992                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
3993                         qcom,tcs-offset = <0xd00>;
3994                         qcom,drv-id = <2>;
3995                         qcom,tcs-config = <ACTIVE_TCS    3>, <SLEEP_TCS     2>,
3996                                           <WAKE_TCS      2>, <CONTROL_TCS   0>;
3997                         power-domains = <&CLUSTER_PD>;
3998
3999                         apps_bcm_voter: bcm-voter {
4000                                 compatible = "qcom,bcm-voter";
4001                         };
4002
4003                         rpmhcc: clock-controller {
4004                                 compatible = "qcom,sm8550-rpmh-clk";
4005                                 #clock-cells = <1>;
4006                                 clock-names = "xo";
4007                                 clocks = <&xo_board>;
4008                         };
4009
4010                         rpmhpd: power-controller {
4011                                 compatible = "qcom,sm8550-rpmhpd";
4012                                 #power-domain-cells = <1>;
4013                                 operating-points-v2 = <&rpmhpd_opp_table>;
4014
4015                                 rpmhpd_opp_table: opp-table {
4016                                         compatible = "operating-points-v2";
4017
4018                                         rpmhpd_opp_ret: opp-16 {
4019                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4020                                         };
4021
4022                                         rpmhpd_opp_min_svs: opp-48 {
4023                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4024                                         };
4025
4026                                         rpmhpd_opp_low_svs_d2: opp-52 {
4027                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
4028                                         };
4029
4030                                         rpmhpd_opp_low_svs_d1: opp-56 {
4031                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
4032                                         };
4033
4034                                         rpmhpd_opp_low_svs_d0: opp-60 {
4035                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
4036                                         };
4037
4038                                         rpmhpd_opp_low_svs: opp-64 {
4039                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4040                                         };
4041
4042                                         rpmhpd_opp_low_svs_l1: opp-80 {
4043                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
4044                                         };
4045
4046                                         rpmhpd_opp_svs: opp-128 {
4047                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4048                                         };
4049
4050                                         rpmhpd_opp_svs_l0: opp-144 {
4051                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
4052                                         };
4053
4054                                         rpmhpd_opp_svs_l1: opp-192 {
4055                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4056                                         };
4057
4058                                         rpmhpd_opp_nom: opp-256 {
4059                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4060                                         };
4061
4062                                         rpmhpd_opp_nom_l1: opp-320 {
4063                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4064                                         };
4065
4066                                         rpmhpd_opp_nom_l2: opp-336 {
4067                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4068                                         };
4069
4070                                         rpmhpd_opp_turbo: opp-384 {
4071                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4072                                         };
4073
4074                                         rpmhpd_opp_turbo_l1: opp-416 {
4075                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4076                                         };
4077                                 };
4078                         };
4079                 };
4080
4081                 cpufreq_hw: cpufreq@17d91000 {
4082                         compatible = "qcom,sm8550-cpufreq-epss", "qcom,cpufreq-epss";
4083                         reg = <0 0x17d91000 0 0x1000>,
4084                               <0 0x17d92000 0 0x1000>,
4085                               <0 0x17d93000 0 0x1000>;
4086                         reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
4087                         clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>;
4088                         clock-names = "xo", "alternate";
4089                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
4090                                      <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
4091                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
4092                         interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
4093                         #freq-domain-cells = <1>;
4094                         #clock-cells = <1>;
4095                 };
4096
4097                 pmu@24091000 {
4098                         compatible = "qcom,sm8550-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
4099                         reg = <0 0x24091000 0 0x1000>;
4100                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
4101                         interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>;
4102
4103                         operating-points-v2 = <&llcc_bwmon_opp_table>;
4104
4105                         llcc_bwmon_opp_table: opp-table {
4106                                 compatible = "operating-points-v2";
4107
4108                                 opp-0 {
4109                                         opp-peak-kBps = <2086000>;
4110                                 };
4111
4112                                 opp-1 {
4113                                         opp-peak-kBps = <2929000>;
4114                                 };
4115
4116                                 opp-2 {
4117                                         opp-peak-kBps = <5931000>;
4118                                 };
4119
4120                                 opp-3 {
4121                                         opp-peak-kBps = <6515000>;
4122                                 };
4123
4124                                 opp-4 {
4125                                         opp-peak-kBps = <7980000>;
4126                                 };
4127
4128                                 opp-5 {
4129                                         opp-peak-kBps = <10437000>;
4130                                 };
4131
4132                                 opp-6 {
4133                                         opp-peak-kBps = <12157000>;
4134                                 };
4135
4136                                 opp-7 {
4137                                         opp-peak-kBps = <14060000>;
4138                                 };
4139
4140                                 opp-8 {
4141                                         opp-peak-kBps = <16113000>;
4142                                 };
4143                         };
4144                 };
4145
4146                 pmu@240b6400 {
4147                         compatible = "qcom,sm8550-cpu-bwmon", "qcom,sdm845-bwmon";
4148                         reg = <0 0x240b6400 0 0x600>;
4149                         interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
4150                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>;
4151
4152                         operating-points-v2 = <&cpu_bwmon_opp_table>;
4153
4154                         cpu_bwmon_opp_table: opp-table {
4155                                 compatible = "operating-points-v2";
4156
4157                                 opp-0 {
4158                                         opp-peak-kBps = <4577000>;
4159                                 };
4160
4161                                 opp-1 {
4162                                         opp-peak-kBps = <7110000>;
4163                                 };
4164
4165                                 opp-2 {
4166                                         opp-peak-kBps = <9155000>;
4167                                 };
4168
4169                                 opp-3 {
4170                                         opp-peak-kBps = <12298000>;
4171                                 };
4172
4173                                 opp-4 {
4174                                         opp-peak-kBps = <14236000>;
4175                                 };
4176
4177                                 opp-5 {
4178                                         opp-peak-kBps = <16265000>;
4179                                 };
4180                         };
4181                 };
4182
4183                 gem_noc: interconnect@24100000 {
4184                         compatible = "qcom,sm8550-gem-noc";
4185                         reg = <0 0x24100000 0 0xbb800>;
4186                         #interconnect-cells = <2>;
4187                         qcom,bcm-voters = <&apps_bcm_voter>;
4188                 };
4189
4190                 system-cache-controller@25000000 {
4191                         compatible = "qcom,sm8550-llcc";
4192                         reg = <0 0x25000000 0 0x200000>,
4193                               <0 0x25200000 0 0x200000>,
4194                               <0 0x25400000 0 0x200000>,
4195                               <0 0x25600000 0 0x200000>,
4196                               <0 0x25800000 0 0x200000>;
4197                         reg-names = "llcc0_base",
4198                                     "llcc1_base",
4199                                     "llcc2_base",
4200                                     "llcc3_base",
4201                                     "llcc_broadcast_base";
4202                         interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
4203                 };
4204
4205                 remoteproc_adsp: remoteproc@30000000 {
4206                         compatible = "qcom,sm8550-adsp-pas";
4207                         reg = <0x0 0x30000000 0x0 0x100>;
4208
4209                         interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
4210                                               <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
4211                                               <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
4212                                               <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
4213                                               <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
4214                         interrupt-names = "wdog", "fatal", "ready",
4215                                           "handover", "stop-ack";
4216
4217                         clocks = <&rpmhcc RPMH_CXO_CLK>;
4218                         clock-names = "xo";
4219
4220                         power-domains = <&rpmhpd RPMHPD_LCX>,
4221                                         <&rpmhpd RPMHPD_LMX>;
4222                         power-domain-names = "lcx", "lmx";
4223
4224                         interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>;
4225
4226                         memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>;
4227
4228                         qcom,qmp = <&aoss_qmp>;
4229
4230                         qcom,smem-states = <&smp2p_adsp_out 0>;
4231                         qcom,smem-state-names = "stop";
4232
4233                         status = "disabled";
4234
4235                         remoteproc_adsp_glink: glink-edge {
4236                                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
4237                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
4238                                                              IRQ_TYPE_EDGE_RISING>;
4239                                 mboxes = <&ipcc IPCC_CLIENT_LPASS
4240                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
4241
4242                                 label = "lpass";
4243                                 qcom,remote-pid = <2>;
4244
4245                                 fastrpc {
4246                                         compatible = "qcom,fastrpc";
4247                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
4248                                         label = "adsp";
4249                                         #address-cells = <1>;
4250                                         #size-cells = <0>;
4251
4252                                         compute-cb@3 {
4253                                                 compatible = "qcom,fastrpc-compute-cb";
4254                                                 reg = <3>;
4255                                                 iommus = <&apps_smmu 0x1003 0x80>,
4256                                                          <&apps_smmu 0x1063 0x0>;
4257                                         };
4258
4259                                         compute-cb@4 {
4260                                                 compatible = "qcom,fastrpc-compute-cb";
4261                                                 reg = <4>;
4262                                                 iommus = <&apps_smmu 0x1004 0x80>,
4263                                                          <&apps_smmu 0x1064 0x0>;
4264                                         };
4265
4266                                         compute-cb@5 {
4267                                                 compatible = "qcom,fastrpc-compute-cb";
4268                                                 reg = <5>;
4269                                                 iommus = <&apps_smmu 0x1005 0x80>,
4270                                                          <&apps_smmu 0x1065 0x0>;
4271                                         };
4272
4273                                         compute-cb@6 {
4274                                                 compatible = "qcom,fastrpc-compute-cb";
4275                                                 reg = <6>;
4276                                                 iommus = <&apps_smmu 0x1006 0x80>,
4277                                                          <&apps_smmu 0x1066 0x0>;
4278                                         };
4279
4280                                         compute-cb@7 {
4281                                                 compatible = "qcom,fastrpc-compute-cb";
4282                                                 reg = <7>;
4283                                                 iommus = <&apps_smmu 0x1007 0x80>,
4284                                                          <&apps_smmu 0x1067 0x0>;
4285                                         };
4286                                 };
4287
4288                                 gpr {
4289                                         compatible = "qcom,gpr";
4290                                         qcom,glink-channels = "adsp_apps";
4291                                         qcom,domain = <GPR_DOMAIN_ID_ADSP>;
4292                                         qcom,intents = <512 20>;
4293                                         #address-cells = <1>;
4294                                         #size-cells = <0>;
4295
4296                                         q6apm: service@1 {
4297                                                 compatible = "qcom,q6apm";
4298                                                 reg = <GPR_APM_MODULE_IID>;
4299                                                 #sound-dai-cells = <0>;
4300                                                 qcom,protection-domain = "avs/audio",
4301                                                                          "msm/adsp/audio_pd";
4302
4303                                                 q6apmdai: dais {
4304                                                         compatible = "qcom,q6apm-dais";
4305                                                         iommus = <&apps_smmu 0x1001 0x80>,
4306                                                                  <&apps_smmu 0x1061 0x0>;
4307                                                 };
4308
4309                                                 q6apmbedai: bedais {
4310                                                         compatible = "qcom,q6apm-lpass-dais";
4311                                                         #sound-dai-cells = <1>;
4312                                                 };
4313                                         };
4314
4315                                         q6prm: service@2 {
4316                                                 compatible = "qcom,q6prm";
4317                                                 reg = <GPR_PRM_MODULE_IID>;
4318                                                 qcom,protection-domain = "avs/audio",
4319                                                                          "msm/adsp/audio_pd";
4320
4321                                                 q6prmcc: clock-controller {
4322                                                         compatible = "qcom,q6prm-lpass-clocks";
4323                                                         #clock-cells = <2>;
4324                                                 };
4325                                         };
4326                                 };
4327                         };
4328                 };
4329
4330                 nsp_noc: interconnect@320c0000 {
4331                         compatible = "qcom,sm8550-nsp-noc";
4332                         reg = <0 0x320c0000 0 0xe080>;
4333                         #interconnect-cells = <2>;
4334                         qcom,bcm-voters = <&apps_bcm_voter>;
4335                 };
4336
4337                 remoteproc_cdsp: remoteproc@32300000 {
4338                         compatible = "qcom,sm8550-cdsp-pas";
4339                         reg = <0x0 0x32300000 0x0 0x1400000>;
4340
4341                         interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
4342                                               <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
4343                                               <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
4344                                               <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
4345                                               <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
4346                         interrupt-names = "wdog", "fatal", "ready",
4347                                           "handover", "stop-ack";
4348
4349                         clocks = <&rpmhcc RPMH_CXO_CLK>;
4350                         clock-names = "xo";
4351
4352                         power-domains = <&rpmhpd RPMHPD_CX>,
4353                                         <&rpmhpd RPMHPD_MXC>,
4354                                         <&rpmhpd RPMHPD_NSP>;
4355                         power-domain-names = "cx", "mxc", "nsp";
4356
4357                         interconnects = <&nsp_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
4358
4359                         memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>;
4360
4361                         qcom,qmp = <&aoss_qmp>;
4362
4363                         qcom,smem-states = <&smp2p_cdsp_out 0>;
4364                         qcom,smem-state-names = "stop";
4365
4366                         status = "disabled";
4367
4368                         glink-edge {
4369                                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
4370                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
4371                                                              IRQ_TYPE_EDGE_RISING>;
4372                                 mboxes = <&ipcc IPCC_CLIENT_CDSP
4373                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
4374
4375                                 label = "cdsp";
4376                                 qcom,remote-pid = <5>;
4377
4378                                 fastrpc {
4379                                         compatible = "qcom,fastrpc";
4380                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
4381                                         label = "cdsp";
4382                                         #address-cells = <1>;
4383                                         #size-cells = <0>;
4384
4385                                         compute-cb@1 {
4386                                                 compatible = "qcom,fastrpc-compute-cb";
4387                                                 reg = <1>;
4388                                                 iommus = <&apps_smmu 0x1961 0x0>,
4389                                                          <&apps_smmu 0x0c01 0x20>,
4390                                                          <&apps_smmu 0x19c1 0x10>;
4391                                         };
4392
4393                                         compute-cb@2 {
4394                                                 compatible = "qcom,fastrpc-compute-cb";
4395                                                 reg = <2>;
4396                                                 iommus = <&apps_smmu 0x1962 0x0>,
4397                                                          <&apps_smmu 0x0c02 0x20>,
4398                                                          <&apps_smmu 0x19c2 0x10>;
4399                                         };
4400
4401                                         compute-cb@3 {
4402                                                 compatible = "qcom,fastrpc-compute-cb";
4403                                                 reg = <3>;
4404                                                 iommus = <&apps_smmu 0x1963 0x0>,
4405                                                          <&apps_smmu 0x0c03 0x20>,
4406                                                          <&apps_smmu 0x19c3 0x10>;
4407                                         };
4408
4409                                         compute-cb@4 {
4410                                                 compatible = "qcom,fastrpc-compute-cb";
4411                                                 reg = <4>;
4412                                                 iommus = <&apps_smmu 0x1964 0x0>,
4413                                                          <&apps_smmu 0x0c04 0x20>,
4414                                                          <&apps_smmu 0x19c4 0x10>;
4415                                         };
4416
4417                                         compute-cb@5 {
4418                                                 compatible = "qcom,fastrpc-compute-cb";
4419                                                 reg = <5>;
4420                                                 iommus = <&apps_smmu 0x1965 0x0>,
4421                                                          <&apps_smmu 0x0c05 0x20>,
4422                                                          <&apps_smmu 0x19c5 0x10>;
4423                                         };
4424
4425                                         compute-cb@6 {
4426                                                 compatible = "qcom,fastrpc-compute-cb";
4427                                                 reg = <6>;
4428                                                 iommus = <&apps_smmu 0x1966 0x0>,
4429                                                          <&apps_smmu 0x0c06 0x20>,
4430                                                          <&apps_smmu 0x19c6 0x10>;
4431                                         };
4432
4433                                         compute-cb@7 {
4434                                                 compatible = "qcom,fastrpc-compute-cb";
4435                                                 reg = <7>;
4436                                                 iommus = <&apps_smmu 0x1967 0x0>,
4437                                                          <&apps_smmu 0x0c07 0x20>,
4438                                                          <&apps_smmu 0x19c7 0x10>;
4439                                         };
4440
4441                                         compute-cb@8 {
4442                                                 compatible = "qcom,fastrpc-compute-cb";
4443                                                 reg = <8>;
4444                                                 iommus = <&apps_smmu 0x1968 0x0>,
4445                                                          <&apps_smmu 0x0c08 0x20>,
4446                                                          <&apps_smmu 0x19c8 0x10>;
4447                                         };
4448
4449                                         /* note: secure cb9 in downstream */
4450                                 };
4451                         };
4452                 };
4453         };
4454
4455         thermal-zones {
4456                 aoss0-thermal {
4457                         polling-delay-passive = <0>;
4458                         polling-delay = <0>;
4459                         thermal-sensors = <&tsens0 0>;
4460
4461                         trips {
4462                                 thermal-engine-config {
4463                                         temperature = <125000>;
4464                                         hysteresis = <1000>;
4465                                         type = "passive";
4466                                 };
4467
4468                                 reset-mon-config {
4469                                         temperature = <115000>;
4470                                         hysteresis = <5000>;
4471                                         type = "passive";
4472                                 };
4473                         };
4474                 };
4475
4476                 cpuss0-thermal {
4477                         polling-delay-passive = <0>;
4478                         polling-delay = <0>;
4479                         thermal-sensors = <&tsens0 1>;
4480
4481                         trips {
4482                                 thermal-engine-config {
4483                                         temperature = <125000>;
4484                                         hysteresis = <1000>;
4485                                         type = "passive";
4486                                 };
4487
4488                                 reset-mon-config {
4489                                         temperature = <115000>;
4490                                         hysteresis = <5000>;
4491                                         type = "passive";
4492                                 };
4493                         };
4494                 };
4495
4496                 cpuss1-thermal {
4497                         polling-delay-passive = <0>;
4498                         polling-delay = <0>;
4499                         thermal-sensors = <&tsens0 2>;
4500
4501                         trips {
4502                                 thermal-engine-config {
4503                                         temperature = <125000>;
4504                                         hysteresis = <1000>;
4505                                         type = "passive";
4506                                 };
4507
4508                                 reset-mon-config {
4509                                         temperature = <115000>;
4510                                         hysteresis = <5000>;
4511                                         type = "passive";
4512                                 };
4513                         };
4514                 };
4515
4516                 cpuss2-thermal {
4517                         polling-delay-passive = <0>;
4518                         polling-delay = <0>;
4519                         thermal-sensors = <&tsens0 3>;
4520
4521                         trips {
4522                                 thermal-engine-config {
4523                                         temperature = <125000>;
4524                                         hysteresis = <1000>;
4525                                         type = "passive";
4526                                 };
4527
4528                                 reset-mon-config {
4529                                         temperature = <115000>;
4530                                         hysteresis = <5000>;
4531                                         type = "passive";
4532                                 };
4533                         };
4534                 };
4535
4536                 cpuss3-thermal {
4537                         polling-delay-passive = <0>;
4538                         polling-delay = <0>;
4539                         thermal-sensors = <&tsens0 4>;
4540
4541                         trips {
4542                                 thermal-engine-config {
4543                                         temperature = <125000>;
4544                                         hysteresis = <1000>;
4545                                         type = "passive";
4546                                 };
4547
4548                                 reset-mon-config {
4549                                         temperature = <115000>;
4550                                         hysteresis = <5000>;
4551                                         type = "passive";
4552                                 };
4553                         };
4554                 };
4555
4556                 cpu3-top-thermal {
4557                         polling-delay-passive = <0>;
4558                         polling-delay = <0>;
4559                         thermal-sensors = <&tsens0 5>;
4560
4561                         trips {
4562                                 cpu3_top_alert0: trip-point0 {
4563                                         temperature = <90000>;
4564                                         hysteresis = <2000>;
4565                                         type = "passive";
4566                                 };
4567
4568                                 cpu3_top_alert1: trip-point1 {
4569                                         temperature = <95000>;
4570                                         hysteresis = <2000>;
4571                                         type = "passive";
4572                                 };
4573
4574                                 cpu3_top_crit: cpu-critical {
4575                                         temperature = <110000>;
4576                                         hysteresis = <1000>;
4577                                         type = "critical";
4578                                 };
4579                         };
4580                 };
4581
4582                 cpu3-bottom-thermal {
4583                         polling-delay-passive = <0>;
4584                         polling-delay = <0>;
4585                         thermal-sensors = <&tsens0 6>;
4586
4587                         trips {
4588                                 cpu3_bottom_alert0: trip-point0 {
4589                                         temperature = <90000>;
4590                                         hysteresis = <2000>;
4591                                         type = "passive";
4592                                 };
4593
4594                                 cpu3_bottom_alert1: trip-point1 {
4595                                         temperature = <95000>;
4596                                         hysteresis = <2000>;
4597                                         type = "passive";
4598                                 };
4599
4600                                 cpu3_bottom_crit: cpu-critical {
4601                                         temperature = <110000>;
4602                                         hysteresis = <1000>;
4603                                         type = "critical";
4604                                 };
4605                         };
4606                 };
4607
4608                 cpu4-top-thermal {
4609                         polling-delay-passive = <0>;
4610                         polling-delay = <0>;
4611                         thermal-sensors = <&tsens0 7>;
4612
4613                         trips {
4614                                 cpu4_top_alert0: trip-point0 {
4615                                         temperature = <90000>;
4616                                         hysteresis = <2000>;
4617                                         type = "passive";
4618                                 };
4619
4620                                 cpu4_top_alert1: trip-point1 {
4621                                         temperature = <95000>;
4622                                         hysteresis = <2000>;
4623                                         type = "passive";
4624                                 };
4625
4626                                 cpu4_top_crit: cpu-critical {
4627                                         temperature = <110000>;
4628                                         hysteresis = <1000>;
4629                                         type = "critical";
4630                                 };
4631                         };
4632                 };
4633
4634                 cpu4-bottom-thermal {
4635                         polling-delay-passive = <0>;
4636                         polling-delay = <0>;
4637                         thermal-sensors = <&tsens0 8>;
4638
4639                         trips {
4640                                 cpu4_bottom_alert0: trip-point0 {
4641                                         temperature = <90000>;
4642                                         hysteresis = <2000>;
4643                                         type = "passive";
4644                                 };
4645
4646                                 cpu4_bottom_alert1: trip-point1 {
4647                                         temperature = <95000>;
4648                                         hysteresis = <2000>;
4649                                         type = "passive";
4650                                 };
4651
4652                                 cpu4_bottom_crit: cpu-critical {
4653                                         temperature = <110000>;
4654                                         hysteresis = <1000>;
4655                                         type = "critical";
4656                                 };
4657                         };
4658                 };
4659
4660                 cpu5-top-thermal {
4661                         polling-delay-passive = <0>;
4662                         polling-delay = <0>;
4663                         thermal-sensors = <&tsens0 9>;
4664
4665                         trips {
4666                                 cpu5_top_alert0: trip-point0 {
4667                                         temperature = <90000>;
4668                                         hysteresis = <2000>;
4669                                         type = "passive";
4670                                 };
4671
4672                                 cpu5_top_alert1: trip-point1 {
4673                                         temperature = <95000>;
4674                                         hysteresis = <2000>;
4675                                         type = "passive";
4676                                 };
4677
4678                                 cpu5_top_crit: cpu-critical {
4679                                         temperature = <110000>;
4680                                         hysteresis = <1000>;
4681                                         type = "critical";
4682                                 };
4683                         };
4684                 };
4685
4686                 cpu5-bottom-thermal {
4687                         polling-delay-passive = <0>;
4688                         polling-delay = <0>;
4689                         thermal-sensors = <&tsens0 10>;
4690
4691                         trips {
4692                                 cpu5_bottom_alert0: trip-point0 {
4693                                         temperature = <90000>;
4694                                         hysteresis = <2000>;
4695                                         type = "passive";
4696                                 };
4697
4698                                 cpu5_bottom_alert1: trip-point1 {
4699                                         temperature = <95000>;
4700                                         hysteresis = <2000>;
4701                                         type = "passive";
4702                                 };
4703
4704                                 cpu5_bottom_crit: cpu-critical {
4705                                         temperature = <110000>;
4706                                         hysteresis = <1000>;
4707                                         type = "critical";
4708                                 };
4709                         };
4710                 };
4711
4712                 cpu6-top-thermal {
4713                         polling-delay-passive = <0>;
4714                         polling-delay = <0>;
4715                         thermal-sensors = <&tsens0 11>;
4716
4717                         trips {
4718                                 cpu6_top_alert0: trip-point0 {
4719                                         temperature = <90000>;
4720                                         hysteresis = <2000>;
4721                                         type = "passive";
4722                                 };
4723
4724                                 cpu6_top_alert1: trip-point1 {
4725                                         temperature = <95000>;
4726                                         hysteresis = <2000>;
4727                                         type = "passive";
4728                                 };
4729
4730                                 cpu6_top_crit: cpu-critical {
4731                                         temperature = <110000>;
4732                                         hysteresis = <1000>;
4733                                         type = "critical";
4734                                 };
4735                         };
4736                 };
4737
4738                 cpu6-bottom-thermal {
4739                         polling-delay-passive = <0>;
4740                         polling-delay = <0>;
4741                         thermal-sensors = <&tsens0 12>;
4742
4743                         trips {
4744                                 cpu6_bottom_alert0: trip-point0 {
4745                                         temperature = <90000>;
4746                                         hysteresis = <2000>;
4747                                         type = "passive";
4748                                 };
4749
4750                                 cpu6_bottom_alert1: trip-point1 {
4751                                         temperature = <95000>;
4752                                         hysteresis = <2000>;
4753                                         type = "passive";
4754                                 };
4755
4756                                 cpu6_bottom_crit: cpu-critical {
4757                                         temperature = <110000>;
4758                                         hysteresis = <1000>;
4759                                         type = "critical";
4760                                 };
4761                         };
4762                 };
4763
4764                 cpu7-top-thermal {
4765                         polling-delay-passive = <0>;
4766                         polling-delay = <0>;
4767                         thermal-sensors = <&tsens0 13>;
4768
4769                         trips {
4770                                 cpu7_top_alert0: trip-point0 {
4771                                         temperature = <90000>;
4772                                         hysteresis = <2000>;
4773                                         type = "passive";
4774                                 };
4775
4776                                 cpu7_top_alert1: trip-point1 {
4777                                         temperature = <95000>;
4778                                         hysteresis = <2000>;
4779                                         type = "passive";
4780                                 };
4781
4782                                 cpu7_top_crit: cpu-critical {
4783                                         temperature = <110000>;
4784                                         hysteresis = <1000>;
4785                                         type = "critical";
4786                                 };
4787                         };
4788                 };
4789
4790                 cpu7-middle-thermal {
4791                         polling-delay-passive = <0>;
4792                         polling-delay = <0>;
4793                         thermal-sensors = <&tsens0 14>;
4794
4795                         trips {
4796                                 cpu7_middle_alert0: trip-point0 {
4797                                         temperature = <90000>;
4798                                         hysteresis = <2000>;
4799                                         type = "passive";
4800                                 };
4801
4802                                 cpu7_middle_alert1: trip-point1 {
4803                                         temperature = <95000>;
4804                                         hysteresis = <2000>;
4805                                         type = "passive";
4806                                 };
4807
4808                                 cpu7_middle_crit: cpu-critical {
4809                                         temperature = <110000>;
4810                                         hysteresis = <1000>;
4811                                         type = "critical";
4812                                 };
4813                         };
4814                 };
4815
4816                 cpu7-bottom-thermal {
4817                         polling-delay-passive = <0>;
4818                         polling-delay = <0>;
4819                         thermal-sensors = <&tsens0 15>;
4820
4821                         trips {
4822                                 cpu7_bottom_alert0: trip-point0 {
4823                                         temperature = <90000>;
4824                                         hysteresis = <2000>;
4825                                         type = "passive";
4826                                 };
4827
4828                                 cpu7_bottom_alert1: trip-point1 {
4829                                         temperature = <95000>;
4830                                         hysteresis = <2000>;
4831                                         type = "passive";
4832                                 };
4833
4834                                 cpu7_bottom_crit: cpu-critical {
4835                                         temperature = <110000>;
4836                                         hysteresis = <1000>;
4837                                         type = "critical";
4838                                 };
4839                         };
4840                 };
4841
4842                 aoss1-thermal {
4843                         polling-delay-passive = <0>;
4844                         polling-delay = <0>;
4845                         thermal-sensors = <&tsens1 0>;
4846
4847                         trips {
4848                                 thermal-engine-config {
4849                                         temperature = <125000>;
4850                                         hysteresis = <1000>;
4851                                         type = "passive";
4852                                 };
4853
4854                                 reset-mon-config {
4855                                         temperature = <115000>;
4856                                         hysteresis = <5000>;
4857                                         type = "passive";
4858                                 };
4859                         };
4860                 };
4861
4862                 cpu0-thermal {
4863                         polling-delay-passive = <0>;
4864                         polling-delay = <0>;
4865                         thermal-sensors = <&tsens1 1>;
4866
4867                         trips {
4868                                 cpu0_alert0: trip-point0 {
4869                                         temperature = <90000>;
4870                                         hysteresis = <2000>;
4871                                         type = "passive";
4872                                 };
4873
4874                                 cpu0_alert1: trip-point1 {
4875                                         temperature = <95000>;
4876                                         hysteresis = <2000>;
4877                                         type = "passive";
4878                                 };
4879
4880                                 cpu0_crit: cpu-critical {
4881                                         temperature = <110000>;
4882                                         hysteresis = <1000>;
4883                                         type = "critical";
4884                                 };
4885                         };
4886                 };
4887
4888                 cpu1-thermal {
4889                         polling-delay-passive = <0>;
4890                         polling-delay = <0>;
4891                         thermal-sensors = <&tsens1 2>;
4892
4893                         trips {
4894                                 cpu1_alert0: trip-point0 {
4895                                         temperature = <90000>;
4896                                         hysteresis = <2000>;
4897                                         type = "passive";
4898                                 };
4899
4900                                 cpu1_alert1: trip-point1 {
4901                                         temperature = <95000>;
4902                                         hysteresis = <2000>;
4903                                         type = "passive";
4904                                 };
4905
4906                                 cpu1_crit: cpu-critical {
4907                                         temperature = <110000>;
4908                                         hysteresis = <1000>;
4909                                         type = "critical";
4910                                 };
4911                         };
4912                 };
4913
4914                 cpu2-thermal {
4915                         polling-delay-passive = <0>;
4916                         polling-delay = <0>;
4917                         thermal-sensors = <&tsens1 3>;
4918
4919                         trips {
4920                                 cpu2_alert0: trip-point0 {
4921                                         temperature = <90000>;
4922                                         hysteresis = <2000>;
4923                                         type = "passive";
4924                                 };
4925
4926                                 cpu2_alert1: trip-point1 {
4927                                         temperature = <95000>;
4928                                         hysteresis = <2000>;
4929                                         type = "passive";
4930                                 };
4931
4932                                 cpu2_crit: cpu-critical {
4933                                         temperature = <110000>;
4934                                         hysteresis = <1000>;
4935                                         type = "critical";
4936                                 };
4937                         };
4938                 };
4939
4940                 cdsp0-thermal {
4941                         polling-delay-passive = <10>;
4942                         polling-delay = <0>;
4943                         thermal-sensors = <&tsens2 4>;
4944
4945                         trips {
4946                                 thermal-engine-config {
4947                                         temperature = <125000>;
4948                                         hysteresis = <1000>;
4949                                         type = "passive";
4950                                 };
4951
4952                                 thermal-hal-config {
4953                                         temperature = <125000>;
4954                                         hysteresis = <1000>;
4955                                         type = "passive";
4956                                 };
4957
4958                                 reset-mon-config {
4959                                         temperature = <115000>;
4960                                         hysteresis = <5000>;
4961                                         type = "passive";
4962                                 };
4963
4964                                 cdsp0_junction_config: junction-config {
4965                                         temperature = <95000>;
4966                                         hysteresis = <5000>;
4967                                         type = "passive";
4968                                 };
4969                         };
4970                 };
4971
4972                 cdsp1-thermal {
4973                         polling-delay-passive = <10>;
4974                         polling-delay = <0>;
4975                         thermal-sensors = <&tsens2 5>;
4976
4977                         trips {
4978                                 thermal-engine-config {
4979                                         temperature = <125000>;
4980                                         hysteresis = <1000>;
4981                                         type = "passive";
4982                                 };
4983
4984                                 thermal-hal-config {
4985                                         temperature = <125000>;
4986                                         hysteresis = <1000>;
4987                                         type = "passive";
4988                                 };
4989
4990                                 reset-mon-config {
4991                                         temperature = <115000>;
4992                                         hysteresis = <5000>;
4993                                         type = "passive";
4994                                 };
4995
4996                                 cdsp1_junction_config: junction-config {
4997                                         temperature = <95000>;
4998                                         hysteresis = <5000>;
4999                                         type = "passive";
5000                                 };
5001                         };
5002                 };
5003
5004                 cdsp2-thermal {
5005                         polling-delay-passive = <10>;
5006                         polling-delay = <0>;
5007                         thermal-sensors = <&tsens2 6>;
5008
5009                         trips {
5010                                 thermal-engine-config {
5011                                         temperature = <125000>;
5012                                         hysteresis = <1000>;
5013                                         type = "passive";
5014                                 };
5015
5016                                 thermal-hal-config {
5017                                         temperature = <125000>;
5018                                         hysteresis = <1000>;
5019                                         type = "passive";
5020                                 };
5021
5022                                 reset-mon-config {
5023                                         temperature = <115000>;
5024                                         hysteresis = <5000>;
5025                                         type = "passive";
5026                                 };
5027
5028                                 cdsp2_junction_config: junction-config {
5029                                         temperature = <95000>;
5030                                         hysteresis = <5000>;
5031                                         type = "passive";
5032                                 };
5033                         };
5034                 };
5035
5036                 cdsp3-thermal {
5037                         polling-delay-passive = <10>;
5038                         polling-delay = <0>;
5039                         thermal-sensors = <&tsens2 7>;
5040
5041                         trips {
5042                                 thermal-engine-config {
5043                                         temperature = <125000>;
5044                                         hysteresis = <1000>;
5045                                         type = "passive";
5046                                 };
5047
5048                                 thermal-hal-config {
5049                                         temperature = <125000>;
5050                                         hysteresis = <1000>;
5051                                         type = "passive";
5052                                 };
5053
5054                                 reset-mon-config {
5055                                         temperature = <115000>;
5056                                         hysteresis = <5000>;
5057                                         type = "passive";
5058                                 };
5059
5060                                 cdsp3_junction_config: junction-config {
5061                                         temperature = <95000>;
5062                                         hysteresis = <5000>;
5063                                         type = "passive";
5064                                 };
5065                         };
5066                 };
5067
5068                 video-thermal {
5069                         polling-delay-passive = <0>;
5070                         polling-delay = <0>;
5071                         thermal-sensors = <&tsens1 8>;
5072
5073                         trips {
5074                                 thermal-engine-config {
5075                                         temperature = <125000>;
5076                                         hysteresis = <1000>;
5077                                         type = "passive";
5078                                 };
5079
5080                                 reset-mon-config {
5081                                         temperature = <115000>;
5082                                         hysteresis = <5000>;
5083                                         type = "passive";
5084                                 };
5085                         };
5086                 };
5087
5088                 mem-thermal {
5089                         polling-delay-passive = <10>;
5090                         polling-delay = <0>;
5091                         thermal-sensors = <&tsens1 9>;
5092
5093                         trips {
5094                                 thermal-engine-config {
5095                                         temperature = <125000>;
5096                                         hysteresis = <1000>;
5097                                         type = "passive";
5098                                 };
5099
5100                                 ddr_config0: ddr0-config {
5101                                         temperature = <90000>;
5102                                         hysteresis = <5000>;
5103                                         type = "passive";
5104                                 };
5105
5106                                 reset-mon-config {
5107                                         temperature = <115000>;
5108                                         hysteresis = <5000>;
5109                                         type = "passive";
5110                                 };
5111                         };
5112                 };
5113
5114                 modem0-thermal {
5115                         polling-delay-passive = <0>;
5116                         polling-delay = <0>;
5117                         thermal-sensors = <&tsens1 10>;
5118
5119                         trips {
5120                                 thermal-engine-config {
5121                                         temperature = <125000>;
5122                                         hysteresis = <1000>;
5123                                         type = "passive";
5124                                 };
5125
5126                                 mdmss0_config0: mdmss0-config0 {
5127                                         temperature = <102000>;
5128                                         hysteresis = <3000>;
5129                                         type = "passive";
5130                                 };
5131
5132                                 mdmss0_config1: mdmss0-config1 {
5133                                         temperature = <105000>;
5134                                         hysteresis = <3000>;
5135                                         type = "passive";
5136                                 };
5137
5138                                 reset-mon-config {
5139                                         temperature = <115000>;
5140                                         hysteresis = <5000>;
5141                                         type = "passive";
5142                                 };
5143                         };
5144                 };
5145
5146                 modem1-thermal {
5147                         polling-delay-passive = <0>;
5148                         polling-delay = <0>;
5149                         thermal-sensors = <&tsens1 11>;
5150
5151                         trips {
5152                                 thermal-engine-config {
5153                                         temperature = <125000>;
5154                                         hysteresis = <1000>;
5155                                         type = "passive";
5156                                 };
5157
5158                                 mdmss1_config0: mdmss1-config0 {
5159                                         temperature = <102000>;
5160                                         hysteresis = <3000>;
5161                                         type = "passive";
5162                                 };
5163
5164                                 mdmss1_config1: mdmss1-config1 {
5165                                         temperature = <105000>;
5166                                         hysteresis = <3000>;
5167                                         type = "passive";
5168                                 };
5169
5170                                 reset-mon-config {
5171                                         temperature = <115000>;
5172                                         hysteresis = <5000>;
5173                                         type = "passive";
5174                                 };
5175                         };
5176                 };
5177
5178                 modem2-thermal {
5179                         polling-delay-passive = <0>;
5180                         polling-delay = <0>;
5181                         thermal-sensors = <&tsens1 12>;
5182
5183                         trips {
5184                                 thermal-engine-config {
5185                                         temperature = <125000>;
5186                                         hysteresis = <1000>;
5187                                         type = "passive";
5188                                 };
5189
5190                                 mdmss2_config0: mdmss2-config0 {
5191                                         temperature = <102000>;
5192                                         hysteresis = <3000>;
5193                                         type = "passive";
5194                                 };
5195
5196                                 mdmss2_config1: mdmss2-config1 {
5197                                         temperature = <105000>;
5198                                         hysteresis = <3000>;
5199                                         type = "passive";
5200                                 };
5201
5202                                 reset-mon-config {
5203                                         temperature = <115000>;
5204                                         hysteresis = <5000>;
5205                                         type = "passive";
5206                                 };
5207                         };
5208                 };
5209
5210                 modem3-thermal {
5211                         polling-delay-passive = <0>;
5212                         polling-delay = <0>;
5213                         thermal-sensors = <&tsens1 13>;
5214
5215                         trips {
5216                                 thermal-engine-config {
5217                                         temperature = <125000>;
5218                                         hysteresis = <1000>;
5219                                         type = "passive";
5220                                 };
5221
5222                                 mdmss3_config0: mdmss3-config0 {
5223                                         temperature = <102000>;
5224                                         hysteresis = <3000>;
5225                                         type = "passive";
5226                                 };
5227
5228                                 mdmss3_config1: mdmss3-config1 {
5229                                         temperature = <105000>;
5230                                         hysteresis = <3000>;
5231                                         type = "passive";
5232                                 };
5233
5234                                 reset-mon-config {
5235                                         temperature = <115000>;
5236                                         hysteresis = <5000>;
5237                                         type = "passive";
5238                                 };
5239                         };
5240                 };
5241
5242                 camera0-thermal {
5243                         polling-delay-passive = <0>;
5244                         polling-delay = <0>;
5245                         thermal-sensors = <&tsens1 14>;
5246
5247                         trips {
5248                                 thermal-engine-config {
5249                                         temperature = <125000>;
5250                                         hysteresis = <1000>;
5251                                         type = "passive";
5252                                 };
5253
5254                                 reset-mon-config {
5255                                         temperature = <115000>;
5256                                         hysteresis = <5000>;
5257                                         type = "passive";
5258                                 };
5259                         };
5260                 };
5261
5262                 camera1-thermal {
5263                         polling-delay-passive = <0>;
5264                         polling-delay = <0>;
5265                         thermal-sensors = <&tsens1 15>;
5266
5267                         trips {
5268                                 thermal-engine-config {
5269                                         temperature = <125000>;
5270                                         hysteresis = <1000>;
5271                                         type = "passive";
5272                                 };
5273
5274                                 reset-mon-config {
5275                                         temperature = <115000>;
5276                                         hysteresis = <5000>;
5277                                         type = "passive";
5278                                 };
5279                         };
5280                 };
5281
5282                 aoss2-thermal {
5283                         polling-delay-passive = <0>;
5284                         polling-delay = <0>;
5285                         thermal-sensors = <&tsens2 0>;
5286
5287                         trips {
5288                                 thermal-engine-config {
5289                                         temperature = <125000>;
5290                                         hysteresis = <1000>;
5291                                         type = "passive";
5292                                 };
5293
5294                                 reset-mon-config {
5295                                         temperature = <115000>;
5296                                         hysteresis = <5000>;
5297                                         type = "passive";
5298                                 };
5299                         };
5300                 };
5301
5302                 gpuss-0-thermal {
5303                         polling-delay-passive = <10>;
5304                         polling-delay = <0>;
5305                         thermal-sensors = <&tsens2 1>;
5306
5307                         trips {
5308                                 thermal-engine-config {
5309                                         temperature = <125000>;
5310                                         hysteresis = <1000>;
5311                                         type = "passive";
5312                                 };
5313
5314                                 thermal-hal-config {
5315                                         temperature = <125000>;
5316                                         hysteresis = <1000>;
5317                                         type = "passive";
5318                                 };
5319
5320                                 reset-mon-config {
5321                                         temperature = <115000>;
5322                                         hysteresis = <5000>;
5323                                         type = "passive";
5324                                 };
5325
5326                                 gpu0_junction_config: junction-config {
5327                                         temperature = <95000>;
5328                                         hysteresis = <5000>;
5329                                         type = "passive";
5330                                 };
5331                         };
5332                 };
5333
5334                 gpuss-1-thermal {
5335                         polling-delay-passive = <10>;
5336                         polling-delay = <0>;
5337                         thermal-sensors = <&tsens2 2>;
5338
5339                         trips {
5340                                 thermal-engine-config {
5341                                         temperature = <125000>;
5342                                         hysteresis = <1000>;
5343                                         type = "passive";
5344                                 };
5345
5346                                 thermal-hal-config {
5347                                         temperature = <125000>;
5348                                         hysteresis = <1000>;
5349                                         type = "passive";
5350                                 };
5351
5352                                 reset-mon-config {
5353                                         temperature = <115000>;
5354                                         hysteresis = <5000>;
5355                                         type = "passive";
5356                                 };
5357
5358                                 gpu1_junction_config: junction-config {
5359                                         temperature = <95000>;
5360                                         hysteresis = <5000>;
5361                                         type = "passive";
5362                                 };
5363                         };
5364                 };
5365
5366                 gpuss-2-thermal {
5367                         polling-delay-passive = <10>;
5368                         polling-delay = <0>;
5369                         thermal-sensors = <&tsens2 3>;
5370
5371                         trips {
5372                                 thermal-engine-config {
5373                                         temperature = <125000>;
5374                                         hysteresis = <1000>;
5375                                         type = "passive";
5376                                 };
5377
5378                                 thermal-hal-config {
5379                                         temperature = <125000>;
5380                                         hysteresis = <1000>;
5381                                         type = "passive";
5382                                 };
5383
5384                                 reset-mon-config {
5385                                         temperature = <115000>;
5386                                         hysteresis = <5000>;
5387                                         type = "passive";
5388                                 };
5389
5390                                 gpu2_junction_config: junction-config {
5391                                         temperature = <95000>;
5392                                         hysteresis = <5000>;
5393                                         type = "passive";
5394                                 };
5395                         };
5396                 };
5397
5398                 gpuss-3-thermal {
5399                         polling-delay-passive = <10>;
5400                         polling-delay = <0>;
5401                         thermal-sensors = <&tsens2 4>;
5402
5403                         trips {
5404                                 thermal-engine-config {
5405                                         temperature = <125000>;
5406                                         hysteresis = <1000>;
5407                                         type = "passive";
5408                                 };
5409
5410                                 thermal-hal-config {
5411                                         temperature = <125000>;
5412                                         hysteresis = <1000>;
5413                                         type = "passive";
5414                                 };
5415
5416                                 reset-mon-config {
5417                                         temperature = <115000>;
5418                                         hysteresis = <5000>;
5419                                         type = "passive";
5420                                 };
5421
5422                                 gpu3_junction_config: junction-config {
5423                                         temperature = <95000>;
5424                                         hysteresis = <5000>;
5425                                         type = "passive";
5426                                 };
5427                         };
5428                 };
5429
5430                 gpuss-4-thermal {
5431                         polling-delay-passive = <10>;
5432                         polling-delay = <0>;
5433                         thermal-sensors = <&tsens2 5>;
5434
5435                         trips {
5436                                 thermal-engine-config {
5437                                         temperature = <125000>;
5438                                         hysteresis = <1000>;
5439                                         type = "passive";
5440                                 };
5441
5442                                 thermal-hal-config {
5443                                         temperature = <125000>;
5444                                         hysteresis = <1000>;
5445                                         type = "passive";
5446                                 };
5447
5448                                 reset-mon-config {
5449                                         temperature = <115000>;
5450                                         hysteresis = <5000>;
5451                                         type = "passive";
5452                                 };
5453
5454                                 gpu4_junction_config: junction-config {
5455                                         temperature = <95000>;
5456                                         hysteresis = <5000>;
5457                                         type = "passive";
5458                                 };
5459                         };
5460                 };
5461
5462                 gpuss-5-thermal {
5463                         polling-delay-passive = <10>;
5464                         polling-delay = <0>;
5465                         thermal-sensors = <&tsens2 6>;
5466
5467                         trips {
5468                                 thermal-engine-config {
5469                                         temperature = <125000>;
5470                                         hysteresis = <1000>;
5471                                         type = "passive";
5472                                 };
5473
5474                                 thermal-hal-config {
5475                                         temperature = <125000>;
5476                                         hysteresis = <1000>;
5477                                         type = "passive";
5478                                 };
5479
5480                                 reset-mon-config {
5481                                         temperature = <115000>;
5482                                         hysteresis = <5000>;
5483                                         type = "passive";
5484                                 };
5485
5486                                 gpu5_junction_config: junction-config {
5487                                         temperature = <95000>;
5488                                         hysteresis = <5000>;
5489                                         type = "passive";
5490                                 };
5491                         };
5492                 };
5493
5494                 gpuss-6-thermal {
5495                         polling-delay-passive = <10>;
5496                         polling-delay = <0>;
5497                         thermal-sensors = <&tsens2 7>;
5498
5499                         trips {
5500                                 thermal-engine-config {
5501                                         temperature = <125000>;
5502                                         hysteresis = <1000>;
5503                                         type = "passive";
5504                                 };
5505
5506                                 thermal-hal-config {
5507                                         temperature = <125000>;
5508                                         hysteresis = <1000>;
5509                                         type = "passive";
5510                                 };
5511
5512                                 reset-mon-config {
5513                                         temperature = <115000>;
5514                                         hysteresis = <5000>;
5515                                         type = "passive";
5516                                 };
5517
5518                                 gpu6_junction_config: junction-config {
5519                                         temperature = <95000>;
5520                                         hysteresis = <5000>;
5521                                         type = "passive";
5522                                 };
5523                         };
5524                 };
5525
5526                 gpuss-7-thermal {
5527                         polling-delay-passive = <10>;
5528                         polling-delay = <0>;
5529                         thermal-sensors = <&tsens2 8>;
5530
5531                         trips {
5532                                 thermal-engine-config {
5533                                         temperature = <125000>;
5534                                         hysteresis = <1000>;
5535                                         type = "passive";
5536                                 };
5537
5538                                 thermal-hal-config {
5539                                         temperature = <125000>;
5540                                         hysteresis = <1000>;
5541                                         type = "passive";
5542                                 };
5543
5544                                 reset-mon-config {
5545                                         temperature = <115000>;
5546                                         hysteresis = <5000>;
5547                                         type = "passive";
5548                                 };
5549
5550                                 gpu7_junction_config: junction-config {
5551                                         temperature = <95000>;
5552                                         hysteresis = <5000>;
5553                                         type = "passive";
5554                                 };
5555                         };
5556                 };
5557         };
5558
5559         timer {
5560                 compatible = "arm,armv8-timer";
5561                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5562                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5563                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5564                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
5565         };
5566 };