arch/arm64/boot/dts/qcom/sm8350.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * Copyright (c) 2020, Linaro Limited
   4  */
   5
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/clock/qcom,gcc-sm8350.h>
   8 #include <dt-bindings/clock/qcom,rpmh.h>
   9 #include <dt-bindings/dma/qcom-gpi.h>
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/interconnect/qcom,sm8350.h>
  12 #include <dt-bindings/mailbox/qcom-ipcc.h>
  13 #include <dt-bindings/power/qcom-rpmpd.h>
  14 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  15 #include <dt-bindings/thermal/thermal.h>
  16 #include <dt-bindings/interconnect/qcom,sm8350.h>
  17
  18 / {
  19         interrupt-parent = <&intc>;
  20
  21         #address-cells = <2>;
  22         #size-cells = <2>;
  23
  24         chosen { };
  25
  26         clocks {
  27                 xo_board: xo-board {
  28                         compatible = "fixed-clock";
  29                         #clock-cells = <0>;
  30                         clock-frequency = <38400000>;
  31                         clock-output-names = "xo_board";
  32                 };
  33
  34                 sleep_clk: sleep-clk {
  35                         compatible = "fixed-clock";
  36                         clock-frequency = <32000>;
  37                         #clock-cells = <0>;
  38                 };
  39
  40                 ufs_phy_rx_symbol_0_clk: ufs-phy-rx-symbol-0 {
  41                         compatible = "fixed-clock";
  42                         clock-frequency = <1000>;
  43                         #clock-cells = <0>;
  44                 };
  45
  46                 ufs_phy_rx_symbol_1_clk: ufs-phy-rx-symbol-1 {
  47                         compatible = "fixed-clock";
  48                         clock-frequency = <1000>;
  49                         #clock-cells = <0>;
  50                 };
  51
  52                 ufs_phy_tx_symbol_0_clk: ufs-phy-tx-symbol-0 {
  53                         compatible = "fixed-clock";
  54                         clock-frequency = <1000>;
  55                         #clock-cells = <0>;
  56                 };
  57         };
  58
  59         cpus {
  60                 #address-cells = <2>;
  61                 #size-cells = <0>;
  62
  63                 CPU0: cpu@0 {
  64                         device_type = "cpu";
  65                         compatible = "qcom,kryo685";
  66                         reg = <0x0 0x0>;
  67                         enable-method = "psci";
  68                         next-level-cache = <&L2_0>;
  69                         qcom,freq-domain = <&cpufreq_hw 0>;
  70                         power-domains = <&CPU_PD0>;
  71                         power-domain-names = "psci";
  72                         #cooling-cells = <2>;
  73                         L2_0: l2-cache {
  74                               compatible = "cache";
  75                               next-level-cache = <&L3_0>;
  76                                 L3_0: l3-cache {
  77                                       compatible = "cache";
  78                                 };
  79                         };
  80                 };
  81
  82                 CPU1: cpu@100 {
  83                         device_type = "cpu";
  84                         compatible = "qcom,kryo685";
  85                         reg = <0x0 0x100>;
  86                         enable-method = "psci";
  87                         next-level-cache = <&L2_100>;
  88                         qcom,freq-domain = <&cpufreq_hw 0>;
  89                         power-domains = <&CPU_PD1>;
  90                         power-domain-names = "psci";
  91                         #cooling-cells = <2>;
  92                         L2_100: l2-cache {
  93                               compatible = "cache";
  94                               next-level-cache = <&L3_0>;
  95                         };
  96                 };
  97
  98                 CPU2: cpu@200 {
  99                         device_type = "cpu";
 100                         compatible = "qcom,kryo685";
 101                         reg = <0x0 0x200>;
 102                         enable-method = "psci";
 103                         next-level-cache = <&L2_200>;
 104                         qcom,freq-domain = <&cpufreq_hw 0>;
 105                         power-domains = <&CPU_PD2>;
 106                         power-domain-names = "psci";
 107                         #cooling-cells = <2>;
 108                         L2_200: l2-cache {
 109                               compatible = "cache";
 110                               next-level-cache = <&L3_0>;
 111                         };
 112                 };
 113
 114                 CPU3: cpu@300 {
 115                         device_type = "cpu";
 116                         compatible = "qcom,kryo685";
 117                         reg = <0x0 0x300>;
 118                         enable-method = "psci";
 119                         next-level-cache = <&L2_300>;
 120                         qcom,freq-domain = <&cpufreq_hw 0>;
 121                         power-domains = <&CPU_PD3>;
 122                         power-domain-names = "psci";
 123                         #cooling-cells = <2>;
 124                         L2_300: l2-cache {
 125                               compatible = "cache";
 126                               next-level-cache = <&L3_0>;
 127                         };
 128                 };
 129
 130                 CPU4: cpu@400 {
 131                         device_type = "cpu";
 132                         compatible = "qcom,kryo685";
 133                         reg = <0x0 0x400>;
 134                         enable-method = "psci";
 135                         next-level-cache = <&L2_400>;
 136                         qcom,freq-domain = <&cpufreq_hw 1>;
 137                         power-domains = <&CPU_PD4>;
 138                         power-domain-names = "psci";
 139                         #cooling-cells = <2>;
 140                         L2_400: l2-cache {
 141                               compatible = "cache";
 142                               next-level-cache = <&L3_0>;
 143                         };
 144                 };
 145
 146                 CPU5: cpu@500 {
 147                         device_type = "cpu";
 148                         compatible = "qcom,kryo685";
 149                         reg = <0x0 0x500>;
 150                         enable-method = "psci";
 151                         next-level-cache = <&L2_500>;
 152                         qcom,freq-domain = <&cpufreq_hw 1>;
 153                         power-domains = <&CPU_PD5>;
 154                         power-domain-names = "psci";
 155                         #cooling-cells = <2>;
 156                         L2_500: l2-cache {
 157                               compatible = "cache";
 158                               next-level-cache = <&L3_0>;
 159                         };
 160
 161                 };
 162
 163                 CPU6: cpu@600 {
 164                         device_type = "cpu";
 165                         compatible = "qcom,kryo685";
 166                         reg = <0x0 0x600>;
 167                         enable-method = "psci";
 168                         next-level-cache = <&L2_600>;
 169                         qcom,freq-domain = <&cpufreq_hw 1>;
 170                         power-domains = <&CPU_PD6>;
 171                         power-domain-names = "psci";
 172                         #cooling-cells = <2>;
 173                         L2_600: l2-cache {
 174                               compatible = "cache";
 175                               next-level-cache = <&L3_0>;
 176                         };
 177                 };
 178
 179                 CPU7: cpu@700 {
 180                         device_type = "cpu";
 181                         compatible = "qcom,kryo685";
 182                         reg = <0x0 0x700>;
 183                         enable-method = "psci";
 184                         next-level-cache = <&L2_700>;
 185                         qcom,freq-domain = <&cpufreq_hw 2>;
 186                         power-domains = <&CPU_PD7>;
 187                         power-domain-names = "psci";
 188                         #cooling-cells = <2>;
 189                         L2_700: l2-cache {
 190                               compatible = "cache";
 191                               next-level-cache = <&L3_0>;
 192                         };
 193                 };
 194
 195                 cpu-map {
 196                         cluster0 {
 197                                 core0 {
 198                                         cpu = <&CPU0>;
 199                                 };
 200
 201                                 core1 {
 202                                         cpu = <&CPU1>;
 203                                 };
 204
 205                                 core2 {
 206                                         cpu = <&CPU2>;
 207                                 };
 208
 209                                 core3 {
 210                                         cpu = <&CPU3>;
 211                                 };
 212
 213                                 core4 {
 214                                         cpu = <&CPU4>;
 215                                 };
 216
 217                                 core5 {
 218                                         cpu = <&CPU5>;
 219                                 };
 220
 221                                 core6 {
 222                                         cpu = <&CPU6>;
 223                                 };
 224
 225                                 core7 {
 226                                         cpu = <&CPU7>;
 227                                 };
 228                         };
 229                 };
 230
 231                 idle-states {
 232                         entry-method = "psci";
 233
 234                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 235                                 compatible = "arm,idle-state";
 236                                 idle-state-name = "silver-rail-power-collapse";
 237                                 arm,psci-suspend-param = <0x40000004>;
 238                                 entry-latency-us = <355>;
 239                                 exit-latency-us = <909>;
 240                                 min-residency-us = <3934>;
 241                                 local-timer-stop;
 242                         };
 243
 244                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 245                                 compatible = "arm,idle-state";
 246                                 idle-state-name = "gold-rail-power-collapse";
 247                                 arm,psci-suspend-param = <0x40000004>;
 248                                 entry-latency-us = <241>;
 249                                 exit-latency-us = <1461>;
 250                                 min-residency-us = <4488>;
 251                                 local-timer-stop;
 252                         };
 253                 };
 254
 255                 domain-idle-states {
 256                         CLUSTER_SLEEP_0: cluster-sleep-0 {
 257                                 compatible = "domain-idle-state";
 258                                 idle-state-name = "cluster-power-collapse";
 259                                 arm,psci-suspend-param = <0x4100c344>;
 260                                 entry-latency-us = <3263>;
 261                                 exit-latency-us = <6562>;
 262                                 min-residency-us = <9987>;
 263                                 local-timer-stop;
 264                         };
 265                 };
 266         };
 267
 268         firmware {
 269                 scm: scm {
 270                         compatible = "qcom,scm-sm8350", "qcom,scm";
 271                         #reset-cells = <1>;
 272                 };
 273         };
 274
 275         memory@80000000 {
 276                 device_type = "memory";
 277                 /* We expect the bootloader to fill in the size */
 278                 reg = <0x0 0x80000000 0x0 0x0>;
 279         };
 280
 281         pmu {
 282                 compatible = "arm,armv8-pmuv3";
 283                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 284         };
 285
 286         psci {
 287                 compatible = "arm,psci-1.0";
 288                 method = "smc";
 289
 290                 CPU_PD0: cpu0 {
 291                         #power-domain-cells = <0>;
 292                         power-domains = <&CLUSTER_PD>;
 293                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 294                 };
 295
 296                 CPU_PD1: cpu1 {
 297                         #power-domain-cells = <0>;
 298                         power-domains = <&CLUSTER_PD>;
 299                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 300                 };
 301
 302                 CPU_PD2: cpu2 {
 303                         #power-domain-cells = <0>;
 304                         power-domains = <&CLUSTER_PD>;
 305                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 306                 };
 307
 308                 CPU_PD3: cpu3 {
 309                         #power-domain-cells = <0>;
 310                         power-domains = <&CLUSTER_PD>;
 311                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 312                 };
 313
 314                 CPU_PD4: cpu4 {
 315                         #power-domain-cells = <0>;
 316                         power-domains = <&CLUSTER_PD>;
 317                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 318                 };
 319
 320                 CPU_PD5: cpu5 {
 321                         #power-domain-cells = <0>;
 322                         power-domains = <&CLUSTER_PD>;
 323                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 324                 };
 325
 326                 CPU_PD6: cpu6 {
 327                         #power-domain-cells = <0>;
 328                         power-domains = <&CLUSTER_PD>;
 329                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 330                 };
 331
 332                 CPU_PD7: cpu7 {
 333                         #power-domain-cells = <0>;
 334                         power-domains = <&CLUSTER_PD>;
 335                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 336                 };
 337
 338                 CLUSTER_PD: cpu-cluster0 {
 339                         #power-domain-cells = <0>;
 340                         domain-idle-states = <&CLUSTER_SLEEP_0>;
 341                 };
 342         };
 343
 344         reserved_memory: reserved-memory {
 345                 #address-cells = <2>;
 346                 #size-cells = <2>;
 347                 ranges;
 348
 349                 hyp_mem: memory@80000000 {
 350                         reg = <0x0 0x80000000 0x0 0x600000>;
 351                         no-map;
 352                 };
 353
 354                 xbl_aop_mem: memory@80700000 {
 355                         no-map;
 356                         reg = <0x0 0x80700000 0x0 0x160000>;
 357                 };
 358
 359                 cmd_db: memory@80860000 {
 360                         compatible = "qcom,cmd-db";
 361                         reg = <0x0 0x80860000 0x0 0x20000>;
 362                         no-map;
 363                 };
 364
 365                 reserved_xbl_uefi_log: memory@80880000 {
 366                         reg = <0x0 0x80880000 0x0 0x14000>;
 367                         no-map;
 368                 };
 369
 370                 smem_mem: memory@80900000 {
 371                         reg = <0x0 0x80900000 0x0 0x200000>;
 372                         no-map;
 373                 };
 374
 375                 cpucp_fw_mem: memory@80b00000 {
 376                         reg = <0x0 0x80b00000 0x0 0x100000>;
 377                         no-map;
 378                 };
 379
 380                 cdsp_secure_heap: memory@80c00000 {
 381                         reg = <0x0 0x80c00000 0x0 0x4600000>;
 382                         no-map;
 383                 };
 384
 385                 pil_camera_mem: mmeory@85200000 {
 386                         reg = <0x0 0x85200000 0x0 0x500000>;
 387                         no-map;
 388                 };
 389
 390                 pil_video_mem: memory@85700000 {
 391                         reg = <0x0 0x85700000 0x0 0x500000>;
 392                         no-map;
 393                 };
 394
 395                 pil_cvp_mem: memory@85c00000 {
 396                         reg = <0x0 0x85c00000 0x0 0x500000>;
 397                         no-map;
 398                 };
 399
 400                 pil_adsp_mem: memory@86100000 {
 401                         reg = <0x0 0x86100000 0x0 0x2100000>;
 402                         no-map;
 403                 };
 404
 405                 pil_slpi_mem: memory@88200000 {
 406                         reg = <0x0 0x88200000 0x0 0x1500000>;
 407                         no-map;
 408                 };
 409
 410                 pil_cdsp_mem: memory@89700000 {
 411                         reg = <0x0 0x89700000 0x0 0x1e00000>;
 412                         no-map;
 413                 };
 414
 415                 pil_ipa_fw_mem: memory@8b500000 {
 416                         reg = <0x0 0x8b500000 0x0 0x10000>;
 417                         no-map;
 418                 };
 419
 420                 pil_ipa_gsi_mem: memory@8b510000 {
 421                         reg = <0x0 0x8b510000 0x0 0xa000>;
 422                         no-map;
 423                 };
 424
 425                 pil_gpu_mem: memory@8b51a000 {
 426                         reg = <0x0 0x8b51a000 0x0 0x2000>;
 427                         no-map;
 428                 };
 429
 430                 pil_spss_mem: memory@8b600000 {
 431                         reg = <0x0 0x8b600000 0x0 0x100000>;
 432                         no-map;
 433                 };
 434
 435                 pil_modem_mem: memory@8b800000 {
 436                         reg = <0x0 0x8b800000 0x0 0x10000000>;
 437                         no-map;
 438                 };
 439
 440                 rmtfs_mem: memory@9b800000 {
 441                         compatible = "qcom,rmtfs-mem";
 442                         reg = <0x0 0x9b800000 0x0 0x280000>;
 443                         no-map;
 444
 445                         qcom,client-id = <1>;
 446                         qcom,vmid = <15>;
 447                 };
 448
 449                 hyp_reserved_mem: memory@d0000000 {
 450                         reg = <0x0 0xd0000000 0x0 0x800000>;
 451                         no-map;
 452                 };
 453
 454                 pil_trustedvm_mem: memory@d0800000 {
 455                         reg = <0x0 0xd0800000 0x0 0x76f7000>;
 456                         no-map;
 457                 };
 458
 459                 qrtr_shbuf: memory@d7ef7000 {
 460                         reg = <0x0 0xd7ef7000 0x0 0x9000>;
 461                         no-map;
 462                 };
 463
 464                 chan0_shbuf: memory@d7f00000 {
 465                         reg = <0x0 0xd7f00000 0x0 0x80000>;
 466                         no-map;
 467                 };
 468
 469                 chan1_shbuf: memory@d7f80000 {
 470                         reg = <0x0 0xd7f80000 0x0 0x80000>;
 471                         no-map;
 472                 };
 473
 474                 removed_mem: memory@d8800000 {
 475                         reg = <0x0 0xd8800000 0x0 0x6800000>;
 476                         no-map;
 477                 };
 478         };
 479
 480         smem: qcom,smem {
 481                 compatible = "qcom,smem";
 482                 memory-region = <&smem_mem>;
 483                 hwlocks = <&tcsr_mutex 3>;
 484         };
 485
 486         smp2p-adsp {
 487                 compatible = "qcom,smp2p";
 488                 qcom,smem = <443>, <429>;
 489                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
 490                                              IPCC_MPROC_SIGNAL_SMP2P
 491                                              IRQ_TYPE_EDGE_RISING>;
 492                 mboxes = <&ipcc IPCC_CLIENT_LPASS
 493                                 IPCC_MPROC_SIGNAL_SMP2P>;
 494
 495                 qcom,local-pid = <0>;
 496                 qcom,remote-pid = <2>;
 497
 498                 smp2p_adsp_out: master-kernel {
 499                         qcom,entry-name = "master-kernel";
 500                         #qcom,smem-state-cells = <1>;
 501                 };
 502
 503                 smp2p_adsp_in: slave-kernel {
 504                         qcom,entry-name = "slave-kernel";
 505                         interrupt-controller;
 506                         #interrupt-cells = <2>;
 507                 };
 508         };
 509
 510         smp2p-cdsp {
 511                 compatible = "qcom,smp2p";
 512                 qcom,smem = <94>, <432>;
 513                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
 514                                              IPCC_MPROC_SIGNAL_SMP2P
 515                                              IRQ_TYPE_EDGE_RISING>;
 516                 mboxes = <&ipcc IPCC_CLIENT_CDSP
 517                                 IPCC_MPROC_SIGNAL_SMP2P>;
 518
 519                 qcom,local-pid = <0>;
 520                 qcom,remote-pid = <5>;
 521
 522                 smp2p_cdsp_out: master-kernel {
 523                         qcom,entry-name = "master-kernel";
 524                         #qcom,smem-state-cells = <1>;
 525                 };
 526
 527                 smp2p_cdsp_in: slave-kernel {
 528                         qcom,entry-name = "slave-kernel";
 529                         interrupt-controller;
 530                         #interrupt-cells = <2>;
 531                 };
 532         };
 533
 534         smp2p-modem {
 535                 compatible = "qcom,smp2p";
 536                 qcom,smem = <435>, <428>;
 537                 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
 538                                              IPCC_MPROC_SIGNAL_SMP2P
 539                                              IRQ_TYPE_EDGE_RISING>;
 540                 mboxes = <&ipcc IPCC_CLIENT_MPSS
 541                                 IPCC_MPROC_SIGNAL_SMP2P>;
 542
 543                 qcom,local-pid = <0>;
 544                 qcom,remote-pid = <1>;
 545
 546                 smp2p_modem_out: master-kernel {
 547                         qcom,entry-name = "master-kernel";
 548                         #qcom,smem-state-cells = <1>;
 549                 };
 550
 551                 smp2p_modem_in: slave-kernel {
 552                         qcom,entry-name = "slave-kernel";
 553                         interrupt-controller;
 554                         #interrupt-cells = <2>;
 555                 };
 556
 557                 ipa_smp2p_out: ipa-ap-to-modem {
 558                         qcom,entry-name = "ipa";
 559                         #qcom,smem-state-cells = <1>;
 560                 };
 561
 562                 ipa_smp2p_in: ipa-modem-to-ap {
 563                         qcom,entry-name = "ipa";
 564                         interrupt-controller;
 565                         #interrupt-cells = <2>;
 566                 };
 567         };
 568
 569         smp2p-slpi {
 570                 compatible = "qcom,smp2p";
 571                 qcom,smem = <481>, <430>;
 572                 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
 573                                              IPCC_MPROC_SIGNAL_SMP2P
 574                                              IRQ_TYPE_EDGE_RISING>;
 575                 mboxes = <&ipcc IPCC_CLIENT_SLPI
 576                                 IPCC_MPROC_SIGNAL_SMP2P>;
 577
 578                 qcom,local-pid = <0>;
 579                 qcom,remote-pid = <3>;
 580
 581                 smp2p_slpi_out: master-kernel {
 582                         qcom,entry-name = "master-kernel";
 583                         #qcom,smem-state-cells = <1>;
 584                 };
 585
 586                 smp2p_slpi_in: slave-kernel {
 587                         qcom,entry-name = "slave-kernel";
 588                         interrupt-controller;
 589                         #interrupt-cells = <2>;
 590                 };
 591         };
 592
 593         soc: soc@0 {
 594                 #address-cells = <2>;
 595                 #size-cells = <2>;
 596                 ranges = <0 0 0 0 0x10 0>;
 597                 dma-ranges = <0 0 0 0 0x10 0>;
 598                 compatible = "simple-bus";
 599
 600                 gcc: clock-controller@100000 {
 601                         compatible = "qcom,gcc-sm8350";
 602                         reg = <0x0 0x00100000 0x0 0x1f0000>;
 603                         #clock-cells = <1>;
 604                         #reset-cells = <1>;
 605                         #power-domain-cells = <1>;
 606                         clock-names = "bi_tcxo",
 607                                       "sleep_clk",
 608                                       "pcie_0_pipe_clk",
 609                                       "pcie_1_pipe_clk",
 610                                       "ufs_card_rx_symbol_0_clk",
 611                                       "ufs_card_rx_symbol_1_clk",
 612                                       "ufs_card_tx_symbol_0_clk",
 613                                       "ufs_phy_rx_symbol_0_clk",
 614                                       "ufs_phy_rx_symbol_1_clk",
 615                                       "ufs_phy_tx_symbol_0_clk",
 616                                       "usb3_phy_wrapper_gcc_usb30_pipe_clk",
 617                                       "usb3_uni_phy_sec_gcc_usb30_pipe_clk";
 618                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 619                                  <&sleep_clk>,
 620                                  <0>,
 621                                  <0>,
 622                                  <0>,
 623                                  <0>,
 624                                  <0>,
 625                                  <&ufs_phy_rx_symbol_0_clk>,
 626                                  <&ufs_phy_rx_symbol_1_clk>,
 627                                  <&ufs_phy_tx_symbol_0_clk>,
 628                                  <0>,
 629                                  <0>;
 630                 };
 631
 632                 ipcc: mailbox@408000 {
 633                         compatible = "qcom,sm8350-ipcc", "qcom,ipcc";
 634                         reg = <0 0x00408000 0 0x1000>;
 635                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
 636                         interrupt-controller;
 637                         #interrupt-cells = <3>;
 638                         #mbox-cells = <2>;
 639                 };
 640
 641                 qup_opp_table_100mhz: qup-100mhz-opp-table {
 642                         compatible = "operating-points-v2";
 643
 644                         opp-50000000 {
 645                                 opp-hz = /bits/ 64 <50000000>;
 646                                 required-opps = <&rpmhpd_opp_min_svs>;
 647                         };
 648
 649                         opp-75000000 {
 650                                 opp-hz = /bits/ 64 <75000000>;
 651                                 required-opps = <&rpmhpd_opp_low_svs>;
 652                         };
 653
 654                         opp-100000000 {
 655                                 opp-hz = /bits/ 64 <100000000>;
 656                                 required-opps = <&rpmhpd_opp_svs>;
 657                         };
 658                 };
 659
 660                 qup_opp_table_120mhz: qup-120mhz-opp-table {
 661                         compatible = "operating-points-v2";
 662
 663                         opp-50000000 {
 664                                 opp-hz = /bits/ 64 <50000000>;
 665                                 required-opps = <&rpmhpd_opp_min_svs>;
 666                         };
 667
 668                         opp-75000000 {
 669                                 opp-hz = /bits/ 64 <75000000>;
 670                                 required-opps = <&rpmhpd_opp_low_svs>;
 671                         };
 672
 673                         opp-120000000 {
 674                                 opp-hz = /bits/ 64 <120000000>;
 675                                 required-opps = <&rpmhpd_opp_svs>;
 676                         };
 677                 };
 678
 679                 gpi_dma2: dma-controller@800000 {
 680                         compatible = "qcom,sm8350-gpi-dma";
 681                         reg = <0 0x00800000 0 0x60000>;
 682                         interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
 683                                      <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
 684                                      <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
 685                                      <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
 686                                      <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
 687                                      <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
 688                                      <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
 689                                      <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
 690                                      <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
 691                                      <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
 692                                      <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
 693                                      <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
 694                         dma-channels = <12>;
 695                         dma-channel-mask = <0xff>;
 696                         iommus = <&apps_smmu 0x5f6 0x0>;
 697                         #dma-cells = <3>;
 698                         status = "disabled";
 699                 };
 700
 701                 qupv3_id_2: geniqup@8c0000 {
 702                         compatible = "qcom,geni-se-qup";
 703                         reg = <0x0 0x008c0000 0x0 0x6000>;
 704                         clock-names = "m-ahb", "s-ahb";
 705                         clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
 706                                  <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
 707                         iommus = <&apps_smmu 0x5e3 0x0>;
 708                         #address-cells = <2>;
 709                         #size-cells = <2>;
 710                         ranges;
 711                         status = "disabled";
 712
 713                         i2c14: i2c@880000 {
 714                                 compatible = "qcom,geni-i2c";
 715                                 reg = <0 0x00880000 0 0x4000>;
 716                                 clock-names = "se";
 717                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
 718                                 pinctrl-names = "default";
 719                                 pinctrl-0 = <&qup_i2c14_default>;
 720                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
 721                                 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
 722                                        <&gpi_dma2 1 0 QCOM_GPI_I2C>;
 723                                 dma-names = "tx", "rx";
 724                                 #address-cells = <1>;
 725                                 #size-cells = <0>;
 726                                 status = "disabled";
 727                         };
 728
 729                         spi14: spi@880000 {
 730                                 compatible = "qcom,geni-spi";
 731                                 reg = <0 0x00880000 0 0x4000>;
 732                                 clock-names = "se";
 733                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
 734                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
 735                                 power-domains = <&rpmhpd SM8350_CX>;
 736                                 operating-points-v2 = <&qup_opp_table_120mhz>;
 737                                 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
 738                                        <&gpi_dma2 1 0 QCOM_GPI_SPI>;
 739                                 dma-names = "tx", "rx";
 740                                 #address-cells = <1>;
 741                                 #size-cells = <0>;
 742                                 status = "disabled";
 743                         };
 744
 745                         i2c15: i2c@884000 {
 746                                 compatible = "qcom,geni-i2c";
 747                                 reg = <0 0x00884000 0 0x4000>;
 748                                 clock-names = "se";
 749                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
 750                                 pinctrl-names = "default";
 751                                 pinctrl-0 = <&qup_i2c15_default>;
 752                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
 753                                 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
 754                                        <&gpi_dma2 1 1 QCOM_GPI_I2C>;
 755                                 dma-names = "tx", "rx";
 756                                 #address-cells = <1>;
 757                                 #size-cells = <0>;
 758                                 status = "disabled";
 759                         };
 760
 761                         spi15: spi@884000 {
 762                                 compatible = "qcom,geni-spi";
 763                                 reg = <0 0x00884000 0 0x4000>;
 764                                 clock-names = "se";
 765                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
 766                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
 767                                 power-domains = <&rpmhpd SM8350_CX>;
 768                                 operating-points-v2 = <&qup_opp_table_120mhz>;
 769                                 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
 770                                        <&gpi_dma2 1 1 QCOM_GPI_SPI>;
 771                                 dma-names = "tx", "rx";
 772                                 #address-cells = <1>;
 773                                 #size-cells = <0>;
 774                                 status = "disabled";
 775                         };
 776
 777                         i2c16: i2c@888000 {
 778                                 compatible = "qcom,geni-i2c";
 779                                 reg = <0 0x00888000 0 0x4000>;
 780                                 clock-names = "se";
 781                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
 782                                 pinctrl-names = "default";
 783                                 pinctrl-0 = <&qup_i2c16_default>;
 784                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
 785                                 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
 786                                        <&gpi_dma2 1 2 QCOM_GPI_I2C>;
 787                                 dma-names = "tx", "rx";
 788                                 #address-cells = <1>;
 789                                 #size-cells = <0>;
 790                                 status = "disabled";
 791                         };
 792
 793                         spi16: spi@888000 {
 794                                 compatible = "qcom,geni-spi";
 795                                 reg = <0 0x00888000 0 0x4000>;
 796                                 clock-names = "se";
 797                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
 798                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
 799                                 power-domains = <&rpmhpd SM8350_CX>;
 800                                 operating-points-v2 = <&qup_opp_table_100mhz>;
 801                                 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
 802                                        <&gpi_dma2 1 2 QCOM_GPI_SPI>;
 803                                 dma-names = "tx", "rx";
 804                                 #address-cells = <1>;
 805                                 #size-cells = <0>;
 806                                 status = "disabled";
 807                         };
 808
 809                         i2c17: i2c@88c000 {
 810                                 compatible = "qcom,geni-i2c";
 811                                 reg = <0 0x0088c000 0 0x4000>;
 812                                 clock-names = "se";
 813                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
 814                                 pinctrl-names = "default";
 815                                 pinctrl-0 = <&qup_i2c17_default>;
 816                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
 817                                 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
 818                                        <&gpi_dma2 1 3 QCOM_GPI_I2C>;
 819                                 dma-names = "tx", "rx";
 820                                 #address-cells = <1>;
 821                                 #size-cells = <0>;
 822                                 status = "disabled";
 823                         };
 824
 825                         spi17: spi@88c000 {
 826                                 compatible = "qcom,geni-spi";
 827                                 reg = <0 0x0088c000 0 0x4000>;
 828                                 clock-names = "se";
 829                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
 830                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
 831                                 power-domains = <&rpmhpd SM8350_CX>;
 832                                 operating-points-v2 = <&qup_opp_table_100mhz>;
 833                                 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
 834                                        <&gpi_dma2 1 3 QCOM_GPI_SPI>;
 835                                 dma-names = "tx", "rx";
 836                                 #address-cells = <1>;
 837                                 #size-cells = <0>;
 838                                 status = "disabled";
 839                         };
 840
 841                         /* QUP no. 18 seems to be strictly SPI/UART-only */
 842
 843                         spi18: spi@890000 {
 844                                 compatible = "qcom,geni-spi";
 845                                 reg = <0 0x00890000 0 0x4000>;
 846                                 clock-names = "se";
 847                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
 848                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
 849                                 power-domains = <&rpmhpd SM8350_CX>;
 850                                 operating-points-v2 = <&qup_opp_table_100mhz>;
 851                                 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
 852                                        <&gpi_dma2 1 4 QCOM_GPI_SPI>;
 853                                 dma-names = "tx", "rx";
 854                                 #address-cells = <1>;
 855                                 #size-cells = <0>;
 856                                 status = "disabled";
 857                         };
 858
 859                         uart18: serial@890000 {
 860                                 compatible = "qcom,geni-uart";
 861                                 reg = <0 0x00890000 0 0x4000>;
 862                                 clock-names = "se";
 863                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
 864                                 pinctrl-names = "default";
 865                                 pinctrl-0 = <&qup_uart18_default>;
 866                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
 867                                 power-domains = <&rpmhpd SM8350_CX>;
 868                                 operating-points-v2 = <&qup_opp_table_100mhz>;
 869                                 status = "disabled";
 870                         };
 871
 872                         i2c19: i2c@894000 {
 873                                 compatible = "qcom,geni-i2c";
 874                                 reg = <0 0x00894000 0 0x4000>;
 875                                 clock-names = "se";
 876                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
 877                                 pinctrl-names = "default";
 878                                 pinctrl-0 = <&qup_i2c19_default>;
 879                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
 880                                 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
 881                                        <&gpi_dma2 1 5 QCOM_GPI_I2C>;
 882                                 dma-names = "tx", "rx";
 883                                 #address-cells = <1>;
 884                                 #size-cells = <0>;
 885                                 status = "disabled";
 886                         };
 887
 888                         spi19: spi@894000 {
 889                                 compatible = "qcom,geni-spi";
 890                                 reg = <0 0x00894000 0 0x4000>;
 891                                 clock-names = "se";
 892                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
 893                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
 894                                 power-domains = <&rpmhpd SM8350_CX>;
 895                                 operating-points-v2 = <&qup_opp_table_100mhz>;
 896                                 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
 897                                        <&gpi_dma2 1 5 QCOM_GPI_SPI>;
 898                                 dma-names = "tx", "rx";
 899                                 #address-cells = <1>;
 900                                 #size-cells = <0>;
 901                                 status = "disabled";
 902                         };
 903                 };
 904
 905                 gpi_dma0: dma-controller@900000 {
 906                         compatible = "qcom,sm8350-gpi-dma";
 907                         reg = <0 0x09800000 0 0x60000>;
 908                         interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
 909                                      <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
 910                                      <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
 911                                      <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
 912                                      <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
 913                                      <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
 914                                      <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
 915                                      <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
 916                                      <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
 917                                      <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
 918                                      <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
 919                                      <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
 920                         dma-channels = <12>;
 921                         dma-channel-mask = <0x7e>;
 922                         iommus = <&apps_smmu 0x5b6 0x0>;
 923                         #dma-cells = <3>;
 924                         status = "disabled";
 925                 };
 926
 927                 qupv3_id_0: geniqup@9c0000 {
 928                         compatible = "qcom,geni-se-qup";
 929                         reg = <0x0 0x009c0000 0x0 0x6000>;
 930                         clock-names = "m-ahb", "s-ahb";
 931                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
 932                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
 933                         iommus = <&apps_smmu 0x5a3 0>;
 934                         #address-cells = <2>;
 935                         #size-cells = <2>;
 936                         ranges;
 937                         status = "disabled";
 938
 939                         i2c0: i2c@980000 {
 940                                 compatible = "qcom,geni-i2c";
 941                                 reg = <0 0x00980000 0 0x4000>;
 942                                 clock-names = "se";
 943                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 944                                 pinctrl-names = "default";
 945                                 pinctrl-0 = <&qup_i2c0_default>;
 946                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 947                                 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
 948                                        <&gpi_dma0 1 0 QCOM_GPI_I2C>;
 949                                 dma-names = "tx", "rx";
 950                                 #address-cells = <1>;
 951                                 #size-cells = <0>;
 952                                 status = "disabled";
 953                         };
 954
 955                         spi0: spi@980000 {
 956                                 compatible = "qcom,geni-spi";
 957                                 reg = <0 0x00980000 0 0x4000>;
 958                                 clock-names = "se";
 959                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 960                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 961                                 power-domains = <&rpmhpd SM8350_CX>;
 962                                 operating-points-v2 = <&qup_opp_table_100mhz>;
 963                                 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
 964                                        <&gpi_dma0 1 0 QCOM_GPI_SPI>;
 965                                 dma-names = "tx", "rx";
 966                                 #address-cells = <1>;
 967                                 #size-cells = <0>;
 968                                 status = "disabled";
 969                         };
 970
 971                         i2c1: i2c@984000 {
 972                                 compatible = "qcom,geni-i2c";
 973                                 reg = <0 0x00984000 0 0x4000>;
 974                                 clock-names = "se";
 975                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 976                                 pinctrl-names = "default";
 977                                 pinctrl-0 = <&qup_i2c1_default>;
 978                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 979                                 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
 980                                        <&gpi_dma0 1 1 QCOM_GPI_I2C>;
 981                                 dma-names = "tx", "rx";
 982                                 #address-cells = <1>;
 983                                 #size-cells = <0>;
 984                                 status = "disabled";
 985                         };
 986
 987                         spi1: spi@984000 {
 988                                 compatible = "qcom,geni-spi";
 989                                 reg = <0 0x00984000 0 0x4000>;
 990                                 clock-names = "se";
 991                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 992                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 993                                 power-domains = <&rpmhpd SM8350_CX>;
 994                                 operating-points-v2 = <&qup_opp_table_100mhz>;
 995                                 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
 996                                        <&gpi_dma0 1 1 QCOM_GPI_SPI>;
 997                                 dma-names = "tx", "rx";
 998                                 #address-cells = <1>;
 999                                 #size-cells = <0>;
1000                                 status = "disabled";
1001                         };
1002
1003                         i2c2: i2c@988000 {
1004                                 compatible = "qcom,geni-i2c";
1005                                 reg = <0 0x00988000 0 0x4000>;
1006                                 clock-names = "se";
1007                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1008                                 pinctrl-names = "default";
1009                                 pinctrl-0 = <&qup_i2c2_default>;
1010                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1011                                 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1012                                        <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1013                                 dma-names = "tx", "rx";
1014                                 #address-cells = <1>;
1015                                 #size-cells = <0>;
1016                                 status = "disabled";
1017                         };
1018
1019                         spi2: spi@988000 {
1020                                 compatible = "qcom,geni-spi";
1021                                 reg = <0 0x00988000 0 0x4000>;
1022                                 clock-names = "se";
1023                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1024                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1025                                 power-domains = <&rpmhpd SM8350_CX>;
1026                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1027                                 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1028                                        <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1029                                 dma-names = "tx", "rx";
1030                                 #address-cells = <1>;
1031                                 #size-cells = <0>;
1032                                 status = "disabled";
1033                         };
1034
1035                         uart2: serial@98c000 {
1036                                 compatible = "qcom,geni-debug-uart";
1037                                 reg = <0 0x0098c000 0 0x4000>;
1038                                 clock-names = "se";
1039                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1040                                 pinctrl-names = "default";
1041                                 pinctrl-0 = <&qup_uart3_default_state>;
1042                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1043                                 power-domains = <&rpmhpd SM8350_CX>;
1044                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1045                                 #address-cells = <1>;
1046                                 #size-cells = <0>;
1047                                 status = "disabled";
1048                         };
1049
1050                         /* QUP no. 3 seems to be strictly SPI-only */
1051
1052                         spi3: spi@98c000 {
1053                                 compatible = "qcom,geni-spi";
1054                                 reg = <0 0x0098c000 0 0x4000>;
1055                                 clock-names = "se";
1056                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1057                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1058                                 power-domains = <&rpmhpd SM8350_CX>;
1059                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1060                                 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1061                                        <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1062                                 dma-names = "tx", "rx";
1063                                 #address-cells = <1>;
1064                                 #size-cells = <0>;
1065                                 status = "disabled";
1066                         };
1067
1068                         i2c4: i2c@990000 {
1069                                 compatible = "qcom,geni-i2c";
1070                                 reg = <0 0x00990000 0 0x4000>;
1071                                 clock-names = "se";
1072                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1073                                 pinctrl-names = "default";
1074                                 pinctrl-0 = <&qup_i2c4_default>;
1075                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1076                                 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1077                                        <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1078                                 dma-names = "tx", "rx";
1079                                 #address-cells = <1>;
1080                                 #size-cells = <0>;
1081                                 status = "disabled";
1082                         };
1083
1084                         spi4: spi@990000 {
1085                                 compatible = "qcom,geni-spi";
1086                                 reg = <0 0x00990000 0 0x4000>;
1087                                 clock-names = "se";
1088                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1089                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1090                                 power-domains = <&rpmhpd SM8350_CX>;
1091                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1092                                 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1093                                        <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1094                                 dma-names = "tx", "rx";
1095                                 #address-cells = <1>;
1096                                 #size-cells = <0>;
1097                                 status = "disabled";
1098                         };
1099
1100                         i2c5: i2c@994000 {
1101                                 compatible = "qcom,geni-i2c";
1102                                 reg = <0 0x00994000 0 0x4000>;
1103                                 clock-names = "se";
1104                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1105                                 pinctrl-names = "default";
1106                                 pinctrl-0 = <&qup_i2c5_default>;
1107                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1108                                 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1109                                        <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1110                                 dma-names = "tx", "rx";
1111                                 #address-cells = <1>;
1112                                 #size-cells = <0>;
1113                                 status = "disabled";
1114                         };
1115
1116                         spi5: spi@994000 {
1117                                 compatible = "qcom,geni-spi";
1118                                 reg = <0 0x00994000 0 0x4000>;
1119                                 clock-names = "se";
1120                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1121                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1122                                 power-domains = <&rpmhpd SM8350_CX>;
1123                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1124                                 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1125                                        <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1126                                 dma-names = "tx", "rx";
1127                                 #address-cells = <1>;
1128                                 #size-cells = <0>;
1129                                 status = "disabled";
1130                         };
1131
1132                         i2c6: i2c@998000 {
1133                                 compatible = "qcom,geni-i2c";
1134                                 reg = <0 0x00998000 0 0x4000>;
1135                                 clock-names = "se";
1136                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1137                                 pinctrl-names = "default";
1138                                 pinctrl-0 = <&qup_i2c6_default>;
1139                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1140                                 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1141                                        <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1142                                 dma-names = "tx", "rx";
1143                                 #address-cells = <1>;
1144                                 #size-cells = <0>;
1145                                 status = "disabled";
1146                         };
1147
1148                         spi6: spi@998000 {
1149                                 compatible = "qcom,geni-spi";
1150                                 reg = <0 0x00998000 0 0x4000>;
1151                                 clock-names = "se";
1152                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1153                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1154                                 power-domains = <&rpmhpd SM8350_CX>;
1155                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1156                                 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1157                                        <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1158                                 dma-names = "tx", "rx";
1159                                 #address-cells = <1>;
1160                                 #size-cells = <0>;
1161                                 status = "disabled";
1162                         };
1163
1164                         uart6: serial@998000 {
1165                                 compatible = "qcom,geni-uart";
1166                                 reg = <0 0x00998000 0 0x4000>;
1167                                 clock-names = "se";
1168                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1169                                 pinctrl-names = "default";
1170                                 pinctrl-0 = <&qup_uart6_default>;
1171                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1172                                 power-domains = <&rpmhpd SM8350_CX>;
1173                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1174                                 status = "disabled";
1175                         };
1176
1177                         i2c7: i2c@99c000 {
1178                                 compatible = "qcom,geni-i2c";
1179                                 reg = <0 0x0099c000 0 0x4000>;
1180                                 clock-names = "se";
1181                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1182                                 pinctrl-names = "default";
1183                                 pinctrl-0 = <&qup_i2c7_default>;
1184                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1185                                 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1186                                        <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1187                                 dma-names = "tx", "rx";
1188                                 #address-cells = <1>;
1189                                 #size-cells = <0>;
1190                                 status = "disabled";
1191                         };
1192
1193                         spi7: spi@99c000 {
1194                                 compatible = "qcom,geni-spi";
1195                                 reg = <0 0x0099c000 0 0x4000>;
1196                                 clock-names = "se";
1197                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1198                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1199                                 power-domains = <&rpmhpd SM8350_CX>;
1200                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1201                                 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1202                                        <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1203                                 dma-names = "tx", "rx";
1204                                 #address-cells = <1>;
1205                                 #size-cells = <0>;
1206                                 status = "disabled";
1207                         };
1208                 };
1209
1210                 gpi_dma1: dma-controller@a00000 {
1211                         compatible = "qcom,sm8350-gpi-dma";
1212                         reg = <0 0x00a00000 0 0x60000>;
1213                         interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1214                                      <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1215                                      <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1216                                      <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1217                                      <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1218                                      <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1219                                      <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1220                                      <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1221                                      <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1222                                      <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1223                                      <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1224                                      <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
1225                         dma-channels = <12>;
1226                         dma-channel-mask = <0xff>;
1227                         iommus = <&apps_smmu 0x56 0x0>;
1228                         #dma-cells = <3>;
1229                         status = "disabled";
1230                 };
1231
1232                 qupv3_id_1: geniqup@ac0000 {
1233                         compatible = "qcom,geni-se-qup";
1234                         reg = <0x0 0x00ac0000 0x0 0x6000>;
1235                         clock-names = "m-ahb", "s-ahb";
1236                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1237                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1238                         iommus = <&apps_smmu 0x43 0>;
1239                         #address-cells = <2>;
1240                         #size-cells = <2>;
1241                         ranges;
1242                         status = "disabled";
1243
1244                         i2c8: i2c@a80000 {
1245                                 compatible = "qcom,geni-i2c";
1246                                 reg = <0 0x00a80000 0 0x4000>;
1247                                 clock-names = "se";
1248                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1249                                 pinctrl-names = "default";
1250                                 pinctrl-0 = <&qup_i2c8_default>;
1251                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1252                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1253                                        <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1254                                 dma-names = "tx", "rx";
1255                                 #address-cells = <1>;
1256                                 #size-cells = <0>;
1257                                 status = "disabled";
1258                         };
1259
1260                         spi8: spi@a80000 {
1261                                 compatible = "qcom,geni-spi";
1262                                 reg = <0 0x00a80000 0 0x4000>;
1263                                 clock-names = "se";
1264                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1265                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1266                                 power-domains = <&rpmhpd SM8350_CX>;
1267                                 operating-points-v2 = <&qup_opp_table_120mhz>;
1268                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1269                                        <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1270                                 dma-names = "tx", "rx";
1271                                 #address-cells = <1>;
1272                                 #size-cells = <0>;
1273                                 status = "disabled";
1274                         };
1275
1276                         i2c9: i2c@a84000 {
1277                                 compatible = "qcom,geni-i2c";
1278                                 reg = <0 0x00a84000 0 0x4000>;
1279                                 clock-names = "se";
1280                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1281                                 pinctrl-names = "default";
1282                                 pinctrl-0 = <&qup_i2c9_default>;
1283                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1284                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1285                                        <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1286                                 dma-names = "tx", "rx";
1287                                 #address-cells = <1>;
1288                                 #size-cells = <0>;
1289                                 status = "disabled";
1290                         };
1291
1292                         spi9: spi@a84000 {
1293                                 compatible = "qcom,geni-spi";
1294                                 reg = <0 0x00a84000 0 0x4000>;
1295                                 clock-names = "se";
1296                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1297                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1298                                 power-domains = <&rpmhpd SM8350_CX>;
1299                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1300                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1301                                        <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1302                                 dma-names = "tx", "rx";
1303                                 #address-cells = <1>;
1304                                 #size-cells = <0>;
1305                                 status = "disabled";
1306                         };
1307
1308                         i2c10: i2c@a88000 {
1309                                 compatible = "qcom,geni-i2c";
1310                                 reg = <0 0x00a88000 0 0x4000>;
1311                                 clock-names = "se";
1312                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1313                                 pinctrl-names = "default";
1314                                 pinctrl-0 = <&qup_i2c10_default>;
1315                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1316                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1317                                        <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1318                                 dma-names = "tx", "rx";
1319                                 #address-cells = <1>;
1320                                 #size-cells = <0>;
1321                                 status = "disabled";
1322                         };
1323
1324                         spi10: spi@a88000 {
1325                                 compatible = "qcom,geni-spi";
1326                                 reg = <0 0x00a88000 0 0x4000>;
1327                                 clock-names = "se";
1328                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1329                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1330                                 power-domains = <&rpmhpd SM8350_CX>;
1331                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1332                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1333                                        <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1334                                 dma-names = "tx", "rx";
1335                                 #address-cells = <1>;
1336                                 #size-cells = <0>;
1337                                 status = "disabled";
1338                         };
1339
1340                         i2c11: i2c@a8c000 {
1341                                 compatible = "qcom,geni-i2c";
1342                                 reg = <0 0x00a8c000 0 0x4000>;
1343                                 clock-names = "se";
1344                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1345                                 pinctrl-names = "default";
1346                                 pinctrl-0 = <&qup_i2c11_default>;
1347                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1348                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1349                                        <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1350                                 dma-names = "tx", "rx";
1351                                 #address-cells = <1>;
1352                                 #size-cells = <0>;
1353                                 status = "disabled";
1354                         };
1355
1356                         spi11: spi@a8c000 {
1357                                 compatible = "qcom,geni-spi";
1358                                 reg = <0 0x00a8c000 0 0x4000>;
1359                                 clock-names = "se";
1360                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1361                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1362                                 power-domains = <&rpmhpd SM8350_CX>;
1363                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1364                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1365                                        <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1366                                 dma-names = "tx", "rx";
1367                                 #address-cells = <1>;
1368                                 #size-cells = <0>;
1369                                 status = "disabled";
1370                         };
1371
1372                         i2c12: i2c@a90000 {
1373                                 compatible = "qcom,geni-i2c";
1374                                 reg = <0 0x00a90000 0 0x4000>;
1375                                 clock-names = "se";
1376                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1377                                 pinctrl-names = "default";
1378                                 pinctrl-0 = <&qup_i2c12_default>;
1379                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1380                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1381                                        <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1382                                 dma-names = "tx", "rx";
1383                                 #address-cells = <1>;
1384                                 #size-cells = <0>;
1385                                 status = "disabled";
1386                         };
1387
1388                         spi12: spi@a90000 {
1389                                 compatible = "qcom,geni-spi";
1390                                 reg = <0 0x00a90000 0 0x4000>;
1391                                 clock-names = "se";
1392                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1393                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1394                                 power-domains = <&rpmhpd SM8350_CX>;
1395                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1396                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1397                                        <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1398                                 dma-names = "tx", "rx";
1399                                 #address-cells = <1>;
1400                                 #size-cells = <0>;
1401                                 status = "disabled";
1402                         };
1403
1404                         i2c13: i2c@a94000 {
1405                                 compatible = "qcom,geni-i2c";
1406                                 reg = <0 0x00a94000 0 0x4000>;
1407                                 clock-names = "se";
1408                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1409                                 pinctrl-names = "default";
1410                                 pinctrl-0 = <&qup_i2c13_default>;
1411                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1412                                 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1413                                        <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1414                                 dma-names = "tx", "rx";
1415                                 #address-cells = <1>;
1416                                 #size-cells = <0>;
1417                                 status = "disabled";
1418                         };
1419
1420                         spi13: spi@a94000 {
1421                                 compatible = "qcom,geni-spi";
1422                                 reg = <0 0x00a94000 0 0x4000>;
1423                                 clock-names = "se";
1424                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1425                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1426                                 power-domains = <&rpmhpd SM8350_CX>;
1427                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1428                                 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1429                                        <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1430                                 dma-names = "tx", "rx";
1431                                 #address-cells = <1>;
1432                                 #size-cells = <0>;
1433                                 status = "disabled";
1434                         };
1435                 };
1436
1437                 apps_smmu: iommu@15000000 {
1438                         compatible = "qcom,sm8350-smmu-500", "arm,mmu-500";
1439                         reg = <0 0x15000000 0 0x100000>;
1440                         #iommu-cells = <2>;
1441                         #global-interrupts = <2>;
1442                         interrupts =    <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
1443                                         <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
1444                                         <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
1445                                         <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1446                                         <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
1447                                         <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1448                                         <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1449                                         <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1450                                         <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1451                                         <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1452                                         <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1453                                         <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1454                                         <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
1455                                         <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1456                                         <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1457                                         <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1458                                         <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
1459                                         <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
1460                                         <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1461                                         <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1462                                         <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1463                                         <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1464                                         <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1465                                         <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1466                                         <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
1467                                         <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
1468                                         <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
1469                                         <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
1470                                         <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
1471                                         <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
1472                                         <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
1473                                         <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
1474                                         <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
1475                                         <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
1476                                         <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
1477                                         <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
1478                                         <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
1479                                         <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
1480                                         <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
1481                                         <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
1482                                         <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
1483                                         <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1484                                         <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
1485                                         <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
1486                                         <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
1487                                         <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
1488                                         <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
1489                                         <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
1490                                         <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
1491                                         <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
1492                                         <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1493                                         <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1494                                         <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
1495                                         <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
1496                                         <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
1497                                         <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1498                                         <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1499                                         <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1500                                         <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
1501                                         <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
1502                                         <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
1503                                         <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
1504                                         <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
1505                                         <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
1506                                         <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
1507                                         <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
1508                                         <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
1509                                         <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
1510                                         <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
1511                                         <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
1512                                         <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
1513                                         <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
1514                                         <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
1515                                         <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
1516                                         <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
1517                                         <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
1518                                         <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
1519                                         <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
1520                                         <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
1521                                         <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
1522                                         <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
1523                                         <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
1524                                         <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
1525                                         <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
1526                                         <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
1527                                         <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
1528                                         <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
1529                                         <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
1530                                         <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
1531                                         <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
1532                                         <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
1533                                         <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
1534                                         <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
1535                                         <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
1536                                         <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
1537                                         <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
1538                                         <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
1539                                         <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
1540                 };
1541
1542                 config_noc: interconnect@1500000 {
1543                         compatible = "qcom,sm8350-config-noc";
1544                         reg = <0 0x01500000 0 0xa580>;
1545                         #interconnect-cells = <1>;
1546                         qcom,bcm-voters = <&apps_bcm_voter>;
1547                 };
1548
1549                 mc_virt: interconnect@1580000 {
1550                         compatible = "qcom,sm8350-mc-virt";
1551                         reg = <0 0x01580000 0 0x1000>;
1552                         #interconnect-cells = <1>;
1553                         qcom,bcm-voters = <&apps_bcm_voter>;
1554                 };
1555
1556                 system_noc: interconnect@1680000 {
1557                         compatible = "qcom,sm8350-system-noc";
1558                         reg = <0 0x01680000 0 0x1c200>;
1559                         #interconnect-cells = <1>;
1560                         qcom,bcm-voters = <&apps_bcm_voter>;
1561                 };
1562
1563                 aggre1_noc: interconnect@16e0000 {
1564                         compatible = "qcom,sm8350-aggre1-noc";
1565                         reg = <0 0x016e0000 0 0x1f180>;
1566                         #interconnect-cells = <1>;
1567                         qcom,bcm-voters = <&apps_bcm_voter>;
1568                 };
1569
1570                 aggre2_noc: interconnect@1700000 {
1571                         compatible = "qcom,sm8350-aggre2-noc";
1572                         reg = <0 0x01700000 0 0x33000>;
1573                         #interconnect-cells = <1>;
1574                         qcom,bcm-voters = <&apps_bcm_voter>;
1575                 };
1576
1577                 mmss_noc: interconnect@1740000 {
1578                         compatible = "qcom,sm8350-mmss-noc";
1579                         reg = <0 0x01740000 0 0x1f080>;
1580                         #interconnect-cells = <1>;
1581                         qcom,bcm-voters = <&apps_bcm_voter>;
1582                 };
1583
1584                 lpass_ag_noc: interconnect@3c40000 {
1585                         compatible = "qcom,sm8350-lpass-ag-noc";
1586                         reg = <0 0x03c40000 0 0xf080>;
1587                         #interconnect-cells = <1>;
1588                         qcom,bcm-voters = <&apps_bcm_voter>;
1589                 };
1590
1591                 compute_noc: interconnect@a0c0000{
1592                         compatible = "qcom,sm8350-compute-noc";
1593                         reg = <0 0x0a0c0000 0 0xa180>;
1594                         #interconnect-cells = <1>;
1595                         qcom,bcm-voters = <&apps_bcm_voter>;
1596                 };
1597
1598                 ipa: ipa@1e40000 {
1599                         compatible = "qcom,sm8350-ipa";
1600
1601                         iommus = <&apps_smmu 0x5c0 0x0>,
1602                                  <&apps_smmu 0x5c2 0x0>;
1603                         reg = <0 0x1e40000 0 0x8000>,
1604                               <0 0x1e50000 0 0x4b20>,
1605                               <0 0x1e04000 0 0x23000>;
1606                         reg-names = "ipa-reg",
1607                                     "ipa-shared",
1608                                     "gsi";
1609
1610                         interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>,
1611                                               <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
1612                                               <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1613                                               <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
1614                         interrupt-names = "ipa",
1615                                           "gsi",
1616                                           "ipa-clock-query",
1617                                           "ipa-setup-ready";
1618
1619                         clocks = <&rpmhcc RPMH_IPA_CLK>;
1620                         clock-names = "core";
1621
1622                         interconnects = <&aggre2_noc MASTER_IPA &mc_virt SLAVE_EBI1>,
1623                                         <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_IPA_CFG>;
1624                         interconnect-names = "memory",
1625                                              "config";
1626
1627                         qcom,qmp = <&aoss_qmp>;
1628
1629                         qcom,smem-states = <&ipa_smp2p_out 0>,
1630                                            <&ipa_smp2p_out 1>;
1631                         qcom,smem-state-names = "ipa-clock-enabled-valid",
1632                                                 "ipa-clock-enabled";
1633
1634                         status = "disabled";
1635                 };
1636
1637                 tcsr_mutex: hwlock@1f40000 {
1638                         compatible = "qcom,tcsr-mutex";
1639                         reg = <0x0 0x01f40000 0x0 0x40000>;
1640                         #hwlock-cells = <1>;
1641                 };
1642
1643                 mpss: remoteproc@4080000 {
1644                         compatible = "qcom,sm8350-mpss-pas";
1645                         reg = <0x0 0x04080000 0x0 0x4040>;
1646
1647                         interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
1648                                               <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
1649                                               <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
1650                                               <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
1651                                               <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
1652                                               <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
1653                         interrupt-names = "wdog", "fatal", "ready", "handover",
1654                                           "stop-ack", "shutdown-ack";
1655
1656                         clocks = <&rpmhcc RPMH_CXO_CLK>;
1657                         clock-names = "xo";
1658
1659                         power-domains = <&rpmhpd 0>,
1660                                         <&rpmhpd 12>;
1661                         power-domain-names = "cx", "mss";
1662
1663                         interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
1664
1665                         memory-region = <&pil_modem_mem>;
1666
1667                         qcom,qmp = <&aoss_qmp>;
1668
1669                         qcom,smem-states = <&smp2p_modem_out 0>;
1670                         qcom,smem-state-names = "stop";
1671
1672                         status = "disabled";
1673
1674                         glink-edge {
1675                                 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
1676                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
1677                                                              IRQ_TYPE_EDGE_RISING>;
1678                                 mboxes = <&ipcc IPCC_CLIENT_MPSS
1679                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
1680                                 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
1681                                 label = "modem";
1682                                 qcom,remote-pid = <1>;
1683                         };
1684                 };
1685
1686                 pdc: interrupt-controller@b220000 {
1687                         compatible = "qcom,sm8350-pdc", "qcom,pdc";
1688                         reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
1689                         qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,   <55 306 4>,
1690                                           <59 312 3>, <62 374 2>,  <64 434 2>,   <66 438 3>,
1691                                           <69 86 1>,  <70 520 54>, <124 609 31>, <155 63 1>,
1692                                           <156 716 12>;
1693                         #interrupt-cells = <2>;
1694                         interrupt-parent = <&intc>;
1695                         interrupt-controller;
1696                 };
1697
1698                 tsens0: thermal-sensor@c263000 {
1699                         compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
1700                         reg = <0 0x0c263000 0 0x1ff>, /* TM */
1701                               <0 0x0c222000 0 0x8>; /* SROT */
1702                         #qcom,sensors = <15>;
1703                         interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
1704                                      <&pdc 28 IRQ_TYPE_LEVEL_HIGH>;
1705                         interrupt-names = "uplow", "critical";
1706                         #thermal-sensor-cells = <1>;
1707                 };
1708
1709                 tsens1: thermal-sensor@c265000 {
1710                         compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
1711                         reg = <0 0x0c265000 0 0x1ff>, /* TM */
1712                               <0 0x0c223000 0 0x8>; /* SROT */
1713                         #qcom,sensors = <14>;
1714                         interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
1715                                      <&pdc 29 IRQ_TYPE_LEVEL_HIGH>;
1716                         interrupt-names = "uplow", "critical";
1717                         #thermal-sensor-cells = <1>;
1718                 };
1719
1720                 aoss_qmp: power-controller@c300000 {
1721                         compatible = "qcom,sm8350-aoss-qmp";
1722                         reg = <0 0x0c300000 0 0x400>;
1723                         interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
1724                                                      IRQ_TYPE_EDGE_RISING>;
1725                         mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
1726
1727                         #clock-cells = <0>;
1728                 };
1729
1730                 sram@c3f0000 {
1731                         compatible = "qcom,rpmh-stats";
1732                         reg = <0 0x0c3f0000 0 0x400>;
1733                 };
1734
1735                 spmi_bus: spmi@c440000 {
1736                         compatible = "qcom,spmi-pmic-arb";
1737                         reg = <0x0 0xc440000 0x0 0x1100>,
1738                               <0x0 0xc600000 0x0 0x2000000>,
1739                               <0x0 0xe600000 0x0 0x100000>,
1740                               <0x0 0xe700000 0x0 0xa0000>,
1741                               <0x0 0xc40a000 0x0 0x26000>;
1742                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1743                         interrupt-names = "periph_irq";
1744                         interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
1745                         qcom,ee = <0>;
1746                         qcom,channel = <0>;
1747                         #address-cells = <2>;
1748                         #size-cells = <0>;
1749                         interrupt-controller;
1750                         #interrupt-cells = <4>;
1751                 };
1752
1753                 tlmm: pinctrl@f100000 {
1754                         compatible = "qcom,sm8350-tlmm";
1755                         reg = <0 0x0f100000 0 0x300000>;
1756                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1757                         gpio-controller;
1758                         #gpio-cells = <2>;
1759                         interrupt-controller;
1760                         #interrupt-cells = <2>;
1761                         gpio-ranges = <&tlmm 0 0 204>;
1762                         wakeup-parent = <&pdc>;
1763
1764                         qup_uart3_default_state: qup-uart3-default-state {
1765                                 rx {
1766                                         pins = "gpio18";
1767                                         function = "qup3";
1768                                 };
1769                                 tx {
1770                                         pins = "gpio19";
1771                                         function = "qup3";
1772                                 };
1773                         };
1774
1775                         qup_uart6_default: qup-uart6-default {
1776                                 pins = "gpio30", "gpio31";
1777                                 function = "qup6";
1778                                 drive-strength = <2>;
1779                                 bias-disable;
1780                         };
1781
1782                         qup_uart18_default: qup-uart18-default {
1783                                 pins = "gpio58", "gpio59";
1784                                 function = "qup18";
1785                                 drive-strength = <2>;
1786                                 bias-disable;
1787                         };
1788
1789                         qup_i2c0_default: qup-i2c0-default {
1790                                 pins = "gpio4", "gpio5";
1791                                 function = "qup0";
1792                                 drive-strength = <2>;
1793                                 bias-pull-up;
1794                         };
1795
1796                         qup_i2c1_default: qup-i2c1-default {
1797                                 pins = "gpio8", "gpio9";
1798                                 function = "qup1";
1799                                 drive-strength = <2>;
1800                                 bias-pull-up;
1801                         };
1802
1803                         qup_i2c2_default: qup-i2c2-default {
1804                                 pins = "gpio12", "gpio13";
1805                                 function = "qup2";
1806                                 drive-strength = <2>;
1807                                 bias-pull-up;
1808                         };
1809
1810                         qup_i2c4_default: qup-i2c4-default {
1811                                 pins = "gpio20", "gpio21";
1812                                 function = "qup4";
1813                                 drive-strength = <2>;
1814                                 bias-pull-up;
1815                         };
1816
1817                         qup_i2c5_default: qup-i2c5-default {
1818                                 pins = "gpio24", "gpio25";
1819                                 function = "qup5";
1820                                 drive-strength = <2>;
1821                                 bias-pull-up;
1822                         };
1823
1824                         qup_i2c6_default: qup-i2c6-default {
1825                                 pins = "gpio28", "gpio29";
1826                                 function = "qup6";
1827                                 drive-strength = <2>;
1828                                 bias-pull-up;
1829                         };
1830
1831                         qup_i2c7_default: qup-i2c7-default {
1832                                 pins = "gpio32", "gpio33";
1833                                 function = "qup7";
1834                                 drive-strength = <2>;
1835                                 bias-disable;
1836                         };
1837
1838                         qup_i2c8_default: qup-i2c8-default {
1839                                 pins = "gpio36", "gpio37";
1840                                 function = "qup8";
1841                                 drive-strength = <2>;
1842                                 bias-pull-up;
1843                         };
1844
1845                         qup_i2c9_default: qup-i2c9-default {
1846                                 pins = "gpio40", "gpio41";
1847                                 function = "qup9";
1848                                 drive-strength = <2>;
1849                                 bias-pull-up;
1850                         };
1851
1852                         qup_i2c10_default: qup-i2c10-default {
1853                                 pins = "gpio44", "gpio45";
1854                                 function = "qup10";
1855                                 drive-strength = <2>;
1856                                 bias-pull-up;
1857                         };
1858
1859                         qup_i2c11_default: qup-i2c11-default {
1860                                 pins = "gpio48", "gpio49";
1861                                 function = "qup11";
1862                                 drive-strength = <2>;
1863                                 bias-pull-up;
1864                         };
1865
1866                         qup_i2c12_default: qup-i2c12-default {
1867                                 pins = "gpio52", "gpio53";
1868                                 function = "qup12";
1869                                 drive-strength = <2>;
1870                                 bias-pull-up;
1871                         };
1872
1873                         qup_i2c13_default: qup-i2c13-default {
1874                                 pins = "gpio0", "gpio1";
1875                                 function = "qup13";
1876                                 drive-strength = <2>;
1877                                 bias-pull-up;
1878                         };
1879
1880                         qup_i2c14_default: qup-i2c14-default {
1881                                 pins = "gpio56", "gpio57";
1882                                 function = "qup14";
1883                                 drive-strength = <2>;
1884                                 bias-disable;
1885                         };
1886
1887                         qup_i2c15_default: qup-i2c15-default {
1888                                 pins = "gpio60", "gpio61";
1889                                 function = "qup15";
1890                                 drive-strength = <2>;
1891                                 bias-disable;
1892                         };
1893
1894                         qup_i2c16_default: qup-i2c16-default {
1895                                 pins = "gpio64", "gpio65";
1896                                 function = "qup16";
1897                                 drive-strength = <2>;
1898                                 bias-disable;
1899                         };
1900
1901                         qup_i2c17_default: qup-i2c17-default {
1902                                 pins = "gpio72", "gpio73";
1903                                 function = "qup17";
1904                                 drive-strength = <2>;
1905                                 bias-disable;
1906                         };
1907
1908                         qup_i2c19_default: qup-i2c19-default {
1909                                 pins = "gpio76", "gpio77";
1910                                 function = "qup19";
1911                                 drive-strength = <2>;
1912                                 bias-disable;
1913                         };
1914                 };
1915
1916                 rng: rng@10d3000 {
1917                         compatible = "qcom,prng-ee";
1918                         reg = <0 0x010d3000 0 0x1000>;
1919                         clocks = <&rpmhcc RPMH_HWKM_CLK>;
1920                         clock-names = "core";
1921                 };
1922
1923                 intc: interrupt-controller@17a00000 {
1924                         compatible = "arm,gic-v3";
1925                         #interrupt-cells = <3>;
1926                         interrupt-controller;
1927                         #redistributor-regions = <1>;
1928                         redistributor-stride = <0 0x20000>;
1929                         reg = <0x0 0x17a00000 0x0 0x10000>,     /* GICD */
1930                               <0x0 0x17a60000 0x0 0x100000>;    /* GICR * 8 */
1931                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1932                 };
1933
1934                 timer@17c20000 {
1935                         compatible = "arm,armv7-timer-mem";
1936                         #address-cells = <2>;
1937                         #size-cells = <2>;
1938                         ranges;
1939                         reg = <0x0 0x17c20000 0x0 0x1000>;
1940                         clock-frequency = <19200000>;
1941
1942                         frame@17c21000 {
1943                                 frame-number = <0>;
1944                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1945                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1946                                 reg = <0x0 0x17c21000 0x0 0x1000>,
1947                                       <0x0 0x17c22000 0x0 0x1000>;
1948                         };
1949
1950                         frame@17c23000 {
1951                                 frame-number = <1>;
1952                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1953                                 reg = <0x0 0x17c23000 0x0 0x1000>;
1954                                 status = "disabled";
1955                         };
1956
1957                         frame@17c25000 {
1958                                 frame-number = <2>;
1959                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1960                                 reg = <0x0 0x17c25000 0x0 0x1000>;
1961                                 status = "disabled";
1962                         };
1963
1964                         frame@17c27000 {
1965                                 frame-number = <3>;
1966                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1967                                 reg = <0x0 0x17c27000 0x0 0x1000>;
1968                                 status = "disabled";
1969                         };
1970
1971                         frame@17c29000 {
1972                                 frame-number = <4>;
1973                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1974                                 reg = <0x0 0x17c29000 0x0 0x1000>;
1975                                 status = "disabled";
1976                         };
1977
1978                         frame@17c2b000 {
1979                                 frame-number = <5>;
1980                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1981                                 reg = <0x0 0x17c2b000 0x0 0x1000>;
1982                                 status = "disabled";
1983                         };
1984
1985                         frame@17c2d000 {
1986                                 frame-number = <6>;
1987                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1988                                 reg = <0x0 0x17c2d000 0x0 0x1000>;
1989                                 status = "disabled";
1990                         };
1991                 };
1992
1993                 apps_rsc: rsc@18200000 {
1994                         label = "apps_rsc";
1995                         compatible = "qcom,rpmh-rsc";
1996                         reg = <0x0 0x18200000 0x0 0x10000>,
1997                                 <0x0 0x18210000 0x0 0x10000>,
1998                                 <0x0 0x18220000 0x0 0x10000>;
1999                         reg-names = "drv-0", "drv-1", "drv-2";
2000                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
2001                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
2002                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
2003                         qcom,tcs-offset = <0xd00>;
2004                         qcom,drv-id = <2>;
2005                         qcom,tcs-config = <ACTIVE_TCS  2>, <SLEEP_TCS   3>,
2006                                           <WAKE_TCS    3>, <CONTROL_TCS 0>;
2007
2008                         rpmhcc: clock-controller {
2009                                 compatible = "qcom,sm8350-rpmh-clk";
2010                                 #clock-cells = <1>;
2011                                 clock-names = "xo";
2012                                 clocks = <&xo_board>;
2013                         };
2014
2015                         rpmhpd: power-controller {
2016                                 compatible = "qcom,sm8350-rpmhpd";
2017                                 #power-domain-cells = <1>;
2018                                 operating-points-v2 = <&rpmhpd_opp_table>;
2019
2020                                 rpmhpd_opp_table: opp-table {
2021                                         compatible = "operating-points-v2";
2022
2023                                         rpmhpd_opp_ret: opp1 {
2024                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
2025                                         };
2026
2027                                         rpmhpd_opp_min_svs: opp2 {
2028                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2029                                         };
2030
2031                                         rpmhpd_opp_low_svs: opp3 {
2032                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2033                                         };
2034
2035                                         rpmhpd_opp_svs: opp4 {
2036                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2037                                         };
2038
2039                                         rpmhpd_opp_svs_l1: opp5 {
2040                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2041                                         };
2042
2043                                         rpmhpd_opp_nom: opp6 {
2044                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2045                                         };
2046
2047                                         rpmhpd_opp_nom_l1: opp7 {
2048                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2049                                         };
2050
2051                                         rpmhpd_opp_nom_l2: opp8 {
2052                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
2053                                         };
2054
2055                                         rpmhpd_opp_turbo: opp9 {
2056                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2057                                         };
2058
2059                                         rpmhpd_opp_turbo_l1: opp10 {
2060                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2061                                         };
2062                                 };
2063                         };
2064
2065                         apps_bcm_voter: bcm-voter {
2066                                 compatible = "qcom,bcm-voter";
2067                         };
2068                 };
2069
2070                 cpufreq_hw: cpufreq@18591000 {
2071                         compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss";
2072                         reg = <0 0x18591000 0 0x1000>,
2073                               <0 0x18592000 0 0x1000>,
2074                               <0 0x18593000 0 0x1000>;
2075                         reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
2076
2077                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
2078                         clock-names = "xo", "alternate";
2079
2080                         #freq-domain-cells = <1>;
2081                 };
2082
2083                 ufs_mem_hc: ufshc@1d84000 {
2084                         compatible = "qcom,sm8350-ufshc", "qcom,ufshc",
2085                                      "jedec,ufs-2.0";
2086                         reg = <0 0x01d84000 0 0x3000>;
2087                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2088                         phys = <&ufs_mem_phy_lanes>;
2089                         phy-names = "ufsphy";
2090                         lanes-per-direction = <2>;
2091                         #reset-cells = <1>;
2092                         resets = <&gcc GCC_UFS_PHY_BCR>;
2093                         reset-names = "rst";
2094
2095                         power-domains = <&gcc UFS_PHY_GDSC>;
2096
2097                         iommus = <&apps_smmu 0xe0 0x0>;
2098
2099                         clock-names =
2100                                 "core_clk",
2101                                 "bus_aggr_clk",
2102                                 "iface_clk",
2103                                 "core_clk_unipro",
2104                                 "ref_clk",
2105                                 "tx_lane0_sync_clk",
2106                                 "rx_lane0_sync_clk",
2107                                 "rx_lane1_sync_clk";
2108                         clocks =
2109                                 <&gcc GCC_UFS_PHY_AXI_CLK>,
2110                                 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2111                                 <&gcc GCC_UFS_PHY_AHB_CLK>,
2112                                 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2113                                 <&rpmhcc RPMH_CXO_CLK>,
2114                                 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2115                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2116                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
2117                         freq-table-hz =
2118                                 <75000000 300000000>,
2119                                 <0 0>,
2120                                 <0 0>,
2121                                 <75000000 300000000>,
2122                                 <0 0>,
2123                                 <0 0>,
2124                                 <0 0>,
2125                                 <0 0>;
2126                         status = "disabled";
2127                 };
2128
2129                 ufs_mem_phy: phy@1d87000 {
2130                         compatible = "qcom,sm8350-qmp-ufs-phy";
2131                         reg = <0 0x01d87000 0 0xe10>;
2132                         #address-cells = <2>;
2133                         #size-cells = <2>;
2134                         ranges;
2135                         clock-names = "ref",
2136                                       "ref_aux";
2137                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2138                                  <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2139
2140                         resets = <&ufs_mem_hc 0>;
2141                         reset-names = "ufsphy";
2142                         status = "disabled";
2143
2144                         ufs_mem_phy_lanes: phy@1d87400 {
2145                                 reg = <0 0x01d87400 0 0x108>,
2146                                       <0 0x01d87600 0 0x1e0>,
2147                                       <0 0x01d87c00 0 0x1dc>,
2148                                       <0 0x01d87800 0 0x108>,
2149                                       <0 0x01d87a00 0 0x1e0>;
2150                                 #phy-cells = <0>;
2151                                 #clock-cells = <0>;
2152                         };
2153                 };
2154
2155                 slpi: remoteproc@5c00000 {
2156                         compatible = "qcom,sm8350-slpi-pas";
2157                         reg = <0 0x05c00000 0 0x4000>;
2158
2159                         interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
2160                                               <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
2161                                               <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
2162                                               <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
2163                                               <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
2164                         interrupt-names = "wdog", "fatal", "ready",
2165                                           "handover", "stop-ack";
2166
2167                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2168                         clock-names = "xo";
2169
2170                         power-domains = <&rpmhpd 4>,
2171                                         <&rpmhpd 5>;
2172                         power-domain-names = "lcx", "lmx";
2173
2174                         memory-region = <&pil_slpi_mem>;
2175
2176                         qcom,qmp = <&aoss_qmp>;
2177
2178                         qcom,smem-states = <&smp2p_slpi_out 0>;
2179                         qcom,smem-state-names = "stop";
2180
2181                         status = "disabled";
2182
2183                         glink-edge {
2184                                 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
2185                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
2186                                                              IRQ_TYPE_EDGE_RISING>;
2187                                 mboxes = <&ipcc IPCC_CLIENT_SLPI
2188                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2189
2190                                 label = "slpi";
2191                                 qcom,remote-pid = <3>;
2192
2193                                 fastrpc {
2194                                         compatible = "qcom,fastrpc";
2195                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
2196                                         label = "sdsp";
2197                                         qcom,non-secure-domain;
2198                                         #address-cells = <1>;
2199                                         #size-cells = <0>;
2200
2201                                         compute-cb@1 {
2202                                                 compatible = "qcom,fastrpc-compute-cb";
2203                                                 reg = <1>;
2204                                                 iommus = <&apps_smmu 0x0541 0x0>;
2205                                         };
2206
2207                                         compute-cb@2 {
2208                                                 compatible = "qcom,fastrpc-compute-cb";
2209                                                 reg = <2>;
2210                                                 iommus = <&apps_smmu 0x0542 0x0>;
2211                                         };
2212
2213                                         compute-cb@3 {
2214                                                 compatible = "qcom,fastrpc-compute-cb";
2215                                                 reg = <3>;
2216                                                 iommus = <&apps_smmu 0x0543 0x0>;
2217                                                 /* note: shared-cb = <4> in downstream */
2218                                         };
2219                                 };
2220                         };
2221                 };
2222
2223                 cdsp: remoteproc@98900000 {
2224                         compatible = "qcom,sm8350-cdsp-pas";
2225                         reg = <0 0x098900000 0 0x1400000>;
2226
2227                         interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
2228                                               <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
2229                                               <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
2230                                               <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
2231                                               <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
2232                         interrupt-names = "wdog", "fatal", "ready",
2233                                           "handover", "stop-ack";
2234
2235                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2236                         clock-names = "xo";
2237
2238                         power-domains = <&rpmhpd 0>,
2239                                         <&rpmhpd 10>;
2240                         power-domain-names = "cx", "mxc";
2241
2242                         interconnects = <&compute_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>;
2243
2244                         memory-region = <&pil_cdsp_mem>;
2245
2246                         qcom,qmp = <&aoss_qmp>;
2247
2248                         qcom,smem-states = <&smp2p_cdsp_out 0>;
2249                         qcom,smem-state-names = "stop";
2250
2251                         status = "disabled";
2252
2253                         glink-edge {
2254                                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
2255                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
2256                                                              IRQ_TYPE_EDGE_RISING>;
2257                                 mboxes = <&ipcc IPCC_CLIENT_CDSP
2258                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2259
2260                                 label = "cdsp";
2261                                 qcom,remote-pid = <5>;
2262
2263                                 fastrpc {
2264                                         compatible = "qcom,fastrpc";
2265                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
2266                                         label = "cdsp";
2267                                         qcom,non-secure-domain;
2268                                         #address-cells = <1>;
2269                                         #size-cells = <0>;
2270
2271                                         compute-cb@1 {
2272                                                 compatible = "qcom,fastrpc-compute-cb";
2273                                                 reg = <1>;
2274                                                 iommus = <&apps_smmu 0x2161 0x0400>,
2275                                                          <&apps_smmu 0x1181 0x0420>;
2276                                         };
2277
2278                                         compute-cb@2 {
2279                                                 compatible = "qcom,fastrpc-compute-cb";
2280                                                 reg = <2>;
2281                                                 iommus = <&apps_smmu 0x2162 0x0400>,
2282                                                          <&apps_smmu 0x1182 0x0420>;
2283                                         };
2284
2285                                         compute-cb@3 {
2286                                                 compatible = "qcom,fastrpc-compute-cb";
2287                                                 reg = <3>;
2288                                                 iommus = <&apps_smmu 0x2163 0x0400>,
2289                                                          <&apps_smmu 0x1183 0x0420>;
2290                                         };
2291
2292                                         compute-cb@4 {
2293                                                 compatible = "qcom,fastrpc-compute-cb";
2294                                                 reg = <4>;
2295                                                 iommus = <&apps_smmu 0x2164 0x0400>,
2296                                                          <&apps_smmu 0x1184 0x0420>;
2297                                         };
2298
2299                                         compute-cb@5 {
2300                                                 compatible = "qcom,fastrpc-compute-cb";
2301                                                 reg = <5>;
2302                                                 iommus = <&apps_smmu 0x2165 0x0400>,
2303                                                          <&apps_smmu 0x1185 0x0420>;
2304                                         };
2305
2306                                         compute-cb@6 {
2307                                                 compatible = "qcom,fastrpc-compute-cb";
2308                                                 reg = <6>;
2309                                                 iommus = <&apps_smmu 0x2166 0x0400>,
2310                                                          <&apps_smmu 0x1186 0x0420>;
2311                                         };
2312
2313                                         compute-cb@7 {
2314                                                 compatible = "qcom,fastrpc-compute-cb";
2315                                                 reg = <7>;
2316                                                 iommus = <&apps_smmu 0x2167 0x0400>,
2317                                                          <&apps_smmu 0x1187 0x0420>;
2318                                         };
2319
2320                                         compute-cb@8 {
2321                                                 compatible = "qcom,fastrpc-compute-cb";
2322                                                 reg = <8>;
2323                                                 iommus = <&apps_smmu 0x2168 0x0400>,
2324                                                          <&apps_smmu 0x1188 0x0420>;
2325                                         };
2326
2327                                         /* note: secure cb9 in downstream */
2328                                 };
2329                         };
2330                 };
2331
2332                 usb_1_hsphy: phy@88e3000 {
2333                         compatible = "qcom,sm8350-usb-hs-phy",
2334                                      "qcom,usb-snps-hs-7nm-phy";
2335                         reg = <0 0x088e3000 0 0x400>;
2336                         status = "disabled";
2337                         #phy-cells = <0>;
2338
2339                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2340                         clock-names = "ref";
2341
2342                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2343                 };
2344
2345                 usb_2_hsphy: phy@88e4000 {
2346                         compatible = "qcom,sm8250-usb-hs-phy",
2347                                      "qcom,usb-snps-hs-7nm-phy";
2348                         reg = <0 0x088e4000 0 0x400>;
2349                         status = "disabled";
2350                         #phy-cells = <0>;
2351
2352                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2353                         clock-names = "ref";
2354
2355                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
2356                 };
2357
2358                 usb_1_qmpphy: phy-wrapper@88e9000 {
2359                         compatible = "qcom,sm8350-qmp-usb3-phy";
2360                         reg = <0 0x088e9000 0 0x200>,
2361                               <0 0x088e8000 0 0x20>;
2362                         status = "disabled";
2363                         #address-cells = <2>;
2364                         #size-cells = <2>;
2365                         ranges;
2366
2367                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2368                                  <&rpmhcc RPMH_CXO_CLK>,
2369                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
2370                         clock-names = "aux", "ref_clk_src", "com_aux";
2371
2372                         resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
2373                                  <&gcc GCC_USB3_PHY_PRIM_BCR>;
2374                         reset-names = "phy", "common";
2375
2376                         usb_1_ssphy: phy@88e9200 {
2377                                 reg = <0 0x088e9200 0 0x200>,
2378                                       <0 0x088e9400 0 0x200>,
2379                                       <0 0x088e9c00 0 0x400>,
2380                                       <0 0x088e9600 0 0x200>,
2381                                       <0 0x088e9800 0 0x200>,
2382                                       <0 0x088e9a00 0 0x100>;
2383                                 #phy-cells = <0>;
2384                                 #clock-cells = <1>;
2385                                 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2386                                 clock-names = "pipe0";
2387                                 clock-output-names = "usb3_phy_pipe_clk_src";
2388                         };
2389                 };
2390
2391                 usb_2_qmpphy: phy-wrapper@88eb000 {
2392                         compatible = "qcom,sm8350-qmp-usb3-uni-phy";
2393                         reg = <0 0x088eb000 0 0x200>;
2394                         status = "disabled";
2395                         #address-cells = <2>;
2396                         #size-cells = <2>;
2397                         ranges;
2398
2399                         clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
2400                                  <&rpmhcc RPMH_CXO_CLK>,
2401                                  <&gcc GCC_USB3_SEC_CLKREF_EN>,
2402                                  <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
2403                         clock-names = "aux", "ref_clk_src", "ref", "com_aux";
2404
2405                         resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
2406                                  <&gcc GCC_USB3_PHY_SEC_BCR>;
2407                         reset-names = "phy", "common";
2408
2409                         usb_2_ssphy: phy@88ebe00 {
2410                                 reg = <0 0x088ebe00 0 0x200>,
2411                                       <0 0x088ec000 0 0x200>,
2412                                       <0 0x088eb200 0 0x1100>;
2413                                 #phy-cells = <0>;
2414                                 #clock-cells = <1>;
2415                                 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
2416                                 clock-names = "pipe0";
2417                                 clock-output-names = "usb3_uni_phy_pipe_clk_src";
2418                         };
2419                 };
2420
2421                 dc_noc: interconnect@90c0000 {
2422                         compatible = "qcom,sm8350-dc-noc";
2423                         reg = <0 0x090c0000 0 0x4200>;
2424                         #interconnect-cells = <1>;
2425                         qcom,bcm-voters = <&apps_bcm_voter>;
2426                 };
2427
2428                 gem_noc: interconnect@9100000 {
2429                         compatible = "qcom,sm8350-gem-noc";
2430                         reg = <0 0x09100000 0 0xb4000>;
2431                         #interconnect-cells = <1>;
2432                         qcom,bcm-voters = <&apps_bcm_voter>;
2433                 };
2434
2435                 system-cache-controller@9200000 {
2436                         compatible = "qcom,sm8350-llcc";
2437                         reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>;
2438                         reg-names = "llcc_base", "llcc_broadcast_base";
2439                 };
2440
2441                 usb_1: usb@a6f8800 {
2442                         compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
2443                         reg = <0 0x0a6f8800 0 0x400>;
2444                         status = "disabled";
2445                         #address-cells = <2>;
2446                         #size-cells = <2>;
2447                         ranges;
2448
2449                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
2450                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
2451                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
2452                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
2453                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
2454                         clock-names = "cfg_noc",
2455                                       "core",
2456                                       "iface",
2457                                       "sleep",
2458                                       "mock_utmi";
2459
2460                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2461                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
2462                         assigned-clock-rates = <19200000>, <200000000>;
2463
2464                         interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
2465                                               <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
2466                                               <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
2467                                               <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
2468                         interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
2469                                           "dm_hs_phy_irq", "ss_phy_irq";
2470
2471                         power-domains = <&gcc USB30_PRIM_GDSC>;
2472
2473                         resets = <&gcc GCC_USB30_PRIM_BCR>;
2474
2475                         usb_1_dwc3: usb@a600000 {
2476                                 compatible = "snps,dwc3";
2477                                 reg = <0 0x0a600000 0 0xcd00>;
2478                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
2479                                 iommus = <&apps_smmu 0x0 0x0>;
2480                                 snps,dis_u2_susphy_quirk;
2481                                 snps,dis_enblslpm_quirk;
2482                                 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
2483                                 phy-names = "usb2-phy", "usb3-phy";
2484                         };
2485                 };
2486
2487                 usb_2: usb@a8f8800 {
2488                         compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
2489                         reg = <0 0x0a8f8800 0 0x400>;
2490                         status = "disabled";
2491                         #address-cells = <2>;
2492                         #size-cells = <2>;
2493                         ranges;
2494
2495                         clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
2496                                  <&gcc GCC_USB30_SEC_MASTER_CLK>,
2497                                  <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
2498                                  <&gcc GCC_USB30_SEC_SLEEP_CLK>,
2499                                  <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2500                                  <&gcc GCC_USB3_SEC_CLKREF_EN>;
2501                         clock-names = "cfg_noc",
2502                                       "core",
2503                                       "iface",
2504                                       "sleep",
2505                                       "mock_utmi",
2506                                       "xo";
2507
2508                         assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2509                                           <&gcc GCC_USB30_SEC_MASTER_CLK>;
2510                         assigned-clock-rates = <19200000>, <200000000>;
2511
2512                         interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
2513                                               <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
2514                                               <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
2515                                               <&pdc 16 IRQ_TYPE_LEVEL_HIGH>;
2516                         interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
2517                                           "dm_hs_phy_irq", "ss_phy_irq";
2518
2519                         power-domains = <&gcc USB30_SEC_GDSC>;
2520
2521                         resets = <&gcc GCC_USB30_SEC_BCR>;
2522
2523                         usb_2_dwc3: usb@a800000 {
2524                                 compatible = "snps,dwc3";
2525                                 reg = <0 0x0a800000 0 0xcd00>;
2526                                 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
2527                                 iommus = <&apps_smmu 0x20 0x0>;
2528                                 snps,dis_u2_susphy_quirk;
2529                                 snps,dis_enblslpm_quirk;
2530                                 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
2531                                 phy-names = "usb2-phy", "usb3-phy";
2532                         };
2533                 };
2534
2535                 adsp: remoteproc@17300000 {
2536                         compatible = "qcom,sm8350-adsp-pas";
2537                         reg = <0 0x17300000 0 0x100>;
2538
2539                         interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
2540                                               <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2541                                               <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
2542                                               <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
2543                                               <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
2544                         interrupt-names = "wdog", "fatal", "ready",
2545                                           "handover", "stop-ack";
2546
2547                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2548                         clock-names = "xo";
2549
2550                         power-domains = <&rpmhpd 4>,
2551                                         <&rpmhpd 5>;
2552                         power-domain-names = "lcx", "lmx";
2553
2554                         memory-region = <&pil_adsp_mem>;
2555
2556                         qcom,qmp = <&aoss_qmp>;
2557
2558                         qcom,smem-states = <&smp2p_adsp_out 0>;
2559                         qcom,smem-state-names = "stop";
2560
2561                         status = "disabled";
2562
2563                         glink-edge {
2564                                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2565                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
2566                                                              IRQ_TYPE_EDGE_RISING>;
2567                                 mboxes = <&ipcc IPCC_CLIENT_LPASS
2568                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2569
2570                                 label = "lpass";
2571                                 qcom,remote-pid = <2>;
2572
2573                                 fastrpc {
2574                                         compatible = "qcom,fastrpc";
2575                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
2576                                         label = "adsp";
2577                                         qcom,non-secure-domain;
2578                                         #address-cells = <1>;
2579                                         #size-cells = <0>;
2580
2581                                         compute-cb@3 {
2582                                                 compatible = "qcom,fastrpc-compute-cb";
2583                                                 reg = <3>;
2584                                                 iommus = <&apps_smmu 0x1803 0x0>;
2585                                         };
2586
2587                                         compute-cb@4 {
2588                                                 compatible = "qcom,fastrpc-compute-cb";
2589                                                 reg = <4>;
2590                                                 iommus = <&apps_smmu 0x1804 0x0>;
2591                                         };
2592
2593                                         compute-cb@5 {
2594                                                 compatible = "qcom,fastrpc-compute-cb";
2595                                                 reg = <5>;
2596                                                 iommus = <&apps_smmu 0x1805 0x0>;
2597                                         };
2598                                 };
2599                         };
2600                 };
2601         };
2602
2603         thermal_zones: thermal-zones {
2604                 cpu0-thermal {
2605                         polling-delay-passive = <250>;
2606                         polling-delay = <1000>;
2607
2608                         thermal-sensors = <&tsens0 1>;
2609
2610                         trips {
2611                                 cpu0_alert0: trip-point0 {
2612                                         temperature = <90000>;
2613                                         hysteresis = <2000>;
2614                                         type = "passive";
2615                                 };
2616
2617                                 cpu0_alert1: trip-point1 {
2618                                         temperature = <95000>;
2619                                         hysteresis = <2000>;
2620                                         type = "passive";
2621                                 };
2622
2623                                 cpu0_crit: cpu_crit {
2624                                         temperature = <110000>;
2625                                         hysteresis = <1000>;
2626                                         type = "critical";
2627                                 };
2628                         };
2629
2630                         cooling-maps {
2631                                 map0 {
2632                                         trip = <&cpu0_alert0>;
2633                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2634                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2635                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2636                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2637                                 };
2638                                 map1 {
2639                                         trip = <&cpu0_alert1>;
2640                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2641                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2642                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2643                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2644                                 };
2645                         };
2646                 };
2647
2648                 cpu1-thermal {
2649                         polling-delay-passive = <250>;
2650                         polling-delay = <1000>;
2651
2652                         thermal-sensors = <&tsens0 2>;
2653
2654                         trips {
2655                                 cpu1_alert0: trip-point0 {
2656                                         temperature = <90000>;
2657                                         hysteresis = <2000>;
2658                                         type = "passive";
2659                                 };
2660
2661                                 cpu1_alert1: trip-point1 {
2662                                         temperature = <95000>;
2663                                         hysteresis = <2000>;
2664                                         type = "passive";
2665                                 };
2666
2667                                 cpu1_crit: cpu_crit {
2668                                         temperature = <110000>;
2669                                         hysteresis = <1000>;
2670                                         type = "critical";
2671                                 };
2672                         };
2673
2674                         cooling-maps {
2675                                 map0 {
2676                                         trip = <&cpu1_alert0>;
2677                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2678                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2679                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2680                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2681                                 };
2682                                 map1 {
2683                                         trip = <&cpu1_alert1>;
2684                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2685                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2686                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2687                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2688                                 };
2689                         };
2690                 };
2691
2692                 cpu2-thermal {
2693                         polling-delay-passive = <250>;
2694                         polling-delay = <1000>;
2695
2696                         thermal-sensors = <&tsens0 3>;
2697
2698                         trips {
2699                                 cpu2_alert0: trip-point0 {
2700                                         temperature = <90000>;
2701                                         hysteresis = <2000>;
2702                                         type = "passive";
2703                                 };
2704
2705                                 cpu2_alert1: trip-point1 {
2706                                         temperature = <95000>;
2707                                         hysteresis = <2000>;
2708                                         type = "passive";
2709                                 };
2710
2711                                 cpu2_crit: cpu_crit {
2712                                         temperature = <110000>;
2713                                         hysteresis = <1000>;
2714                                         type = "critical";
2715                                 };
2716                         };
2717
2718                         cooling-maps {
2719                                 map0 {
2720                                         trip = <&cpu2_alert0>;
2721                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2722                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2723                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2724                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2725                                 };
2726                                 map1 {
2727                                         trip = <&cpu2_alert1>;
2728                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2729                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2730                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2731                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2732                                 };
2733                         };
2734                 };
2735
2736                 cpu3-thermal {
2737                         polling-delay-passive = <250>;
2738                         polling-delay = <1000>;
2739
2740                         thermal-sensors = <&tsens0 4>;
2741
2742                         trips {
2743                                 cpu3_alert0: trip-point0 {
2744                                         temperature = <90000>;
2745                                         hysteresis = <2000>;
2746                                         type = "passive";
2747                                 };
2748
2749                                 cpu3_alert1: trip-point1 {
2750                                         temperature = <95000>;
2751                                         hysteresis = <2000>;
2752                                         type = "passive";
2753                                 };
2754
2755                                 cpu3_crit: cpu_crit {
2756                                         temperature = <110000>;
2757                                         hysteresis = <1000>;
2758                                         type = "critical";
2759                                 };
2760                         };
2761
2762                         cooling-maps {
2763                                 map0 {
2764                                         trip = <&cpu3_alert0>;
2765                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2766                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2767                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2768                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2769                                 };
2770                                 map1 {
2771                                         trip = <&cpu3_alert1>;
2772                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2773                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2774                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2775                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2776                                 };
2777                         };
2778                 };
2779
2780                 cpu4-top-thermal {
2781                         polling-delay-passive = <250>;
2782                         polling-delay = <1000>;
2783
2784                         thermal-sensors = <&tsens0 7>;
2785
2786                         trips {
2787                                 cpu4_top_alert0: trip-point0 {
2788                                         temperature = <90000>;
2789                                         hysteresis = <2000>;
2790                                         type = "passive";
2791                                 };
2792
2793                                 cpu4_top_alert1: trip-point1 {
2794                                         temperature = <95000>;
2795                                         hysteresis = <2000>;
2796                                         type = "passive";
2797                                 };
2798
2799                                 cpu4_top_crit: cpu_crit {
2800                                         temperature = <110000>;
2801                                         hysteresis = <1000>;
2802                                         type = "critical";
2803                                 };
2804                         };
2805
2806                         cooling-maps {
2807                                 map0 {
2808                                         trip = <&cpu4_top_alert0>;
2809                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2810                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2811                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2812                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2813                                 };
2814                                 map1 {
2815                                         trip = <&cpu4_top_alert1>;
2816                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2817                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2818                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2819                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2820                                 };
2821                         };
2822                 };
2823
2824                 cpu5-top-thermal {
2825                         polling-delay-passive = <250>;
2826                         polling-delay = <1000>;
2827
2828                         thermal-sensors = <&tsens0 8>;
2829
2830                         trips {
2831                                 cpu5_top_alert0: trip-point0 {
2832                                         temperature = <90000>;
2833                                         hysteresis = <2000>;
2834                                         type = "passive";
2835                                 };
2836
2837                                 cpu5_top_alert1: trip-point1 {
2838                                         temperature = <95000>;
2839                                         hysteresis = <2000>;
2840                                         type = "passive";
2841                                 };
2842
2843                                 cpu5_top_crit: cpu_crit {
2844                                         temperature = <110000>;
2845                                         hysteresis = <1000>;
2846                                         type = "critical";
2847                                 };
2848                         };
2849
2850                         cooling-maps {
2851                                 map0 {
2852                                         trip = <&cpu5_top_alert0>;
2853                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2854                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2855                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2856                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2857                                 };
2858                                 map1 {
2859                                         trip = <&cpu5_top_alert1>;
2860                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2861                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2862                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2863                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2864                                 };
2865                         };
2866                 };
2867
2868                 cpu6-top-thermal {
2869                         polling-delay-passive = <250>;
2870                         polling-delay = <1000>;
2871
2872                         thermal-sensors = <&tsens0 9>;
2873
2874                         trips {
2875                                 cpu6_top_alert0: trip-point0 {
2876                                         temperature = <90000>;
2877                                         hysteresis = <2000>;
2878                                         type = "passive";
2879                                 };
2880
2881                                 cpu6_top_alert1: trip-point1 {
2882                                         temperature = <95000>;
2883                                         hysteresis = <2000>;
2884                                         type = "passive";
2885                                 };
2886
2887                                 cpu6_top_crit: cpu_crit {
2888                                         temperature = <110000>;
2889                                         hysteresis = <1000>;
2890                                         type = "critical";
2891                                 };
2892                         };
2893
2894                         cooling-maps {
2895                                 map0 {
2896                                         trip = <&cpu6_top_alert0>;
2897                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2898                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2899                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2900                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2901                                 };
2902                                 map1 {
2903                                         trip = <&cpu6_top_alert1>;
2904                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2905                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2906                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2907                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2908                                 };
2909                         };
2910                 };
2911
2912                 cpu7-top-thermal {
2913                         polling-delay-passive = <250>;
2914                         polling-delay = <1000>;
2915
2916                         thermal-sensors = <&tsens0 10>;
2917
2918                         trips {
2919                                 cpu7_top_alert0: trip-point0 {
2920                                         temperature = <90000>;
2921                                         hysteresis = <2000>;
2922                                         type = "passive";
2923                                 };
2924
2925                                 cpu7_top_alert1: trip-point1 {
2926                                         temperature = <95000>;
2927                                         hysteresis = <2000>;
2928                                         type = "passive";
2929                                 };
2930
2931                                 cpu7_top_crit: cpu_crit {
2932                                         temperature = <110000>;
2933                                         hysteresis = <1000>;
2934                                         type = "critical";
2935                                 };
2936                         };
2937
2938                         cooling-maps {
2939                                 map0 {
2940                                         trip = <&cpu7_top_alert0>;
2941                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2942                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2943                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2944                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2945                                 };
2946                                 map1 {
2947                                         trip = <&cpu7_top_alert1>;
2948                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2949                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2950                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2951                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2952                                 };
2953                         };
2954                 };
2955
2956                 cpu4-bottom-thermal {
2957                         polling-delay-passive = <250>;
2958                         polling-delay = <1000>;
2959
2960                         thermal-sensors = <&tsens0 11>;
2961
2962                         trips {
2963                                 cpu4_bottom_alert0: trip-point0 {
2964                                         temperature = <90000>;
2965                                         hysteresis = <2000>;
2966                                         type = "passive";
2967                                 };
2968
2969                                 cpu4_bottom_alert1: trip-point1 {
2970                                         temperature = <95000>;
2971                                         hysteresis = <2000>;
2972                                         type = "passive";
2973                                 };
2974
2975                                 cpu4_bottom_crit: cpu_crit {
2976                                         temperature = <110000>;
2977                                         hysteresis = <1000>;
2978                                         type = "critical";
2979                                 };
2980                         };
2981
2982                         cooling-maps {
2983                                 map0 {
2984                                         trip = <&cpu4_bottom_alert0>;
2985                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2986                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2987                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2988                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2989                                 };
2990                                 map1 {
2991                                         trip = <&cpu4_bottom_alert1>;
2992                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2993                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2994                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2995                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2996                                 };
2997                         };
2998                 };
2999
3000                 cpu5-bottom-thermal {
3001                         polling-delay-passive = <250>;
3002                         polling-delay = <1000>;
3003
3004                         thermal-sensors = <&tsens0 12>;
3005
3006                         trips {
3007                                 cpu5_bottom_alert0: trip-point0 {
3008                                         temperature = <90000>;
3009                                         hysteresis = <2000>;
3010                                         type = "passive";
3011                                 };
3012
3013                                 cpu5_bottom_alert1: trip-point1 {
3014                                         temperature = <95000>;
3015                                         hysteresis = <2000>;
3016                                         type = "passive";
3017                                 };
3018
3019                                 cpu5_bottom_crit: cpu_crit {
3020                                         temperature = <110000>;
3021                                         hysteresis = <1000>;
3022                                         type = "critical";
3023                                 };
3024                         };
3025
3026                         cooling-maps {
3027                                 map0 {
3028                                         trip = <&cpu5_bottom_alert0>;
3029                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3030                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3031                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3032                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3033                                 };
3034                                 map1 {
3035                                         trip = <&cpu5_bottom_alert1>;
3036                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3037                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3038                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3039                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3040                                 };
3041                         };
3042                 };
3043
3044                 cpu6-bottom-thermal {
3045                         polling-delay-passive = <250>;
3046                         polling-delay = <1000>;
3047
3048                         thermal-sensors = <&tsens0 13>;
3049
3050                         trips {
3051                                 cpu6_bottom_alert0: trip-point0 {
3052                                         temperature = <90000>;
3053                                         hysteresis = <2000>;
3054                                         type = "passive";
3055                                 };
3056
3057                                 cpu6_bottom_alert1: trip-point1 {
3058                                         temperature = <95000>;
3059                                         hysteresis = <2000>;
3060                                         type = "passive";
3061                                 };
3062
3063                                 cpu6_bottom_crit: cpu_crit {
3064                                         temperature = <110000>;
3065                                         hysteresis = <1000>;
3066                                         type = "critical";
3067                                 };
3068                         };
3069
3070                         cooling-maps {
3071                                 map0 {
3072                                         trip = <&cpu6_bottom_alert0>;
3073                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3074                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3075                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3076                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3077                                 };
3078                                 map1 {
3079                                         trip = <&cpu6_bottom_alert1>;
3080                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3081                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3082                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3083                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3084                                 };
3085                         };
3086                 };
3087
3088                 cpu7-bottom-thermal {
3089                         polling-delay-passive = <250>;
3090                         polling-delay = <1000>;
3091
3092                         thermal-sensors = <&tsens0 14>;
3093
3094                         trips {
3095                                 cpu7_bottom_alert0: trip-point0 {
3096                                         temperature = <90000>;
3097                                         hysteresis = <2000>;
3098                                         type = "passive";
3099                                 };
3100
3101                                 cpu7_bottom_alert1: trip-point1 {
3102                                         temperature = <95000>;
3103                                         hysteresis = <2000>;
3104                                         type = "passive";
3105                                 };
3106
3107                                 cpu7_bottom_crit: cpu_crit {
3108                                         temperature = <110000>;
3109                                         hysteresis = <1000>;
3110                                         type = "critical";
3111                                 };
3112                         };
3113
3114                         cooling-maps {
3115                                 map0 {
3116                                         trip = <&cpu7_bottom_alert0>;
3117                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3118                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3119                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3120                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3121                                 };
3122                                 map1 {
3123                                         trip = <&cpu7_bottom_alert1>;
3124                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3125                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3126                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3127                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3128                                 };
3129                         };
3130                 };
3131
3132                 aoss0-thermal {
3133                         polling-delay-passive = <250>;
3134                         polling-delay = <1000>;
3135
3136                         thermal-sensors = <&tsens0 0>;
3137
3138                         trips {
3139                                 aoss0_alert0: trip-point0 {
3140                                         temperature = <90000>;
3141                                         hysteresis = <2000>;
3142                                         type = "hot";
3143                                 };
3144                         };
3145                 };
3146
3147                 cluster0-thermal {
3148                         polling-delay-passive = <250>;
3149                         polling-delay = <1000>;
3150
3151                         thermal-sensors = <&tsens0 5>;
3152
3153                         trips {
3154                                 cluster0_alert0: trip-point0 {
3155                                         temperature = <90000>;
3156                                         hysteresis = <2000>;
3157                                         type = "hot";
3158                                 };
3159                                 cluster0_crit: cluster0_crit {
3160                                         temperature = <110000>;
3161                                         hysteresis = <2000>;
3162                                         type = "critical";
3163                                 };
3164                         };
3165                 };
3166
3167                 cluster1-thermal {
3168                         polling-delay-passive = <250>;
3169                         polling-delay = <1000>;
3170
3171                         thermal-sensors = <&tsens0 6>;
3172
3173                         trips {
3174                                 cluster1_alert0: trip-point0 {
3175                                         temperature = <90000>;
3176                                         hysteresis = <2000>;
3177                                         type = "hot";
3178                                 };
3179                                 cluster1_crit: cluster1_crit {
3180                                         temperature = <110000>;
3181                                         hysteresis = <2000>;
3182                                         type = "critical";
3183                                 };
3184                         };
3185                 };
3186
3187                 aoss1-thermal {
3188                         polling-delay-passive = <250>;
3189                         polling-delay = <1000>;
3190
3191                         thermal-sensors = <&tsens1 0>;
3192
3193                         trips {
3194                                 aoss1_alert0: trip-point0 {
3195                                         temperature = <90000>;
3196                                         hysteresis = <2000>;
3197                                         type = "hot";
3198                                 };
3199                         };
3200                 };
3201
3202                 gpu-top-thermal {
3203                         polling-delay-passive = <250>;
3204                         polling-delay = <1000>;
3205
3206                         thermal-sensors = <&tsens1 1>;
3207
3208                         trips {
3209                                 gpu1_alert0: trip-point0 {
3210                                         temperature = <90000>;
3211                                         hysteresis = <1000>;
3212                                         type = "hot";
3213                                 };
3214                         };
3215                 };
3216
3217                 gpu-bottom-thermal {
3218                         polling-delay-passive = <250>;
3219                         polling-delay = <1000>;
3220
3221                         thermal-sensors = <&tsens1 2>;
3222
3223                         trips {
3224                                 gpu2_alert0: trip-point0 {
3225                                         temperature = <90000>;
3226                                         hysteresis = <1000>;
3227                                         type = "hot";
3228                                 };
3229                         };
3230                 };
3231
3232                 nspss1-thermal {
3233                         polling-delay-passive = <250>;
3234                         polling-delay = <1000>;
3235
3236                         thermal-sensors = <&tsens1 3>;
3237
3238                         trips {
3239                                 nspss1_alert0: trip-point0 {
3240                                         temperature = <90000>;
3241                                         hysteresis = <1000>;
3242                                         type = "hot";
3243                                 };
3244                         };
3245                 };
3246
3247                 nspss2-thermal {
3248                         polling-delay-passive = <250>;
3249                         polling-delay = <1000>;
3250
3251                         thermal-sensors = <&tsens1 4>;
3252
3253                         trips {
3254                                 nspss2_alert0: trip-point0 {
3255                                         temperature = <90000>;
3256                                         hysteresis = <1000>;
3257                                         type = "hot";
3258                                 };
3259                         };
3260                 };
3261
3262                 nspss3-thermal {
3263                         polling-delay-passive = <250>;
3264                         polling-delay = <1000>;
3265
3266                         thermal-sensors = <&tsens1 5>;
3267
3268                         trips {
3269                                 nspss3_alert0: trip-point0 {
3270                                         temperature = <90000>;
3271                                         hysteresis = <1000>;
3272                                         type = "hot";
3273                                 };
3274                         };
3275                 };
3276
3277                 video-thermal {
3278                         polling-delay-passive = <250>;
3279                         polling-delay = <1000>;
3280
3281                         thermal-sensors = <&tsens1 6>;
3282
3283                         trips {
3284                                 video_alert0: trip-point0 {
3285                                         temperature = <90000>;
3286                                         hysteresis = <2000>;
3287                                         type = "hot";
3288                                 };
3289                         };
3290                 };
3291
3292                 mem-thermal {
3293                         polling-delay-passive = <250>;
3294                         polling-delay = <1000>;
3295
3296                         thermal-sensors = <&tsens1 7>;
3297
3298                         trips {
3299                                 mem_alert0: trip-point0 {
3300                                         temperature = <90000>;
3301                                         hysteresis = <2000>;
3302                                         type = "hot";
3303                                 };
3304                         };
3305                 };
3306
3307                 modem1-top-thermal {
3308                         polling-delay-passive = <250>;
3309                         polling-delay = <1000>;
3310
3311                         thermal-sensors = <&tsens1 8>;
3312
3313                         trips {
3314                                 modem1_alert0: trip-point0 {
3315                                         temperature = <90000>;
3316                                         hysteresis = <2000>;
3317                                         type = "hot";
3318                                 };
3319                         };
3320                 };
3321
3322                 modem2-top-thermal {
3323                         polling-delay-passive = <250>;
3324                         polling-delay = <1000>;
3325
3326                         thermal-sensors = <&tsens1 9>;
3327
3328                         trips {
3329                                 modem2_alert0: trip-point0 {
3330                                         temperature = <90000>;
3331                                         hysteresis = <2000>;
3332                                         type = "hot";
3333                                 };
3334                         };
3335                 };
3336
3337                 modem3-top-thermal {
3338                         polling-delay-passive = <250>;
3339                         polling-delay = <1000>;
3340
3341                         thermal-sensors = <&tsens1 10>;
3342
3343                         trips {
3344                                 modem3_alert0: trip-point0 {
3345                                         temperature = <90000>;
3346                                         hysteresis = <2000>;
3347                                         type = "hot";
3348                                 };
3349                         };
3350                 };
3351
3352                 modem4-top-thermal {
3353                         polling-delay-passive = <250>;
3354                         polling-delay = <1000>;
3355
3356                         thermal-sensors = <&tsens1 11>;
3357
3358                         trips {
3359                                 modem4_alert0: trip-point0 {
3360                                         temperature = <90000>;
3361                                         hysteresis = <2000>;
3362                                         type = "hot";
3363                                 };
3364                         };
3365                 };
3366
3367                 camera-top-thermal {
3368                         polling-delay-passive = <250>;
3369                         polling-delay = <1000>;
3370
3371                         thermal-sensors = <&tsens1 12>;
3372
3373                         trips {
3374                                 camera1_alert0: trip-point0 {
3375                                         temperature = <90000>;
3376                                         hysteresis = <2000>;
3377                                         type = "hot";
3378                                 };
3379                         };
3380                 };
3381
3382                 cam-bottom-thermal {
3383                         polling-delay-passive = <250>;
3384                         polling-delay = <1000>;
3385
3386                         thermal-sensors = <&tsens1 13>;
3387
3388                         trips {
3389                                 camera2_alert0: trip-point0 {
3390                                         temperature = <90000>;
3391                                         hysteresis = <2000>;
3392                                         type = "hot";
3393                                 };
3394                         };
3395                 };
3396         };
3397
3398         timer {
3399                 compatible = "arm,armv8-timer";
3400                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
3401                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
3402                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
3403                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
3404         };
3405 };