arch/arm64/boot/dts/qcom/sm8250.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * Copyright (c) 2020, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
   8 #include <dt-bindings/clock/qcom,gpucc-sm8250.h>
   9 #include <dt-bindings/clock/qcom,rpmh.h>
  10 #include <dt-bindings/interconnect/qcom,osm-l3.h>
  11 #include <dt-bindings/mailbox/qcom-ipcc.h>
  12 #include <dt-bindings/power/qcom-aoss-qmp.h>
  13 #include <dt-bindings/power/qcom-rpmpd.h>
  14 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  15 #include <dt-bindings/thermal/thermal.h>
  16
  17 / {
  18         interrupt-parent = <&intc>;
  19
  20         #address-cells = <2>;
  21         #size-cells = <2>;
  22
  23         aliases {
  24                 i2c0 = &i2c0;
  25                 i2c1 = &i2c1;
  26                 i2c2 = &i2c2;
  27                 i2c3 = &i2c3;
  28                 i2c4 = &i2c4;
  29                 i2c5 = &i2c5;
  30                 i2c6 = &i2c6;
  31                 i2c7 = &i2c7;
  32                 i2c8 = &i2c8;
  33                 i2c9 = &i2c9;
  34                 i2c10 = &i2c10;
  35                 i2c11 = &i2c11;
  36                 i2c12 = &i2c12;
  37                 i2c13 = &i2c13;
  38                 i2c14 = &i2c14;
  39                 i2c15 = &i2c15;
  40                 i2c16 = &i2c16;
  41                 i2c17 = &i2c17;
  42                 i2c18 = &i2c18;
  43                 i2c19 = &i2c19;
  44                 spi0 = &spi0;
  45                 spi1 = &spi1;
  46                 spi2 = &spi2;
  47                 spi3 = &spi3;
  48                 spi4 = &spi4;
  49                 spi5 = &spi5;
  50                 spi6 = &spi6;
  51                 spi7 = &spi7;
  52                 spi8 = &spi8;
  53                 spi9 = &spi9;
  54                 spi10 = &spi10;
  55                 spi11 = &spi11;
  56                 spi12 = &spi12;
  57                 spi13 = &spi13;
  58                 spi14 = &spi14;
  59                 spi15 = &spi15;
  60                 spi16 = &spi16;
  61                 spi17 = &spi17;
  62                 spi18 = &spi18;
  63                 spi19 = &spi19;
  64         };
  65
  66         chosen { };
  67
  68         clocks {
  69                 xo_board: xo-board {
  70                         compatible = "fixed-clock";
  71                         #clock-cells = <0>;
  72                         clock-frequency = <38400000>;
  73                         clock-output-names = "xo_board";
  74                 };
  75
  76                 sleep_clk: sleep-clk {
  77                         compatible = "fixed-clock";
  78                         clock-frequency = <32768>;
  79                         #clock-cells = <0>;
  80                 };
  81         };
  82
  83         cpus {
  84                 #address-cells = <2>;
  85                 #size-cells = <0>;
  86
  87                 CPU0: cpu@0 {
  88                         device_type = "cpu";
  89                         compatible = "qcom,kryo485";
  90                         reg = <0x0 0x0>;
  91                         enable-method = "psci";
  92                         next-level-cache = <&L2_0>;
  93                         qcom,freq-domain = <&cpufreq_hw 0>;
  94                         #cooling-cells = <2>;
  95                         L2_0: l2-cache {
  96                               compatible = "cache";
  97                               next-level-cache = <&L3_0>;
  98                                 L3_0: l3-cache {
  99                                       compatible = "cache";
 100                                 };
 101                         };
 102                 };
 103
 104                 CPU1: cpu@100 {
 105                         device_type = "cpu";
 106                         compatible = "qcom,kryo485";
 107                         reg = <0x0 0x100>;
 108                         enable-method = "psci";
 109                         next-level-cache = <&L2_100>;
 110                         qcom,freq-domain = <&cpufreq_hw 0>;
 111                         #cooling-cells = <2>;
 112                         L2_100: l2-cache {
 113                               compatible = "cache";
 114                               next-level-cache = <&L3_0>;
 115                         };
 116                 };
 117
 118                 CPU2: cpu@200 {
 119                         device_type = "cpu";
 120                         compatible = "qcom,kryo485";
 121                         reg = <0x0 0x200>;
 122                         enable-method = "psci";
 123                         next-level-cache = <&L2_200>;
 124                         qcom,freq-domain = <&cpufreq_hw 0>;
 125                         #cooling-cells = <2>;
 126                         L2_200: l2-cache {
 127                               compatible = "cache";
 128                               next-level-cache = <&L3_0>;
 129                         };
 130                 };
 131
 132                 CPU3: cpu@300 {
 133                         device_type = "cpu";
 134                         compatible = "qcom,kryo485";
 135                         reg = <0x0 0x300>;
 136                         enable-method = "psci";
 137                         next-level-cache = <&L2_300>;
 138                         qcom,freq-domain = <&cpufreq_hw 0>;
 139                         #cooling-cells = <2>;
 140                         L2_300: l2-cache {
 141                               compatible = "cache";
 142                               next-level-cache = <&L3_0>;
 143                         };
 144                 };
 145
 146                 CPU4: cpu@400 {
 147                         device_type = "cpu";
 148                         compatible = "qcom,kryo485";
 149                         reg = <0x0 0x400>;
 150                         enable-method = "psci";
 151                         next-level-cache = <&L2_400>;
 152                         qcom,freq-domain = <&cpufreq_hw 1>;
 153                         #cooling-cells = <2>;
 154                         L2_400: l2-cache {
 155                               compatible = "cache";
 156                               next-level-cache = <&L3_0>;
 157                         };
 158                 };
 159
 160                 CPU5: cpu@500 {
 161                         device_type = "cpu";
 162                         compatible = "qcom,kryo485";
 163                         reg = <0x0 0x500>;
 164                         enable-method = "psci";
 165                         next-level-cache = <&L2_500>;
 166                         qcom,freq-domain = <&cpufreq_hw 1>;
 167                         #cooling-cells = <2>;
 168                         L2_500: l2-cache {
 169                               compatible = "cache";
 170                               next-level-cache = <&L3_0>;
 171                         };
 172
 173                 };
 174
 175                 CPU6: cpu@600 {
 176                         device_type = "cpu";
 177                         compatible = "qcom,kryo485";
 178                         reg = <0x0 0x600>;
 179                         enable-method = "psci";
 180                         next-level-cache = <&L2_600>;
 181                         qcom,freq-domain = <&cpufreq_hw 1>;
 182                         #cooling-cells = <2>;
 183                         L2_600: l2-cache {
 184                               compatible = "cache";
 185                               next-level-cache = <&L3_0>;
 186                         };
 187                 };
 188
 189                 CPU7: cpu@700 {
 190                         device_type = "cpu";
 191                         compatible = "qcom,kryo485";
 192                         reg = <0x0 0x700>;
 193                         enable-method = "psci";
 194                         next-level-cache = <&L2_700>;
 195                         qcom,freq-domain = <&cpufreq_hw 2>;
 196                         #cooling-cells = <2>;
 197                         L2_700: l2-cache {
 198                               compatible = "cache";
 199                               next-level-cache = <&L3_0>;
 200                         };
 201                 };
 202         };
 203
 204         firmware {
 205                 scm: scm {
 206                         compatible = "qcom,scm";
 207                         #reset-cells = <1>;
 208                 };
 209         };
 210
 211         memory@80000000 {
 212                 device_type = "memory";
 213                 /* We expect the bootloader to fill in the size */
 214                 reg = <0x0 0x80000000 0x0 0x0>;
 215         };
 216
 217         pmu {
 218                 compatible = "arm,armv8-pmuv3";
 219                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
 220         };
 221
 222         psci {
 223                 compatible = "arm,psci-1.0";
 224                 method = "smc";
 225         };
 226
 227         reserved-memory {
 228                 #address-cells = <2>;
 229                 #size-cells = <2>;
 230                 ranges;
 231
 232                 hyp_mem: memory@80000000 {
 233                         reg = <0x0 0x80000000 0x0 0x600000>;
 234                         no-map;
 235                 };
 236
 237                 xbl_aop_mem: memory@80700000 {
 238                         reg = <0x0 0x80700000 0x0 0x160000>;
 239                         no-map;
 240                 };
 241
 242                 cmd_db: memory@80860000 {
 243                         compatible = "qcom,cmd-db";
 244                         reg = <0x0 0x80860000 0x0 0x20000>;
 245                         no-map;
 246                 };
 247
 248                 smem_mem: memory@80900000 {
 249                         reg = <0x0 0x80900000 0x0 0x200000>;
 250                         no-map;
 251                 };
 252
 253                 removed_mem: memory@80b00000 {
 254                         reg = <0x0 0x80b00000 0x0 0x5300000>;
 255                         no-map;
 256                 };
 257
 258                 camera_mem: memory@86200000 {
 259                         reg = <0x0 0x86200000 0x0 0x500000>;
 260                         no-map;
 261                 };
 262
 263                 wlan_mem: memory@86700000 {
 264                         reg = <0x0 0x86700000 0x0 0x100000>;
 265                         no-map;
 266                 };
 267
 268                 ipa_fw_mem: memory@86800000 {
 269                         reg = <0x0 0x86800000 0x0 0x10000>;
 270                         no-map;
 271                 };
 272
 273                 ipa_gsi_mem: memory@86810000 {
 274                         reg = <0x0 0x86810000 0x0 0xa000>;
 275                         no-map;
 276                 };
 277
 278                 gpu_mem: memory@8681a000 {
 279                         reg = <0x0 0x8681a000 0x0 0x2000>;
 280                         no-map;
 281                 };
 282
 283                 npu_mem: memory@86900000 {
 284                         reg = <0x0 0x86900000 0x0 0x500000>;
 285                         no-map;
 286                 };
 287
 288                 video_mem: memory@86e00000 {
 289                         reg = <0x0 0x86e00000 0x0 0x500000>;
 290                         no-map;
 291                 };
 292
 293                 cvp_mem: memory@87300000 {
 294                         reg = <0x0 0x87300000 0x0 0x500000>;
 295                         no-map;
 296                 };
 297
 298                 cdsp_mem: memory@87800000 {
 299                         reg = <0x0 0x87800000 0x0 0x1400000>;
 300                         no-map;
 301                 };
 302
 303                 slpi_mem: memory@88c00000 {
 304                         reg = <0x0 0x88c00000 0x0 0x1500000>;
 305                         no-map;
 306                 };
 307
 308                 adsp_mem: memory@8a100000 {
 309                         reg = <0x0 0x8a100000 0x0 0x1d00000>;
 310                         no-map;
 311                 };
 312
 313                 spss_mem: memory@8be00000 {
 314                         reg = <0x0 0x8be00000 0x0 0x100000>;
 315                         no-map;
 316                 };
 317
 318                 cdsp_secure_heap: memory@8bf00000 {
 319                         reg = <0x0 0x8bf00000 0x0 0x4600000>;
 320                         no-map;
 321                 };
 322         };
 323
 324         smem: qcom,smem {
 325                 compatible = "qcom,smem";
 326                 memory-region = <&smem_mem>;
 327                 hwlocks = <&tcsr_mutex 3>;
 328         };
 329
 330         smp2p-adsp {
 331                 compatible = "qcom,smp2p";
 332                 qcom,smem = <443>, <429>;
 333                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
 334                                              IPCC_MPROC_SIGNAL_SMP2P
 335                                              IRQ_TYPE_EDGE_RISING>;
 336                 mboxes = <&ipcc IPCC_CLIENT_LPASS
 337                                 IPCC_MPROC_SIGNAL_SMP2P>;
 338
 339                 qcom,local-pid = <0>;
 340                 qcom,remote-pid = <2>;
 341
 342                 smp2p_adsp_out: master-kernel {
 343                         qcom,entry-name = "master-kernel";
 344                         #qcom,smem-state-cells = <1>;
 345                 };
 346
 347                 smp2p_adsp_in: slave-kernel {
 348                         qcom,entry-name = "slave-kernel";
 349                         interrupt-controller;
 350                         #interrupt-cells = <2>;
 351                 };
 352         };
 353
 354         smp2p-cdsp {
 355                 compatible = "qcom,smp2p";
 356                 qcom,smem = <94>, <432>;
 357                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
 358                                              IPCC_MPROC_SIGNAL_SMP2P
 359                                              IRQ_TYPE_EDGE_RISING>;
 360                 mboxes = <&ipcc IPCC_CLIENT_CDSP
 361                                 IPCC_MPROC_SIGNAL_SMP2P>;
 362
 363                 qcom,local-pid = <0>;
 364                 qcom,remote-pid = <5>;
 365
 366                 smp2p_cdsp_out: master-kernel {
 367                         qcom,entry-name = "master-kernel";
 368                         #qcom,smem-state-cells = <1>;
 369                 };
 370
 371                 smp2p_cdsp_in: slave-kernel {
 372                         qcom,entry-name = "slave-kernel";
 373                         interrupt-controller;
 374                         #interrupt-cells = <2>;
 375                 };
 376         };
 377
 378         smp2p-slpi {
 379                 compatible = "qcom,smp2p";
 380                 qcom,smem = <481>, <430>;
 381                 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
 382                                              IPCC_MPROC_SIGNAL_SMP2P
 383                                              IRQ_TYPE_EDGE_RISING>;
 384                 mboxes = <&ipcc IPCC_CLIENT_SLPI
 385                                 IPCC_MPROC_SIGNAL_SMP2P>;
 386
 387                 qcom,local-pid = <0>;
 388                 qcom,remote-pid = <3>;
 389
 390                 smp2p_slpi_out: master-kernel {
 391                         qcom,entry-name = "master-kernel";
 392                         #qcom,smem-state-cells = <1>;
 393                 };
 394
 395                 smp2p_slpi_in: slave-kernel {
 396                         qcom,entry-name = "slave-kernel";
 397                         interrupt-controller;
 398                         #interrupt-cells = <2>;
 399                 };
 400         };
 401
 402         soc: soc@0 {
 403                 #address-cells = <2>;
 404                 #size-cells = <2>;
 405                 ranges = <0 0 0 0 0x10 0>;
 406                 dma-ranges = <0 0 0 0 0x10 0>;
 407                 compatible = "simple-bus";
 408
 409                 gcc: clock-controller@100000 {
 410                         compatible = "qcom,gcc-sm8250";
 411                         reg = <0x0 0x00100000 0x0 0x1f0000>;
 412                         #clock-cells = <1>;
 413                         #reset-cells = <1>;
 414                         #power-domain-cells = <1>;
 415                         clock-names = "bi_tcxo",
 416                                       "bi_tcxo_ao",
 417                                       "sleep_clk";
 418                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 419                                  <&rpmhcc RPMH_CXO_CLK_A>,
 420                                  <&sleep_clk>;
 421                 };
 422
 423                 ipcc: mailbox@408000 {
 424                         compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
 425                         reg = <0 0x00408000 0 0x1000>;
 426                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
 427                         interrupt-controller;
 428                         #interrupt-cells = <3>;
 429                         #mbox-cells = <2>;
 430                 };
 431
 432                 qup_opp_table: qup-opp-table {
 433                         compatible = "operating-points-v2";
 434
 435                         opp-50000000 {
 436                                 opp-hz = /bits/ 64 <50000000>;
 437                                 required-opps = <&rpmhpd_opp_min_svs>;
 438                         };
 439
 440                         opp-75000000 {
 441                                 opp-hz = /bits/ 64 <75000000>;
 442                                 required-opps = <&rpmhpd_opp_low_svs>;
 443                         };
 444
 445                         opp-120000000 {
 446                                 opp-hz = /bits/ 64 <120000000>;
 447                                 required-opps = <&rpmhpd_opp_svs>;
 448                         };
 449                 };
 450
 451                 qupv3_id_2: geniqup@8c0000 {
 452                         compatible = "qcom,geni-se-qup";
 453                         reg = <0x0 0x008c0000 0x0 0x6000>;
 454                         clock-names = "m-ahb", "s-ahb";
 455                         clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
 456                                  <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
 457                         #address-cells = <2>;
 458                         #size-cells = <2>;
 459                         ranges;
 460                         status = "disabled";
 461
 462                         i2c14: i2c@880000 {
 463                                 compatible = "qcom,geni-i2c";
 464                                 reg = <0 0x00880000 0 0x4000>;
 465                                 clock-names = "se";
 466                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
 467                                 pinctrl-names = "default";
 468                                 pinctrl-0 = <&qup_i2c14_default>;
 469                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
 470                                 #address-cells = <1>;
 471                                 #size-cells = <0>;
 472                                 status = "disabled";
 473                         };
 474
 475                         spi14: spi@880000 {
 476                                 compatible = "qcom,geni-spi";
 477                                 reg = <0 0x00880000 0 0x4000>;
 478                                 clock-names = "se";
 479                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
 480                                 pinctrl-names = "default";
 481                                 pinctrl-0 = <&qup_spi14_default>;
 482                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
 483                                 #address-cells = <1>;
 484                                 #size-cells = <0>;
 485                                 power-domains = <&rpmhpd SM8250_CX>;
 486                                 operating-points-v2 = <&qup_opp_table>;
 487                                 status = "disabled";
 488                         };
 489
 490                         i2c15: i2c@884000 {
 491                                 compatible = "qcom,geni-i2c";
 492                                 reg = <0 0x00884000 0 0x4000>;
 493                                 clock-names = "se";
 494                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
 495                                 pinctrl-names = "default";
 496                                 pinctrl-0 = <&qup_i2c15_default>;
 497                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
 498                                 #address-cells = <1>;
 499                                 #size-cells = <0>;
 500                                 status = "disabled";
 501                         };
 502
 503                         spi15: spi@884000 {
 504                                 compatible = "qcom,geni-spi";
 505                                 reg = <0 0x00884000 0 0x4000>;
 506                                 clock-names = "se";
 507                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
 508                                 pinctrl-names = "default";
 509                                 pinctrl-0 = <&qup_spi15_default>;
 510                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
 511                                 #address-cells = <1>;
 512                                 #size-cells = <0>;
 513                                 power-domains = <&rpmhpd SM8250_CX>;
 514                                 operating-points-v2 = <&qup_opp_table>;
 515                                 status = "disabled";
 516                         };
 517
 518                         i2c16: i2c@888000 {
 519                                 compatible = "qcom,geni-i2c";
 520                                 reg = <0 0x00888000 0 0x4000>;
 521                                 clock-names = "se";
 522                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
 523                                 pinctrl-names = "default";
 524                                 pinctrl-0 = <&qup_i2c16_default>;
 525                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
 526                                 #address-cells = <1>;
 527                                 #size-cells = <0>;
 528                                 status = "disabled";
 529                         };
 530
 531                         spi16: spi@888000 {
 532                                 compatible = "qcom,geni-spi";
 533                                 reg = <0 0x00888000 0 0x4000>;
 534                                 clock-names = "se";
 535                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
 536                                 pinctrl-names = "default";
 537                                 pinctrl-0 = <&qup_spi16_default>;
 538                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
 539                                 #address-cells = <1>;
 540                                 #size-cells = <0>;
 541                                 power-domains = <&rpmhpd SM8250_CX>;
 542                                 operating-points-v2 = <&qup_opp_table>;
 543                                 status = "disabled";
 544                         };
 545
 546                         i2c17: i2c@88c000 {
 547                                 compatible = "qcom,geni-i2c";
 548                                 reg = <0 0x0088c000 0 0x4000>;
 549                                 clock-names = "se";
 550                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
 551                                 pinctrl-names = "default";
 552                                 pinctrl-0 = <&qup_i2c17_default>;
 553                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
 554                                 #address-cells = <1>;
 555                                 #size-cells = <0>;
 556                                 status = "disabled";
 557                         };
 558
 559                         spi17: spi@88c000 {
 560                                 compatible = "qcom,geni-spi";
 561                                 reg = <0 0x0088c000 0 0x4000>;
 562                                 clock-names = "se";
 563                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
 564                                 pinctrl-names = "default";
 565                                 pinctrl-0 = <&qup_spi17_default>;
 566                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
 567                                 #address-cells = <1>;
 568                                 #size-cells = <0>;
 569                                 power-domains = <&rpmhpd SM8250_CX>;
 570                                 operating-points-v2 = <&qup_opp_table>;
 571                                 status = "disabled";
 572                         };
 573
 574                         uart17: serial@88c000 {
 575                                 compatible = "qcom,geni-uart";
 576                                 reg = <0 0x0088c000 0 0x4000>;
 577                                 clock-names = "se";
 578                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
 579                                 pinctrl-names = "default";
 580                                 pinctrl-0 = <&qup_uart17_default>;
 581                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
 582                                 power-domains = <&rpmhpd SM8250_CX>;
 583                                 operating-points-v2 = <&qup_opp_table>;
 584                                 status = "disabled";
 585                         };
 586
 587                         i2c18: i2c@890000 {
 588                                 compatible = "qcom,geni-i2c";
 589                                 reg = <0 0x00890000 0 0x4000>;
 590                                 clock-names = "se";
 591                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
 592                                 pinctrl-names = "default";
 593                                 pinctrl-0 = <&qup_i2c18_default>;
 594                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
 595                                 #address-cells = <1>;
 596                                 #size-cells = <0>;
 597                                 status = "disabled";
 598                         };
 599
 600                         spi18: spi@890000 {
 601                                 compatible = "qcom,geni-spi";
 602                                 reg = <0 0x00890000 0 0x4000>;
 603                                 clock-names = "se";
 604                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
 605                                 pinctrl-names = "default";
 606                                 pinctrl-0 = <&qup_spi18_default>;
 607                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
 608                                 #address-cells = <1>;
 609                                 #size-cells = <0>;
 610                                 power-domains = <&rpmhpd SM8250_CX>;
 611                                 operating-points-v2 = <&qup_opp_table>;
 612                                 status = "disabled";
 613                         };
 614
 615                         uart18: serial@890000 {
 616                                 compatible = "qcom,geni-uart";
 617                                 reg = <0 0x00890000 0 0x4000>;
 618                                 clock-names = "se";
 619                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
 620                                 pinctrl-names = "default";
 621                                 pinctrl-0 = <&qup_uart18_default>;
 622                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
 623                                 power-domains = <&rpmhpd SM8250_CX>;
 624                                 operating-points-v2 = <&qup_opp_table>;
 625                                 status = "disabled";
 626                         };
 627
 628                         i2c19: i2c@894000 {
 629                                 compatible = "qcom,geni-i2c";
 630                                 reg = <0 0x00894000 0 0x4000>;
 631                                 clock-names = "se";
 632                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
 633                                 pinctrl-names = "default";
 634                                 pinctrl-0 = <&qup_i2c19_default>;
 635                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
 636                                 #address-cells = <1>;
 637                                 #size-cells = <0>;
 638                                 status = "disabled";
 639                         };
 640
 641                         spi19: spi@894000 {
 642                                 compatible = "qcom,geni-spi";
 643                                 reg = <0 0x00894000 0 0x4000>;
 644                                 clock-names = "se";
 645                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
 646                                 pinctrl-names = "default";
 647                                 pinctrl-0 = <&qup_spi19_default>;
 648                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
 649                                 #address-cells = <1>;
 650                                 #size-cells = <0>;
 651                                 power-domains = <&rpmhpd SM8250_CX>;
 652                                 operating-points-v2 = <&qup_opp_table>;
 653                                 status = "disabled";
 654                         };
 655                 };
 656
 657                 qupv3_id_0: geniqup@9c0000 {
 658                         compatible = "qcom,geni-se-qup";
 659                         reg = <0x0 0x009c0000 0x0 0x6000>;
 660                         clock-names = "m-ahb", "s-ahb";
 661                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
 662                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
 663                         #address-cells = <2>;
 664                         #size-cells = <2>;
 665                         ranges;
 666                         status = "disabled";
 667
 668                         i2c0: i2c@980000 {
 669                                 compatible = "qcom,geni-i2c";
 670                                 reg = <0 0x00980000 0 0x4000>;
 671                                 clock-names = "se";
 672                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 673                                 pinctrl-names = "default";
 674                                 pinctrl-0 = <&qup_i2c0_default>;
 675                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 676                                 #address-cells = <1>;
 677                                 #size-cells = <0>;
 678                                 status = "disabled";
 679                         };
 680
 681                         spi0: spi@980000 {
 682                                 compatible = "qcom,geni-spi";
 683                                 reg = <0 0x00980000 0 0x4000>;
 684                                 clock-names = "se";
 685                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 686                                 pinctrl-names = "default";
 687                                 pinctrl-0 = <&qup_spi0_default>;
 688                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 689                                 #address-cells = <1>;
 690                                 #size-cells = <0>;
 691                                 power-domains = <&rpmhpd SM8250_CX>;
 692                                 operating-points-v2 = <&qup_opp_table>;
 693                                 status = "disabled";
 694                         };
 695
 696                         i2c1: i2c@984000 {
 697                                 compatible = "qcom,geni-i2c";
 698                                 reg = <0 0x00984000 0 0x4000>;
 699                                 clock-names = "se";
 700                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 701                                 pinctrl-names = "default";
 702                                 pinctrl-0 = <&qup_i2c1_default>;
 703                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 704                                 #address-cells = <1>;
 705                                 #size-cells = <0>;
 706                                 status = "disabled";
 707                         };
 708
 709                         spi1: spi@984000 {
 710                                 compatible = "qcom,geni-spi";
 711                                 reg = <0 0x00984000 0 0x4000>;
 712                                 clock-names = "se";
 713                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 714                                 pinctrl-names = "default";
 715                                 pinctrl-0 = <&qup_spi1_default>;
 716                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 717                                 #address-cells = <1>;
 718                                 #size-cells = <0>;
 719                                 power-domains = <&rpmhpd SM8250_CX>;
 720                                 operating-points-v2 = <&qup_opp_table>;
 721                                 status = "disabled";
 722                         };
 723
 724                         i2c2: i2c@988000 {
 725                                 compatible = "qcom,geni-i2c";
 726                                 reg = <0 0x00988000 0 0x4000>;
 727                                 clock-names = "se";
 728                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 729                                 pinctrl-names = "default";
 730                                 pinctrl-0 = <&qup_i2c2_default>;
 731                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
 732                                 #address-cells = <1>;
 733                                 #size-cells = <0>;
 734                                 status = "disabled";
 735                         };
 736
 737                         spi2: spi@988000 {
 738                                 compatible = "qcom,geni-spi";
 739                                 reg = <0 0x00988000 0 0x4000>;
 740                                 clock-names = "se";
 741                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 742                                 pinctrl-names = "default";
 743                                 pinctrl-0 = <&qup_spi2_default>;
 744                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
 745                                 #address-cells = <1>;
 746                                 #size-cells = <0>;
 747                                 power-domains = <&rpmhpd SM8250_CX>;
 748                                 operating-points-v2 = <&qup_opp_table>;
 749                                 status = "disabled";
 750                         };
 751
 752                         uart2: serial@988000 {
 753                                 compatible = "qcom,geni-debug-uart";
 754                                 reg = <0 0x00988000 0 0x4000>;
 755                                 clock-names = "se";
 756                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 757                                 pinctrl-names = "default";
 758                                 pinctrl-0 = <&qup_uart2_default>;
 759                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
 760                                 power-domains = <&rpmhpd SM8250_CX>;
 761                                 operating-points-v2 = <&qup_opp_table>;
 762                                 status = "disabled";
 763                         };
 764
 765                         i2c3: i2c@98c000 {
 766                                 compatible = "qcom,geni-i2c";
 767                                 reg = <0 0x0098c000 0 0x4000>;
 768                                 clock-names = "se";
 769                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 770                                 pinctrl-names = "default";
 771                                 pinctrl-0 = <&qup_i2c3_default>;
 772                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 773                                 #address-cells = <1>;
 774                                 #size-cells = <0>;
 775                                 status = "disabled";
 776                         };
 777
 778                         spi3: spi@98c000 {
 779                                 compatible = "qcom,geni-spi";
 780                                 reg = <0 0x0098c000 0 0x4000>;
 781                                 clock-names = "se";
 782                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 783                                 pinctrl-names = "default";
 784                                 pinctrl-0 = <&qup_spi3_default>;
 785                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 786                                 #address-cells = <1>;
 787                                 #size-cells = <0>;
 788                                 power-domains = <&rpmhpd SM8250_CX>;
 789                                 operating-points-v2 = <&qup_opp_table>;
 790                                 status = "disabled";
 791                         };
 792
 793                         i2c4: i2c@990000 {
 794                                 compatible = "qcom,geni-i2c";
 795                                 reg = <0 0x00990000 0 0x4000>;
 796                                 clock-names = "se";
 797                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
 798                                 pinctrl-names = "default";
 799                                 pinctrl-0 = <&qup_i2c4_default>;
 800                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
 801                                 #address-cells = <1>;
 802                                 #size-cells = <0>;
 803                                 status = "disabled";
 804                         };
 805
 806                         spi4: spi@990000 {
 807                                 compatible = "qcom,geni-spi";
 808                                 reg = <0 0x00990000 0 0x4000>;
 809                                 clock-names = "se";
 810                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
 811                                 pinctrl-names = "default";
 812                                 pinctrl-0 = <&qup_spi4_default>;
 813                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
 814                                 #address-cells = <1>;
 815                                 #size-cells = <0>;
 816                                 power-domains = <&rpmhpd SM8250_CX>;
 817                                 operating-points-v2 = <&qup_opp_table>;
 818                                 status = "disabled";
 819                         };
 820
 821                         i2c5: i2c@994000 {
 822                                 compatible = "qcom,geni-i2c";
 823                                 reg = <0 0x00994000 0 0x4000>;
 824                                 clock-names = "se";
 825                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
 826                                 pinctrl-names = "default";
 827                                 pinctrl-0 = <&qup_i2c5_default>;
 828                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
 829                                 #address-cells = <1>;
 830                                 #size-cells = <0>;
 831                                 status = "disabled";
 832                         };
 833
 834                         spi5: spi@994000 {
 835                                 compatible = "qcom,geni-spi";
 836                                 reg = <0 0x00994000 0 0x4000>;
 837                                 clock-names = "se";
 838                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
 839                                 pinctrl-names = "default";
 840                                 pinctrl-0 = <&qup_spi5_default>;
 841                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
 842                                 #address-cells = <1>;
 843                                 #size-cells = <0>;
 844                                 power-domains = <&rpmhpd SM8250_CX>;
 845                                 operating-points-v2 = <&qup_opp_table>;
 846                                 status = "disabled";
 847                         };
 848
 849                         i2c6: i2c@998000 {
 850                                 compatible = "qcom,geni-i2c";
 851                                 reg = <0 0x00998000 0 0x4000>;
 852                                 clock-names = "se";
 853                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
 854                                 pinctrl-names = "default";
 855                                 pinctrl-0 = <&qup_i2c6_default>;
 856                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
 857                                 #address-cells = <1>;
 858                                 #size-cells = <0>;
 859                                 status = "disabled";
 860                         };
 861
 862                         spi6: spi@998000 {
 863                                 compatible = "qcom,geni-spi";
 864                                 reg = <0 0x00998000 0 0x4000>;
 865                                 clock-names = "se";
 866                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
 867                                 pinctrl-names = "default";
 868                                 pinctrl-0 = <&qup_spi6_default>;
 869                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
 870                                 #address-cells = <1>;
 871                                 #size-cells = <0>;
 872                                 power-domains = <&rpmhpd SM8250_CX>;
 873                                 operating-points-v2 = <&qup_opp_table>;
 874                                 status = "disabled";
 875                         };
 876
 877                         uart6: serial@998000 {
 878                                 compatible = "qcom,geni-uart";
 879                                 reg = <0 0x00998000 0 0x4000>;
 880                                 clock-names = "se";
 881                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
 882                                 pinctrl-names = "default";
 883                                 pinctrl-0 = <&qup_uart6_default>;
 884                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
 885                                 power-domains = <&rpmhpd SM8250_CX>;
 886                                 operating-points-v2 = <&qup_opp_table>;
 887                                 status = "disabled";
 888                         };
 889
 890                         i2c7: i2c@99c000 {
 891                                 compatible = "qcom,geni-i2c";
 892                                 reg = <0 0x0099c000 0 0x4000>;
 893                                 clock-names = "se";
 894                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
 895                                 pinctrl-names = "default";
 896                                 pinctrl-0 = <&qup_i2c7_default>;
 897                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
 898                                 #address-cells = <1>;
 899                                 #size-cells = <0>;
 900                                 status = "disabled";
 901                         };
 902
 903                         spi7: spi@99c000 {
 904                                 compatible = "qcom,geni-spi";
 905                                 reg = <0 0x0099c000 0 0x4000>;
 906                                 clock-names = "se";
 907                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
 908                                 pinctrl-names = "default";
 909                                 pinctrl-0 = <&qup_spi7_default>;
 910                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
 911                                 #address-cells = <1>;
 912                                 #size-cells = <0>;
 913                                 power-domains = <&rpmhpd SM8250_CX>;
 914                                 operating-points-v2 = <&qup_opp_table>;
 915                                 status = "disabled";
 916                         };
 917                 };
 918
 919                 qupv3_id_1: geniqup@ac0000 {
 920                         compatible = "qcom,geni-se-qup";
 921                         reg = <0x0 0x00ac0000 0x0 0x6000>;
 922                         clock-names = "m-ahb", "s-ahb";
 923                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
 924                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
 925                         #address-cells = <2>;
 926                         #size-cells = <2>;
 927                         ranges;
 928                         status = "disabled";
 929
 930                         i2c8: i2c@a80000 {
 931                                 compatible = "qcom,geni-i2c";
 932                                 reg = <0 0x00a80000 0 0x4000>;
 933                                 clock-names = "se";
 934                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
 935                                 pinctrl-names = "default";
 936                                 pinctrl-0 = <&qup_i2c8_default>;
 937                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
 938                                 #address-cells = <1>;
 939                                 #size-cells = <0>;
 940                                 status = "disabled";
 941                         };
 942
 943                         spi8: spi@a80000 {
 944                                 compatible = "qcom,geni-spi";
 945                                 reg = <0 0x00a80000 0 0x4000>;
 946                                 clock-names = "se";
 947                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
 948                                 pinctrl-names = "default";
 949                                 pinctrl-0 = <&qup_spi8_default>;
 950                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
 951                                 #address-cells = <1>;
 952                                 #size-cells = <0>;
 953                                 power-domains = <&rpmhpd SM8250_CX>;
 954                                 operating-points-v2 = <&qup_opp_table>;
 955                                 status = "disabled";
 956                         };
 957
 958                         i2c9: i2c@a84000 {
 959                                 compatible = "qcom,geni-i2c";
 960                                 reg = <0 0x00a84000 0 0x4000>;
 961                                 clock-names = "se";
 962                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
 963                                 pinctrl-names = "default";
 964                                 pinctrl-0 = <&qup_i2c9_default>;
 965                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
 966                                 #address-cells = <1>;
 967                                 #size-cells = <0>;
 968                                 status = "disabled";
 969                         };
 970
 971                         spi9: spi@a84000 {
 972                                 compatible = "qcom,geni-spi";
 973                                 reg = <0 0x00a84000 0 0x4000>;
 974                                 clock-names = "se";
 975                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
 976                                 pinctrl-names = "default";
 977                                 pinctrl-0 = <&qup_spi9_default>;
 978                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
 979                                 #address-cells = <1>;
 980                                 #size-cells = <0>;
 981                                 power-domains = <&rpmhpd SM8250_CX>;
 982                                 operating-points-v2 = <&qup_opp_table>;
 983                                 status = "disabled";
 984                         };
 985
 986                         i2c10: i2c@a88000 {
 987                                 compatible = "qcom,geni-i2c";
 988                                 reg = <0 0x00a88000 0 0x4000>;
 989                                 clock-names = "se";
 990                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
 991                                 pinctrl-names = "default";
 992                                 pinctrl-0 = <&qup_i2c10_default>;
 993                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
 994                                 #address-cells = <1>;
 995                                 #size-cells = <0>;
 996                                 status = "disabled";
 997                         };
 998
 999                         spi10: spi@a88000 {
1000                                 compatible = "qcom,geni-spi";
1001                                 reg = <0 0x00a88000 0 0x4000>;
1002                                 clock-names = "se";
1003                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1004                                 pinctrl-names = "default";
1005                                 pinctrl-0 = <&qup_spi10_default>;
1006                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1007                                 #address-cells = <1>;
1008                                 #size-cells = <0>;
1009                                 power-domains = <&rpmhpd SM8250_CX>;
1010                                 operating-points-v2 = <&qup_opp_table>;
1011                                 status = "disabled";
1012                         };
1013
1014                         i2c11: i2c@a8c000 {
1015                                 compatible = "qcom,geni-i2c";
1016                                 reg = <0 0x00a8c000 0 0x4000>;
1017                                 clock-names = "se";
1018                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1019                                 pinctrl-names = "default";
1020                                 pinctrl-0 = <&qup_i2c11_default>;
1021                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1022                                 #address-cells = <1>;
1023                                 #size-cells = <0>;
1024                                 status = "disabled";
1025                         };
1026
1027                         spi11: spi@a8c000 {
1028                                 compatible = "qcom,geni-spi";
1029                                 reg = <0 0x00a8c000 0 0x4000>;
1030                                 clock-names = "se";
1031                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1032                                 pinctrl-names = "default";
1033                                 pinctrl-0 = <&qup_spi11_default>;
1034                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1035                                 #address-cells = <1>;
1036                                 #size-cells = <0>;
1037                                 power-domains = <&rpmhpd SM8250_CX>;
1038                                 operating-points-v2 = <&qup_opp_table>;
1039                                 status = "disabled";
1040                         };
1041
1042                         i2c12: i2c@a90000 {
1043                                 compatible = "qcom,geni-i2c";
1044                                 reg = <0 0x00a90000 0 0x4000>;
1045                                 clock-names = "se";
1046                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1047                                 pinctrl-names = "default";
1048                                 pinctrl-0 = <&qup_i2c12_default>;
1049                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1050                                 #address-cells = <1>;
1051                                 #size-cells = <0>;
1052                                 status = "disabled";
1053                         };
1054
1055                         spi12: spi@a90000 {
1056                                 compatible = "qcom,geni-spi";
1057                                 reg = <0 0x00a90000 0 0x4000>;
1058                                 clock-names = "se";
1059                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1060                                 pinctrl-names = "default";
1061                                 pinctrl-0 = <&qup_spi12_default>;
1062                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1063                                 #address-cells = <1>;
1064                                 #size-cells = <0>;
1065                                 power-domains = <&rpmhpd SM8250_CX>;
1066                                 operating-points-v2 = <&qup_opp_table>;
1067                                 status = "disabled";
1068                         };
1069
1070                         uart12: serial@a90000 {
1071                                 compatible = "qcom,geni-debug-uart";
1072                                 reg = <0x0 0x00a90000 0x0 0x4000>;
1073                                 clock-names = "se";
1074                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1075                                 pinctrl-names = "default";
1076                                 pinctrl-0 = <&qup_uart12_default>;
1077                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1078                                 power-domains = <&rpmhpd SM8250_CX>;
1079                                 operating-points-v2 = <&qup_opp_table>;
1080                                 status = "disabled";
1081                         };
1082
1083                         i2c13: i2c@a94000 {
1084                                 compatible = "qcom,geni-i2c";
1085                                 reg = <0 0x00a94000 0 0x4000>;
1086                                 clock-names = "se";
1087                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1088                                 pinctrl-names = "default";
1089                                 pinctrl-0 = <&qup_i2c13_default>;
1090                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1091                                 #address-cells = <1>;
1092                                 #size-cells = <0>;
1093                                 status = "disabled";
1094                         };
1095
1096                         spi13: spi@a94000 {
1097                                 compatible = "qcom,geni-spi";
1098                                 reg = <0 0x00a94000 0 0x4000>;
1099                                 clock-names = "se";
1100                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1101                                 pinctrl-names = "default";
1102                                 pinctrl-0 = <&qup_spi13_default>;
1103                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1104                                 #address-cells = <1>;
1105                                 #size-cells = <0>;
1106                                 power-domains = <&rpmhpd SM8250_CX>;
1107                                 operating-points-v2 = <&qup_opp_table>;
1108                                 status = "disabled";
1109                         };
1110                 };
1111
1112                 config_noc: interconnect@1500000 {
1113                         compatible = "qcom,sm8250-config-noc";
1114                         reg = <0 0x01500000 0 0xa580>;
1115                         #interconnect-cells = <1>;
1116                         qcom,bcm-voters = <&apps_bcm_voter>;
1117                 };
1118
1119                 system_noc: interconnect@1620000 {
1120                         compatible = "qcom,sm8250-system-noc";
1121                         reg = <0 0x01620000 0 0x1c200>;
1122                         #interconnect-cells = <1>;
1123                         qcom,bcm-voters = <&apps_bcm_voter>;
1124                 };
1125
1126                 mc_virt: interconnect@163d000 {
1127                         compatible = "qcom,sm8250-mc-virt";
1128                         reg = <0 0x0163d000 0 0x1000>;
1129                         #interconnect-cells = <1>;
1130                         qcom,bcm-voters = <&apps_bcm_voter>;
1131                 };
1132
1133                 aggre1_noc: interconnect@16e0000 {
1134                         compatible = "qcom,sm8250-aggre1-noc";
1135                         reg = <0 0x016e0000 0 0x1f180>;
1136                         #interconnect-cells = <1>;
1137                         qcom,bcm-voters = <&apps_bcm_voter>;
1138                 };
1139
1140                 aggre2_noc: interconnect@1700000 {
1141                         compatible = "qcom,sm8250-aggre2-noc";
1142                         reg = <0 0x01700000 0 0x33000>;
1143                         #interconnect-cells = <1>;
1144                         qcom,bcm-voters = <&apps_bcm_voter>;
1145                 };
1146
1147                 compute_noc: interconnect@1733000 {
1148                         compatible = "qcom,sm8250-compute-noc";
1149                         reg = <0 0x01733000 0 0xa180>;
1150                         #interconnect-cells = <1>;
1151                         qcom,bcm-voters = <&apps_bcm_voter>;
1152                 };
1153
1154                 mmss_noc: interconnect@1740000 {
1155                         compatible = "qcom,sm8250-mmss-noc";
1156                         reg = <0 0x01740000 0 0x1f080>;
1157                         #interconnect-cells = <1>;
1158                         qcom,bcm-voters = <&apps_bcm_voter>;
1159                 };
1160
1161                 ufs_mem_hc: ufshc@1d84000 {
1162                         compatible = "qcom,sm8250-ufshc", "qcom,ufshc",
1163                                      "jedec,ufs-2.0";
1164                         reg = <0 0x01d84000 0 0x3000>;
1165                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1166                         phys = <&ufs_mem_phy_lanes>;
1167                         phy-names = "ufsphy";
1168                         lanes-per-direction = <2>;
1169                         #reset-cells = <1>;
1170                         resets = <&gcc GCC_UFS_PHY_BCR>;
1171                         reset-names = "rst";
1172
1173                         power-domains = <&gcc UFS_PHY_GDSC>;
1174
1175                         clock-names =
1176                                 "core_clk",
1177                                 "bus_aggr_clk",
1178                                 "iface_clk",
1179                                 "core_clk_unipro",
1180                                 "ref_clk",
1181                                 "tx_lane0_sync_clk",
1182                                 "rx_lane0_sync_clk",
1183                                 "rx_lane1_sync_clk";
1184                         clocks =
1185                                 <&gcc GCC_UFS_PHY_AXI_CLK>,
1186                                 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1187                                 <&gcc GCC_UFS_PHY_AHB_CLK>,
1188                                 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1189                                 <&rpmhcc RPMH_CXO_CLK>,
1190                                 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1191                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
1192                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
1193                         freq-table-hz =
1194                                 <37500000 300000000>,
1195                                 <0 0>,
1196                                 <0 0>,
1197                                 <37500000 300000000>,
1198                                 <0 0>,
1199                                 <0 0>,
1200                                 <0 0>,
1201                                 <0 0>;
1202
1203                         status = "disabled";
1204                 };
1205
1206                 ufs_mem_phy: phy@1d87000 {
1207                         compatible = "qcom,sm8250-qmp-ufs-phy";
1208                         reg = <0 0x01d87000 0 0x1c0>;
1209                         #address-cells = <2>;
1210                         #size-cells = <2>;
1211                         ranges;
1212                         clock-names = "ref",
1213                                       "ref_aux";
1214                         clocks = <&rpmhcc RPMH_CXO_CLK>,
1215                                  <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
1216
1217                         resets = <&ufs_mem_hc 0>;
1218                         reset-names = "ufsphy";
1219                         status = "disabled";
1220
1221                         ufs_mem_phy_lanes: lanes@1d87400 {
1222                                 reg = <0 0x01d87400 0 0x108>,
1223                                       <0 0x01d87600 0 0x1e0>,
1224                                       <0 0x01d87c00 0 0x1dc>,
1225                                       <0 0x01d87800 0 0x108>,
1226                                       <0 0x01d87a00 0 0x1e0>;
1227                                 #phy-cells = <0>;
1228                         };
1229                 };
1230
1231                 ipa_virt: interconnect@1e00000 {
1232                         compatible = "qcom,sm8250-ipa-virt";
1233                         reg = <0 0x01e00000 0 0x1000>;
1234                         #interconnect-cells = <1>;
1235                         qcom,bcm-voters = <&apps_bcm_voter>;
1236                 };
1237
1238                 tcsr_mutex: hwlock@1f40000 {
1239                         compatible = "qcom,tcsr-mutex";
1240                         reg = <0x0 0x01f40000 0x0 0x40000>;
1241                         #hwlock-cells = <1>;
1242                 };
1243
1244                 gpu: gpu@3d00000 {
1245                         /*
1246                          * note: the amd,imageon compatible makes it possible
1247                          * to use the drm/msm driver without the display node,
1248                          * make sure to remove it when display node is added
1249                          */
1250                         compatible = "qcom,adreno-650.2",
1251                                      "qcom,adreno",
1252                                      "amd,imageon";
1253                         #stream-id-cells = <16>;
1254
1255                         reg = <0 0x03d00000 0 0x40000>;
1256                         reg-names = "kgsl_3d0_reg_memory";
1257
1258                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1259
1260                         iommus = <&adreno_smmu 0 0x401>;
1261
1262                         operating-points-v2 = <&gpu_opp_table>;
1263
1264                         qcom,gmu = <&gmu>;
1265
1266                         zap-shader {
1267                                 memory-region = <&gpu_mem>;
1268                         };
1269
1270                         /* note: downstream checks gpu binning for 670 Mhz */
1271                         gpu_opp_table: opp-table {
1272                                 compatible = "operating-points-v2";
1273
1274                                 opp-670000000 {
1275                                         opp-hz = /bits/ 64 <670000000>;
1276                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1277                                 };
1278
1279                                 opp-587000000 {
1280                                         opp-hz = /bits/ 64 <587000000>;
1281                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1282                                 };
1283
1284                                 opp-525000000 {
1285                                         opp-hz = /bits/ 64 <525000000>;
1286                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
1287                                 };
1288
1289                                 opp-490000000 {
1290                                         opp-hz = /bits/ 64 <490000000>;
1291                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1292                                 };
1293
1294                                 opp-441600000 {
1295                                         opp-hz = /bits/ 64 <441600000>;
1296                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
1297                                 };
1298
1299                                 opp-400000000 {
1300                                         opp-hz = /bits/ 64 <400000000>;
1301                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1302                                 };
1303
1304                                 opp-305000000 {
1305                                         opp-hz = /bits/ 64 <305000000>;
1306                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1307                                 };
1308                         };
1309                 };
1310
1311                 gmu: gmu@3d6a000 {
1312                         compatible="qcom,adreno-gmu-650.2", "qcom,adreno-gmu";
1313
1314                         reg = <0 0x03d6a000 0 0x30000>,
1315                               <0 0x3de0000 0 0x10000>,
1316                               <0 0xb290000 0 0x10000>,
1317                               <0 0xb490000 0 0x10000>;
1318                         reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq";
1319
1320                         interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
1321                                      <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
1322                         interrupt-names = "hfi", "gmu";
1323
1324                         clocks = <&gpucc GPU_CC_AHB_CLK>,
1325                                  <&gpucc GPU_CC_CX_GMU_CLK>,
1326                                  <&gpucc GPU_CC_CXO_CLK>,
1327                                  <&gcc GCC_DDRSS_GPU_AXI_CLK>,
1328                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
1329                         clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
1330
1331                         power-domains = <&gpucc GPU_CX_GDSC>,
1332                                         <&gpucc GPU_GX_GDSC>;
1333                         power-domain-names = "cx", "gx";
1334
1335                         iommus = <&adreno_smmu 5 0x400>;
1336
1337                         operating-points-v2 = <&gmu_opp_table>;
1338
1339                         gmu_opp_table: opp-table {
1340                                 compatible = "operating-points-v2";
1341
1342                                 opp-200000000 {
1343                                         opp-hz = /bits/ 64 <200000000>;
1344                                         opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1345                                 };
1346                         };
1347                 };
1348
1349                 gpucc: clock-controller@3d90000 {
1350                         compatible = "qcom,sm8250-gpucc";
1351                         reg = <0 0x03d90000 0 0x9000>;
1352                         clocks = <&rpmhcc RPMH_CXO_CLK>,
1353                                  <&gcc GCC_GPU_GPLL0_CLK_SRC>,
1354                                  <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
1355                         clock-names = "bi_tcxo",
1356                                       "gcc_gpu_gpll0_clk_src",
1357                                       "gcc_gpu_gpll0_div_clk_src";
1358                         #clock-cells = <1>;
1359                         #reset-cells = <1>;
1360                         #power-domain-cells = <1>;
1361                 };
1362
1363                 adreno_smmu: iommu@3da0000 {
1364                         compatible = "qcom,sm8250-smmu-500", "arm,mmu-500";
1365                         reg = <0 0x03da0000 0 0x10000>;
1366                         #iommu-cells = <2>;
1367                         #global-interrupts = <2>;
1368                         interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
1369                                      <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
1370                                      <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
1371                                      <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
1372                                      <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
1373                                      <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
1374                                      <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
1375                                      <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
1376                                      <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
1377                                      <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>;
1378                         clocks = <&gpucc GPU_CC_AHB_CLK>,
1379                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
1380                                  <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
1381                         clock-names = "ahb", "bus", "iface";
1382
1383                         power-domains = <&gpucc GPU_CX_GDSC>;
1384                 };
1385
1386                 slpi: remoteproc@5c00000 {
1387                         compatible = "qcom,sm8250-slpi-pas";
1388                         reg = <0 0x05c00000 0 0x4000>;
1389
1390                         interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
1391                                               <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
1392                                               <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
1393                                               <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
1394                                               <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
1395                         interrupt-names = "wdog", "fatal", "ready",
1396                                           "handover", "stop-ack";
1397
1398                         clocks = <&rpmhcc RPMH_CXO_CLK>;
1399                         clock-names = "xo";
1400
1401                         power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>,
1402                                         <&rpmhpd SM8250_LCX>,
1403                                         <&rpmhpd SM8250_LMX>;
1404                         power-domain-names = "load_state", "lcx", "lmx";
1405
1406                         memory-region = <&slpi_mem>;
1407
1408                         qcom,smem-states = <&smp2p_slpi_out 0>;
1409                         qcom,smem-state-names = "stop";
1410
1411                         status = "disabled";
1412
1413                         glink-edge {
1414                                 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
1415                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
1416                                                              IRQ_TYPE_EDGE_RISING>;
1417                                 mboxes = <&ipcc IPCC_CLIENT_SLPI
1418                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
1419
1420                                 label = "lpass";
1421                                 qcom,remote-pid = <3>;
1422                         };
1423                 };
1424
1425                 cdsp: remoteproc@8300000 {
1426                         compatible = "qcom,sm8250-cdsp-pas";
1427                         reg = <0 0x08300000 0 0x10000>;
1428
1429                         interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
1430                                               <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
1431                                               <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
1432                                               <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
1433                                               <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
1434                         interrupt-names = "wdog", "fatal", "ready",
1435                                           "handover", "stop-ack";
1436
1437                         clocks = <&rpmhcc RPMH_CXO_CLK>;
1438                         clock-names = "xo";
1439
1440                         power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>,
1441                                         <&rpmhpd SM8250_CX>;
1442                         power-domain-names = "load_state", "cx";
1443
1444                         memory-region = <&cdsp_mem>;
1445
1446                         qcom,smem-states = <&smp2p_cdsp_out 0>;
1447                         qcom,smem-state-names = "stop";
1448
1449                         status = "disabled";
1450
1451                         glink-edge {
1452                                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
1453                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
1454                                                              IRQ_TYPE_EDGE_RISING>;
1455                                 mboxes = <&ipcc IPCC_CLIENT_CDSP
1456                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
1457
1458                                 label = "lpass";
1459                                 qcom,remote-pid = <5>;
1460                         };
1461                 };
1462
1463                 dc_noc: interconnect@90c0000 {
1464                         compatible = "qcom,sm8250-dc-noc";
1465                         reg = <0 0x090c0000 0 0x4200>;
1466                         #interconnect-cells = <1>;
1467                         qcom,bcm-voters = <&apps_bcm_voter>;
1468                 };
1469
1470                 gem_noc: interconnect@9100000 {
1471                         compatible = "qcom,sm8250-gem-noc";
1472                         reg = <0 0x09100000 0 0xb4000>;
1473                         #interconnect-cells = <1>;
1474                         qcom,bcm-voters = <&apps_bcm_voter>;
1475                 };
1476
1477                 npu_noc: interconnect@9990000 {
1478                         compatible = "qcom,sm8250-npu-noc";
1479                         reg = <0 0x09990000 0 0x1600>;
1480                         #interconnect-cells = <1>;
1481                         qcom,bcm-voters = <&apps_bcm_voter>;
1482                 };
1483
1484                 pdc: interrupt-controller@b220000 {
1485                         compatible = "qcom,sm8250-pdc", "qcom,pdc";
1486                         reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
1487                         qcom,pdc-ranges = <0 480 94>, <94 609 31>,
1488                                           <125 63 1>, <126 716 12>;
1489                         #interrupt-cells = <2>;
1490                         interrupt-parent = <&intc>;
1491                         interrupt-controller;
1492                 };
1493
1494                 tsens0: thermal-sensor@c263000 {
1495                         compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
1496                         reg = <0 0x0c263000 0 0x1ff>, /* TM */
1497                               <0 0x0c222000 0 0x1ff>; /* SROT */
1498                         #qcom,sensors = <16>;
1499                         interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
1500                                      <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
1501                         interrupt-names = "uplow", "critical";
1502                         #thermal-sensor-cells = <1>;
1503                 };
1504
1505                 tsens1: thermal-sensor@c265000 {
1506                         compatible = "qcom,sm8250-tsens", "qcom,tsens-v2";
1507                         reg = <0 0x0c265000 0 0x1ff>, /* TM */
1508                               <0 0x0c223000 0 0x1ff>; /* SROT */
1509                         #qcom,sensors = <9>;
1510                         interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
1511                                      <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
1512                         interrupt-names = "uplow", "critical";
1513                         #thermal-sensor-cells = <1>;
1514                 };
1515
1516                 aoss_qmp: qmp@c300000 {
1517                         compatible = "qcom,sm8250-aoss-qmp";
1518                         reg = <0 0x0c300000 0 0x100000>;
1519                         interrupts-extended = <&ipcc IPCC_CLIENT_AOP
1520                                                      IPCC_MPROC_SIGNAL_GLINK_QMP
1521                                                      IRQ_TYPE_EDGE_RISING>;
1522                         mboxes = <&ipcc IPCC_CLIENT_AOP
1523                                         IPCC_MPROC_SIGNAL_GLINK_QMP>;
1524
1525                         #clock-cells = <0>;
1526                         #power-domain-cells = <1>;
1527                 };
1528
1529                 spmi_bus: spmi@c440000 {
1530                         compatible = "qcom,spmi-pmic-arb";
1531                         reg = <0x0 0x0c440000 0x0 0x0001100>,
1532                               <0x0 0x0c600000 0x0 0x2000000>,
1533                               <0x0 0x0e600000 0x0 0x0100000>,
1534                               <0x0 0x0e700000 0x0 0x00a0000>,
1535                               <0x0 0x0c40a000 0x0 0x0026000>;
1536                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1537                         interrupt-names = "periph_irq";
1538                         interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
1539                         qcom,ee = <0>;
1540                         qcom,channel = <0>;
1541                         #address-cells = <2>;
1542                         #size-cells = <0>;
1543                         interrupt-controller;
1544                         #interrupt-cells = <4>;
1545                 };
1546
1547                 tlmm: pinctrl@f100000 {
1548                         compatible = "qcom,sm8250-pinctrl";
1549                         reg = <0 0x0f100000 0 0x300000>,
1550                               <0 0x0f500000 0 0x300000>,
1551                               <0 0x0f900000 0 0x300000>;
1552                         reg-names = "west", "south", "north";
1553                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1554                         gpio-controller;
1555                         #gpio-cells = <2>;
1556                         interrupt-controller;
1557                         #interrupt-cells = <2>;
1558                         gpio-ranges = <&tlmm 0 0 180>;
1559                         wakeup-parent = <&pdc>;
1560
1561                         qup_i2c0_default: qup-i2c0-default {
1562                                 mux {
1563                                         pins = "gpio28", "gpio29";
1564                                         function = "qup0";
1565                                 };
1566
1567                                 config {
1568                                         pins = "gpio28", "gpio29";
1569                                         drive-strength = <2>;
1570                                         bias-disable;
1571                                 };
1572                         };
1573
1574                         qup_i2c1_default: qup-i2c1-default {
1575                                 pinmux {
1576                                         pins = "gpio4", "gpio5";
1577                                         function = "qup1";
1578                                 };
1579
1580                                 config {
1581                                         pins = "gpio4", "gpio5";
1582                                         drive-strength = <2>;
1583                                         bias-disable;
1584                                 };
1585                         };
1586
1587                         qup_i2c2_default: qup-i2c2-default {
1588                                 mux {
1589                                         pins = "gpio115", "gpio116";
1590                                         function = "qup2";
1591                                 };
1592
1593                                 config {
1594                                         pins = "gpio115", "gpio116";
1595                                         drive-strength = <2>;
1596                                         bias-disable;
1597                                 };
1598                         };
1599
1600                         qup_i2c3_default: qup-i2c3-default {
1601                                 mux {
1602                                         pins = "gpio119", "gpio120";
1603                                         function = "qup3";
1604                                 };
1605
1606                                 config {
1607                                         pins = "gpio119", "gpio120";
1608                                         drive-strength = <2>;
1609                                         bias-disable;
1610                                 };
1611                         };
1612
1613                         qup_i2c4_default: qup-i2c4-default {
1614                                 mux {
1615                                         pins = "gpio8", "gpio9";
1616                                         function = "qup4";
1617                                 };
1618
1619                                 config {
1620                                         pins = "gpio8", "gpio9";
1621                                         drive-strength = <2>;
1622                                         bias-disable;
1623                                 };
1624                         };
1625
1626                         qup_i2c5_default: qup-i2c5-default {
1627                                 mux {
1628                                         pins = "gpio12", "gpio13";
1629                                         function = "qup5";
1630                                 };
1631
1632                                 config {
1633                                         pins = "gpio12", "gpio13";
1634                                         drive-strength = <2>;
1635                                         bias-disable;
1636                                 };
1637                         };
1638
1639                         qup_i2c6_default: qup-i2c6-default {
1640                                 mux {
1641                                         pins = "gpio16", "gpio17";
1642                                         function = "qup6";
1643                                 };
1644
1645                                 config {
1646                                         pins = "gpio16", "gpio17";
1647                                         drive-strength = <2>;
1648                                         bias-disable;
1649                                 };
1650                         };
1651
1652                         qup_i2c7_default: qup-i2c7-default {
1653                                 mux {
1654                                         pins = "gpio20", "gpio21";
1655                                         function = "qup7";
1656                                 };
1657
1658                                 config {
1659                                         pins = "gpio20", "gpio21";
1660                                         drive-strength = <2>;
1661                                         bias-disable;
1662                                 };
1663                         };
1664
1665                         qup_i2c8_default: qup-i2c8-default {
1666                                 mux {
1667                                         pins = "gpio24", "gpio25";
1668                                         function = "qup8";
1669                                 };
1670
1671                                 config {
1672                                         pins = "gpio24", "gpio25";
1673                                         drive-strength = <2>;
1674                                         bias-disable;
1675                                 };
1676                         };
1677
1678                         qup_i2c9_default: qup-i2c9-default {
1679                                 mux {
1680                                         pins = "gpio125", "gpio126";
1681                                         function = "qup9";
1682                                 };
1683
1684                                 config {
1685                                         pins = "gpio125", "gpio126";
1686                                         drive-strength = <2>;
1687                                         bias-disable;
1688                                 };
1689                         };
1690
1691                         qup_i2c10_default: qup-i2c10-default {
1692                                 mux {
1693                                         pins = "gpio129", "gpio130";
1694                                         function = "qup10";
1695                                 };
1696
1697                                 config {
1698                                         pins = "gpio129", "gpio130";
1699                                         drive-strength = <2>;
1700                                         bias-disable;
1701                                 };
1702                         };
1703
1704                         qup_i2c11_default: qup-i2c11-default {
1705                                 mux {
1706                                         pins = "gpio60", "gpio61";
1707                                         function = "qup11";
1708                                 };
1709
1710                                 config {
1711                                         pins = "gpio60", "gpio61";
1712                                         drive-strength = <2>;
1713                                         bias-disable;
1714                                 };
1715                         };
1716
1717                         qup_i2c12_default: qup-i2c12-default {
1718                                 mux {
1719                                         pins = "gpio32", "gpio33";
1720                                         function = "qup12";
1721                                 };
1722
1723                                 config {
1724                                         pins = "gpio32", "gpio33";
1725                                         drive-strength = <2>;
1726                                         bias-disable;
1727                                 };
1728                         };
1729
1730                         qup_i2c13_default: qup-i2c13-default {
1731                                 mux {
1732                                         pins = "gpio36", "gpio37";
1733                                         function = "qup13";
1734                                 };
1735
1736                                 config {
1737                                         pins = "gpio36", "gpio37";
1738                                         drive-strength = <2>;
1739                                         bias-disable;
1740                                 };
1741                         };
1742
1743                         qup_i2c14_default: qup-i2c14-default {
1744                                 mux {
1745                                         pins = "gpio40", "gpio41";
1746                                         function = "qup14";
1747                                 };
1748
1749                                 config {
1750                                         pins = "gpio40", "gpio41";
1751                                         drive-strength = <2>;
1752                                         bias-disable;
1753                                 };
1754                         };
1755
1756                         qup_i2c15_default: qup-i2c15-default {
1757                                 mux {
1758                                         pins = "gpio44", "gpio45";
1759                                         function = "qup15";
1760                                 };
1761
1762                                 config {
1763                                         pins = "gpio44", "gpio45";
1764                                         drive-strength = <2>;
1765                                         bias-disable;
1766                                 };
1767                         };
1768
1769                         qup_i2c16_default: qup-i2c16-default {
1770                                 mux {
1771                                         pins = "gpio48", "gpio49";
1772                                         function = "qup16";
1773                                 };
1774
1775                                 config {
1776                                         pins = "gpio48", "gpio49";
1777                                         drive-strength = <2>;
1778                                         bias-disable;
1779                                 };
1780                         };
1781
1782                         qup_i2c17_default: qup-i2c17-default {
1783                                 mux {
1784                                         pins = "gpio52", "gpio53";
1785                                         function = "qup17";
1786                                 };
1787
1788                                 config {
1789                                         pins = "gpio52", "gpio53";
1790                                         drive-strength = <2>;
1791                                         bias-disable;
1792                                 };
1793                         };
1794
1795                         qup_i2c18_default: qup-i2c18-default {
1796                                 mux {
1797                                         pins = "gpio56", "gpio57";
1798                                         function = "qup18";
1799                                 };
1800
1801                                 config {
1802                                         pins = "gpio56", "gpio57";
1803                                         drive-strength = <2>;
1804                                         bias-disable;
1805                                 };
1806                         };
1807
1808                         qup_i2c19_default: qup-i2c19-default {
1809                                 mux {
1810                                         pins = "gpio0", "gpio1";
1811                                         function = "qup19";
1812                                 };
1813
1814                                 config {
1815                                         pins = "gpio0", "gpio1";
1816                                         drive-strength = <2>;
1817                                         bias-disable;
1818                                 };
1819                         };
1820
1821                         qup_spi0_default: qup-spi0-default {
1822                                 mux {
1823                                         pins = "gpio28", "gpio29",
1824                                                "gpio30", "gpio31";
1825                                         function = "qup0";
1826                                 };
1827
1828                                 config {
1829                                         pins = "gpio28", "gpio29",
1830                                                "gpio30", "gpio31";
1831                                         drive-strength = <6>;
1832                                         bias-disable;
1833                                 };
1834                         };
1835
1836                         qup_spi1_default: qup-spi1-default {
1837                                 mux {
1838                                         pins = "gpio4", "gpio5",
1839                                                "gpio6", "gpio7";
1840                                         function = "qup1";
1841                                 };
1842
1843                                 config {
1844                                         pins = "gpio4", "gpio5",
1845                                                "gpio6", "gpio7";
1846                                         drive-strength = <6>;
1847                                         bias-disable;
1848                                 };
1849                         };
1850
1851                         qup_spi2_default: qup-spi2-default {
1852                                 mux {
1853                                         pins = "gpio115", "gpio116",
1854                                                "gpio117", "gpio118";
1855                                         function = "qup2";
1856                                 };
1857
1858                                 config {
1859                                         pins = "gpio115", "gpio116",
1860                                                "gpio117", "gpio118";
1861                                         drive-strength = <6>;
1862                                         bias-disable;
1863                                 };
1864                         };
1865
1866                         qup_spi3_default: qup-spi3-default {
1867                                 mux {
1868                                         pins = "gpio119", "gpio120",
1869                                                "gpio121", "gpio122";
1870                                         function = "qup3";
1871                                 };
1872
1873                                 config {
1874                                         pins = "gpio119", "gpio120",
1875                                                "gpio121", "gpio122";
1876                                         drive-strength = <6>;
1877                                         bias-disable;
1878                                 };
1879                         };
1880
1881                         qup_spi4_default: qup-spi4-default {
1882                                 mux {
1883                                         pins = "gpio8", "gpio9",
1884                                                "gpio10", "gpio11";
1885                                         function = "qup4";
1886                                 };
1887
1888                                 config {
1889                                         pins = "gpio8", "gpio9",
1890                                                "gpio10", "gpio11";
1891                                         drive-strength = <6>;
1892                                         bias-disable;
1893                                 };
1894                         };
1895
1896                         qup_spi5_default: qup-spi5-default {
1897                                 mux {
1898                                         pins = "gpio12", "gpio13",
1899                                                "gpio14", "gpio15";
1900                                         function = "qup5";
1901                                 };
1902
1903                                 config {
1904                                         pins = "gpio12", "gpio13",
1905                                                "gpio14", "gpio15";
1906                                         drive-strength = <6>;
1907                                         bias-disable;
1908                                 };
1909                         };
1910
1911                         qup_spi6_default: qup-spi6-default {
1912                                 mux {
1913                                         pins = "gpio16", "gpio17",
1914                                                "gpio18", "gpio19";
1915                                         function = "qup6";
1916                                 };
1917
1918                                 config {
1919                                         pins = "gpio16", "gpio17",
1920                                                "gpio18", "gpio19";
1921                                         drive-strength = <6>;
1922                                         bias-disable;
1923                                 };
1924                         };
1925
1926                         qup_spi7_default: qup-spi7-default {
1927                                 mux {
1928                                         pins = "gpio20", "gpio21",
1929                                                "gpio22", "gpio23";
1930                                         function = "qup7";
1931                                 };
1932
1933                                 config {
1934                                         pins = "gpio20", "gpio21",
1935                                                "gpio22", "gpio23";
1936                                         drive-strength = <6>;
1937                                         bias-disable;
1938                                 };
1939                         };
1940
1941                         qup_spi8_default: qup-spi8-default {
1942                                 mux {
1943                                         pins = "gpio24", "gpio25",
1944                                                "gpio26", "gpio27";
1945                                         function = "qup8";
1946                                 };
1947
1948                                 config {
1949                                         pins = "gpio24", "gpio25",
1950                                                "gpio26", "gpio27";
1951                                         drive-strength = <6>;
1952                                         bias-disable;
1953                                 };
1954                         };
1955
1956                         qup_spi9_default: qup-spi9-default {
1957                                 mux {
1958                                         pins = "gpio125", "gpio126",
1959                                                "gpio127", "gpio128";
1960                                         function = "qup9";
1961                                 };
1962
1963                                 config {
1964                                         pins = "gpio125", "gpio126",
1965                                                "gpio127", "gpio128";
1966                                         drive-strength = <6>;
1967                                         bias-disable;
1968                                 };
1969                         };
1970
1971                         qup_spi10_default: qup-spi10-default {
1972                                 mux {
1973                                         pins = "gpio129", "gpio130",
1974                                                "gpio131", "gpio132";
1975                                         function = "qup10";
1976                                 };
1977
1978                                 config {
1979                                         pins = "gpio129", "gpio130",
1980                                                "gpio131", "gpio132";
1981                                         drive-strength = <6>;
1982                                         bias-disable;
1983                                 };
1984                         };
1985
1986                         qup_spi11_default: qup-spi11-default {
1987                                 mux {
1988                                         pins = "gpio60", "gpio61",
1989                                                "gpio62", "gpio63";
1990                                         function = "qup11";
1991                                 };
1992
1993                                 config {
1994                                         pins = "gpio60", "gpio61",
1995                                                "gpio62", "gpio63";
1996                                         drive-strength = <6>;
1997                                         bias-disable;
1998                                 };
1999                         };
2000
2001                         qup_spi12_default: qup-spi12-default {
2002                                 mux {
2003                                         pins = "gpio32", "gpio33",
2004                                                "gpio34", "gpio35";
2005                                         function = "qup12";
2006                                 };
2007
2008                                 config {
2009                                         pins = "gpio32", "gpio33",
2010                                                "gpio34", "gpio35";
2011                                         drive-strength = <6>;
2012                                         bias-disable;
2013                                 };
2014                         };
2015
2016                         qup_spi13_default: qup-spi13-default {
2017                                 mux {
2018                                         pins = "gpio36", "gpio37",
2019                                                "gpio38", "gpio39";
2020                                         function = "qup13";
2021                                 };
2022
2023                                 config {
2024                                         pins = "gpio36", "gpio37",
2025                                                "gpio38", "gpio39";
2026                                         drive-strength = <6>;
2027                                         bias-disable;
2028                                 };
2029                         };
2030
2031                         qup_spi14_default: qup-spi14-default {
2032                                 mux {
2033                                         pins = "gpio40", "gpio41",
2034                                                "gpio42", "gpio43";
2035                                         function = "qup14";
2036                                 };
2037
2038                                 config {
2039                                         pins = "gpio40", "gpio41",
2040                                                "gpio42", "gpio43";
2041                                         drive-strength = <6>;
2042                                         bias-disable;
2043                                 };
2044                         };
2045
2046                         qup_spi15_default: qup-spi15-default {
2047                                 mux {
2048                                         pins = "gpio44", "gpio45",
2049                                                "gpio46", "gpio47";
2050                                         function = "qup15";
2051                                 };
2052
2053                                 config {
2054                                         pins = "gpio44", "gpio45",
2055                                                "gpio46", "gpio47";
2056                                         drive-strength = <6>;
2057                                         bias-disable;
2058                                 };
2059                         };
2060
2061                         qup_spi16_default: qup-spi16-default {
2062                                 mux {
2063                                         pins = "gpio48", "gpio49",
2064                                                "gpio50", "gpio51";
2065                                         function = "qup16";
2066                                 };
2067
2068                                 config {
2069                                         pins = "gpio48", "gpio49",
2070                                                "gpio50", "gpio51";
2071                                         drive-strength = <6>;
2072                                         bias-disable;
2073                                 };
2074                         };
2075
2076                         qup_spi17_default: qup-spi17-default {
2077                                 mux {
2078                                         pins = "gpio52", "gpio53",
2079                                                "gpio54", "gpio55";
2080                                         function = "qup17";
2081                                 };
2082
2083                                 config {
2084                                         pins = "gpio52", "gpio53",
2085                                                "gpio54", "gpio55";
2086                                         drive-strength = <6>;
2087                                         bias-disable;
2088                                 };
2089                         };
2090
2091                         qup_spi18_default: qup-spi18-default {
2092                                 mux {
2093                                         pins = "gpio56", "gpio57",
2094                                                "gpio58", "gpio59";
2095                                         function = "qup18";
2096                                 };
2097
2098                                 config {
2099                                         pins = "gpio56", "gpio57",
2100                                                "gpio58", "gpio59";
2101                                         drive-strength = <6>;
2102                                         bias-disable;
2103                                 };
2104                         };
2105
2106                         qup_spi19_default: qup-spi19-default {
2107                                 mux {
2108                                         pins = "gpio0", "gpio1",
2109                                                "gpio2", "gpio3";
2110                                         function = "qup19";
2111                                 };
2112
2113                                 config {
2114                                         pins = "gpio0", "gpio1",
2115                                                "gpio2", "gpio3";
2116                                         drive-strength = <6>;
2117                                         bias-disable;
2118                                 };
2119                         };
2120
2121                         qup_uart2_default: qup-uart2-default {
2122                                 mux {
2123                                         pins = "gpio117", "gpio118";
2124                                         function = "qup2";
2125                                 };
2126                         };
2127
2128                         qup_uart6_default: qup-uart6-default {
2129                                 mux {
2130                                         pins = "gpio16", "gpio17",
2131                                                 "gpio18", "gpio19";
2132                                         function = "qup6";
2133                                 };
2134                         };
2135
2136                         qup_uart12_default: qup-uart12-default {
2137                                 mux {
2138                                         pins = "gpio34", "gpio35";
2139                                         function = "qup12";
2140                                 };
2141                         };
2142
2143                         qup_uart17_default: qup-uart17-default {
2144                                 mux {
2145                                         pins = "gpio52", "gpio53",
2146                                                 "gpio54", "gpio55";
2147                                         function = "qup17";
2148                                 };
2149                         };
2150
2151                         qup_uart18_default: qup-uart18-default {
2152                                 mux {
2153                                         pins = "gpio58", "gpio59";
2154                                         function = "qup18";
2155                                 };
2156                         };
2157                 };
2158
2159                 adsp: remoteproc@17300000 {
2160                         compatible = "qcom,sm8250-adsp-pas";
2161                         reg = <0 0x17300000 0 0x100>;
2162
2163                         interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
2164                                               <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2165                                               <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
2166                                               <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
2167                                               <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
2168                         interrupt-names = "wdog", "fatal", "ready",
2169                                           "handover", "stop-ack";
2170
2171                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2172                         clock-names = "xo";
2173
2174                         power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>,
2175                                         <&rpmhpd SM8250_LCX>,
2176                                         <&rpmhpd SM8250_LMX>;
2177                         power-domain-names = "load_state", "lcx", "lmx";
2178
2179                         memory-region = <&adsp_mem>;
2180
2181                         qcom,smem-states = <&smp2p_adsp_out 0>;
2182                         qcom,smem-state-names = "stop";
2183
2184                         status = "disabled";
2185
2186                         glink-edge {
2187                                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2188                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
2189                                                              IRQ_TYPE_EDGE_RISING>;
2190                                 mboxes = <&ipcc IPCC_CLIENT_LPASS
2191                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2192
2193                                 label = "lpass";
2194                                 qcom,remote-pid = <2>;
2195                         };
2196                 };
2197
2198                 intc: interrupt-controller@17a00000 {
2199                         compatible = "arm,gic-v3";
2200                         #interrupt-cells = <3>;
2201                         interrupt-controller;
2202                         reg = <0x0 0x17a00000 0x0 0x10000>,     /* GICD */
2203                               <0x0 0x17a60000 0x0 0x100000>;    /* GICR * 8 */
2204                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
2205                 };
2206
2207                 watchdog@17c10000 {
2208                         compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt";
2209                         reg = <0 0x17c10000 0 0x1000>;
2210                         clocks = <&sleep_clk>;
2211                 };
2212
2213                 timer@17c20000 {
2214                         #address-cells = <2>;
2215                         #size-cells = <2>;
2216                         ranges;
2217                         compatible = "arm,armv7-timer-mem";
2218                         reg = <0x0 0x17c20000 0x0 0x1000>;
2219                         clock-frequency = <19200000>;
2220
2221                         frame@17c21000 {
2222                                 frame-number = <0>;
2223                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
2224                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
2225                                 reg = <0x0 0x17c21000 0x0 0x1000>,
2226                                       <0x0 0x17c22000 0x0 0x1000>;
2227                         };
2228
2229                         frame@17c23000 {
2230                                 frame-number = <1>;
2231                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
2232                                 reg = <0x0 0x17c23000 0x0 0x1000>;
2233                                 status = "disabled";
2234                         };
2235
2236                         frame@17c25000 {
2237                                 frame-number = <2>;
2238                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
2239                                 reg = <0x0 0x17c25000 0x0 0x1000>;
2240                                 status = "disabled";
2241                         };
2242
2243                         frame@17c27000 {
2244                                 frame-number = <3>;
2245                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
2246                                 reg = <0x0 0x17c27000 0x0 0x1000>;
2247                                 status = "disabled";
2248                         };
2249
2250                         frame@17c29000 {
2251                                 frame-number = <4>;
2252                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
2253                                 reg = <0x0 0x17c29000 0x0 0x1000>;
2254                                 status = "disabled";
2255                         };
2256
2257                         frame@17c2b000 {
2258                                 frame-number = <5>;
2259                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
2260                                 reg = <0x0 0x17c2b000 0x0 0x1000>;
2261                                 status = "disabled";
2262                         };
2263
2264                         frame@17c2d000 {
2265                                 frame-number = <6>;
2266                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
2267                                 reg = <0x0 0x17c2d000 0x0 0x1000>;
2268                                 status = "disabled";
2269                         };
2270                 };
2271
2272                 apps_rsc: rsc@18200000 {
2273                         label = "apps_rsc";
2274                         compatible = "qcom,rpmh-rsc";
2275                         reg = <0x0 0x18200000 0x0 0x10000>,
2276                                 <0x0 0x18210000 0x0 0x10000>,
2277                                 <0x0 0x18220000 0x0 0x10000>;
2278                         reg-names = "drv-0", "drv-1", "drv-2";
2279                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
2280                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
2281                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
2282                         qcom,tcs-offset = <0xd00>;
2283                         qcom,drv-id = <2>;
2284                         qcom,tcs-config = <ACTIVE_TCS  2>, <SLEEP_TCS   3>,
2285                                           <WAKE_TCS    3>, <CONTROL_TCS 1>;
2286
2287                         rpmhcc: clock-controller {
2288                                 compatible = "qcom,sm8250-rpmh-clk";
2289                                 #clock-cells = <1>;
2290                                 clock-names = "xo";
2291                                 clocks = <&xo_board>;
2292                         };
2293
2294                         rpmhpd: power-controller {
2295                                 compatible = "qcom,sm8250-rpmhpd";
2296                                 #power-domain-cells = <1>;
2297                                 operating-points-v2 = <&rpmhpd_opp_table>;
2298
2299                                 rpmhpd_opp_table: opp-table {
2300                                         compatible = "operating-points-v2";
2301
2302                                         rpmhpd_opp_ret: opp1 {
2303                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
2304                                         };
2305
2306                                         rpmhpd_opp_min_svs: opp2 {
2307                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2308                                         };
2309
2310                                         rpmhpd_opp_low_svs: opp3 {
2311                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2312                                         };
2313
2314                                         rpmhpd_opp_svs: opp4 {
2315                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2316                                         };
2317
2318                                         rpmhpd_opp_svs_l1: opp5 {
2319                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2320                                         };
2321
2322                                         rpmhpd_opp_nom: opp6 {
2323                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2324                                         };
2325
2326                                         rpmhpd_opp_nom_l1: opp7 {
2327                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2328                                         };
2329
2330                                         rpmhpd_opp_nom_l2: opp8 {
2331                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
2332                                         };
2333
2334                                         rpmhpd_opp_turbo: opp9 {
2335                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2336                                         };
2337
2338                                         rpmhpd_opp_turbo_l1: opp10 {
2339                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2340                                         };
2341                                 };
2342                         };
2343
2344                         apps_bcm_voter: bcm_voter {
2345                                 compatible = "qcom,bcm-voter";
2346                         };
2347                 };
2348
2349                 epss_l3: interconnect@18591000 {
2350                         compatible = "qcom,sm8250-epss-l3";
2351                         reg = <0 0x18590000 0 0x1000>;
2352
2353                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
2354                         clock-names = "xo", "alternate";
2355
2356                         #interconnect-cells = <1>;
2357                 };
2358
2359                 cpufreq_hw: cpufreq@18591000 {
2360                         compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss";
2361                         reg = <0 0x18591000 0 0x1000>,
2362                               <0 0x18592000 0 0x1000>,
2363                               <0 0x18593000 0 0x1000>;
2364                         reg-names = "freq-domain0", "freq-domain1",
2365                                     "freq-domain2";
2366
2367                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
2368                         clock-names = "xo", "alternate";
2369
2370                         #freq-domain-cells = <1>;
2371                 };
2372         };
2373
2374         timer {
2375                 compatible = "arm,armv8-timer";
2376                 interrupts = <GIC_PPI 13
2377                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2378                              <GIC_PPI 14
2379                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2380                              <GIC_PPI 11
2381                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2382                              <GIC_PPI 12
2383                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
2384         };
2385
2386         thermal-zones {
2387                 cpu0-thermal {
2388                         polling-delay-passive = <250>;
2389                         polling-delay = <1000>;
2390
2391                         thermal-sensors = <&tsens0 1>;
2392
2393                         trips {
2394                                 cpu0_alert0: trip-point0 {
2395                                         temperature = <90000>;
2396                                         hysteresis = <2000>;
2397                                         type = "passive";
2398                                 };
2399
2400                                 cpu0_alert1: trip-point1 {
2401                                         temperature = <95000>;
2402                                         hysteresis = <2000>;
2403                                         type = "passive";
2404                                 };
2405
2406                                 cpu0_crit: cpu_crit {
2407                                         temperature = <110000>;
2408                                         hysteresis = <1000>;
2409                                         type = "critical";
2410                                 };
2411                         };
2412
2413                         cooling-maps {
2414                                 map0 {
2415                                         trip = <&cpu0_alert0>;
2416                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2417                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2418                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2419                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2420                                 };
2421                                 map1 {
2422                                         trip = <&cpu0_alert1>;
2423                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2424                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2425                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2426                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2427                                 };
2428                         };
2429                 };
2430
2431                 cpu1-thermal {
2432                         polling-delay-passive = <250>;
2433                         polling-delay = <1000>;
2434
2435                         thermal-sensors = <&tsens0 2>;
2436
2437                         trips {
2438                                 cpu1_alert0: trip-point0 {
2439                                         temperature = <90000>;
2440                                         hysteresis = <2000>;
2441                                         type = "passive";
2442                                 };
2443
2444                                 cpu1_alert1: trip-point1 {
2445                                         temperature = <95000>;
2446                                         hysteresis = <2000>;
2447                                         type = "passive";
2448                                 };
2449
2450                                 cpu1_crit: cpu_crit {
2451                                         temperature = <110000>;
2452                                         hysteresis = <1000>;
2453                                         type = "critical";
2454                                 };
2455                         };
2456
2457                         cooling-maps {
2458                                 map0 {
2459                                         trip = <&cpu1_alert0>;
2460                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2461                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2462                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2463                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2464                                 };
2465                                 map1 {
2466                                         trip = <&cpu1_alert1>;
2467                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2468                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2469                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2470                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2471                                 };
2472                         };
2473                 };
2474
2475                 cpu2-thermal {
2476                         polling-delay-passive = <250>;
2477                         polling-delay = <1000>;
2478
2479                         thermal-sensors = <&tsens0 3>;
2480
2481                         trips {
2482                                 cpu2_alert0: trip-point0 {
2483                                         temperature = <90000>;
2484                                         hysteresis = <2000>;
2485                                         type = "passive";
2486                                 };
2487
2488                                 cpu2_alert1: trip-point1 {
2489                                         temperature = <95000>;
2490                                         hysteresis = <2000>;
2491                                         type = "passive";
2492                                 };
2493
2494                                 cpu2_crit: cpu_crit {
2495                                         temperature = <110000>;
2496                                         hysteresis = <1000>;
2497                                         type = "critical";
2498                                 };
2499                         };
2500
2501                         cooling-maps {
2502                                 map0 {
2503                                         trip = <&cpu2_alert0>;
2504                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2505                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2506                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2507                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2508                                 };
2509                                 map1 {
2510                                         trip = <&cpu2_alert1>;
2511                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2512                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2513                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2514                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2515                                 };
2516                         };
2517                 };
2518
2519                 cpu3-thermal {
2520                         polling-delay-passive = <250>;
2521                         polling-delay = <1000>;
2522
2523                         thermal-sensors = <&tsens0 4>;
2524
2525                         trips {
2526                                 cpu3_alert0: trip-point0 {
2527                                         temperature = <90000>;
2528                                         hysteresis = <2000>;
2529                                         type = "passive";
2530                                 };
2531
2532                                 cpu3_alert1: trip-point1 {
2533                                         temperature = <95000>;
2534                                         hysteresis = <2000>;
2535                                         type = "passive";
2536                                 };
2537
2538                                 cpu3_crit: cpu_crit {
2539                                         temperature = <110000>;
2540                                         hysteresis = <1000>;
2541                                         type = "critical";
2542                                 };
2543                         };
2544
2545                         cooling-maps {
2546                                 map0 {
2547                                         trip = <&cpu3_alert0>;
2548                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2549                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2550                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2551                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2552                                 };
2553                                 map1 {
2554                                         trip = <&cpu3_alert1>;
2555                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2556                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2557                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2558                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2559                                 };
2560                         };
2561                 };
2562
2563                 cpu4-top-thermal {
2564                         polling-delay-passive = <250>;
2565                         polling-delay = <1000>;
2566
2567                         thermal-sensors = <&tsens0 7>;
2568
2569                         trips {
2570                                 cpu4_top_alert0: trip-point0 {
2571                                         temperature = <90000>;
2572                                         hysteresis = <2000>;
2573                                         type = "passive";
2574                                 };
2575
2576                                 cpu4_top_alert1: trip-point1 {
2577                                         temperature = <95000>;
2578                                         hysteresis = <2000>;
2579                                         type = "passive";
2580                                 };
2581
2582                                 cpu4_top_crit: cpu_crit {
2583                                         temperature = <110000>;
2584                                         hysteresis = <1000>;
2585                                         type = "critical";
2586                                 };
2587                         };
2588
2589                         cooling-maps {
2590                                 map0 {
2591                                         trip = <&cpu4_top_alert0>;
2592                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2593                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2594                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2595                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2596                                 };
2597                                 map1 {
2598                                         trip = <&cpu4_top_alert1>;
2599                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2600                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2601                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2602                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2603                                 };
2604                         };
2605                 };
2606
2607                 cpu5-top-thermal {
2608                         polling-delay-passive = <250>;
2609                         polling-delay = <1000>;
2610
2611                         thermal-sensors = <&tsens0 8>;
2612
2613                         trips {
2614                                 cpu5_top_alert0: trip-point0 {
2615                                         temperature = <90000>;
2616                                         hysteresis = <2000>;
2617                                         type = "passive";
2618                                 };
2619
2620                                 cpu5_top_alert1: trip-point1 {
2621                                         temperature = <95000>;
2622                                         hysteresis = <2000>;
2623                                         type = "passive";
2624                                 };
2625
2626                                 cpu5_top_crit: cpu_crit {
2627                                         temperature = <110000>;
2628                                         hysteresis = <1000>;
2629                                         type = "critical";
2630                                 };
2631                         };
2632
2633                         cooling-maps {
2634                                 map0 {
2635                                         trip = <&cpu5_top_alert0>;
2636                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2637                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2638                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2639                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2640                                 };
2641                                 map1 {
2642                                         trip = <&cpu5_top_alert1>;
2643                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2644                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2645                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2646                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2647                                 };
2648                         };
2649                 };
2650
2651                 cpu6-top-thermal {
2652                         polling-delay-passive = <250>;
2653                         polling-delay = <1000>;
2654
2655                         thermal-sensors = <&tsens0 9>;
2656
2657                         trips {
2658                                 cpu6_top_alert0: trip-point0 {
2659                                         temperature = <90000>;
2660                                         hysteresis = <2000>;
2661                                         type = "passive";
2662                                 };
2663
2664                                 cpu6_top_alert1: trip-point1 {
2665                                         temperature = <95000>;
2666                                         hysteresis = <2000>;
2667                                         type = "passive";
2668                                 };
2669
2670                                 cpu6_top_crit: cpu_crit {
2671                                         temperature = <110000>;
2672                                         hysteresis = <1000>;
2673                                         type = "critical";
2674                                 };
2675                         };
2676
2677                         cooling-maps {
2678                                 map0 {
2679                                         trip = <&cpu6_top_alert0>;
2680                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2681                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2682                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2683                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2684                                 };
2685                                 map1 {
2686                                         trip = <&cpu6_top_alert1>;
2687                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2688                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2689                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2690                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2691                                 };
2692                         };
2693                 };
2694
2695                 cpu7-top-thermal {
2696                         polling-delay-passive = <250>;
2697                         polling-delay = <1000>;
2698
2699                         thermal-sensors = <&tsens0 10>;
2700
2701                         trips {
2702                                 cpu7_top_alert0: trip-point0 {
2703                                         temperature = <90000>;
2704                                         hysteresis = <2000>;
2705                                         type = "passive";
2706                                 };
2707
2708                                 cpu7_top_alert1: trip-point1 {
2709                                         temperature = <95000>;
2710                                         hysteresis = <2000>;
2711                                         type = "passive";
2712                                 };
2713
2714                                 cpu7_top_crit: cpu_crit {
2715                                         temperature = <110000>;
2716                                         hysteresis = <1000>;
2717                                         type = "critical";
2718                                 };
2719                         };
2720
2721                         cooling-maps {
2722                                 map0 {
2723                                         trip = <&cpu7_top_alert0>;
2724                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2725                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2726                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2727                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2728                                 };
2729                                 map1 {
2730                                         trip = <&cpu7_top_alert1>;
2731                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2732                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2733                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2734                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2735                                 };
2736                         };
2737                 };
2738
2739                 cpu4-bottom-thermal {
2740                         polling-delay-passive = <250>;
2741                         polling-delay = <1000>;
2742
2743                         thermal-sensors = <&tsens0 11>;
2744
2745                         trips {
2746                                 cpu4_bottom_alert0: trip-point0 {
2747                                         temperature = <90000>;
2748                                         hysteresis = <2000>;
2749                                         type = "passive";
2750                                 };
2751
2752                                 cpu4_bottom_alert1: trip-point1 {
2753                                         temperature = <95000>;
2754                                         hysteresis = <2000>;
2755                                         type = "passive";
2756                                 };
2757
2758                                 cpu4_bottom_crit: cpu_crit {
2759                                         temperature = <110000>;
2760                                         hysteresis = <1000>;
2761                                         type = "critical";
2762                                 };
2763                         };
2764
2765                         cooling-maps {
2766                                 map0 {
2767                                         trip = <&cpu4_bottom_alert0>;
2768                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2769                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2770                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2771                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2772                                 };
2773                                 map1 {
2774                                         trip = <&cpu4_bottom_alert1>;
2775                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2776                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2777                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2778                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2779                                 };
2780                         };
2781                 };
2782
2783                 cpu5-bottom-thermal {
2784                         polling-delay-passive = <250>;
2785                         polling-delay = <1000>;
2786
2787                         thermal-sensors = <&tsens0 12>;
2788
2789                         trips {
2790                                 cpu5_bottom_alert0: trip-point0 {
2791                                         temperature = <90000>;
2792                                         hysteresis = <2000>;
2793                                         type = "passive";
2794                                 };
2795
2796                                 cpu5_bottom_alert1: trip-point1 {
2797                                         temperature = <95000>;
2798                                         hysteresis = <2000>;
2799                                         type = "passive";
2800                                 };
2801
2802                                 cpu5_bottom_crit: cpu_crit {
2803                                         temperature = <110000>;
2804                                         hysteresis = <1000>;
2805                                         type = "critical";
2806                                 };
2807                         };
2808
2809                         cooling-maps {
2810                                 map0 {
2811                                         trip = <&cpu5_bottom_alert0>;
2812                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2813                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2814                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2815                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2816                                 };
2817                                 map1 {
2818                                         trip = <&cpu5_bottom_alert1>;
2819                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2820                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2821                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2822                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2823                                 };
2824                         };
2825                 };
2826
2827                 cpu6-bottom-thermal {
2828                         polling-delay-passive = <250>;
2829                         polling-delay = <1000>;
2830
2831                         thermal-sensors = <&tsens0 13>;
2832
2833                         trips {
2834                                 cpu6_bottom_alert0: trip-point0 {
2835                                         temperature = <90000>;
2836                                         hysteresis = <2000>;
2837                                         type = "passive";
2838                                 };
2839
2840                                 cpu6_bottom_alert1: trip-point1 {
2841                                         temperature = <95000>;
2842                                         hysteresis = <2000>;
2843                                         type = "passive";
2844                                 };
2845
2846                                 cpu6_bottom_crit: cpu_crit {
2847                                         temperature = <110000>;
2848                                         hysteresis = <1000>;
2849                                         type = "critical";
2850                                 };
2851                         };
2852
2853                         cooling-maps {
2854                                 map0 {
2855                                         trip = <&cpu6_bottom_alert0>;
2856                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2857                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2858                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2859                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2860                                 };
2861                                 map1 {
2862                                         trip = <&cpu6_bottom_alert1>;
2863                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2864                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2865                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2866                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2867                                 };
2868                         };
2869                 };
2870
2871                 cpu7-bottom-thermal {
2872                         polling-delay-passive = <250>;
2873                         polling-delay = <1000>;
2874
2875                         thermal-sensors = <&tsens0 14>;
2876
2877                         trips {
2878                                 cpu7_bottom_alert0: trip-point0 {
2879                                         temperature = <90000>;
2880                                         hysteresis = <2000>;
2881                                         type = "passive";
2882                                 };
2883
2884                                 cpu7_bottom_alert1: trip-point1 {
2885                                         temperature = <95000>;
2886                                         hysteresis = <2000>;
2887                                         type = "passive";
2888                                 };
2889
2890                                 cpu7_bottom_crit: cpu_crit {
2891                                         temperature = <110000>;
2892                                         hysteresis = <1000>;
2893                                         type = "critical";
2894                                 };
2895                         };
2896
2897                         cooling-maps {
2898                                 map0 {
2899                                         trip = <&cpu7_bottom_alert0>;
2900                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2901                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2902                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2903                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2904                                 };
2905                                 map1 {
2906                                         trip = <&cpu7_bottom_alert1>;
2907                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2908                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2909                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2910                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2911                                 };
2912                         };
2913                 };
2914
2915                 aoss0-thermal {
2916                         polling-delay-passive = <250>;
2917                         polling-delay = <1000>;
2918
2919                         thermal-sensors = <&tsens0 0>;
2920
2921                         trips {
2922                                 aoss0_alert0: trip-point0 {
2923                                         temperature = <90000>;
2924                                         hysteresis = <2000>;
2925                                         type = "hot";
2926                                 };
2927                         };
2928                 };
2929
2930                 cluster0-thermal {
2931                         polling-delay-passive = <250>;
2932                         polling-delay = <1000>;
2933
2934                         thermal-sensors = <&tsens0 5>;
2935
2936                         trips {
2937                                 cluster0_alert0: trip-point0 {
2938                                         temperature = <90000>;
2939                                         hysteresis = <2000>;
2940                                         type = "hot";
2941                                 };
2942                                 cluster0_crit: cluster0_crit {
2943                                         temperature = <110000>;
2944                                         hysteresis = <2000>;
2945                                         type = "critical";
2946                                 };
2947                         };
2948                 };
2949
2950                 cluster1-thermal {
2951                         polling-delay-passive = <250>;
2952                         polling-delay = <1000>;
2953
2954                         thermal-sensors = <&tsens0 6>;
2955
2956                         trips {
2957                                 cluster1_alert0: trip-point0 {
2958                                         temperature = <90000>;
2959                                         hysteresis = <2000>;
2960                                         type = "hot";
2961                                 };
2962                                 cluster1_crit: cluster1_crit {
2963                                         temperature = <110000>;
2964                                         hysteresis = <2000>;
2965                                         type = "critical";
2966                                 };
2967                         };
2968                 };
2969
2970                 gpu-thermal-top {
2971                         polling-delay-passive = <250>;
2972                         polling-delay = <1000>;
2973
2974                         thermal-sensors = <&tsens0 15>;
2975
2976                         trips {
2977                                 gpu1_alert0: trip-point0 {
2978                                         temperature = <90000>;
2979                                         hysteresis = <2000>;
2980                                         type = "hot";
2981                                 };
2982                         };
2983                 };
2984
2985                 aoss1-thermal {
2986                         polling-delay-passive = <250>;
2987                         polling-delay = <1000>;
2988
2989                         thermal-sensors = <&tsens1 0>;
2990
2991                         trips {
2992                                 aoss1_alert0: trip-point0 {
2993                                         temperature = <90000>;
2994                                         hysteresis = <2000>;
2995                                         type = "hot";
2996                                 };
2997                         };
2998                 };
2999
3000                 wlan-thermal {
3001                         polling-delay-passive = <250>;
3002                         polling-delay = <1000>;
3003
3004                         thermal-sensors = <&tsens1 1>;
3005
3006                         trips {
3007                                 wlan_alert0: trip-point0 {
3008                                         temperature = <90000>;
3009                                         hysteresis = <2000>;
3010                                         type = "hot";
3011                                 };
3012                         };
3013                 };
3014
3015                 video-thermal {
3016                         polling-delay-passive = <250>;
3017                         polling-delay = <1000>;
3018
3019                         thermal-sensors = <&tsens1 2>;
3020
3021                         trips {
3022                                 video_alert0: trip-point0 {
3023                                         temperature = <90000>;
3024                                         hysteresis = <2000>;
3025                                         type = "hot";
3026                                 };
3027                         };
3028                 };
3029
3030                 mem-thermal {
3031                         polling-delay-passive = <250>;
3032                         polling-delay = <1000>;
3033
3034                         thermal-sensors = <&tsens1 3>;
3035
3036                         trips {
3037                                 mem_alert0: trip-point0 {
3038                                         temperature = <90000>;
3039                                         hysteresis = <2000>;
3040                                         type = "hot";
3041                                 };
3042                         };
3043                 };
3044
3045                 q6-hvx-thermal {
3046                         polling-delay-passive = <250>;
3047                         polling-delay = <1000>;
3048
3049                         thermal-sensors = <&tsens1 4>;
3050
3051                         trips {
3052                                 q6_hvx_alert0: trip-point0 {
3053                                         temperature = <90000>;
3054                                         hysteresis = <2000>;
3055                                         type = "hot";
3056                                 };
3057                         };
3058                 };
3059
3060                 camera-thermal {
3061                         polling-delay-passive = <250>;
3062                         polling-delay = <1000>;
3063
3064                         thermal-sensors = <&tsens1 5>;
3065
3066                         trips {
3067                                 camera_alert0: trip-point0 {
3068                                         temperature = <90000>;
3069                                         hysteresis = <2000>;
3070                                         type = "hot";
3071                                 };
3072                         };
3073                 };
3074
3075                 compute-thermal {
3076                         polling-delay-passive = <250>;
3077                         polling-delay = <1000>;
3078
3079                         thermal-sensors = <&tsens1 6>;
3080
3081                         trips {
3082                                 compute_alert0: trip-point0 {
3083                                         temperature = <90000>;
3084                                         hysteresis = <2000>;
3085                                         type = "hot";
3086                                 };
3087                         };
3088                 };
3089
3090                 npu-thermal {
3091                         polling-delay-passive = <250>;
3092                         polling-delay = <1000>;
3093
3094                         thermal-sensors = <&tsens1 7>;
3095
3096                         trips {
3097                                 npu_alert0: trip-point0 {
3098                                         temperature = <90000>;
3099                                         hysteresis = <2000>;
3100                                         type = "hot";
3101                                 };
3102                         };
3103                 };
3104
3105                 gpu-thermal-bottom {
3106                         polling-delay-passive = <250>;
3107                         polling-delay = <1000>;
3108
3109                         thermal-sensors = <&tsens1 8>;
3110
3111                         trips {
3112                                 gpu2_alert0: trip-point0 {
3113                                         temperature = <90000>;
3114                                         hysteresis = <2000>;
3115                                         type = "hot";
3116                                 };
3117                         };
3118                 };
3119         };
3120 };