arch/arm64/boot/dts/qcom/sm8150.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
   4  * Copyright (c) 2019, Linaro Limited
   5  */
   6
   7 #include <dt-bindings/dma/qcom-gpi.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/power/qcom-rpmpd.h>
  10 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  11 #include <dt-bindings/clock/qcom,rpmh.h>
  12 #include <dt-bindings/clock/qcom,gcc-sm8150.h>
  13 #include <dt-bindings/clock/qcom,gpucc-sm8150.h>
  14 #include <dt-bindings/interconnect/qcom,osm-l3.h>
  15 #include <dt-bindings/interconnect/qcom,sm8150.h>
  16 #include <dt-bindings/thermal/thermal.h>
  17
  18 / {
  19         interrupt-parent = <&intc>;
  20
  21         #address-cells = <2>;
  22         #size-cells = <2>;
  23
  24         chosen { };
  25
  26         clocks {
  27                 xo_board: xo-board {
  28                         compatible = "fixed-clock";
  29                         #clock-cells = <0>;
  30                         clock-frequency = <38400000>;
  31                         clock-output-names = "xo_board";
  32                 };
  33
  34                 sleep_clk: sleep-clk {
  35                         compatible = "fixed-clock";
  36                         #clock-cells = <0>;
  37                         clock-frequency = <32764>;
  38                         clock-output-names = "sleep_clk";
  39                 };
  40         };
  41
  42         cpus {
  43                 #address-cells = <2>;
  44                 #size-cells = <0>;
  45
  46                 CPU0: cpu@0 {
  47                         device_type = "cpu";
  48                         compatible = "qcom,kryo485";
  49                         reg = <0x0 0x0>;
  50                         enable-method = "psci";
  51                         capacity-dmips-mhz = <488>;
  52                         dynamic-power-coefficient = <232>;
  53                         next-level-cache = <&L2_0>;
  54                         qcom,freq-domain = <&cpufreq_hw 0>;
  55                         operating-points-v2 = <&cpu0_opp_table>;
  56                         interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
  57                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
  58                         power-domains = <&CPU_PD0>;
  59                         power-domain-names = "psci";
  60                         #cooling-cells = <2>;
  61                         L2_0: l2-cache {
  62                                 compatible = "cache";
  63                                 next-level-cache = <&L3_0>;
  64                                 L3_0: l3-cache {
  65                                       compatible = "cache";
  66                                 };
  67                         };
  68                 };
  69
  70                 CPU1: cpu@100 {
  71                         device_type = "cpu";
  72                         compatible = "qcom,kryo485";
  73                         reg = <0x0 0x100>;
  74                         enable-method = "psci";
  75                         capacity-dmips-mhz = <488>;
  76                         dynamic-power-coefficient = <232>;
  77                         next-level-cache = <&L2_100>;
  78                         qcom,freq-domain = <&cpufreq_hw 0>;
  79                         operating-points-v2 = <&cpu0_opp_table>;
  80                         interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
  81                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
  82                         power-domains = <&CPU_PD1>;
  83                         power-domain-names = "psci";
  84                         #cooling-cells = <2>;
  85                         L2_100: l2-cache {
  86                                 compatible = "cache";
  87                                 next-level-cache = <&L3_0>;
  88                         };
  89
  90                 };
  91
  92                 CPU2: cpu@200 {
  93                         device_type = "cpu";
  94                         compatible = "qcom,kryo485";
  95                         reg = <0x0 0x200>;
  96                         enable-method = "psci";
  97                         capacity-dmips-mhz = <488>;
  98                         dynamic-power-coefficient = <232>;
  99                         next-level-cache = <&L2_200>;
 100                         qcom,freq-domain = <&cpufreq_hw 0>;
 101                         operating-points-v2 = <&cpu0_opp_table>;
 102                         interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
 103                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 104                         power-domains = <&CPU_PD2>;
 105                         power-domain-names = "psci";
 106                         #cooling-cells = <2>;
 107                         L2_200: l2-cache {
 108                                 compatible = "cache";
 109                                 next-level-cache = <&L3_0>;
 110                         };
 111                 };
 112
 113                 CPU3: cpu@300 {
 114                         device_type = "cpu";
 115                         compatible = "qcom,kryo485";
 116                         reg = <0x0 0x300>;
 117                         enable-method = "psci";
 118                         capacity-dmips-mhz = <488>;
 119                         dynamic-power-coefficient = <232>;
 120                         next-level-cache = <&L2_300>;
 121                         qcom,freq-domain = <&cpufreq_hw 0>;
 122                         operating-points-v2 = <&cpu0_opp_table>;
 123                         interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
 124                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 125                         power-domains = <&CPU_PD3>;
 126                         power-domain-names = "psci";
 127                         #cooling-cells = <2>;
 128                         L2_300: l2-cache {
 129                                 compatible = "cache";
 130                                 next-level-cache = <&L3_0>;
 131                         };
 132                 };
 133
 134                 CPU4: cpu@400 {
 135                         device_type = "cpu";
 136                         compatible = "qcom,kryo485";
 137                         reg = <0x0 0x400>;
 138                         enable-method = "psci";
 139                         capacity-dmips-mhz = <1024>;
 140                         dynamic-power-coefficient = <369>;
 141                         next-level-cache = <&L2_400>;
 142                         qcom,freq-domain = <&cpufreq_hw 1>;
 143                         operating-points-v2 = <&cpu4_opp_table>;
 144                         interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
 145                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 146                         power-domains = <&CPU_PD4>;
 147                         power-domain-names = "psci";
 148                         #cooling-cells = <2>;
 149                         L2_400: l2-cache {
 150                                 compatible = "cache";
 151                                 next-level-cache = <&L3_0>;
 152                         };
 153                 };
 154
 155                 CPU5: cpu@500 {
 156                         device_type = "cpu";
 157                         compatible = "qcom,kryo485";
 158                         reg = <0x0 0x500>;
 159                         enable-method = "psci";
 160                         capacity-dmips-mhz = <1024>;
 161                         dynamic-power-coefficient = <369>;
 162                         next-level-cache = <&L2_500>;
 163                         qcom,freq-domain = <&cpufreq_hw 1>;
 164                         operating-points-v2 = <&cpu4_opp_table>;
 165                         interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
 166                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 167                         power-domains = <&CPU_PD5>;
 168                         power-domain-names = "psci";
 169                         #cooling-cells = <2>;
 170                         L2_500: l2-cache {
 171                                 compatible = "cache";
 172                                 next-level-cache = <&L3_0>;
 173                         };
 174                 };
 175
 176                 CPU6: cpu@600 {
 177                         device_type = "cpu";
 178                         compatible = "qcom,kryo485";
 179                         reg = <0x0 0x600>;
 180                         enable-method = "psci";
 181                         capacity-dmips-mhz = <1024>;
 182                         dynamic-power-coefficient = <369>;
 183                         next-level-cache = <&L2_600>;
 184                         qcom,freq-domain = <&cpufreq_hw 1>;
 185                         operating-points-v2 = <&cpu4_opp_table>;
 186                         interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
 187                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 188                         power-domains = <&CPU_PD6>;
 189                         power-domain-names = "psci";
 190                         #cooling-cells = <2>;
 191                         L2_600: l2-cache {
 192                                 compatible = "cache";
 193                                 next-level-cache = <&L3_0>;
 194                         };
 195                 };
 196
 197                 CPU7: cpu@700 {
 198                         device_type = "cpu";
 199                         compatible = "qcom,kryo485";
 200                         reg = <0x0 0x700>;
 201                         enable-method = "psci";
 202                         capacity-dmips-mhz = <1024>;
 203                         dynamic-power-coefficient = <421>;
 204                         next-level-cache = <&L2_700>;
 205                         qcom,freq-domain = <&cpufreq_hw 2>;
 206                         operating-points-v2 = <&cpu7_opp_table>;
 207                         interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
 208                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 209                         power-domains = <&CPU_PD7>;
 210                         power-domain-names = "psci";
 211                         #cooling-cells = <2>;
 212                         L2_700: l2-cache {
 213                                 compatible = "cache";
 214                                 next-level-cache = <&L3_0>;
 215                         };
 216                 };
 217
 218                 cpu-map {
 219                         cluster0 {
 220                                 core0 {
 221                                         cpu = <&CPU0>;
 222                                 };
 223
 224                                 core1 {
 225                                         cpu = <&CPU1>;
 226                                 };
 227
 228                                 core2 {
 229                                         cpu = <&CPU2>;
 230                                 };
 231
 232                                 core3 {
 233                                         cpu = <&CPU3>;
 234                                 };
 235
 236                                 core4 {
 237                                         cpu = <&CPU4>;
 238                                 };
 239
 240                                 core5 {
 241                                         cpu = <&CPU5>;
 242                                 };
 243
 244                                 core6 {
 245                                         cpu = <&CPU6>;
 246                                 };
 247
 248                                 core7 {
 249                                         cpu = <&CPU7>;
 250                                 };
 251                         };
 252                 };
 253
 254                 idle-states {
 255                         entry-method = "psci";
 256
 257                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 258                                 compatible = "arm,idle-state";
 259                                 idle-state-name = "little-rail-power-collapse";
 260                                 arm,psci-suspend-param = <0x40000004>;
 261                                 entry-latency-us = <355>;
 262                                 exit-latency-us = <909>;
 263                                 min-residency-us = <3934>;
 264                                 local-timer-stop;
 265                         };
 266
 267                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 268                                 compatible = "arm,idle-state";
 269                                 idle-state-name = "big-rail-power-collapse";
 270                                 arm,psci-suspend-param = <0x40000004>;
 271                                 entry-latency-us = <241>;
 272                                 exit-latency-us = <1461>;
 273                                 min-residency-us = <4488>;
 274                                 local-timer-stop;
 275                         };
 276                 };
 277
 278                 domain-idle-states {
 279                         CLUSTER_SLEEP_0: cluster-sleep-0 {
 280                                 compatible = "domain-idle-state";
 281                                 idle-state-name = "cluster-power-collapse";
 282                                 arm,psci-suspend-param = <0x4100c244>;
 283                                 entry-latency-us = <3263>;
 284                                 exit-latency-us = <6562>;
 285                                 min-residency-us = <9987>;
 286                                 local-timer-stop;
 287                         };
 288                 };
 289         };
 290
 291         cpu0_opp_table: cpu0_opp_table {
 292                 compatible = "operating-points-v2";
 293                 opp-shared;
 294
 295                 cpu0_opp1: opp-300000000 {
 296                         opp-hz = /bits/ 64 <300000000>;
 297                         opp-peak-kBps = <800000 9600000>;
 298                 };
 299
 300                 cpu0_opp2: opp-403200000 {
 301                         opp-hz = /bits/ 64 <403200000>;
 302                         opp-peak-kBps = <800000 9600000>;
 303                 };
 304
 305                 cpu0_opp3: opp-499200000 {
 306                         opp-hz = /bits/ 64 <499200000>;
 307                         opp-peak-kBps = <800000 12902400>;
 308                 };
 309
 310                 cpu0_opp4: opp-576000000 {
 311                         opp-hz = /bits/ 64 <576000000>;
 312                         opp-peak-kBps = <800000 12902400>;
 313                 };
 314
 315                 cpu0_opp5: opp-672000000 {
 316                         opp-hz = /bits/ 64 <672000000>;
 317                         opp-peak-kBps = <800000 15974400>;
 318                 };
 319
 320                 cpu0_opp6: opp-768000000 {
 321                         opp-hz = /bits/ 64 <768000000>;
 322                         opp-peak-kBps = <1804000 19660800>;
 323                 };
 324
 325                 cpu0_opp7: opp-844800000 {
 326                         opp-hz = /bits/ 64 <844800000>;
 327                         opp-peak-kBps = <1804000 19660800>;
 328                 };
 329
 330                 cpu0_opp8: opp-940800000 {
 331                         opp-hz = /bits/ 64 <940800000>;
 332                         opp-peak-kBps = <1804000 22732800>;
 333                 };
 334
 335                 cpu0_opp9: opp-1036800000 {
 336                         opp-hz = /bits/ 64 <1036800000>;
 337                         opp-peak-kBps = <1804000 22732800>;
 338                 };
 339
 340                 cpu0_opp10: opp-1113600000 {
 341                         opp-hz = /bits/ 64 <1113600000>;
 342                         opp-peak-kBps = <2188000 25804800>;
 343                 };
 344
 345                 cpu0_opp11: opp-1209600000 {
 346                         opp-hz = /bits/ 64 <1209600000>;
 347                         opp-peak-kBps = <2188000 31948800>;
 348                 };
 349
 350                 cpu0_opp12: opp-1305600000 {
 351                         opp-hz = /bits/ 64 <1305600000>;
 352                         opp-peak-kBps = <3072000 31948800>;
 353                 };
 354
 355                 cpu0_opp13: opp-1382400000 {
 356                         opp-hz = /bits/ 64 <1382400000>;
 357                         opp-peak-kBps = <3072000 31948800>;
 358                 };
 359
 360                 cpu0_opp14: opp-1478400000 {
 361                         opp-hz = /bits/ 64 <1478400000>;
 362                         opp-peak-kBps = <3072000 31948800>;
 363                 };
 364
 365                 cpu0_opp15: opp-1555200000 {
 366                         opp-hz = /bits/ 64 <1555200000>;
 367                         opp-peak-kBps = <3072000 40550400>;
 368                 };
 369
 370                 cpu0_opp16: opp-1632000000 {
 371                         opp-hz = /bits/ 64 <1632000000>;
 372                         opp-peak-kBps = <3072000 40550400>;
 373                 };
 374
 375                 cpu0_opp17: opp-1708800000 {
 376                         opp-hz = /bits/ 64 <1708800000>;
 377                         opp-peak-kBps = <3072000 43008000>;
 378                 };
 379
 380                 cpu0_opp18: opp-1785600000 {
 381                         opp-hz = /bits/ 64 <1785600000>;
 382                         opp-peak-kBps = <3072000 43008000>;
 383                 };
 384         };
 385
 386         cpu4_opp_table: cpu4_opp_table {
 387                 compatible = "operating-points-v2";
 388                 opp-shared;
 389
 390                 cpu4_opp1: opp-710400000 {
 391                         opp-hz = /bits/ 64 <710400000>;
 392                         opp-peak-kBps = <1804000 15974400>;
 393                 };
 394
 395                 cpu4_opp2: opp-825600000 {
 396                         opp-hz = /bits/ 64 <825600000>;
 397                         opp-peak-kBps = <2188000 19660800>;
 398                 };
 399
 400                 cpu4_opp3: opp-940800000 {
 401                         opp-hz = /bits/ 64 <940800000>;
 402                         opp-peak-kBps = <2188000 22732800>;
 403                 };
 404
 405                 cpu4_opp4: opp-1056000000 {
 406                         opp-hz = /bits/ 64 <1056000000>;
 407                         opp-peak-kBps = <3072000 25804800>;
 408                 };
 409
 410                 cpu4_opp5: opp-1171200000 {
 411                         opp-hz = /bits/ 64 <1171200000>;
 412                         opp-peak-kBps = <3072000 31948800>;
 413                 };
 414
 415                 cpu4_opp6: opp-1286400000 {
 416                         opp-hz = /bits/ 64 <1286400000>;
 417                         opp-peak-kBps = <4068000 31948800>;
 418                 };
 419
 420                 cpu4_opp7: opp-1401600000 {
 421                         opp-hz = /bits/ 64 <1401600000>;
 422                         opp-peak-kBps = <4068000 31948800>;
 423                 };
 424
 425                 cpu4_opp8: opp-1497600000 {
 426                         opp-hz = /bits/ 64 <1497600000>;
 427                         opp-peak-kBps = <4068000 40550400>;
 428                 };
 429
 430                 cpu4_opp9: opp-1612800000 {
 431                         opp-hz = /bits/ 64 <1612800000>;
 432                         opp-peak-kBps = <4068000 40550400>;
 433                 };
 434
 435                 cpu4_opp10: opp-1708800000 {
 436                         opp-hz = /bits/ 64 <1708800000>;
 437                         opp-peak-kBps = <4068000 43008000>;
 438                 };
 439
 440                 cpu4_opp11: opp-1804800000 {
 441                         opp-hz = /bits/ 64 <1804800000>;
 442                         opp-peak-kBps = <6220000 43008000>;
 443                 };
 444
 445                 cpu4_opp12: opp-1920000000 {
 446                         opp-hz = /bits/ 64 <1920000000>;
 447                         opp-peak-kBps = <6220000 49152000>;
 448                 };
 449
 450                 cpu4_opp13: opp-2016000000 {
 451                         opp-hz = /bits/ 64 <2016000000>;
 452                         opp-peak-kBps = <7216000 49152000>;
 453                 };
 454
 455                 cpu4_opp14: opp-2131200000 {
 456                         opp-hz = /bits/ 64 <2131200000>;
 457                         opp-peak-kBps = <8368000 49152000>;
 458                 };
 459
 460                 cpu4_opp15: opp-2227200000 {
 461                         opp-hz = /bits/ 64 <2227200000>;
 462                         opp-peak-kBps = <8368000 51609600>;
 463                 };
 464
 465                 cpu4_opp16: opp-2323200000 {
 466                         opp-hz = /bits/ 64 <2323200000>;
 467                         opp-peak-kBps = <8368000 51609600>;
 468                 };
 469
 470                 cpu4_opp17: opp-2419200000 {
 471                         opp-hz = /bits/ 64 <2419200000>;
 472                         opp-peak-kBps = <8368000 51609600>;
 473                 };
 474         };
 475
 476         cpu7_opp_table: cpu7_opp_table {
 477                 compatible = "operating-points-v2";
 478                 opp-shared;
 479
 480                 cpu7_opp1: opp-825600000 {
 481                         opp-hz = /bits/ 64 <825600000>;
 482                         opp-peak-kBps = <2188000 19660800>;
 483                 };
 484
 485                 cpu7_opp2: opp-940800000 {
 486                         opp-hz = /bits/ 64 <940800000>;
 487                         opp-peak-kBps = <2188000 22732800>;
 488                 };
 489
 490                 cpu7_opp3: opp-1056000000 {
 491                         opp-hz = /bits/ 64 <1056000000>;
 492                         opp-peak-kBps = <3072000 25804800>;
 493                 };
 494
 495                 cpu7_opp4: opp-1171200000 {
 496                         opp-hz = /bits/ 64 <1171200000>;
 497                         opp-peak-kBps = <3072000 31948800>;
 498                 };
 499
 500                 cpu7_opp5: opp-1286400000 {
 501                         opp-hz = /bits/ 64 <1286400000>;
 502                         opp-peak-kBps = <4068000 31948800>;
 503                 };
 504
 505                 cpu7_opp6: opp-1401600000 {
 506                         opp-hz = /bits/ 64 <1401600000>;
 507                         opp-peak-kBps = <4068000 31948800>;
 508                 };
 509
 510                 cpu7_opp7: opp-1497600000 {
 511                         opp-hz = /bits/ 64 <1497600000>;
 512                         opp-peak-kBps = <4068000 40550400>;
 513                 };
 514
 515                 cpu7_opp8: opp-1612800000 {
 516                         opp-hz = /bits/ 64 <1612800000>;
 517                         opp-peak-kBps = <4068000 40550400>;
 518                 };
 519
 520                 cpu7_opp9: opp-1708800000 {
 521                         opp-hz = /bits/ 64 <1708800000>;
 522                         opp-peak-kBps = <4068000 43008000>;
 523                 };
 524
 525                 cpu7_opp10: opp-1804800000 {
 526                         opp-hz = /bits/ 64 <1804800000>;
 527                         opp-peak-kBps = <6220000 43008000>;
 528                 };
 529
 530                 cpu7_opp11: opp-1920000000 {
 531                         opp-hz = /bits/ 64 <1920000000>;
 532                         opp-peak-kBps = <6220000 49152000>;
 533                 };
 534
 535                 cpu7_opp12: opp-2016000000 {
 536                         opp-hz = /bits/ 64 <2016000000>;
 537                         opp-peak-kBps = <7216000 49152000>;
 538                 };
 539
 540                 cpu7_opp13: opp-2131200000 {
 541                         opp-hz = /bits/ 64 <2131200000>;
 542                         opp-peak-kBps = <8368000 49152000>;
 543                 };
 544
 545                 cpu7_opp14: opp-2227200000 {
 546                         opp-hz = /bits/ 64 <2227200000>;
 547                         opp-peak-kBps = <8368000 51609600>;
 548                 };
 549
 550                 cpu7_opp15: opp-2323200000 {
 551                         opp-hz = /bits/ 64 <2323200000>;
 552                         opp-peak-kBps = <8368000 51609600>;
 553                 };
 554
 555                 cpu7_opp16: opp-2419200000 {
 556                         opp-hz = /bits/ 64 <2419200000>;
 557                         opp-peak-kBps = <8368000 51609600>;
 558                 };
 559
 560                 cpu7_opp17: opp-2534400000 {
 561                         opp-hz = /bits/ 64 <2534400000>;
 562                         opp-peak-kBps = <8368000 51609600>;
 563                 };
 564
 565                 cpu7_opp18: opp-2649600000 {
 566                         opp-hz = /bits/ 64 <2649600000>;
 567                         opp-peak-kBps = <8368000 51609600>;
 568                 };
 569
 570                 cpu7_opp19: opp-2745600000 {
 571                         opp-hz = /bits/ 64 <2745600000>;
 572                         opp-peak-kBps = <8368000 51609600>;
 573                 };
 574
 575                 cpu7_opp20: opp-2841600000 {
 576                         opp-hz = /bits/ 64 <2841600000>;
 577                         opp-peak-kBps = <8368000 51609600>;
 578                 };
 579         };
 580
 581         firmware {
 582                 scm: scm {
 583                         compatible = "qcom,scm-sm8150", "qcom,scm";
 584                         #reset-cells = <1>;
 585                 };
 586         };
 587
 588         tcsr_mutex: hwlock {
 589                 compatible = "qcom,tcsr-mutex";
 590                 syscon = <&tcsr_mutex_regs 0 0x1000>;
 591                 #hwlock-cells = <1>;
 592         };
 593
 594         memory@80000000 {
 595                 device_type = "memory";
 596                 /* We expect the bootloader to fill in the size */
 597                 reg = <0x0 0x80000000 0x0 0x0>;
 598         };
 599
 600         pmu {
 601                 compatible = "arm,armv8-pmuv3";
 602                 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
 603         };
 604
 605         psci {
 606                 compatible = "arm,psci-1.0";
 607                 method = "smc";
 608
 609                 CPU_PD0: cpu0 {
 610                         #power-domain-cells = <0>;
 611                         power-domains = <&CLUSTER_PD>;
 612                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 613                 };
 614
 615                 CPU_PD1: cpu1 {
 616                         #power-domain-cells = <0>;
 617                         power-domains = <&CLUSTER_PD>;
 618                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 619                 };
 620
 621                 CPU_PD2: cpu2 {
 622                         #power-domain-cells = <0>;
 623                         power-domains = <&CLUSTER_PD>;
 624                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 625                 };
 626
 627                 CPU_PD3: cpu3 {
 628                         #power-domain-cells = <0>;
 629                         power-domains = <&CLUSTER_PD>;
 630                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 631                 };
 632
 633                 CPU_PD4: cpu4 {
 634                         #power-domain-cells = <0>;
 635                         power-domains = <&CLUSTER_PD>;
 636                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 637                 };
 638
 639                 CPU_PD5: cpu5 {
 640                         #power-domain-cells = <0>;
 641                         power-domains = <&CLUSTER_PD>;
 642                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 643                 };
 644
 645                 CPU_PD6: cpu6 {
 646                         #power-domain-cells = <0>;
 647                         power-domains = <&CLUSTER_PD>;
 648                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 649                 };
 650
 651                 CPU_PD7: cpu7 {
 652                         #power-domain-cells = <0>;
 653                         power-domains = <&CLUSTER_PD>;
 654                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 655                 };
 656
 657                 CLUSTER_PD: cpu-cluster0 {
 658                         #power-domain-cells = <0>;
 659                         domain-idle-states = <&CLUSTER_SLEEP_0>;
 660                 };
 661         };
 662
 663         reserved-memory {
 664                 #address-cells = <2>;
 665                 #size-cells = <2>;
 666                 ranges;
 667
 668                 hyp_mem: memory@85700000 {
 669                         reg = <0x0 0x85700000 0x0 0x600000>;
 670                         no-map;
 671                 };
 672
 673                 xbl_mem: memory@85d00000 {
 674                         reg = <0x0 0x85d00000 0x0 0x140000>;
 675                         no-map;
 676                 };
 677
 678                 aop_mem: memory@85f00000 {
 679                         reg = <0x0 0x85f00000 0x0 0x20000>;
 680                         no-map;
 681                 };
 682
 683                 aop_cmd_db: memory@85f20000 {
 684                         compatible = "qcom,cmd-db";
 685                         reg = <0x0 0x85f20000 0x0 0x20000>;
 686                         no-map;
 687                 };
 688
 689                 smem_mem: memory@86000000 {
 690                         reg = <0x0 0x86000000 0x0 0x200000>;
 691                         no-map;
 692                 };
 693
 694                 tz_mem: memory@86200000 {
 695                         reg = <0x0 0x86200000 0x0 0x3900000>;
 696                         no-map;
 697                 };
 698
 699                 rmtfs_mem: memory@89b00000 {
 700                         compatible = "qcom,rmtfs-mem";
 701                         reg = <0x0 0x89b00000 0x0 0x200000>;
 702                         no-map;
 703
 704                         qcom,client-id = <1>;
 705                         qcom,vmid = <15>;
 706                 };
 707
 708                 camera_mem: memory@8b700000 {
 709                         reg = <0x0 0x8b700000 0x0 0x500000>;
 710                         no-map;
 711                 };
 712
 713                 wlan_mem: memory@8bc00000 {
 714                         reg = <0x0 0x8bc00000 0x0 0x180000>;
 715                         no-map;
 716                 };
 717
 718                 npu_mem: memory@8bd80000 {
 719                         reg = <0x0 0x8bd80000 0x0 0x80000>;
 720                         no-map;
 721                 };
 722
 723                 adsp_mem: memory@8be00000 {
 724                         reg = <0x0 0x8be00000 0x0 0x1a00000>;
 725                         no-map;
 726                 };
 727
 728                 mpss_mem: memory@8d800000 {
 729                         reg = <0x0 0x8d800000 0x0 0x9600000>;
 730                         no-map;
 731                 };
 732
 733                 venus_mem: memory@96e00000 {
 734                         reg = <0x0 0x96e00000 0x0 0x500000>;
 735                         no-map;
 736                 };
 737
 738                 slpi_mem: memory@97300000 {
 739                         reg = <0x0 0x97300000 0x0 0x1400000>;
 740                         no-map;
 741                 };
 742
 743                 ipa_fw_mem: memory@98700000 {
 744                         reg = <0x0 0x98700000 0x0 0x10000>;
 745                         no-map;
 746                 };
 747
 748                 ipa_gsi_mem: memory@98710000 {
 749                         reg = <0x0 0x98710000 0x0 0x5000>;
 750                         no-map;
 751                 };
 752
 753                 gpu_mem: memory@98715000 {
 754                         reg = <0x0 0x98715000 0x0 0x2000>;
 755                         no-map;
 756                 };
 757
 758                 spss_mem: memory@98800000 {
 759                         reg = <0x0 0x98800000 0x0 0x100000>;
 760                         no-map;
 761                 };
 762
 763                 cdsp_mem: memory@98900000 {
 764                         reg = <0x0 0x98900000 0x0 0x1400000>;
 765                         no-map;
 766                 };
 767
 768                 qseecom_mem: memory@9e400000 {
 769                         reg = <0x0 0x9e400000 0x0 0x1400000>;
 770                         no-map;
 771                 };
 772         };
 773
 774         smem {
 775                 compatible = "qcom,smem";
 776                 memory-region = <&smem_mem>;
 777                 hwlocks = <&tcsr_mutex 3>;
 778         };
 779
 780         smp2p-cdsp {
 781                 compatible = "qcom,smp2p";
 782                 qcom,smem = <94>, <432>;
 783
 784                 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
 785
 786                 mboxes = <&apss_shared 6>;
 787
 788                 qcom,local-pid = <0>;
 789                 qcom,remote-pid = <5>;
 790
 791                 cdsp_smp2p_out: master-kernel {
 792                         qcom,entry-name = "master-kernel";
 793                         #qcom,smem-state-cells = <1>;
 794                 };
 795
 796                 cdsp_smp2p_in: slave-kernel {
 797                         qcom,entry-name = "slave-kernel";
 798
 799                         interrupt-controller;
 800                         #interrupt-cells = <2>;
 801                 };
 802         };
 803
 804         smp2p-lpass {
 805                 compatible = "qcom,smp2p";
 806                 qcom,smem = <443>, <429>;
 807
 808                 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
 809
 810                 mboxes = <&apss_shared 10>;
 811
 812                 qcom,local-pid = <0>;
 813                 qcom,remote-pid = <2>;
 814
 815                 adsp_smp2p_out: master-kernel {
 816                         qcom,entry-name = "master-kernel";
 817                         #qcom,smem-state-cells = <1>;
 818                 };
 819
 820                 adsp_smp2p_in: slave-kernel {
 821                         qcom,entry-name = "slave-kernel";
 822
 823                         interrupt-controller;
 824                         #interrupt-cells = <2>;
 825                 };
 826         };
 827
 828         smp2p-mpss {
 829                 compatible = "qcom,smp2p";
 830                 qcom,smem = <435>, <428>;
 831
 832                 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
 833
 834                 mboxes = <&apss_shared 14>;
 835
 836                 qcom,local-pid = <0>;
 837                 qcom,remote-pid = <1>;
 838
 839                 modem_smp2p_out: master-kernel {
 840                         qcom,entry-name = "master-kernel";
 841                         #qcom,smem-state-cells = <1>;
 842                 };
 843
 844                 modem_smp2p_in: slave-kernel {
 845                         qcom,entry-name = "slave-kernel";
 846
 847                         interrupt-controller;
 848                         #interrupt-cells = <2>;
 849                 };
 850         };
 851
 852         smp2p-slpi {
 853                 compatible = "qcom,smp2p";
 854                 qcom,smem = <481>, <430>;
 855
 856                 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
 857
 858                 mboxes = <&apss_shared 26>;
 859
 860                 qcom,local-pid = <0>;
 861                 qcom,remote-pid = <3>;
 862
 863                 slpi_smp2p_out: master-kernel {
 864                         qcom,entry-name = "master-kernel";
 865                         #qcom,smem-state-cells = <1>;
 866                 };
 867
 868                 slpi_smp2p_in: slave-kernel {
 869                         qcom,entry-name = "slave-kernel";
 870
 871                         interrupt-controller;
 872                         #interrupt-cells = <2>;
 873                 };
 874         };
 875
 876         soc: soc@0 {
 877                 #address-cells = <2>;
 878                 #size-cells = <2>;
 879                 ranges = <0 0 0 0 0x10 0>;
 880                 dma-ranges = <0 0 0 0 0x10 0>;
 881                 compatible = "simple-bus";
 882
 883                 gcc: clock-controller@100000 {
 884                         compatible = "qcom,gcc-sm8150";
 885                         reg = <0x0 0x00100000 0x0 0x1f0000>;
 886                         #clock-cells = <1>;
 887                         #reset-cells = <1>;
 888                         #power-domain-cells = <1>;
 889                         clock-names = "bi_tcxo",
 890                                       "sleep_clk";
 891                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 892                                  <&sleep_clk>;
 893                 };
 894
 895                 gpi_dma0: dma-controller@800000 {
 896                         compatible = "qcom,sm8150-gpi-dma";
 897                         reg = <0 0x800000 0 0x60000>;
 898                         interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
 899                                      <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
 900                                      <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
 901                                      <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
 902                                      <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
 903                                      <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
 904                                      <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
 905                                      <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
 906                                      <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
 907                                      <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
 908                                      <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
 909                                      <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
 910                                      <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
 911                         dma-channels = <13>;
 912                         dma-channel-mask = <0xfa>;
 913                         iommus = <&apps_smmu 0x00d6 0x0>;
 914                         #dma-cells = <3>;
 915                         status = "disabled";
 916                 };
 917
 918                 qupv3_id_0: geniqup@8c0000 {
 919                         compatible = "qcom,geni-se-qup";
 920                         reg = <0x0 0x008c0000 0x0 0x6000>;
 921                         clock-names = "m-ahb", "s-ahb";
 922                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
 923                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
 924                         iommus = <&apps_smmu 0xc3 0x0>;
 925                         #address-cells = <2>;
 926                         #size-cells = <2>;
 927                         ranges;
 928                         status = "disabled";
 929
 930                         i2c0: i2c@880000 {
 931                                 compatible = "qcom,geni-i2c";
 932                                 reg = <0 0x00880000 0 0x4000>;
 933                                 clock-names = "se";
 934                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 935                                 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
 936                                        <&gpi_dma0 1 0 QCOM_GPI_I2C>;
 937                                 dma-names = "tx", "rx";
 938                                 pinctrl-names = "default";
 939                                 pinctrl-0 = <&qup_i2c0_default>;
 940                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 941                                 #address-cells = <1>;
 942                                 #size-cells = <0>;
 943                                 status = "disabled";
 944                         };
 945
 946                         spi0: spi@880000 {
 947                                 compatible = "qcom,geni-spi";
 948                                 reg = <0 0x880000 0 0x4000>;
 949                                 reg-names = "se";
 950                                 clock-names = "se";
 951                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 952                                 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
 953                                        <&gpi_dma0 1 0 QCOM_GPI_SPI>;
 954                                 dma-names = "tx", "rx";
 955                                 pinctrl-names = "default";
 956                                 pinctrl-0 = <&qup_spi0_default>;
 957                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 958                                 spi-max-frequency = <50000000>;
 959                                 #address-cells = <1>;
 960                                 #size-cells = <0>;
 961                                 status = "disabled";
 962                         };
 963
 964                         i2c1: i2c@884000 {
 965                                 compatible = "qcom,geni-i2c";
 966                                 reg = <0 0x00884000 0 0x4000>;
 967                                 clock-names = "se";
 968                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 969                                 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
 970                                        <&gpi_dma0 1 1 QCOM_GPI_I2C>;
 971                                 dma-names = "tx", "rx";
 972                                 pinctrl-names = "default";
 973                                 pinctrl-0 = <&qup_i2c1_default>;
 974                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 975                                 #address-cells = <1>;
 976                                 #size-cells = <0>;
 977                                 status = "disabled";
 978                         };
 979
 980                         spi1: spi@884000 {
 981                                 compatible = "qcom,geni-spi";
 982                                 reg = <0 0x884000 0 0x4000>;
 983                                 reg-names = "se";
 984                                 clock-names = "se";
 985                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 986                                 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
 987                                        <&gpi_dma0 1 1 QCOM_GPI_SPI>;
 988                                 dma-names = "tx", "rx";
 989                                 pinctrl-names = "default";
 990                                 pinctrl-0 = <&qup_spi1_default>;
 991                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 992                                 spi-max-frequency = <50000000>;
 993                                 #address-cells = <1>;
 994                                 #size-cells = <0>;
 995                                 status = "disabled";
 996                         };
 997
 998                         i2c2: i2c@888000 {
 999                                 compatible = "qcom,geni-i2c";
1000                                 reg = <0 0x00888000 0 0x4000>;
1001                                 clock-names = "se";
1002                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1003                                 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1004                                        <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1005                                 dma-names = "tx", "rx";
1006                                 pinctrl-names = "default";
1007                                 pinctrl-0 = <&qup_i2c2_default>;
1008                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1009                                 #address-cells = <1>;
1010                                 #size-cells = <0>;
1011                                 status = "disabled";
1012                         };
1013
1014                         spi2: spi@888000 {
1015                                 compatible = "qcom,geni-spi";
1016                                 reg = <0 0x888000 0 0x4000>;
1017                                 reg-names = "se";
1018                                 clock-names = "se";
1019                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1020                                 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1021                                        <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1022                                 dma-names = "tx", "rx";
1023                                 pinctrl-names = "default";
1024                                 pinctrl-0 = <&qup_spi2_default>;
1025                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1026                                 spi-max-frequency = <50000000>;
1027                                 #address-cells = <1>;
1028                                 #size-cells = <0>;
1029                                 status = "disabled";
1030                         };
1031
1032                         i2c3: i2c@88c000 {
1033                                 compatible = "qcom,geni-i2c";
1034                                 reg = <0 0x0088c000 0 0x4000>;
1035                                 clock-names = "se";
1036                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1037                                 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1038                                        <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1039                                 dma-names = "tx", "rx";
1040                                 pinctrl-names = "default";
1041                                 pinctrl-0 = <&qup_i2c3_default>;
1042                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1043                                 #address-cells = <1>;
1044                                 #size-cells = <0>;
1045                                 status = "disabled";
1046                         };
1047
1048                         spi3: spi@88c000 {
1049                                 compatible = "qcom,geni-spi";
1050                                 reg = <0 0x88c000 0 0x4000>;
1051                                 reg-names = "se";
1052                                 clock-names = "se";
1053                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1054                                 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1055                                        <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1056                                 dma-names = "tx", "rx";
1057                                 pinctrl-names = "default";
1058                                 pinctrl-0 = <&qup_spi3_default>;
1059                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1060                                 spi-max-frequency = <50000000>;
1061                                 #address-cells = <1>;
1062                                 #size-cells = <0>;
1063                                 status = "disabled";
1064                         };
1065
1066                         i2c4: i2c@890000 {
1067                                 compatible = "qcom,geni-i2c";
1068                                 reg = <0 0x00890000 0 0x4000>;
1069                                 clock-names = "se";
1070                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1071                                 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1072                                        <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1073                                 dma-names = "tx", "rx";
1074                                 pinctrl-names = "default";
1075                                 pinctrl-0 = <&qup_i2c4_default>;
1076                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1077                                 #address-cells = <1>;
1078                                 #size-cells = <0>;
1079                                 status = "disabled";
1080                         };
1081
1082                         spi4: spi@890000 {
1083                                 compatible = "qcom,geni-spi";
1084                                 reg = <0 0x890000 0 0x4000>;
1085                                 reg-names = "se";
1086                                 clock-names = "se";
1087                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1088                                 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1089                                        <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1090                                 dma-names = "tx", "rx";
1091                                 pinctrl-names = "default";
1092                                 pinctrl-0 = <&qup_spi4_default>;
1093                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1094                                 spi-max-frequency = <50000000>;
1095                                 #address-cells = <1>;
1096                                 #size-cells = <0>;
1097                                 status = "disabled";
1098                         };
1099
1100                         i2c5: i2c@894000 {
1101                                 compatible = "qcom,geni-i2c";
1102                                 reg = <0 0x00894000 0 0x4000>;
1103                                 clock-names = "se";
1104                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1105                                 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1106                                        <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1107                                 dma-names = "tx", "rx";
1108                                 pinctrl-names = "default";
1109                                 pinctrl-0 = <&qup_i2c5_default>;
1110                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1111                                 #address-cells = <1>;
1112                                 #size-cells = <0>;
1113                                 status = "disabled";
1114                         };
1115
1116                         spi5: spi@894000 {
1117                                 compatible = "qcom,geni-spi";
1118                                 reg = <0 0x894000 0 0x4000>;
1119                                 reg-names = "se";
1120                                 clock-names = "se";
1121                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1122                                 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1123                                        <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1124                                 dma-names = "tx", "rx";
1125                                 pinctrl-names = "default";
1126                                 pinctrl-0 = <&qup_spi5_default>;
1127                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1128                                 spi-max-frequency = <50000000>;
1129                                 #address-cells = <1>;
1130                                 #size-cells = <0>;
1131                                 status = "disabled";
1132                         };
1133
1134                         i2c6: i2c@898000 {
1135                                 compatible = "qcom,geni-i2c";
1136                                 reg = <0 0x00898000 0 0x4000>;
1137                                 clock-names = "se";
1138                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1139                                 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1140                                        <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1141                                 dma-names = "tx", "rx";
1142                                 pinctrl-names = "default";
1143                                 pinctrl-0 = <&qup_i2c6_default>;
1144                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1145                                 #address-cells = <1>;
1146                                 #size-cells = <0>;
1147                                 status = "disabled";
1148                         };
1149
1150                         spi6: spi@898000 {
1151                                 compatible = "qcom,geni-spi";
1152                                 reg = <0 0x898000 0 0x4000>;
1153                                 reg-names = "se";
1154                                 clock-names = "se";
1155                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1156                                 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1157                                        <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1158                                 dma-names = "tx", "rx";
1159                                 pinctrl-names = "default";
1160                                 pinctrl-0 = <&qup_spi6_default>;
1161                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1162                                 spi-max-frequency = <50000000>;
1163                                 #address-cells = <1>;
1164                                 #size-cells = <0>;
1165                                 status = "disabled";
1166                         };
1167
1168                         i2c7: i2c@89c000 {
1169                                 compatible = "qcom,geni-i2c";
1170                                 reg = <0 0x0089c000 0 0x4000>;
1171                                 clock-names = "se";
1172                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1173                                 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1174                                        <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1175                                 dma-names = "tx", "rx";
1176                                 pinctrl-names = "default";
1177                                 pinctrl-0 = <&qup_i2c7_default>;
1178                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1179                                 #address-cells = <1>;
1180                                 #size-cells = <0>;
1181                                 status = "disabled";
1182                         };
1183
1184                         spi7: spi@89c000 {
1185                                 compatible = "qcom,geni-spi";
1186                                 reg = <0 0x89c000 0 0x4000>;
1187                                 reg-names = "se";
1188                                 clock-names = "se";
1189                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1190                                 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1191                                        <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1192                                 dma-names = "tx", "rx";
1193                                 pinctrl-names = "default";
1194                                 pinctrl-0 = <&qup_spi7_default>;
1195                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1196                                 spi-max-frequency = <50000000>;
1197                                 #address-cells = <1>;
1198                                 #size-cells = <0>;
1199                                 status = "disabled";
1200                         };
1201                 };
1202
1203                 gpi_dma1: dma-controller@a00000 {
1204                         compatible = "qcom,sm8150-gpi-dma";
1205                         reg = <0 0xa00000 0 0x60000>;
1206                         interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1207                                      <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1208                                      <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1209                                      <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1210                                      <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1211                                      <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1212                                      <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1213                                      <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1214                                      <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1215                                      <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1216                                      <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1217                                      <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
1218                                      <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
1219                         dma-channels = <13>;
1220                         dma-channel-mask = <0xfa>;
1221                         iommus = <&apps_smmu 0x0616 0x0>;
1222                         #dma-cells = <3>;
1223                         status = "disabled";
1224                 };
1225
1226                 qupv3_id_1: geniqup@ac0000 {
1227                         compatible = "qcom,geni-se-qup";
1228                         reg = <0x0 0x00ac0000 0x0 0x6000>;
1229                         clock-names = "m-ahb", "s-ahb";
1230                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1231                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1232                         iommus = <&apps_smmu 0x603 0x0>;
1233                         #address-cells = <2>;
1234                         #size-cells = <2>;
1235                         ranges;
1236                         status = "disabled";
1237
1238                         i2c8: i2c@a80000 {
1239                                 compatible = "qcom,geni-i2c";
1240                                 reg = <0 0x00a80000 0 0x4000>;
1241                                 clock-names = "se";
1242                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1243                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1244                                        <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1245                                 dma-names = "tx", "rx";
1246                                 pinctrl-names = "default";
1247                                 pinctrl-0 = <&qup_i2c8_default>;
1248                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1249                                 #address-cells = <1>;
1250                                 #size-cells = <0>;
1251                                 status = "disabled";
1252                         };
1253
1254                         spi8: spi@a80000 {
1255                                 compatible = "qcom,geni-spi";
1256                                 reg = <0 0xa80000 0 0x4000>;
1257                                 reg-names = "se";
1258                                 clock-names = "se";
1259                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1260                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1261                                        <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1262                                 dma-names = "tx", "rx";
1263                                 pinctrl-names = "default";
1264                                 pinctrl-0 = <&qup_spi8_default>;
1265                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1266                                 spi-max-frequency = <50000000>;
1267                                 #address-cells = <1>;
1268                                 #size-cells = <0>;
1269                                 status = "disabled";
1270                         };
1271
1272                         i2c9: i2c@a84000 {
1273                                 compatible = "qcom,geni-i2c";
1274                                 reg = <0 0x00a84000 0 0x4000>;
1275                                 clock-names = "se";
1276                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1277                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1278                                        <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1279                                 dma-names = "tx", "rx";
1280                                 pinctrl-names = "default";
1281                                 pinctrl-0 = <&qup_i2c9_default>;
1282                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1283                                 #address-cells = <1>;
1284                                 #size-cells = <0>;
1285                                 status = "disabled";
1286                         };
1287
1288                         spi9: spi@a84000 {
1289                                 compatible = "qcom,geni-spi";
1290                                 reg = <0 0xa84000 0 0x4000>;
1291                                 reg-names = "se";
1292                                 clock-names = "se";
1293                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1294                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1295                                        <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1296                                 dma-names = "tx", "rx";
1297                                 pinctrl-names = "default";
1298                                 pinctrl-0 = <&qup_spi9_default>;
1299                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1300                                 spi-max-frequency = <50000000>;
1301                                 #address-cells = <1>;
1302                                 #size-cells = <0>;
1303                                 status = "disabled";
1304                         };
1305
1306                         i2c10: i2c@a88000 {
1307                                 compatible = "qcom,geni-i2c";
1308                                 reg = <0 0x00a88000 0 0x4000>;
1309                                 clock-names = "se";
1310                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1311                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1312                                        <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1313                                 dma-names = "tx", "rx";
1314                                 pinctrl-names = "default";
1315                                 pinctrl-0 = <&qup_i2c10_default>;
1316                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1317                                 #address-cells = <1>;
1318                                 #size-cells = <0>;
1319                                 status = "disabled";
1320                         };
1321
1322                         spi10: spi@a88000 {
1323                                 compatible = "qcom,geni-spi";
1324                                 reg = <0 0xa88000 0 0x4000>;
1325                                 reg-names = "se";
1326                                 clock-names = "se";
1327                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1328                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1329                                        <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1330                                 dma-names = "tx", "rx";
1331                                 pinctrl-names = "default";
1332                                 pinctrl-0 = <&qup_spi10_default>;
1333                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1334                                 spi-max-frequency = <50000000>;
1335                                 #address-cells = <1>;
1336                                 #size-cells = <0>;
1337                                 status = "disabled";
1338                         };
1339
1340                         i2c11: i2c@a8c000 {
1341                                 compatible = "qcom,geni-i2c";
1342                                 reg = <0 0x00a8c000 0 0x4000>;
1343                                 clock-names = "se";
1344                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1345                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1346                                        <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1347                                 dma-names = "tx", "rx";
1348                                 pinctrl-names = "default";
1349                                 pinctrl-0 = <&qup_i2c11_default>;
1350                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1351                                 #address-cells = <1>;
1352                                 #size-cells = <0>;
1353                                 status = "disabled";
1354                         };
1355
1356                         spi11: spi@a8c000 {
1357                                 compatible = "qcom,geni-spi";
1358                                 reg = <0 0xa8c000 0 0x4000>;
1359                                 reg-names = "se";
1360                                 clock-names = "se";
1361                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1362                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1363                                        <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1364                                 dma-names = "tx", "rx";
1365                                 pinctrl-names = "default";
1366                                 pinctrl-0 = <&qup_spi11_default>;
1367                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1368                                 spi-max-frequency = <50000000>;
1369                                 #address-cells = <1>;
1370                                 #size-cells = <0>;
1371                                 status = "disabled";
1372                         };
1373
1374                         uart2: serial@a90000 {
1375                                 compatible = "qcom,geni-debug-uart";
1376                                 reg = <0x0 0x00a90000 0x0 0x4000>;
1377                                 clock-names = "se";
1378                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1379                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1380                                 status = "disabled";
1381                         };
1382
1383                         i2c12: i2c@a90000 {
1384                                 compatible = "qcom,geni-i2c";
1385                                 reg = <0 0x00a90000 0 0x4000>;
1386                                 clock-names = "se";
1387                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1388                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1389                                        <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1390                                 dma-names = "tx", "rx";
1391                                 pinctrl-names = "default";
1392                                 pinctrl-0 = <&qup_i2c12_default>;
1393                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1394                                 #address-cells = <1>;
1395                                 #size-cells = <0>;
1396                                 status = "disabled";
1397                         };
1398
1399                         spi12: spi@a90000 {
1400                                 compatible = "qcom,geni-spi";
1401                                 reg = <0 0xa90000 0 0x4000>;
1402                                 reg-names = "se";
1403                                 clock-names = "se";
1404                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1405                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1406                                        <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1407                                 dma-names = "tx", "rx";
1408                                 pinctrl-names = "default";
1409                                 pinctrl-0 = <&qup_spi12_default>;
1410                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1411                                 spi-max-frequency = <50000000>;
1412                                 #address-cells = <1>;
1413                                 #size-cells = <0>;
1414                                 status = "disabled";
1415                         };
1416
1417                         i2c16: i2c@94000 {
1418                                 compatible = "qcom,geni-i2c";
1419                                 reg = <0 0x0094000 0 0x4000>;
1420                                 clock-names = "se";
1421                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1422                                 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1423                                        <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1424                                 dma-names = "tx", "rx";
1425                                 pinctrl-names = "default";
1426                                 pinctrl-0 = <&qup_i2c16_default>;
1427                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1428                                 #address-cells = <1>;
1429                                 #size-cells = <0>;
1430                                 status = "disabled";
1431                         };
1432
1433                         spi16: spi@a94000 {
1434                                 compatible = "qcom,geni-spi";
1435                                 reg = <0 0xa94000 0 0x4000>;
1436                                 reg-names = "se";
1437                                 clock-names = "se";
1438                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1439                                 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1440                                        <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1441                                 dma-names = "tx", "rx";
1442                                 pinctrl-names = "default";
1443                                 pinctrl-0 = <&qup_spi16_default>;
1444                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1445                                 spi-max-frequency = <50000000>;
1446                                 #address-cells = <1>;
1447                                 #size-cells = <0>;
1448                                 status = "disabled";
1449                         };
1450                 };
1451
1452                 gpi_dma2: dma-controller@c00000 {
1453                         compatible = "qcom,sm8150-gpi-dma";
1454                         reg = <0 0xc00000 0 0x60000>;
1455                         interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
1456                                      <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
1457                                      <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
1458                                      <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
1459                                      <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
1460                                      <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
1461                                      <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
1462                                      <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
1463                                      <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
1464                                      <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
1465                                      <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
1466                                      <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>,
1467                                      <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>;
1468                         dma-channels = <13>;
1469                         dma-channel-mask = <0xfa>;
1470                         iommus = <&apps_smmu 0x07b6 0x0>;
1471                         #dma-cells = <3>;
1472                         status = "disabled";
1473                 };
1474
1475                 qupv3_id_2: geniqup@cc0000 {
1476                         compatible = "qcom,geni-se-qup";
1477                         reg = <0x0 0x00cc0000 0x0 0x6000>;
1478
1479                         clock-names = "m-ahb", "s-ahb";
1480                         clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
1481                                  <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
1482                         iommus = <&apps_smmu 0x7a3 0x0>;
1483                         #address-cells = <2>;
1484                         #size-cells = <2>;
1485                         ranges;
1486                         status = "disabled";
1487
1488                         i2c17: i2c@c80000 {
1489                                 compatible = "qcom,geni-i2c";
1490                                 reg = <0 0x00c80000 0 0x4000>;
1491                                 clock-names = "se";
1492                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1493                                 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
1494                                        <&gpi_dma2 1 0 QCOM_GPI_I2C>;
1495                                 dma-names = "tx", "rx";
1496                                 pinctrl-names = "default";
1497                                 pinctrl-0 = <&qup_i2c17_default>;
1498                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1499                                 #address-cells = <1>;
1500                                 #size-cells = <0>;
1501                                 status = "disabled";
1502                         };
1503
1504                         spi17: spi@c80000 {
1505                                 compatible = "qcom,geni-spi";
1506                                 reg = <0 0xc80000 0 0x4000>;
1507                                 reg-names = "se";
1508                                 clock-names = "se";
1509                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1510                                 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
1511                                        <&gpi_dma2 1 0 QCOM_GPI_SPI>;
1512                                 dma-names = "tx", "rx";
1513                                 pinctrl-names = "default";
1514                                 pinctrl-0 = <&qup_spi17_default>;
1515                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1516                                 spi-max-frequency = <50000000>;
1517                                 #address-cells = <1>;
1518                                 #size-cells = <0>;
1519                                 status = "disabled";
1520                         };
1521
1522                         i2c18: i2c@c84000 {
1523                                 compatible = "qcom,geni-i2c";
1524                                 reg = <0 0x00c84000 0 0x4000>;
1525                                 clock-names = "se";
1526                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1527                                 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
1528                                        <&gpi_dma2 1 1 QCOM_GPI_I2C>;
1529                                 dma-names = "tx", "rx";
1530                                 pinctrl-names = "default";
1531                                 pinctrl-0 = <&qup_i2c18_default>;
1532                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1533                                 #address-cells = <1>;
1534                                 #size-cells = <0>;
1535                                 status = "disabled";
1536                         };
1537
1538                         spi18: spi@c84000 {
1539                                 compatible = "qcom,geni-spi";
1540                                 reg = <0 0xc84000 0 0x4000>;
1541                                 reg-names = "se";
1542                                 clock-names = "se";
1543                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1544                                 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
1545                                        <&gpi_dma2 1 1 QCOM_GPI_SPI>;
1546                                 dma-names = "tx", "rx";
1547                                 pinctrl-names = "default";
1548                                 pinctrl-0 = <&qup_spi18_default>;
1549                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1550                                 spi-max-frequency = <50000000>;
1551                                 #address-cells = <1>;
1552                                 #size-cells = <0>;
1553                                 status = "disabled";
1554                         };
1555
1556                         i2c19: i2c@c88000 {
1557                                 compatible = "qcom,geni-i2c";
1558                                 reg = <0 0x00c88000 0 0x4000>;
1559                                 clock-names = "se";
1560                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1561                                 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
1562                                        <&gpi_dma2 1 2 QCOM_GPI_I2C>;
1563                                 dma-names = "tx", "rx";
1564                                 pinctrl-names = "default";
1565                                 pinctrl-0 = <&qup_i2c19_default>;
1566                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1567                                 #address-cells = <1>;
1568                                 #size-cells = <0>;
1569                                 status = "disabled";
1570                         };
1571
1572                         spi19: spi@c88000 {
1573                                 compatible = "qcom,geni-spi";
1574                                 reg = <0 0xc88000 0 0x4000>;
1575                                 reg-names = "se";
1576                                 clock-names = "se";
1577                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1578                                 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1579                                        <&gpi_dma2 1 2 QCOM_GPI_SPI>;
1580                                 dma-names = "tx", "rx";
1581                                 pinctrl-names = "default";
1582                                 pinctrl-0 = <&qup_spi19_default>;
1583                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1584                                 spi-max-frequency = <50000000>;
1585                                 #address-cells = <1>;
1586                                 #size-cells = <0>;
1587                                 status = "disabled";
1588                         };
1589
1590                         i2c13: i2c@c8c000 {
1591                                 compatible = "qcom,geni-i2c";
1592                                 reg = <0 0x00c8c000 0 0x4000>;
1593                                 clock-names = "se";
1594                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1595                                 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1596                                        <&gpi_dma2 1 3 QCOM_GPI_I2C>;
1597                                 dma-names = "tx", "rx";
1598                                 pinctrl-names = "default";
1599                                 pinctrl-0 = <&qup_i2c13_default>;
1600                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1601                                 #address-cells = <1>;
1602                                 #size-cells = <0>;
1603                                 status = "disabled";
1604                         };
1605
1606                         spi13: spi@c8c000 {
1607                                 compatible = "qcom,geni-spi";
1608                                 reg = <0 0xc8c000 0 0x4000>;
1609                                 reg-names = "se";
1610                                 clock-names = "se";
1611                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1612                                 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1613                                        <&gpi_dma2 1 3 QCOM_GPI_SPI>;
1614                                 dma-names = "tx", "rx";
1615                                 pinctrl-names = "default";
1616                                 pinctrl-0 = <&qup_spi13_default>;
1617                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1618                                 spi-max-frequency = <50000000>;
1619                                 #address-cells = <1>;
1620                                 #size-cells = <0>;
1621                                 status = "disabled";
1622                         };
1623
1624                         i2c14: i2c@c90000 {
1625                                 compatible = "qcom,geni-i2c";
1626                                 reg = <0 0x00c90000 0 0x4000>;
1627                                 clock-names = "se";
1628                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1629                                 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1630                                        <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1631                                 dma-names = "tx", "rx";
1632                                 pinctrl-names = "default";
1633                                 pinctrl-0 = <&qup_i2c14_default>;
1634                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1635                                 #address-cells = <1>;
1636                                 #size-cells = <0>;
1637                                 status = "disabled";
1638                         };
1639
1640                         spi14: spi@c90000 {
1641                                 compatible = "qcom,geni-spi";
1642                                 reg = <0 0xc90000 0 0x4000>;
1643                                 reg-names = "se";
1644                                 clock-names = "se";
1645                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1646                                 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1647                                        <&gpi_dma2 1 4 QCOM_GPI_SPI>;
1648                                 dma-names = "tx", "rx";
1649                                 pinctrl-names = "default";
1650                                 pinctrl-0 = <&qup_spi14_default>;
1651                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1652                                 spi-max-frequency = <50000000>;
1653                                 #address-cells = <1>;
1654                                 #size-cells = <0>;
1655                                 status = "disabled";
1656                         };
1657
1658                         i2c15: i2c@c94000 {
1659                                 compatible = "qcom,geni-i2c";
1660                                 reg = <0 0x00c94000 0 0x4000>;
1661                                 clock-names = "se";
1662                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1663                                 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1664                                        <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1665                                 dma-names = "tx", "rx";
1666                                 pinctrl-names = "default";
1667                                 pinctrl-0 = <&qup_i2c15_default>;
1668                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1669                                 #address-cells = <1>;
1670                                 #size-cells = <0>;
1671                                 status = "disabled";
1672                         };
1673
1674                         spi15: spi@c94000 {
1675                                 compatible = "qcom,geni-spi";
1676                                 reg = <0 0xc94000 0 0x4000>;
1677                                 reg-names = "se";
1678                                 clock-names = "se";
1679                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1680                                 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1681                                        <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1682                                 dma-names = "tx", "rx";
1683                                 pinctrl-names = "default";
1684                                 pinctrl-0 = <&qup_spi15_default>;
1685                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1686                                 spi-max-frequency = <50000000>;
1687                                 #address-cells = <1>;
1688                                 #size-cells = <0>;
1689                                 status = "disabled";
1690                         };
1691                 };
1692
1693                 config_noc: interconnect@1500000 {
1694                         compatible = "qcom,sm8150-config-noc";
1695                         reg = <0 0x01500000 0 0x7400>;
1696                         #interconnect-cells = <1>;
1697                         qcom,bcm-voters = <&apps_bcm_voter>;
1698                 };
1699
1700                 system_noc: interconnect@1620000 {
1701                         compatible = "qcom,sm8150-system-noc";
1702                         reg = <0 0x01620000 0 0x19400>;
1703                         #interconnect-cells = <1>;
1704                         qcom,bcm-voters = <&apps_bcm_voter>;
1705                 };
1706
1707                 mc_virt: interconnect@163a000 {
1708                         compatible = "qcom,sm8150-mc-virt";
1709                         reg = <0 0x0163a000 0 0x1000>;
1710                         #interconnect-cells = <1>;
1711                         qcom,bcm-voters = <&apps_bcm_voter>;
1712                 };
1713
1714                 aggre1_noc: interconnect@16e0000 {
1715                         compatible = "qcom,sm8150-aggre1-noc";
1716                         reg = <0 0x016e0000 0 0xd080>;
1717                         #interconnect-cells = <1>;
1718                         qcom,bcm-voters = <&apps_bcm_voter>;
1719                 };
1720
1721                 aggre2_noc: interconnect@1700000 {
1722                         compatible = "qcom,sm8150-aggre2-noc";
1723                         reg = <0 0x01700000 0 0x20000>;
1724                         #interconnect-cells = <1>;
1725                         qcom,bcm-voters = <&apps_bcm_voter>;
1726                 };
1727
1728                 compute_noc: interconnect@1720000 {
1729                         compatible = "qcom,sm8150-compute-noc";
1730                         reg = <0 0x01720000 0 0x7000>;
1731                         #interconnect-cells = <1>;
1732                         qcom,bcm-voters = <&apps_bcm_voter>;
1733                 };
1734
1735                 mmss_noc: interconnect@1740000 {
1736                         compatible = "qcom,sm8150-mmss-noc";
1737                         reg = <0 0x01740000 0 0x1c100>;
1738                         #interconnect-cells = <1>;
1739                         qcom,bcm-voters = <&apps_bcm_voter>;
1740                 };
1741
1742                 system-cache-controller@9200000 {
1743                         compatible = "qcom,sm8150-llcc";
1744                         reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>;
1745                         reg-names = "llcc_base", "llcc_broadcast_base";
1746                         interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
1747                 };
1748
1749                 ufs_mem_hc: ufshc@1d84000 {
1750                         compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
1751                                      "jedec,ufs-2.0";
1752                         reg = <0 0x01d84000 0 0x2500>,
1753                               <0 0x01d90000 0 0x8000>;
1754                         reg-names = "std", "ice";
1755                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1756                         phys = <&ufs_mem_phy_lanes>;
1757                         phy-names = "ufsphy";
1758                         lanes-per-direction = <2>;
1759                         #reset-cells = <1>;
1760                         resets = <&gcc GCC_UFS_PHY_BCR>;
1761                         reset-names = "rst";
1762
1763                         iommus = <&apps_smmu 0x300 0>;
1764
1765                         clock-names =
1766                                 "core_clk",
1767                                 "bus_aggr_clk",
1768                                 "iface_clk",
1769                                 "core_clk_unipro",
1770                                 "ref_clk",
1771                                 "tx_lane0_sync_clk",
1772                                 "rx_lane0_sync_clk",
1773                                 "rx_lane1_sync_clk",
1774                                 "ice_core_clk";
1775                         clocks =
1776                                 <&gcc GCC_UFS_PHY_AXI_CLK>,
1777                                 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1778                                 <&gcc GCC_UFS_PHY_AHB_CLK>,
1779                                 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1780                                 <&rpmhcc RPMH_CXO_CLK>,
1781                                 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1782                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
1783                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
1784                                 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
1785                         freq-table-hz =
1786                                 <37500000 300000000>,
1787                                 <0 0>,
1788                                 <0 0>,
1789                                 <37500000 300000000>,
1790                                 <0 0>,
1791                                 <0 0>,
1792                                 <0 0>,
1793                                 <0 0>,
1794                                 <0 300000000>;
1795
1796                         status = "disabled";
1797                 };
1798
1799                 ufs_mem_phy: phy@1d87000 {
1800                         compatible = "qcom,sm8150-qmp-ufs-phy";
1801                         reg = <0 0x01d87000 0 0x1c0>;
1802                         #address-cells = <2>;
1803                         #size-cells = <2>;
1804                         ranges;
1805                         clock-names = "ref",
1806                                       "ref_aux";
1807                         clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
1808                                  <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
1809
1810                         resets = <&ufs_mem_hc 0>;
1811                         reset-names = "ufsphy";
1812                         status = "disabled";
1813
1814                         ufs_mem_phy_lanes: phy@1d87400 {
1815                                 reg = <0 0x01d87400 0 0x108>,
1816                                       <0 0x01d87600 0 0x1e0>,
1817                                       <0 0x01d87c00 0 0x1dc>,
1818                                       <0 0x01d87800 0 0x108>,
1819                                       <0 0x01d87a00 0 0x1e0>;
1820                                 #phy-cells = <0>;
1821                         };
1822                 };
1823
1824                 ipa_virt: interconnect@1e00000 {
1825                         compatible = "qcom,sm8150-ipa-virt";
1826                         reg = <0 0x01e00000 0 0x1000>;
1827                         #interconnect-cells = <1>;
1828                         qcom,bcm-voters = <&apps_bcm_voter>;
1829                 };
1830
1831                 tcsr_mutex_regs: syscon@1f40000 {
1832                         compatible = "syscon";
1833                         reg = <0x0 0x01f40000 0x0 0x40000>;
1834                 };
1835
1836                 remoteproc_slpi: remoteproc@2400000 {
1837                         compatible = "qcom,sm8150-slpi-pas";
1838                         reg = <0x0 0x02400000 0x0 0x4040>;
1839
1840                         interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>,
1841                                               <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1842                                               <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1843                                               <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1844                                               <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1845                         interrupt-names = "wdog", "fatal", "ready",
1846                                           "handover", "stop-ack";
1847
1848                         clocks = <&rpmhcc RPMH_CXO_CLK>;
1849                         clock-names = "xo";
1850
1851                         power-domains = <&rpmhpd 3>,
1852                                         <&rpmhpd 2>;
1853                         power-domain-names = "lcx", "lmx";
1854
1855                         memory-region = <&slpi_mem>;
1856
1857                         qcom,qmp = <&aoss_qmp>;
1858
1859                         qcom,smem-states = <&slpi_smp2p_out 0>;
1860                         qcom,smem-state-names = "stop";
1861
1862                         status = "disabled";
1863
1864                         glink-edge {
1865                                 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>;
1866                                 label = "dsps";
1867                                 qcom,remote-pid = <3>;
1868                                 mboxes = <&apss_shared 24>;
1869
1870                                 fastrpc {
1871                                         compatible = "qcom,fastrpc";
1872                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
1873                                         label = "sdsp";
1874                                         qcom,non-secure-domain;
1875                                         #address-cells = <1>;
1876                                         #size-cells = <0>;
1877
1878                                         compute-cb@1 {
1879                                                 compatible = "qcom,fastrpc-compute-cb";
1880                                                 reg = <1>;
1881                                                 iommus = <&apps_smmu 0x05a1 0x0>;
1882                                         };
1883
1884                                         compute-cb@2 {
1885                                                 compatible = "qcom,fastrpc-compute-cb";
1886                                                 reg = <2>;
1887                                                 iommus = <&apps_smmu 0x05a2 0x0>;
1888                                         };
1889
1890                                         compute-cb@3 {
1891                                                 compatible = "qcom,fastrpc-compute-cb";
1892                                                 reg = <3>;
1893                                                 iommus = <&apps_smmu 0x05a3 0x0>;
1894                                                 /* note: shared-cb = <4> in downstream */
1895                                         };
1896                                 };
1897                         };
1898                 };
1899
1900                 gpu: gpu@2c00000 {
1901                         /*
1902                          * note: the amd,imageon compatible makes it possible
1903                          * to use the drm/msm driver without the display node,
1904                          * make sure to remove it when display node is added
1905                          */
1906                         compatible = "qcom,adreno-640.1",
1907                                      "qcom,adreno",
1908                                      "amd,imageon";
1909
1910                         reg = <0 0x02c00000 0 0x40000>;
1911                         reg-names = "kgsl_3d0_reg_memory";
1912
1913                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1914
1915                         iommus = <&adreno_smmu 0 0x401>;
1916
1917                         operating-points-v2 = <&gpu_opp_table>;
1918
1919                         qcom,gmu = <&gmu>;
1920
1921                         status = "disabled";
1922
1923                         zap-shader {
1924                                 memory-region = <&gpu_mem>;
1925                         };
1926
1927                         /* note: downstream checks gpu binning for 675 Mhz */
1928                         gpu_opp_table: opp-table {
1929                                 compatible = "operating-points-v2";
1930
1931                                 opp-675000000 {
1932                                         opp-hz = /bits/ 64 <675000000>;
1933                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1934                                 };
1935
1936                                 opp-585000000 {
1937                                         opp-hz = /bits/ 64 <585000000>;
1938                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1939                                 };
1940
1941                                 opp-499200000 {
1942                                         opp-hz = /bits/ 64 <499200000>;
1943                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
1944                                 };
1945
1946                                 opp-427000000 {
1947                                         opp-hz = /bits/ 64 <427000000>;
1948                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1949                                 };
1950
1951                                 opp-345000000 {
1952                                         opp-hz = /bits/ 64 <345000000>;
1953                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1954                                 };
1955
1956                                 opp-257000000 {
1957                                         opp-hz = /bits/ 64 <257000000>;
1958                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1959                                 };
1960                         };
1961                 };
1962
1963                 gmu: gmu@2c6a000 {
1964                         compatible="qcom,adreno-gmu-640.1", "qcom,adreno-gmu";
1965
1966                         reg = <0 0x02c6a000 0 0x30000>,
1967                               <0 0x0b290000 0 0x10000>,
1968                               <0 0x0b490000 0 0x10000>;
1969                         reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
1970
1971                         interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
1972                                      <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
1973                         interrupt-names = "hfi", "gmu";
1974
1975                         clocks = <&gpucc GPU_CC_AHB_CLK>,
1976                                  <&gpucc GPU_CC_CX_GMU_CLK>,
1977                                  <&gpucc GPU_CC_CXO_CLK>,
1978                                  <&gcc GCC_DDRSS_GPU_AXI_CLK>,
1979                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
1980                         clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
1981
1982                         power-domains = <&gpucc GPU_CX_GDSC>,
1983                                         <&gpucc GPU_GX_GDSC>;
1984                         power-domain-names = "cx", "gx";
1985
1986                         iommus = <&adreno_smmu 5 0x400>;
1987
1988                         operating-points-v2 = <&gmu_opp_table>;
1989
1990                         status = "disabled";
1991
1992                         gmu_opp_table: opp-table {
1993                                 compatible = "operating-points-v2";
1994
1995                                 opp-200000000 {
1996                                         opp-hz = /bits/ 64 <200000000>;
1997                                         opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1998                                 };
1999                         };
2000                 };
2001
2002                 gpucc: clock-controller@2c90000 {
2003                         compatible = "qcom,sm8150-gpucc";
2004                         reg = <0 0x02c90000 0 0x9000>;
2005                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2006                                  <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2007                                  <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2008                         clock-names = "bi_tcxo",
2009                                       "gcc_gpu_gpll0_clk_src",
2010                                       "gcc_gpu_gpll0_div_clk_src";
2011                         #clock-cells = <1>;
2012                         #reset-cells = <1>;
2013                         #power-domain-cells = <1>;
2014                 };
2015
2016                 adreno_smmu: iommu@2ca0000 {
2017                         compatible = "qcom,sm8150-smmu-500", "arm,mmu-500";
2018                         reg = <0 0x02ca0000 0 0x10000>;
2019                         #iommu-cells = <2>;
2020                         #global-interrupts = <1>;
2021                         interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
2022                                 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
2023                                 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
2024                                 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
2025                                 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
2026                                 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
2027                                 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
2028                                 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
2029                                 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>;
2030                         clocks = <&gpucc GPU_CC_AHB_CLK>,
2031                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2032                                  <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
2033                         clock-names = "ahb", "bus", "iface";
2034
2035                         power-domains = <&gpucc GPU_CX_GDSC>;
2036                 };
2037
2038                 tlmm: pinctrl@3100000 {
2039                         compatible = "qcom,sm8150-pinctrl";
2040                         reg = <0x0 0x03100000 0x0 0x300000>,
2041                               <0x0 0x03500000 0x0 0x300000>,
2042                               <0x0 0x03900000 0x0 0x300000>,
2043                               <0x0 0x03D00000 0x0 0x300000>;
2044                         reg-names = "west", "east", "north", "south";
2045                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2046                         gpio-ranges = <&tlmm 0 0 176>;
2047                         gpio-controller;
2048                         #gpio-cells = <2>;
2049                         interrupt-controller;
2050                         #interrupt-cells = <2>;
2051
2052                         qup_i2c0_default: qup-i2c0-default {
2053                                 mux {
2054                                         pins = "gpio0", "gpio1";
2055                                         function = "qup0";
2056                                 };
2057
2058                                 config {
2059                                         pins = "gpio0", "gpio1";
2060                                         drive-strength = <0x02>;
2061                                         bias-disable;
2062                                 };
2063                         };
2064
2065                         qup_spi0_default: qup-spi0-default {
2066                                 pins = "gpio0", "gpio1", "gpio2", "gpio3";
2067                                 function = "qup0";
2068                                 drive-strength = <6>;
2069                                 bias-disable;
2070                         };
2071
2072                         qup_i2c1_default: qup-i2c1-default {
2073                                 mux {
2074                                         pins = "gpio114", "gpio115";
2075                                         function = "qup1";
2076                                 };
2077
2078                                 config {
2079                                         pins = "gpio114", "gpio115";
2080                                         drive-strength = <0x02>;
2081                                         bias-disable;
2082                                 };
2083                         };
2084
2085                         qup_spi1_default: qup-spi1-default {
2086                                 pins = "gpio114", "gpio115", "gpio116", "gpio117";
2087                                 function = "qup1";
2088                                 drive-strength = <6>;
2089                                 bias-disable;
2090                         };
2091
2092                         qup_i2c2_default: qup-i2c2-default {
2093                                 mux {
2094                                         pins = "gpio126", "gpio127";
2095                                         function = "qup2";
2096                                 };
2097
2098                                 config {
2099                                         pins = "gpio126", "gpio127";
2100                                         drive-strength = <0x02>;
2101                                         bias-disable;
2102                                 };
2103                         };
2104
2105                         qup_spi2_default: qup-spi2-default {
2106                                 pins = "gpio126", "gpio127", "gpio128", "gpio129";
2107                                 function = "qup2";
2108                                 drive-strength = <6>;
2109                                 bias-disable;
2110                         };
2111
2112                         qup_i2c3_default: qup-i2c3-default {
2113                                 mux {
2114                                         pins = "gpio144", "gpio145";
2115                                         function = "qup3";
2116                                 };
2117
2118                                 config {
2119                                         pins = "gpio144", "gpio145";
2120                                         drive-strength = <0x02>;
2121                                         bias-disable;
2122                                 };
2123                         };
2124
2125                         qup_spi3_default: qup-spi3-default {
2126                                 pins = "gpio144", "gpio145", "gpio146", "gpio147";
2127                                 function = "qup3";
2128                                 drive-strength = <6>;
2129                                 bias-disable;
2130                         };
2131
2132                         qup_i2c4_default: qup-i2c4-default {
2133                                 mux {
2134                                         pins = "gpio51", "gpio52";
2135                                         function = "qup4";
2136                                 };
2137
2138                                 config {
2139                                         pins = "gpio51", "gpio52";
2140                                         drive-strength = <0x02>;
2141                                         bias-disable;
2142                                 };
2143                         };
2144
2145                         qup_spi4_default: qup-spi4-default {
2146                                 pins = "gpio51", "gpio52", "gpio53", "gpio54";
2147                                 function = "qup4";
2148                                 drive-strength = <6>;
2149                                 bias-disable;
2150                         };
2151
2152                         qup_i2c5_default: qup-i2c5-default {
2153                                 mux {
2154                                         pins = "gpio121", "gpio122";
2155                                         function = "qup5";
2156                                 };
2157
2158                                 config {
2159                                         pins = "gpio121", "gpio122";
2160                                         drive-strength = <0x02>;
2161                                         bias-disable;
2162                                 };
2163                         };
2164
2165                         qup_spi5_default: qup-spi5-default {
2166                                 pins = "gpio119", "gpio120", "gpio121", "gpio122";
2167                                 function = "qup5";
2168                                 drive-strength = <6>;
2169                                 bias-disable;
2170                         };
2171
2172                         qup_i2c6_default: qup-i2c6-default {
2173                                 mux {
2174                                         pins = "gpio6", "gpio7";
2175                                         function = "qup6";
2176                                 };
2177
2178                                 config {
2179                                         pins = "gpio6", "gpio7";
2180                                         drive-strength = <0x02>;
2181                                         bias-disable;
2182                                 };
2183                         };
2184
2185                         qup_spi6_default: qup-spi6_default {
2186                                 pins = "gpio4", "gpio5", "gpio6", "gpio7";
2187                                 function = "qup6";
2188                                 drive-strength = <6>;
2189                                 bias-disable;
2190                         };
2191
2192                         qup_i2c7_default: qup-i2c7-default {
2193                                 mux {
2194                                         pins = "gpio98", "gpio99";
2195                                         function = "qup7";
2196                                 };
2197
2198                                 config {
2199                                         pins = "gpio98", "gpio99";
2200                                         drive-strength = <0x02>;
2201                                         bias-disable;
2202                                 };
2203                         };
2204
2205                         qup_spi7_default: qup-spi7_default {
2206                                 pins = "gpio98", "gpio99", "gpio100", "gpio101";
2207                                 function = "qup7";
2208                                 drive-strength = <6>;
2209                                 bias-disable;
2210                         };
2211
2212                         qup_i2c8_default: qup-i2c8-default {
2213                                 mux {
2214                                         pins = "gpio88", "gpio89";
2215                                         function = "qup8";
2216                                 };
2217
2218                                 config {
2219                                         pins = "gpio88", "gpio89";
2220                                         drive-strength = <0x02>;
2221                                         bias-disable;
2222                                 };
2223                         };
2224
2225                         qup_spi8_default: qup-spi8-default {
2226                                 pins = "gpio88", "gpio89", "gpio90", "gpio91";
2227                                 function = "qup8";
2228                                 drive-strength = <6>;
2229                                 bias-disable;
2230                         };
2231
2232                         qup_i2c9_default: qup-i2c9-default {
2233                                 mux {
2234                                         pins = "gpio39", "gpio40";
2235                                         function = "qup9";
2236                                 };
2237
2238                                 config {
2239                                         pins = "gpio39", "gpio40";
2240                                         drive-strength = <0x02>;
2241                                         bias-disable;
2242                                 };
2243                         };
2244
2245                         qup_spi9_default: qup-spi9-default {
2246                                 pins = "gpio39", "gpio40", "gpio41", "gpio42";
2247                                 function = "qup9";
2248                                 drive-strength = <6>;
2249                                 bias-disable;
2250                         };
2251
2252                         qup_i2c10_default: qup-i2c10-default {
2253                                 mux {
2254                                         pins = "gpio9", "gpio10";
2255                                         function = "qup10";
2256                                 };
2257
2258                                 config {
2259                                         pins = "gpio9", "gpio10";
2260                                         drive-strength = <0x02>;
2261                                         bias-disable;
2262                                 };
2263                         };
2264
2265                         qup_spi10_default: qup-spi10-default {
2266                                 pins = "gpio9", "gpio10", "gpio11", "gpio12";
2267                                 function = "qup10";
2268                                 drive-strength = <6>;
2269                                 bias-disable;
2270                         };
2271
2272                         qup_i2c11_default: qup-i2c11-default {
2273                                 mux {
2274                                         pins = "gpio94", "gpio95";
2275                                         function = "qup11";
2276                                 };
2277
2278                                 config {
2279                                         pins = "gpio94", "gpio95";
2280                                         drive-strength = <0x02>;
2281                                         bias-disable;
2282                                 };
2283                         };
2284
2285                         qup_spi11_default: qup-spi11-default {
2286                                 pins = "gpio92", "gpio93", "gpio94", "gpio95";
2287                                 function = "qup11";
2288                                 drive-strength = <6>;
2289                                 bias-disable;
2290                         };
2291
2292                         qup_i2c12_default: qup-i2c12-default {
2293                                 mux {
2294                                         pins = "gpio83", "gpio84";
2295                                         function = "qup12";
2296                                 };
2297
2298                                 config {
2299                                         pins = "gpio83", "gpio84";
2300                                         drive-strength = <0x02>;
2301                                         bias-disable;
2302                                 };
2303                         };
2304
2305                         qup_spi12_default: qup-spi12-default {
2306                                 pins = "gpio83", "gpio84", "gpio85", "gpio86";
2307                                 function = "qup12";
2308                                 drive-strength = <6>;
2309                                 bias-disable;
2310                         };
2311
2312                         qup_i2c13_default: qup-i2c13-default {
2313                                 mux {
2314                                         pins = "gpio43", "gpio44";
2315                                         function = "qup13";
2316                                 };
2317
2318                                 config {
2319                                         pins = "gpio43", "gpio44";
2320                                         drive-strength = <0x02>;
2321                                         bias-disable;
2322                                 };
2323                         };
2324
2325                         qup_spi13_default: qup-spi13-default {
2326                                 pins = "gpio43", "gpio44", "gpio45", "gpio46";
2327                                 function = "qup13";
2328                                 drive-strength = <6>;
2329                                 bias-disable;
2330                         };
2331
2332                         qup_i2c14_default: qup-i2c14-default {
2333                                 mux {
2334                                         pins = "gpio47", "gpio48";
2335                                         function = "qup14";
2336                                 };
2337
2338                                 config {
2339                                         pins = "gpio47", "gpio48";
2340                                         drive-strength = <0x02>;
2341                                         bias-disable;
2342                                 };
2343                         };
2344
2345                         qup_spi14_default: qup-spi14-default {
2346                                 pins = "gpio47", "gpio48", "gpio49", "gpio50";
2347                                 function = "qup14";
2348                                 drive-strength = <6>;
2349                                 bias-disable;
2350                         };
2351
2352                         qup_i2c15_default: qup-i2c15-default {
2353                                 mux {
2354                                         pins = "gpio27", "gpio28";
2355                                         function = "qup15";
2356                                 };
2357
2358                                 config {
2359                                         pins = "gpio27", "gpio28";
2360                                         drive-strength = <0x02>;
2361                                         bias-disable;
2362                                 };
2363                         };
2364
2365                         qup_spi15_default: qup-spi15-default {
2366                                 pins = "gpio27", "gpio28", "gpio29", "gpio30";
2367                                 function = "qup15";
2368                                 drive-strength = <6>;
2369                                 bias-disable;
2370                         };
2371
2372                         qup_i2c16_default: qup-i2c16-default {
2373                                 mux {
2374                                         pins = "gpio86", "gpio85";
2375                                         function = "qup16";
2376                                 };
2377
2378                                 config {
2379                                         pins = "gpio86", "gpio85";
2380                                         drive-strength = <0x02>;
2381                                         bias-disable;
2382                                 };
2383                         };
2384
2385                         qup_spi16_default: qup-spi16-default {
2386                                 pins = "gpio83", "gpio84", "gpio85", "gpio86";
2387                                 function = "qup16";
2388                                 drive-strength = <6>;
2389                                 bias-disable;
2390                         };
2391
2392                         qup_i2c17_default: qup-i2c17-default {
2393                                 mux {
2394                                         pins = "gpio55", "gpio56";
2395                                         function = "qup17";
2396                                 };
2397
2398                                 config {
2399                                         pins = "gpio55", "gpio56";
2400                                         drive-strength = <0x02>;
2401                                         bias-disable;
2402                                 };
2403                         };
2404
2405                         qup_spi17_default: qup-spi17-default {
2406                                 pins = "gpio55", "gpio56", "gpio57", "gpio58";
2407                                 function = "qup17";
2408                                 drive-strength = <6>;
2409                                 bias-disable;
2410                         };
2411
2412                         qup_i2c18_default: qup-i2c18-default {
2413                                 mux {
2414                                         pins = "gpio23", "gpio24";
2415                                         function = "qup18";
2416                                 };
2417
2418                                 config {
2419                                         pins = "gpio23", "gpio24";
2420                                         drive-strength = <0x02>;
2421                                         bias-disable;
2422                                 };
2423                         };
2424
2425                         qup_spi18_default: qup-spi18-default {
2426                                 pins = "gpio23", "gpio24", "gpio25", "gpio26";
2427                                 function = "qup18";
2428                                 drive-strength = <6>;
2429                                 bias-disable;
2430                         };
2431
2432                         qup_i2c19_default: qup-i2c19-default {
2433                                 mux {
2434                                         pins = "gpio57", "gpio58";
2435                                         function = "qup19";
2436                                 };
2437
2438                                 config {
2439                                         pins = "gpio57", "gpio58";
2440                                         drive-strength = <0x02>;
2441                                         bias-disable;
2442                                 };
2443                         };
2444
2445                         qup_spi19_default: qup-spi19-default {
2446                                 pins = "gpio55", "gpio56", "gpio57", "gpio58";
2447                                 function = "qup19";
2448                                 drive-strength = <6>;
2449                                 bias-disable;
2450                         };
2451                 };
2452
2453                 remoteproc_mpss: remoteproc@4080000 {
2454                         compatible = "qcom,sm8150-mpss-pas";
2455                         reg = <0x0 0x04080000 0x0 0x4040>;
2456
2457                         interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2458                                               <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2459                                               <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2460                                               <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2461                                               <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2462                                               <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2463                         interrupt-names = "wdog", "fatal", "ready", "handover",
2464                                           "stop-ack", "shutdown-ack";
2465
2466                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2467                         clock-names = "xo";
2468
2469                         power-domains = <&rpmhpd 7>,
2470                                         <&rpmhpd 0>;
2471                         power-domain-names = "cx", "mss";
2472
2473                         memory-region = <&mpss_mem>;
2474
2475                         qcom,qmp = <&aoss_qmp>;
2476
2477                         qcom,smem-states = <&modem_smp2p_out 0>;
2478                         qcom,smem-state-names = "stop";
2479
2480                         status = "disabled";
2481
2482                         glink-edge {
2483                                 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
2484                                 label = "modem";
2485                                 qcom,remote-pid = <1>;
2486                                 mboxes = <&apss_shared 12>;
2487                         };
2488                 };
2489
2490                 stm@6002000 {
2491                         compatible = "arm,coresight-stm", "arm,primecell";
2492                         reg = <0 0x06002000 0 0x1000>,
2493                               <0 0x16280000 0 0x180000>;
2494                         reg-names = "stm-base", "stm-stimulus-base";
2495
2496                         clocks = <&aoss_qmp>;
2497                         clock-names = "apb_pclk";
2498
2499                         out-ports {
2500                                 port {
2501                                         stm_out: endpoint {
2502                                                 remote-endpoint = <&funnel0_in7>;
2503                                         };
2504                                 };
2505                         };
2506                 };
2507
2508                 funnel@6041000 {
2509                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2510                         reg = <0 0x06041000 0 0x1000>;
2511
2512                         clocks = <&aoss_qmp>;
2513                         clock-names = "apb_pclk";
2514
2515                         out-ports {
2516                                 port {
2517                                         funnel0_out: endpoint {
2518                                                 remote-endpoint = <&merge_funnel_in0>;
2519                                         };
2520                                 };
2521                         };
2522
2523                         in-ports {
2524                                 #address-cells = <1>;
2525                                 #size-cells = <0>;
2526
2527                                 port@7 {
2528                                         reg = <7>;
2529                                         funnel0_in7: endpoint {
2530                                                 remote-endpoint = <&stm_out>;
2531                                         };
2532                                 };
2533                         };
2534                 };
2535
2536                 funnel@6042000 {
2537                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2538                         reg = <0 0x06042000 0 0x1000>;
2539
2540                         clocks = <&aoss_qmp>;
2541                         clock-names = "apb_pclk";
2542
2543                         out-ports {
2544                                 port {
2545                                         funnel1_out: endpoint {
2546                                                 remote-endpoint = <&merge_funnel_in1>;
2547                                         };
2548                                 };
2549                         };
2550
2551                         in-ports {
2552                                 #address-cells = <1>;
2553                                 #size-cells = <0>;
2554
2555                                 port@4 {
2556                                         reg = <4>;
2557                                         funnel1_in4: endpoint {
2558                                                 remote-endpoint = <&swao_replicator_out>;
2559                                         };
2560                                 };
2561                         };
2562                 };
2563
2564                 funnel@6043000 {
2565                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2566                         reg = <0 0x06043000 0 0x1000>;
2567
2568                         clocks = <&aoss_qmp>;
2569                         clock-names = "apb_pclk";
2570
2571                         out-ports {
2572                                 port {
2573                                         funnel2_out: endpoint {
2574                                                 remote-endpoint = <&merge_funnel_in2>;
2575                                         };
2576                                 };
2577                         };
2578
2579                         in-ports {
2580                                 #address-cells = <1>;
2581                                 #size-cells = <0>;
2582
2583                                 port@2 {
2584                                         reg = <2>;
2585                                         funnel2_in2: endpoint {
2586                                                 remote-endpoint = <&apss_merge_funnel_out>;
2587                                         };
2588                                 };
2589                         };
2590                 };
2591
2592                 funnel@6045000 {
2593                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2594                         reg = <0 0x06045000 0 0x1000>;
2595
2596                         clocks = <&aoss_qmp>;
2597                         clock-names = "apb_pclk";
2598
2599                         out-ports {
2600                                 port {
2601                                         merge_funnel_out: endpoint {
2602                                                 remote-endpoint = <&etf_in>;
2603                                         };
2604                                 };
2605                         };
2606
2607                         in-ports {
2608                                 #address-cells = <1>;
2609                                 #size-cells = <0>;
2610
2611                                 port@0 {
2612                                         reg = <0>;
2613                                         merge_funnel_in0: endpoint {
2614                                                 remote-endpoint = <&funnel0_out>;
2615                                         };
2616                                 };
2617
2618                                 port@1 {
2619                                         reg = <1>;
2620                                         merge_funnel_in1: endpoint {
2621                                                 remote-endpoint = <&funnel1_out>;
2622                                         };
2623                                 };
2624
2625                                 port@2 {
2626                                         reg = <2>;
2627                                         merge_funnel_in2: endpoint {
2628                                                 remote-endpoint = <&funnel2_out>;
2629                                         };
2630                                 };
2631                         };
2632                 };
2633
2634                 replicator@6046000 {
2635                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2636                         reg = <0 0x06046000 0 0x1000>;
2637
2638                         clocks = <&aoss_qmp>;
2639                         clock-names = "apb_pclk";
2640
2641                         out-ports {
2642                                 #address-cells = <1>;
2643                                 #size-cells = <0>;
2644
2645                                 port@0 {
2646                                         reg = <0>;
2647                                         replicator_out0: endpoint {
2648                                                 remote-endpoint = <&etr_in>;
2649                                         };
2650                                 };
2651
2652                                 port@1 {
2653                                         reg = <1>;
2654                                         replicator_out1: endpoint {
2655                                                 remote-endpoint = <&replicator1_in>;
2656                                         };
2657                                 };
2658                         };
2659
2660                         in-ports {
2661                                 port {
2662                                         replicator_in0: endpoint {
2663                                                 remote-endpoint = <&etf_out>;
2664                                         };
2665                                 };
2666                         };
2667                 };
2668
2669                 etf@6047000 {
2670                         compatible = "arm,coresight-tmc", "arm,primecell";
2671                         reg = <0 0x06047000 0 0x1000>;
2672
2673                         clocks = <&aoss_qmp>;
2674                         clock-names = "apb_pclk";
2675
2676                         out-ports {
2677                                 port {
2678                                         etf_out: endpoint {
2679                                                 remote-endpoint = <&replicator_in0>;
2680                                         };
2681                                 };
2682                         };
2683
2684                         in-ports {
2685                                 port {
2686                                         etf_in: endpoint {
2687                                                 remote-endpoint = <&merge_funnel_out>;
2688                                         };
2689                                 };
2690                         };
2691                 };
2692
2693                 etr@6048000 {
2694                         compatible = "arm,coresight-tmc", "arm,primecell";
2695                         reg = <0 0x06048000 0 0x1000>;
2696                         iommus = <&apps_smmu 0x05e0 0x0>;
2697
2698                         clocks = <&aoss_qmp>;
2699                         clock-names = "apb_pclk";
2700                         arm,scatter-gather;
2701
2702                         in-ports {
2703                                 port {
2704                                         etr_in: endpoint {
2705                                                 remote-endpoint = <&replicator_out0>;
2706                                         };
2707                                 };
2708                         };
2709                 };
2710
2711                 replicator@604a000 {
2712                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2713                         reg = <0 0x0604a000 0 0x1000>;
2714
2715                         clocks = <&aoss_qmp>;
2716                         clock-names = "apb_pclk";
2717
2718                         out-ports {
2719                                 #address-cells = <1>;
2720                                 #size-cells = <0>;
2721
2722                                 port@1 {
2723                                         reg = <1>;
2724                                         replicator1_out: endpoint {
2725                                                 remote-endpoint = <&swao_funnel_in>;
2726                                         };
2727                                 };
2728                         };
2729
2730                         in-ports {
2731                                 #address-cells = <1>;
2732                                 #size-cells = <0>;
2733
2734                                 port@1 {
2735                                         reg = <1>;
2736                                         replicator1_in: endpoint {
2737                                                 remote-endpoint = <&replicator_out1>;
2738                                         };
2739                                 };
2740                         };
2741                 };
2742
2743                 funnel@6b08000 {
2744                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2745                         reg = <0 0x06b08000 0 0x1000>;
2746
2747                         clocks = <&aoss_qmp>;
2748                         clock-names = "apb_pclk";
2749
2750                         out-ports {
2751                                 port {
2752                                         swao_funnel_out: endpoint {
2753                                                 remote-endpoint = <&swao_etf_in>;
2754                                         };
2755                                 };
2756                         };
2757
2758                         in-ports {
2759                                 #address-cells = <1>;
2760                                 #size-cells = <0>;
2761
2762                                 port@6 {
2763                                         reg = <6>;
2764                                         swao_funnel_in: endpoint {
2765                                                 remote-endpoint = <&replicator1_out>;
2766                                         };
2767                                 };
2768                         };
2769                 };
2770
2771                 etf@6b09000 {
2772                         compatible = "arm,coresight-tmc", "arm,primecell";
2773                         reg = <0 0x06b09000 0 0x1000>;
2774
2775                         clocks = <&aoss_qmp>;
2776                         clock-names = "apb_pclk";
2777
2778                         out-ports {
2779                                 port {
2780                                         swao_etf_out: endpoint {
2781                                                 remote-endpoint = <&swao_replicator_in>;
2782                                         };
2783                                 };
2784                         };
2785
2786                         in-ports {
2787                                 port {
2788                                         swao_etf_in: endpoint {
2789                                                 remote-endpoint = <&swao_funnel_out>;
2790                                         };
2791                                 };
2792                         };
2793                 };
2794
2795                 replicator@6b0a000 {
2796                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2797                         reg = <0 0x06b0a000 0 0x1000>;
2798
2799                         clocks = <&aoss_qmp>;
2800                         clock-names = "apb_pclk";
2801                         qcom,replicator-loses-context;
2802
2803                         out-ports {
2804                                 port {
2805                                         swao_replicator_out: endpoint {
2806                                                 remote-endpoint = <&funnel1_in4>;
2807                                         };
2808                                 };
2809                         };
2810
2811                         in-ports {
2812                                 port {
2813                                         swao_replicator_in: endpoint {
2814                                                 remote-endpoint = <&swao_etf_out>;
2815                                         };
2816                                 };
2817                         };
2818                 };
2819
2820                 etm@7040000 {
2821                         compatible = "arm,coresight-etm4x", "arm,primecell";
2822                         reg = <0 0x07040000 0 0x1000>;
2823
2824                         cpu = <&CPU0>;
2825
2826                         clocks = <&aoss_qmp>;
2827                         clock-names = "apb_pclk";
2828                         arm,coresight-loses-context-with-cpu;
2829                         qcom,skip-power-up;
2830
2831                         out-ports {
2832                                 port {
2833                                         etm0_out: endpoint {
2834                                                 remote-endpoint = <&apss_funnel_in0>;
2835                                         };
2836                                 };
2837                         };
2838                 };
2839
2840                 etm@7140000 {
2841                         compatible = "arm,coresight-etm4x", "arm,primecell";
2842                         reg = <0 0x07140000 0 0x1000>;
2843
2844                         cpu = <&CPU1>;
2845
2846                         clocks = <&aoss_qmp>;
2847                         clock-names = "apb_pclk";
2848                         arm,coresight-loses-context-with-cpu;
2849                         qcom,skip-power-up;
2850
2851                         out-ports {
2852                                 port {
2853                                         etm1_out: endpoint {
2854                                                 remote-endpoint = <&apss_funnel_in1>;
2855                                         };
2856                                 };
2857                         };
2858                 };
2859
2860                 etm@7240000 {
2861                         compatible = "arm,coresight-etm4x", "arm,primecell";
2862                         reg = <0 0x07240000 0 0x1000>;
2863
2864                         cpu = <&CPU2>;
2865
2866                         clocks = <&aoss_qmp>;
2867                         clock-names = "apb_pclk";
2868                         arm,coresight-loses-context-with-cpu;
2869                         qcom,skip-power-up;
2870
2871                         out-ports {
2872                                 port {
2873                                         etm2_out: endpoint {
2874                                                 remote-endpoint = <&apss_funnel_in2>;
2875                                         };
2876                                 };
2877                         };
2878                 };
2879
2880                 etm@7340000 {
2881                         compatible = "arm,coresight-etm4x", "arm,primecell";
2882                         reg = <0 0x07340000 0 0x1000>;
2883
2884                         cpu = <&CPU3>;
2885
2886                         clocks = <&aoss_qmp>;
2887                         clock-names = "apb_pclk";
2888                         arm,coresight-loses-context-with-cpu;
2889                         qcom,skip-power-up;
2890
2891                         out-ports {
2892                                 port {
2893                                         etm3_out: endpoint {
2894                                                 remote-endpoint = <&apss_funnel_in3>;
2895                                         };
2896                                 };
2897                         };
2898                 };
2899
2900                 etm@7440000 {
2901                         compatible = "arm,coresight-etm4x", "arm,primecell";
2902                         reg = <0 0x07440000 0 0x1000>;
2903
2904                         cpu = <&CPU4>;
2905
2906                         clocks = <&aoss_qmp>;
2907                         clock-names = "apb_pclk";
2908                         arm,coresight-loses-context-with-cpu;
2909                         qcom,skip-power-up;
2910
2911                         out-ports {
2912                                 port {
2913                                         etm4_out: endpoint {
2914                                                 remote-endpoint = <&apss_funnel_in4>;
2915                                         };
2916                                 };
2917                         };
2918                 };
2919
2920                 etm@7540000 {
2921                         compatible = "arm,coresight-etm4x", "arm,primecell";
2922                         reg = <0 0x07540000 0 0x1000>;
2923
2924                         cpu = <&CPU5>;
2925
2926                         clocks = <&aoss_qmp>;
2927                         clock-names = "apb_pclk";
2928                         arm,coresight-loses-context-with-cpu;
2929                         qcom,skip-power-up;
2930
2931                         out-ports {
2932                                 port {
2933                                         etm5_out: endpoint {
2934                                                 remote-endpoint = <&apss_funnel_in5>;
2935                                         };
2936                                 };
2937                         };
2938                 };
2939
2940                 etm@7640000 {
2941                         compatible = "arm,coresight-etm4x", "arm,primecell";
2942                         reg = <0 0x07640000 0 0x1000>;
2943
2944                         cpu = <&CPU6>;
2945
2946                         clocks = <&aoss_qmp>;
2947                         clock-names = "apb_pclk";
2948                         arm,coresight-loses-context-with-cpu;
2949                         qcom,skip-power-up;
2950
2951                         out-ports {
2952                                 port {
2953                                         etm6_out: endpoint {
2954                                                 remote-endpoint = <&apss_funnel_in6>;
2955                                         };
2956                                 };
2957                         };
2958                 };
2959
2960                 etm@7740000 {
2961                         compatible = "arm,coresight-etm4x", "arm,primecell";
2962                         reg = <0 0x07740000 0 0x1000>;
2963
2964                         cpu = <&CPU7>;
2965
2966                         clocks = <&aoss_qmp>;
2967                         clock-names = "apb_pclk";
2968                         arm,coresight-loses-context-with-cpu;
2969                         qcom,skip-power-up;
2970
2971                         out-ports {
2972                                 port {
2973                                         etm7_out: endpoint {
2974                                                 remote-endpoint = <&apss_funnel_in7>;
2975                                         };
2976                                 };
2977                         };
2978                 };
2979
2980                 funnel@7800000 { /* APSS Funnel */
2981                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2982                         reg = <0 0x07800000 0 0x1000>;
2983
2984                         clocks = <&aoss_qmp>;
2985                         clock-names = "apb_pclk";
2986
2987                         out-ports {
2988                                 port {
2989                                         apss_funnel_out: endpoint {
2990                                                 remote-endpoint = <&apss_merge_funnel_in>;
2991                                         };
2992                                 };
2993                         };
2994
2995                         in-ports {
2996                                 #address-cells = <1>;
2997                                 #size-cells = <0>;
2998
2999                                 port@0 {
3000                                         reg = <0>;
3001                                         apss_funnel_in0: endpoint {
3002                                                 remote-endpoint = <&etm0_out>;
3003                                         };
3004                                 };
3005
3006                                 port@1 {
3007                                         reg = <1>;
3008                                         apss_funnel_in1: endpoint {
3009                                                 remote-endpoint = <&etm1_out>;
3010                                         };
3011                                 };
3012
3013                                 port@2 {
3014                                         reg = <2>;
3015                                         apss_funnel_in2: endpoint {
3016                                                 remote-endpoint = <&etm2_out>;
3017                                         };
3018                                 };
3019
3020                                 port@3 {
3021                                         reg = <3>;
3022                                         apss_funnel_in3: endpoint {
3023                                                 remote-endpoint = <&etm3_out>;
3024                                         };
3025                                 };
3026
3027                                 port@4 {
3028                                         reg = <4>;
3029                                         apss_funnel_in4: endpoint {
3030                                                 remote-endpoint = <&etm4_out>;
3031                                         };
3032                                 };
3033
3034                                 port@5 {
3035                                         reg = <5>;
3036                                         apss_funnel_in5: endpoint {
3037                                                 remote-endpoint = <&etm5_out>;
3038                                         };
3039                                 };
3040
3041                                 port@6 {
3042                                         reg = <6>;
3043                                         apss_funnel_in6: endpoint {
3044                                                 remote-endpoint = <&etm6_out>;
3045                                         };
3046                                 };
3047
3048                                 port@7 {
3049                                         reg = <7>;
3050                                         apss_funnel_in7: endpoint {
3051                                                 remote-endpoint = <&etm7_out>;
3052                                         };
3053                                 };
3054                         };
3055                 };
3056
3057                 funnel@7810000 {
3058                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3059                         reg = <0 0x07810000 0 0x1000>;
3060
3061                         clocks = <&aoss_qmp>;
3062                         clock-names = "apb_pclk";
3063
3064                         out-ports {
3065                                 port {
3066                                         apss_merge_funnel_out: endpoint {
3067                                                 remote-endpoint = <&funnel2_in2>;
3068                                         };
3069                                 };
3070                         };
3071
3072                         in-ports {
3073                                 port {
3074                                         apss_merge_funnel_in: endpoint {
3075                                                 remote-endpoint = <&apss_funnel_out>;
3076                                         };
3077                                 };
3078                         };
3079                 };
3080
3081                 remoteproc_cdsp: remoteproc@8300000 {
3082                         compatible = "qcom,sm8150-cdsp-pas";
3083                         reg = <0x0 0x08300000 0x0 0x4040>;
3084
3085                         interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
3086                                               <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3087                                               <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3088                                               <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3089                                               <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3090                         interrupt-names = "wdog", "fatal", "ready",
3091                                           "handover", "stop-ack";
3092
3093                         clocks = <&rpmhcc RPMH_CXO_CLK>;
3094                         clock-names = "xo";
3095
3096                         power-domains = <&rpmhpd 7>;
3097
3098                         memory-region = <&cdsp_mem>;
3099
3100                         qcom,qmp = <&aoss_qmp>;
3101
3102                         qcom,smem-states = <&cdsp_smp2p_out 0>;
3103                         qcom,smem-state-names = "stop";
3104
3105                         status = "disabled";
3106
3107                         glink-edge {
3108                                 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
3109                                 label = "cdsp";
3110                                 qcom,remote-pid = <5>;
3111                                 mboxes = <&apss_shared 4>;
3112
3113                                 fastrpc {
3114                                         compatible = "qcom,fastrpc";
3115                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
3116                                         label = "cdsp";
3117                                         qcom,non-secure-domain;
3118                                         #address-cells = <1>;
3119                                         #size-cells = <0>;
3120
3121                                         compute-cb@1 {
3122                                                 compatible = "qcom,fastrpc-compute-cb";
3123                                                 reg = <1>;
3124                                                 iommus = <&apps_smmu 0x1401 0x2040>,
3125                                                          <&apps_smmu 0x1421 0x0>,
3126                                                          <&apps_smmu 0x2001 0x420>,
3127                                                          <&apps_smmu 0x2041 0x0>;
3128                                         };
3129
3130                                         compute-cb@2 {
3131                                                 compatible = "qcom,fastrpc-compute-cb";
3132                                                 reg = <2>;
3133                                                 iommus = <&apps_smmu 0x2 0x3440>,
3134                                                          <&apps_smmu 0x22 0x3400>;
3135                                         };
3136
3137                                         compute-cb@3 {
3138                                                 compatible = "qcom,fastrpc-compute-cb";
3139                                                 reg = <3>;
3140                                                 iommus = <&apps_smmu 0x3 0x3440>,
3141                                                          <&apps_smmu 0x1423 0x0>,
3142                                                          <&apps_smmu 0x2023 0x0>;
3143                                         };
3144
3145                                         compute-cb@4 {
3146                                                 compatible = "qcom,fastrpc-compute-cb";
3147                                                 reg = <4>;
3148                                                 iommus = <&apps_smmu 0x4 0x3440>,
3149                                                          <&apps_smmu 0x24 0x3400>;
3150                                         };
3151
3152                                         compute-cb@5 {
3153                                                 compatible = "qcom,fastrpc-compute-cb";
3154                                                 reg = <5>;
3155                                                 iommus = <&apps_smmu 0x5 0x3440>,
3156                                                          <&apps_smmu 0x25 0x3400>;
3157                                         };
3158
3159                                         compute-cb@6 {
3160                                                 compatible = "qcom,fastrpc-compute-cb";
3161                                                 reg = <6>;
3162                                                 iommus = <&apps_smmu 0x6 0x3460>;
3163                                         };
3164
3165                                         compute-cb@7 {
3166                                                 compatible = "qcom,fastrpc-compute-cb";
3167                                                 reg = <7>;
3168                                                 iommus = <&apps_smmu 0x7 0x3460>;
3169                                         };
3170
3171                                         compute-cb@8 {
3172                                                 compatible = "qcom,fastrpc-compute-cb";
3173                                                 reg = <8>;
3174                                                 iommus = <&apps_smmu 0x8 0x3460>;
3175                                         };
3176
3177                                         /* note: secure cb9 in downstream */
3178                                 };
3179                         };
3180                 };
3181
3182                 usb_1_hsphy: phy@88e2000 {
3183                         compatible = "qcom,sm8150-usb-hs-phy",
3184                                      "qcom,usb-snps-hs-7nm-phy";
3185                         reg = <0 0x088e2000 0 0x400>;
3186                         status = "disabled";
3187                         #phy-cells = <0>;
3188
3189                         clocks = <&rpmhcc RPMH_CXO_CLK>;
3190                         clock-names = "ref";
3191
3192                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3193                 };
3194
3195                 usb_2_hsphy: phy@88e3000 {
3196                         compatible = "qcom,sm8150-usb-hs-phy",
3197                                      "qcom,usb-snps-hs-7nm-phy";
3198                         reg = <0 0x088e3000 0 0x400>;
3199                         status = "disabled";
3200                         #phy-cells = <0>;
3201
3202                         clocks = <&rpmhcc RPMH_CXO_CLK>;
3203                         clock-names = "ref";
3204
3205                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3206                 };
3207
3208                 usb_1_qmpphy: phy@88e9000 {
3209                         compatible = "qcom,sm8150-qmp-usb3-phy";
3210                         reg = <0 0x088e9000 0 0x18c>,
3211                               <0 0x088e8000 0 0x10>;
3212                         status = "disabled";
3213                         #address-cells = <2>;
3214                         #size-cells = <2>;
3215                         ranges;
3216
3217                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3218                                  <&rpmhcc RPMH_CXO_CLK>,
3219                                  <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
3220                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
3221                         clock-names = "aux", "ref_clk_src", "ref", "com_aux";
3222
3223                         resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
3224                                  <&gcc GCC_USB3_PHY_PRIM_BCR>;
3225                         reset-names = "phy", "common";
3226
3227                         usb_1_ssphy: phy@88e9200 {
3228                                 reg = <0 0x088e9200 0 0x200>,
3229                                       <0 0x088e9400 0 0x200>,
3230                                       <0 0x088e9c00 0 0x218>,
3231                                       <0 0x088e9600 0 0x200>,
3232                                       <0 0x088e9800 0 0x200>,
3233                                       <0 0x088e9a00 0 0x100>;
3234                                 #clock-cells = <0>;
3235                                 #phy-cells = <0>;
3236                                 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3237                                 clock-names = "pipe0";
3238                                 clock-output-names = "usb3_phy_pipe_clk_src";
3239                         };
3240                 };
3241
3242                 usb_2_qmpphy: phy@88eb000 {
3243                         compatible = "qcom,sm8150-qmp-usb3-uni-phy";
3244                         reg = <0 0x088eb000 0 0x200>;
3245                         status = "disabled";
3246                         #address-cells = <2>;
3247                         #size-cells = <2>;
3248                         ranges;
3249
3250                         clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
3251                                  <&rpmhcc RPMH_CXO_CLK>,
3252                                  <&gcc GCC_USB3_SEC_CLKREF_CLK>,
3253                                  <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
3254                         clock-names = "aux", "ref_clk_src", "ref", "com_aux";
3255
3256                         resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
3257                                  <&gcc GCC_USB3_PHY_SEC_BCR>;
3258                         reset-names = "phy", "common";
3259
3260                         usb_2_ssphy: phy@88eb200 {
3261                                 reg = <0 0x088eb200 0 0x200>,
3262                                       <0 0x088eb400 0 0x200>,
3263                                       <0 0x088eb800 0 0x800>,
3264                                       <0 0x088eb600 0 0x200>;
3265                                 #clock-cells = <0>;
3266                                 #phy-cells = <0>;
3267                                 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
3268                                 clock-names = "pipe0";
3269                                 clock-output-names = "usb3_uni_phy_pipe_clk_src";
3270                         };
3271                 };
3272
3273                 dc_noc: interconnect@9160000 {
3274                         compatible = "qcom,sm8150-dc-noc";
3275                         reg = <0 0x09160000 0 0x3200>;
3276                         #interconnect-cells = <1>;
3277                         qcom,bcm-voters = <&apps_bcm_voter>;
3278                 };
3279
3280                 gem_noc: interconnect@9680000 {
3281                         compatible = "qcom,sm8150-gem-noc";
3282                         reg = <0 0x09680000 0 0x3e200>;
3283                         #interconnect-cells = <1>;
3284                         qcom,bcm-voters = <&apps_bcm_voter>;
3285                 };
3286
3287                 usb_1: usb@a6f8800 {
3288                         compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
3289                         reg = <0 0x0a6f8800 0 0x400>;
3290                         status = "disabled";
3291                         #address-cells = <2>;
3292                         #size-cells = <2>;
3293                         ranges;
3294                         dma-ranges;
3295
3296                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3297                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3298                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3299                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3300                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
3301                                  <&gcc GCC_USB3_SEC_CLKREF_CLK>;
3302                         clock-names = "cfg_noc", "core", "iface", "mock_utmi",
3303                                       "sleep", "xo";
3304
3305                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3306                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3307                         assigned-clock-rates = <19200000>, <200000000>;
3308
3309                         interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3310                                      <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
3311                                      <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
3312                                      <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
3313                         interrupt-names = "hs_phy_irq", "ss_phy_irq",
3314                                           "dm_hs_phy_irq", "dp_hs_phy_irq";
3315
3316                         power-domains = <&gcc USB30_PRIM_GDSC>;
3317
3318                         resets = <&gcc GCC_USB30_PRIM_BCR>;
3319
3320                         usb_1_dwc3: dwc3@a600000 {
3321                                 compatible = "snps,dwc3";
3322                                 reg = <0 0x0a600000 0 0xcd00>;
3323                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3324                                 iommus = <&apps_smmu 0x140 0>;
3325                                 snps,dis_u2_susphy_quirk;
3326                                 snps,dis_enblslpm_quirk;
3327                                 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
3328                                 phy-names = "usb2-phy", "usb3-phy";
3329                         };
3330                 };
3331
3332                 usb_2: usb@a8f8800 {
3333                         compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
3334                         reg = <0 0x0a8f8800 0 0x400>;
3335                         status = "disabled";
3336                         #address-cells = <2>;
3337                         #size-cells = <2>;
3338                         ranges;
3339                         dma-ranges;
3340
3341                         clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
3342                                  <&gcc GCC_USB30_SEC_MASTER_CLK>,
3343                                  <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
3344                                  <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3345                                  <&gcc GCC_USB30_SEC_SLEEP_CLK>,
3346                                  <&gcc GCC_USB3_SEC_CLKREF_CLK>;
3347                         clock-names = "cfg_noc", "core", "iface", "mock_utmi",
3348                                       "sleep", "xo";
3349
3350                         assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3351                                           <&gcc GCC_USB30_SEC_MASTER_CLK>;
3352                         assigned-clock-rates = <19200000>, <200000000>;
3353
3354                         interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
3355                                      <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
3356                                      <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
3357                                      <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
3358                         interrupt-names = "hs_phy_irq", "ss_phy_irq",
3359                                           "dm_hs_phy_irq", "dp_hs_phy_irq";
3360
3361                         power-domains = <&gcc USB30_SEC_GDSC>;
3362
3363                         resets = <&gcc GCC_USB30_SEC_BCR>;
3364
3365                         usb_2_dwc3: usb@a800000 {
3366                                 compatible = "snps,dwc3";
3367                                 reg = <0 0x0a800000 0 0xcd00>;
3368                                 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
3369                                 iommus = <&apps_smmu 0x160 0>;
3370                                 snps,dis_u2_susphy_quirk;
3371                                 snps,dis_enblslpm_quirk;
3372                                 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
3373                                 phy-names = "usb2-phy", "usb3-phy";
3374                         };
3375                 };
3376
3377                 camnoc_virt: interconnect@ac00000 {
3378                         compatible = "qcom,sm8150-camnoc-virt";
3379                         reg = <0 0x0ac00000 0 0x1000>;
3380                         #interconnect-cells = <1>;
3381                         qcom,bcm-voters = <&apps_bcm_voter>;
3382                 };
3383
3384                 aoss_qmp: power-controller@c300000 {
3385                         compatible = "qcom,sm8150-aoss-qmp";
3386                         reg = <0x0 0x0c300000 0x0 0x400>;
3387                         interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
3388                         mboxes = <&apss_shared 0>;
3389
3390                         #clock-cells = <0>;
3391                 };
3392
3393                 sram@c3f0000 {
3394                         compatible = "qcom,rpmh-stats";
3395                         reg = <0 0x0c3f0000 0 0x400>;
3396                 };
3397
3398                 tsens0: thermal-sensor@c263000 {
3399                         compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
3400                         reg = <0 0x0c263000 0 0x1ff>, /* TM */
3401                               <0 0x0c222000 0 0x1ff>; /* SROT */
3402                         #qcom,sensors = <16>;
3403                         interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3404                                      <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
3405                         interrupt-names = "uplow", "critical";
3406                         #thermal-sensor-cells = <1>;
3407                 };
3408
3409                 tsens1: thermal-sensor@c265000 {
3410                         compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
3411                         reg = <0 0x0c265000 0 0x1ff>, /* TM */
3412                               <0 0x0c223000 0 0x1ff>; /* SROT */
3413                         #qcom,sensors = <8>;
3414                         interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
3415                                      <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
3416                         interrupt-names = "uplow", "critical";
3417                         #thermal-sensor-cells = <1>;
3418                 };
3419
3420                 spmi_bus: spmi@c440000 {
3421                         compatible = "qcom,spmi-pmic-arb";
3422                         reg = <0x0 0x0c440000 0x0 0x0001100>,
3423                               <0x0 0x0c600000 0x0 0x2000000>,
3424                               <0x0 0x0e600000 0x0 0x0100000>,
3425                               <0x0 0x0e700000 0x0 0x00a0000>,
3426                               <0x0 0x0c40a000 0x0 0x0026000>;
3427                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3428                         interrupt-names = "periph_irq";
3429                         interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
3430                         qcom,ee = <0>;
3431                         qcom,channel = <0>;
3432                         #address-cells = <2>;
3433                         #size-cells = <0>;
3434                         interrupt-controller;
3435                         #interrupt-cells = <4>;
3436                         cell-index = <0>;
3437                 };
3438
3439                 apps_smmu: iommu@15000000 {
3440                         compatible = "qcom,sm8150-smmu-500", "arm,mmu-500";
3441                         reg = <0 0x15000000 0 0x100000>;
3442                         #iommu-cells = <2>;
3443                         #global-interrupts = <1>;
3444                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
3445                                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
3446                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
3447                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
3448                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
3449                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
3450                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3451                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3452                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3453                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3454                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3455                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3456                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3457                                      <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3458                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3459                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3460                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3461                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3462                                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3463                                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3464                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3465                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3466                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3467                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3468                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3469                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3470                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3471                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3472                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3473                                      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3474                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3475                                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3476                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3477                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3478                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3479                                      <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3480                                      <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3481                                      <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3482                                      <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3483                                      <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3484                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3485                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3486                                      <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3487                                      <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3488                                      <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3489                                      <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3490                                      <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3491                                      <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3492                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3493                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3494                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3495                                      <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3496                                      <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3497                                      <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3498                                      <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3499                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3500                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3501                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3502                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3503                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3504                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3505                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3506                                      <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3507                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
3508                                      <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
3509                                      <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
3510                                      <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
3511                                      <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
3512                                      <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
3513                                      <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
3514                                      <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
3515                                      <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
3516                                      <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
3517                                      <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
3518                                      <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
3519                                      <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
3520                                      <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
3521                                      <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
3522                                      <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
3523                                      <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
3524                                      <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
3525                 };
3526
3527                 remoteproc_adsp: remoteproc@17300000 {
3528                         compatible = "qcom,sm8150-adsp-pas";
3529                         reg = <0x0 0x17300000 0x0 0x4040>;
3530
3531                         interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
3532                                               <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3533                                               <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3534                                               <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3535                                               <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3536                         interrupt-names = "wdog", "fatal", "ready",
3537                                           "handover", "stop-ack";
3538
3539                         clocks = <&rpmhcc RPMH_CXO_CLK>;
3540                         clock-names = "xo";
3541
3542                         power-domains = <&rpmhpd 7>;
3543
3544                         memory-region = <&adsp_mem>;
3545
3546                         qcom,qmp = <&aoss_qmp>;
3547
3548                         qcom,smem-states = <&adsp_smp2p_out 0>;
3549                         qcom,smem-state-names = "stop";
3550
3551                         status = "disabled";
3552
3553                         glink-edge {
3554                                 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
3555                                 label = "lpass";
3556                                 qcom,remote-pid = <2>;
3557                                 mboxes = <&apss_shared 8>;
3558
3559                                 fastrpc {
3560                                         compatible = "qcom,fastrpc";
3561                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
3562                                         label = "adsp";
3563                                         qcom,non-secure-domain;
3564                                         #address-cells = <1>;
3565                                         #size-cells = <0>;
3566
3567                                         compute-cb@3 {
3568                                                 compatible = "qcom,fastrpc-compute-cb";
3569                                                 reg = <3>;
3570                                                 iommus = <&apps_smmu 0x1b23 0x0>;
3571                                         };
3572
3573                                         compute-cb@4 {
3574                                                 compatible = "qcom,fastrpc-compute-cb";
3575                                                 reg = <4>;
3576                                                 iommus = <&apps_smmu 0x1b24 0x0>;
3577                                         };
3578
3579                                         compute-cb@5 {
3580                                                 compatible = "qcom,fastrpc-compute-cb";
3581                                                 reg = <5>;
3582                                                 iommus = <&apps_smmu 0x1b25 0x0>;
3583                                         };
3584                                 };
3585                         };
3586                 };
3587
3588                 intc: interrupt-controller@17a00000 {
3589                         compatible = "arm,gic-v3";
3590                         interrupt-controller;
3591                         #interrupt-cells = <3>;
3592                         reg = <0x0 0x17a00000 0x0 0x10000>,     /* GICD */
3593                               <0x0 0x17a60000 0x0 0x100000>;    /* GICR * 8 */
3594                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3595                 };
3596
3597                 apss_shared: mailbox@17c00000 {
3598                         compatible = "qcom,sm8150-apss-shared";
3599                         reg = <0x0 0x17c00000 0x0 0x1000>;
3600                         #mbox-cells = <1>;
3601                 };
3602
3603                 watchdog@17c10000 {
3604                         compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt";
3605                         reg = <0 0x17c10000 0 0x1000>;
3606                         clocks = <&sleep_clk>;
3607                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
3608                 };
3609
3610                 timer@17c20000 {
3611                         #address-cells = <2>;
3612                         #size-cells = <2>;
3613                         ranges;
3614                         compatible = "arm,armv7-timer-mem";
3615                         reg = <0x0 0x17c20000 0x0 0x1000>;
3616                         clock-frequency = <19200000>;
3617
3618                         frame@17c21000{
3619                                 frame-number = <0>;
3620                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3621                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
3622                                 reg = <0x0 0x17c21000 0x0 0x1000>,
3623                                       <0x0 0x17c22000 0x0 0x1000>;
3624                         };
3625
3626                         frame@17c23000 {
3627                                 frame-number = <1>;
3628                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3629                                 reg = <0x0 0x17c23000 0x0 0x1000>;
3630                                 status = "disabled";
3631                         };
3632
3633                         frame@17c25000 {
3634                                 frame-number = <2>;
3635                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3636                                 reg = <0x0 0x17c25000 0x0 0x1000>;
3637                                 status = "disabled";
3638                         };
3639
3640                         frame@17c27000 {
3641                                 frame-number = <3>;
3642                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3643                                 reg = <0x0 0x17c26000 0x0 0x1000>;
3644                                 status = "disabled";
3645                         };
3646
3647                         frame@17c29000 {
3648                                 frame-number = <4>;
3649                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3650                                 reg = <0x0 0x17c29000 0x0 0x1000>;
3651                                 status = "disabled";
3652                         };
3653
3654                         frame@17c2b000 {
3655                                 frame-number = <5>;
3656                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3657                                 reg = <0x0 0x17c2b000 0x0 0x1000>;
3658                                 status = "disabled";
3659                         };
3660
3661                         frame@17c2d000 {
3662                                 frame-number = <6>;
3663                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3664                                 reg = <0x0 0x17c2d000 0x0 0x1000>;
3665                                 status = "disabled";
3666                         };
3667                 };
3668
3669                 apps_rsc: rsc@18200000 {
3670                         label = "apps_rsc";
3671                         compatible = "qcom,rpmh-rsc";
3672                         reg = <0x0 0x18200000 0x0 0x10000>,
3673                               <0x0 0x18210000 0x0 0x10000>,
3674                               <0x0 0x18220000 0x0 0x10000>;
3675                         reg-names = "drv-0", "drv-1", "drv-2";
3676                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
3677                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
3678                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
3679                         qcom,tcs-offset = <0xd00>;
3680                         qcom,drv-id = <2>;
3681                         qcom,tcs-config = <ACTIVE_TCS  2>,
3682                                           <SLEEP_TCS   3>,
3683                                           <WAKE_TCS    3>,
3684                                           <CONTROL_TCS 1>;
3685
3686                         rpmhcc: clock-controller {
3687                                 compatible = "qcom,sm8150-rpmh-clk";
3688                                 #clock-cells = <1>;
3689                                 clock-names = "xo";
3690                                 clocks = <&xo_board>;
3691                         };
3692
3693                         rpmhpd: power-controller {
3694                                 compatible = "qcom,sm8150-rpmhpd";
3695                                 #power-domain-cells = <1>;
3696                                 operating-points-v2 = <&rpmhpd_opp_table>;
3697
3698                                 rpmhpd_opp_table: opp-table {
3699                                         compatible = "operating-points-v2";
3700
3701                                         rpmhpd_opp_ret: opp1 {
3702                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3703                                         };
3704
3705                                         rpmhpd_opp_min_svs: opp2 {
3706                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3707                                         };
3708
3709                                         rpmhpd_opp_low_svs: opp3 {
3710                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3711                                         };
3712
3713                                         rpmhpd_opp_svs: opp4 {
3714                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3715                                         };
3716
3717                                         rpmhpd_opp_svs_l1: opp5 {
3718                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3719                                         };
3720
3721                                         rpmhpd_opp_svs_l2: opp6 {
3722                                                 opp-level = <224>;
3723                                         };
3724
3725                                         rpmhpd_opp_nom: opp7 {
3726                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3727                                         };
3728
3729                                         rpmhpd_opp_nom_l1: opp8 {
3730                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3731                                         };
3732
3733                                         rpmhpd_opp_nom_l2: opp9 {
3734                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3735                                         };
3736
3737                                         rpmhpd_opp_turbo: opp10 {
3738                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3739                                         };
3740
3741                                         rpmhpd_opp_turbo_l1: opp11 {
3742                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3743                                         };
3744                                 };
3745                         };
3746
3747                         apps_bcm_voter: bcm_voter {
3748                                 compatible = "qcom,bcm-voter";
3749                         };
3750                 };
3751
3752                 osm_l3: interconnect@18321000 {
3753                         compatible = "qcom,sm8150-osm-l3";
3754                         reg = <0 0x18321000 0 0x1400>;
3755
3756                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3757                         clock-names = "xo", "alternate";
3758
3759                         #interconnect-cells = <1>;
3760                 };
3761
3762                 cpufreq_hw: cpufreq@18323000 {
3763                         compatible = "qcom,cpufreq-hw";
3764                         reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>,
3765                               <0 0x18327800 0 0x1400>;
3766                         reg-names = "freq-domain0", "freq-domain1",
3767                                     "freq-domain2";
3768
3769                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3770                         clock-names = "xo", "alternate";
3771
3772                         #freq-domain-cells = <1>;
3773                 };
3774
3775                 lmh_cluster1: lmh@18350800 {
3776                         compatible = "qcom,sm8150-lmh";
3777                         reg = <0 0x18350800 0 0x400>;
3778                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
3779                         cpus = <&CPU4>;
3780                         qcom,lmh-temp-arm-millicelsius = <60000>;
3781                         qcom,lmh-temp-low-millicelsius = <84500>;
3782                         qcom,lmh-temp-high-millicelsius = <85000>;
3783                         interrupt-controller;
3784                         #interrupt-cells = <1>;
3785                 };
3786
3787                 lmh_cluster0: lmh@18358800 {
3788                         compatible = "qcom,sm8150-lmh";
3789                         reg = <0 0x18358800 0 0x400>;
3790                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
3791                         cpus = <&CPU0>;
3792                         qcom,lmh-temp-arm-millicelsius = <60000>;
3793                         qcom,lmh-temp-low-millicelsius = <84500>;
3794                         qcom,lmh-temp-high-millicelsius = <85000>;
3795                         interrupt-controller;
3796                         #interrupt-cells = <1>;
3797                 };
3798
3799                 wifi: wifi@18800000 {
3800                         compatible = "qcom,wcn3990-wifi";
3801                         reg = <0 0x18800000 0 0x800000>;
3802                         reg-names = "membase";
3803                         memory-region = <&wlan_mem>;
3804                         clock-names = "cxo_ref_clk_pin", "qdss";
3805                         clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>;
3806                         interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
3807                                      <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
3808                                      <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
3809                                      <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
3810                                      <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
3811                                      <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
3812                                      <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
3813                                      <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
3814                                      <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
3815                                      <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
3816                                      <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
3817                                      <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
3818                         iommus = <&apps_smmu 0x0640 0x1>;
3819                         status = "disabled";
3820                 };
3821         };
3822
3823         timer {
3824                 compatible = "arm,armv8-timer";
3825                 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
3826                              <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
3827                              <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
3828                              <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
3829         };
3830
3831         thermal-zones {
3832                 cpu0-thermal {
3833                         polling-delay-passive = <250>;
3834                         polling-delay = <1000>;
3835
3836                         thermal-sensors = <&tsens0 1>;
3837
3838                         trips {
3839                                 cpu0_alert0: trip-point0 {
3840                                         temperature = <90000>;
3841                                         hysteresis = <2000>;
3842                                         type = "passive";
3843                                 };
3844
3845                                 cpu0_alert1: trip-point1 {
3846                                         temperature = <95000>;
3847                                         hysteresis = <2000>;
3848                                         type = "passive";
3849                                 };
3850
3851                                 cpu0_crit: cpu_crit {
3852                                         temperature = <110000>;
3853                                         hysteresis = <1000>;
3854                                         type = "critical";
3855                                 };
3856                         };
3857
3858                         cooling-maps {
3859                                 map0 {
3860                                         trip = <&cpu0_alert0>;
3861                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3862                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3863                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3864                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3865                                 };
3866                                 map1 {
3867                                         trip = <&cpu0_alert1>;
3868                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3869                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3870                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3871                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3872                                 };
3873                         };
3874                 };
3875
3876                 cpu1-thermal {
3877                         polling-delay-passive = <250>;
3878                         polling-delay = <1000>;
3879
3880                         thermal-sensors = <&tsens0 2>;
3881
3882                         trips {
3883                                 cpu1_alert0: trip-point0 {
3884                                         temperature = <90000>;
3885                                         hysteresis = <2000>;
3886                                         type = "passive";
3887                                 };
3888
3889                                 cpu1_alert1: trip-point1 {
3890                                         temperature = <95000>;
3891                                         hysteresis = <2000>;
3892                                         type = "passive";
3893                                 };
3894
3895                                 cpu1_crit: cpu_crit {
3896                                         temperature = <110000>;
3897                                         hysteresis = <1000>;
3898                                         type = "critical";
3899                                 };
3900                         };
3901
3902                         cooling-maps {
3903                                 map0 {
3904                                         trip = <&cpu1_alert0>;
3905                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3906                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3907                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3908                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3909                                 };
3910                                 map1 {
3911                                         trip = <&cpu1_alert1>;
3912                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3913                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3914                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3915                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3916                                 };
3917                         };
3918                 };
3919
3920                 cpu2-thermal {
3921                         polling-delay-passive = <250>;
3922                         polling-delay = <1000>;
3923
3924                         thermal-sensors = <&tsens0 3>;
3925
3926                         trips {
3927                                 cpu2_alert0: trip-point0 {
3928                                         temperature = <90000>;
3929                                         hysteresis = <2000>;
3930                                         type = "passive";
3931                                 };
3932
3933                                 cpu2_alert1: trip-point1 {
3934                                         temperature = <95000>;
3935                                         hysteresis = <2000>;
3936                                         type = "passive";
3937                                 };
3938
3939                                 cpu2_crit: cpu_crit {
3940                                         temperature = <110000>;
3941                                         hysteresis = <1000>;
3942                                         type = "critical";
3943                                 };
3944                         };
3945
3946                         cooling-maps {
3947                                 map0 {
3948                                         trip = <&cpu2_alert0>;
3949                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3950                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3951                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3952                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3953                                 };
3954                                 map1 {
3955                                         trip = <&cpu2_alert1>;
3956                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3957                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3958                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3959                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3960                                 };
3961                         };
3962                 };
3963
3964                 cpu3-thermal {
3965                         polling-delay-passive = <250>;
3966                         polling-delay = <1000>;
3967
3968                         thermal-sensors = <&tsens0 4>;
3969
3970                         trips {
3971                                 cpu3_alert0: trip-point0 {
3972                                         temperature = <90000>;
3973                                         hysteresis = <2000>;
3974                                         type = "passive";
3975                                 };
3976
3977                                 cpu3_alert1: trip-point1 {
3978                                         temperature = <95000>;
3979                                         hysteresis = <2000>;
3980                                         type = "passive";
3981                                 };
3982
3983                                 cpu3_crit: cpu_crit {
3984                                         temperature = <110000>;
3985                                         hysteresis = <1000>;
3986                                         type = "critical";
3987                                 };
3988                         };
3989
3990                         cooling-maps {
3991                                 map0 {
3992                                         trip = <&cpu3_alert0>;
3993                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3994                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3995                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3996                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3997                                 };
3998                                 map1 {
3999                                         trip = <&cpu3_alert1>;
4000                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4001                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4002                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4003                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4004                                 };
4005                         };
4006                 };
4007
4008                 cpu4-top-thermal {
4009                         polling-delay-passive = <250>;
4010                         polling-delay = <1000>;
4011
4012                         thermal-sensors = <&tsens0 7>;
4013
4014                         trips {
4015                                 cpu4_top_alert0: trip-point0 {
4016                                         temperature = <90000>;
4017                                         hysteresis = <2000>;
4018                                         type = "passive";
4019                                 };
4020
4021                                 cpu4_top_alert1: trip-point1 {
4022                                         temperature = <95000>;
4023                                         hysteresis = <2000>;
4024                                         type = "passive";
4025                                 };
4026
4027                                 cpu4_top_crit: cpu_crit {
4028                                         temperature = <110000>;
4029                                         hysteresis = <1000>;
4030                                         type = "critical";
4031                                 };
4032                         };
4033
4034                         cooling-maps {
4035                                 map0 {
4036                                         trip = <&cpu4_top_alert0>;
4037                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4038                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4039                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4040                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4041                                 };
4042                                 map1 {
4043                                         trip = <&cpu4_top_alert1>;
4044                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4045                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4046                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4047                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4048                                 };
4049                         };
4050                 };
4051
4052                 cpu5-top-thermal {
4053                         polling-delay-passive = <250>;
4054                         polling-delay = <1000>;
4055
4056                         thermal-sensors = <&tsens0 8>;
4057
4058                         trips {
4059                                 cpu5_top_alert0: trip-point0 {
4060                                         temperature = <90000>;
4061                                         hysteresis = <2000>;
4062                                         type = "passive";
4063                                 };
4064
4065                                 cpu5_top_alert1: trip-point1 {
4066                                         temperature = <95000>;
4067                                         hysteresis = <2000>;
4068                                         type = "passive";
4069                                 };
4070
4071                                 cpu5_top_crit: cpu_crit {
4072                                         temperature = <110000>;
4073                                         hysteresis = <1000>;
4074                                         type = "critical";
4075                                 };
4076                         };
4077
4078                         cooling-maps {
4079                                 map0 {
4080                                         trip = <&cpu5_top_alert0>;
4081                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4082                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4083                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4084                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4085                                 };
4086                                 map1 {
4087                                         trip = <&cpu5_top_alert1>;
4088                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4089                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4090                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4091                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4092                                 };
4093                         };
4094                 };
4095
4096                 cpu6-top-thermal {
4097                         polling-delay-passive = <250>;
4098                         polling-delay = <1000>;
4099
4100                         thermal-sensors = <&tsens0 9>;
4101
4102                         trips {
4103                                 cpu6_top_alert0: trip-point0 {
4104                                         temperature = <90000>;
4105                                         hysteresis = <2000>;
4106                                         type = "passive";
4107                                 };
4108
4109                                 cpu6_top_alert1: trip-point1 {
4110                                         temperature = <95000>;
4111                                         hysteresis = <2000>;
4112                                         type = "passive";
4113                                 };
4114
4115                                 cpu6_top_crit: cpu_crit {
4116                                         temperature = <110000>;
4117                                         hysteresis = <1000>;
4118                                         type = "critical";
4119                                 };
4120                         };
4121
4122                         cooling-maps {
4123                                 map0 {
4124                                         trip = <&cpu6_top_alert0>;
4125                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4126                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4127                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4128                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4129                                 };
4130                                 map1 {
4131                                         trip = <&cpu6_top_alert1>;
4132                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4133                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4134                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4135                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4136                                 };
4137                         };
4138                 };
4139
4140                 cpu7-top-thermal {
4141                         polling-delay-passive = <250>;
4142                         polling-delay = <1000>;
4143
4144                         thermal-sensors = <&tsens0 10>;
4145
4146                         trips {
4147                                 cpu7_top_alert0: trip-point0 {
4148                                         temperature = <90000>;
4149                                         hysteresis = <2000>;
4150                                         type = "passive";
4151                                 };
4152
4153                                 cpu7_top_alert1: trip-point1 {
4154                                         temperature = <95000>;
4155                                         hysteresis = <2000>;
4156                                         type = "passive";
4157                                 };
4158
4159                                 cpu7_top_crit: cpu_crit {
4160                                         temperature = <110000>;
4161                                         hysteresis = <1000>;
4162                                         type = "critical";
4163                                 };
4164                         };
4165
4166                         cooling-maps {
4167                                 map0 {
4168                                         trip = <&cpu7_top_alert0>;
4169                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4170                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4171                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4172                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4173                                 };
4174                                 map1 {
4175                                         trip = <&cpu7_top_alert1>;
4176                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4177                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4178                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4179                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4180                                 };
4181                         };
4182                 };
4183
4184                 cpu4-bottom-thermal {
4185                         polling-delay-passive = <250>;
4186                         polling-delay = <1000>;
4187
4188                         thermal-sensors = <&tsens0 11>;
4189
4190                         trips {
4191                                 cpu4_bottom_alert0: trip-point0 {
4192                                         temperature = <90000>;
4193                                         hysteresis = <2000>;
4194                                         type = "passive";
4195                                 };
4196
4197                                 cpu4_bottom_alert1: trip-point1 {
4198                                         temperature = <95000>;
4199                                         hysteresis = <2000>;
4200                                         type = "passive";
4201                                 };
4202
4203                                 cpu4_bottom_crit: cpu_crit {
4204                                         temperature = <110000>;
4205                                         hysteresis = <1000>;
4206                                         type = "critical";
4207                                 };
4208                         };
4209
4210                         cooling-maps {
4211                                 map0 {
4212                                         trip = <&cpu4_bottom_alert0>;
4213                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4214                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4215                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4216                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4217                                 };
4218                                 map1 {
4219                                         trip = <&cpu4_bottom_alert1>;
4220                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4221                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4222                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4223                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4224                                 };
4225                         };
4226                 };
4227
4228                 cpu5-bottom-thermal {
4229                         polling-delay-passive = <250>;
4230                         polling-delay = <1000>;
4231
4232                         thermal-sensors = <&tsens0 12>;
4233
4234                         trips {
4235                                 cpu5_bottom_alert0: trip-point0 {
4236                                         temperature = <90000>;
4237                                         hysteresis = <2000>;
4238                                         type = "passive";
4239                                 };
4240
4241                                 cpu5_bottom_alert1: trip-point1 {
4242                                         temperature = <95000>;
4243                                         hysteresis = <2000>;
4244                                         type = "passive";
4245                                 };
4246
4247                                 cpu5_bottom_crit: cpu_crit {
4248                                         temperature = <110000>;
4249                                         hysteresis = <1000>;
4250                                         type = "critical";
4251                                 };
4252                         };
4253
4254                         cooling-maps {
4255                                 map0 {
4256                                         trip = <&cpu5_bottom_alert0>;
4257                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4258                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4259                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4260                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4261                                 };
4262                                 map1 {
4263                                         trip = <&cpu5_bottom_alert1>;
4264                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4265                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4266                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4267                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4268                                 };
4269                         };
4270                 };
4271
4272                 cpu6-bottom-thermal {
4273                         polling-delay-passive = <250>;
4274                         polling-delay = <1000>;
4275
4276                         thermal-sensors = <&tsens0 13>;
4277
4278                         trips {
4279                                 cpu6_bottom_alert0: trip-point0 {
4280                                         temperature = <90000>;
4281                                         hysteresis = <2000>;
4282                                         type = "passive";
4283                                 };
4284
4285                                 cpu6_bottom_alert1: trip-point1 {
4286                                         temperature = <95000>;
4287                                         hysteresis = <2000>;
4288                                         type = "passive";
4289                                 };
4290
4291                                 cpu6_bottom_crit: cpu_crit {
4292                                         temperature = <110000>;
4293                                         hysteresis = <1000>;
4294                                         type = "critical";
4295                                 };
4296                         };
4297
4298                         cooling-maps {
4299                                 map0 {
4300                                         trip = <&cpu6_bottom_alert0>;
4301                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4302                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4303                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4304                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4305                                 };
4306                                 map1 {
4307                                         trip = <&cpu6_bottom_alert1>;
4308                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4309                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4310                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4311                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4312                                 };
4313                         };
4314                 };
4315
4316                 cpu7-bottom-thermal {
4317                         polling-delay-passive = <250>;
4318                         polling-delay = <1000>;
4319
4320                         thermal-sensors = <&tsens0 14>;
4321
4322                         trips {
4323                                 cpu7_bottom_alert0: trip-point0 {
4324                                         temperature = <90000>;
4325                                         hysteresis = <2000>;
4326                                         type = "passive";
4327                                 };
4328
4329                                 cpu7_bottom_alert1: trip-point1 {
4330                                         temperature = <95000>;
4331                                         hysteresis = <2000>;
4332                                         type = "passive";
4333                                 };
4334
4335                                 cpu7_bottom_crit: cpu_crit {
4336                                         temperature = <110000>;
4337                                         hysteresis = <1000>;
4338                                         type = "critical";
4339                                 };
4340                         };
4341
4342                         cooling-maps {
4343                                 map0 {
4344                                         trip = <&cpu7_bottom_alert0>;
4345                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4346                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4347                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4348                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4349                                 };
4350                                 map1 {
4351                                         trip = <&cpu7_bottom_alert1>;
4352                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4353                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4354                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4355                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4356                                 };
4357                         };
4358                 };
4359
4360                 aoss0-thermal {
4361                         polling-delay-passive = <250>;
4362                         polling-delay = <1000>;
4363
4364                         thermal-sensors = <&tsens0 0>;
4365
4366                         trips {
4367                                 aoss0_alert0: trip-point0 {
4368                                         temperature = <90000>;
4369                                         hysteresis = <2000>;
4370                                         type = "hot";
4371                                 };
4372                         };
4373                 };
4374
4375                 cluster0-thermal {
4376                         polling-delay-passive = <250>;
4377                         polling-delay = <1000>;
4378
4379                         thermal-sensors = <&tsens0 5>;
4380
4381                         trips {
4382                                 cluster0_alert0: trip-point0 {
4383                                         temperature = <90000>;
4384                                         hysteresis = <2000>;
4385                                         type = "hot";
4386                                 };
4387                                 cluster0_crit: cluster0_crit {
4388                                         temperature = <110000>;
4389                                         hysteresis = <2000>;
4390                                         type = "critical";
4391                                 };
4392                         };
4393                 };
4394
4395                 cluster1-thermal {
4396                         polling-delay-passive = <250>;
4397                         polling-delay = <1000>;
4398
4399                         thermal-sensors = <&tsens0 6>;
4400
4401                         trips {
4402                                 cluster1_alert0: trip-point0 {
4403                                         temperature = <90000>;
4404                                         hysteresis = <2000>;
4405                                         type = "hot";
4406                                 };
4407                                 cluster1_crit: cluster1_crit {
4408                                         temperature = <110000>;
4409                                         hysteresis = <2000>;
4410                                         type = "critical";
4411                                 };
4412                         };
4413                 };
4414
4415                 gpu-top-thermal {
4416                         polling-delay-passive = <250>;
4417                         polling-delay = <1000>;
4418
4419                         thermal-sensors = <&tsens0 15>;
4420
4421                         trips {
4422                                 gpu1_alert0: trip-point0 {
4423                                         temperature = <90000>;
4424                                         hysteresis = <2000>;
4425                                         type = "hot";
4426                                 };
4427                         };
4428                 };
4429
4430                 aoss1-thermal {
4431                         polling-delay-passive = <250>;
4432                         polling-delay = <1000>;
4433
4434                         thermal-sensors = <&tsens1 0>;
4435
4436                         trips {
4437                                 aoss1_alert0: trip-point0 {
4438                                         temperature = <90000>;
4439                                         hysteresis = <2000>;
4440                                         type = "hot";
4441                                 };
4442                         };
4443                 };
4444
4445                 wlan-thermal {
4446                         polling-delay-passive = <250>;
4447                         polling-delay = <1000>;
4448
4449                         thermal-sensors = <&tsens1 1>;
4450
4451                         trips {
4452                                 wlan_alert0: trip-point0 {
4453                                         temperature = <90000>;
4454                                         hysteresis = <2000>;
4455                                         type = "hot";
4456                                 };
4457                         };
4458                 };
4459
4460                 video-thermal {
4461                         polling-delay-passive = <250>;
4462                         polling-delay = <1000>;
4463
4464                         thermal-sensors = <&tsens1 2>;
4465
4466                         trips {
4467                                 video_alert0: trip-point0 {
4468                                         temperature = <90000>;
4469                                         hysteresis = <2000>;
4470                                         type = "hot";
4471                                 };
4472                         };
4473                 };
4474
4475                 mem-thermal {
4476                         polling-delay-passive = <250>;
4477                         polling-delay = <1000>;
4478
4479                         thermal-sensors = <&tsens1 3>;
4480
4481                         trips {
4482                                 mem_alert0: trip-point0 {
4483                                         temperature = <90000>;
4484                                         hysteresis = <2000>;
4485                                         type = "hot";
4486                                 };
4487                         };
4488                 };
4489
4490                 q6-hvx-thermal {
4491                         polling-delay-passive = <250>;
4492                         polling-delay = <1000>;
4493
4494                         thermal-sensors = <&tsens1 4>;
4495
4496                         trips {
4497                                 q6_hvx_alert0: trip-point0 {
4498                                         temperature = <90000>;
4499                                         hysteresis = <2000>;
4500                                         type = "hot";
4501                                 };
4502                         };
4503                 };
4504
4505                 camera-thermal {
4506                         polling-delay-passive = <250>;
4507                         polling-delay = <1000>;
4508
4509                         thermal-sensors = <&tsens1 5>;
4510
4511                         trips {
4512                                 camera_alert0: trip-point0 {
4513                                         temperature = <90000>;
4514                                         hysteresis = <2000>;
4515                                         type = "hot";
4516                                 };
4517                         };
4518                 };
4519
4520                 compute-thermal {
4521                         polling-delay-passive = <250>;
4522                         polling-delay = <1000>;
4523
4524                         thermal-sensors = <&tsens1 6>;
4525
4526                         trips {
4527                                 compute_alert0: trip-point0 {
4528                                         temperature = <90000>;
4529                                         hysteresis = <2000>;
4530                                         type = "hot";
4531                                 };
4532                         };
4533                 };
4534
4535                 modem-thermal {
4536                         polling-delay-passive = <250>;
4537                         polling-delay = <1000>;
4538
4539                         thermal-sensors = <&tsens1 7>;
4540
4541                         trips {
4542                                 modem_alert0: trip-point0 {
4543                                         temperature = <90000>;
4544                                         hysteresis = <2000>;
4545                                         type = "hot";
4546                                 };
4547                         };
4548                 };
4549
4550                 npu-thermal {
4551                         polling-delay-passive = <250>;
4552                         polling-delay = <1000>;
4553
4554                         thermal-sensors = <&tsens1 8>;
4555
4556                         trips {
4557                                 npu_alert0: trip-point0 {
4558                                         temperature = <90000>;
4559                                         hysteresis = <2000>;
4560                                         type = "hot";
4561                                 };
4562                         };
4563                 };
4564
4565                 modem-vec-thermal {
4566                         polling-delay-passive = <250>;
4567                         polling-delay = <1000>;
4568
4569                         thermal-sensors = <&tsens1 9>;
4570
4571                         trips {
4572                                 modem_vec_alert0: trip-point0 {
4573                                         temperature = <90000>;
4574                                         hysteresis = <2000>;
4575                                         type = "hot";
4576                                 };
4577                         };
4578                 };
4579
4580                 modem-scl-thermal {
4581                         polling-delay-passive = <250>;
4582                         polling-delay = <1000>;
4583
4584                         thermal-sensors = <&tsens1 10>;
4585
4586                         trips {
4587                                 modem_scl_alert0: trip-point0 {
4588                                         temperature = <90000>;
4589                                         hysteresis = <2000>;
4590                                         type = "hot";
4591                                 };
4592                         };
4593                 };
4594
4595                 gpu-bottom-thermal {
4596                         polling-delay-passive = <250>;
4597                         polling-delay = <1000>;
4598
4599                         thermal-sensors = <&tsens1 11>;
4600
4601                         trips {
4602                                 gpu2_alert0: trip-point0 {
4603                                         temperature = <90000>;
4604                                         hysteresis = <2000>;
4605                                         type = "hot";
4606                                 };
4607                         };
4608                 };
4609         };
4610 };