arch/arm64/boot/dts/qcom/sdm630.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * Copyright (c) 2020, Konrad Dybcio <konradybcio@gmail.com>
   4  * Copyright (c) 2020, AngeloGioacchino Del Regno <kholk11@gmail.com>
   5  */
   6
   7 #include <dt-bindings/clock/qcom,gcc-sdm660.h>
   8 #include <dt-bindings/clock/qcom,gpucc-sdm660.h>
   9 #include <dt-bindings/clock/qcom,mmcc-sdm660.h>
  10 #include <dt-bindings/clock/qcom,rpmcc.h>
  11 #include <dt-bindings/firmware/qcom,scm.h>
  12 #include <dt-bindings/interconnect/qcom,sdm660.h>
  13 #include <dt-bindings/power/qcom-rpmpd.h>
  14 #include <dt-bindings/gpio/gpio.h>
  15 #include <dt-bindings/interrupt-controller/arm-gic.h>
  16 #include <dt-bindings/soc/qcom,apr.h>
  17
  18 / {
  19         interrupt-parent = <&intc>;
  20
  21         #address-cells = <2>;
  22         #size-cells = <2>;
  23
  24         aliases {
  25                 mmc1 = &sdhc_1;
  26                 mmc2 = &sdhc_2;
  27         };
  28
  29         chosen { };
  30
  31         clocks {
  32                 xo_board: xo-board {
  33                         compatible = "fixed-clock";
  34                         #clock-cells = <0>;
  35                         clock-frequency = <19200000>;
  36                         clock-output-names = "xo_board";
  37                 };
  38
  39                 sleep_clk: sleep-clk {
  40                         compatible = "fixed-clock";
  41                         #clock-cells = <0>;
  42                         clock-frequency = <32764>;
  43                         clock-output-names = "sleep_clk";
  44                 };
  45         };
  46
  47         cpus {
  48                 #address-cells = <2>;
  49                 #size-cells = <0>;
  50
  51                 CPU0: cpu@100 {
  52                         device_type = "cpu";
  53                         compatible = "arm,cortex-a53";
  54                         reg = <0x0 0x100>;
  55                         enable-method = "psci";
  56                         cpu-idle-states = <&PERF_CPU_SLEEP_0
  57                                                 &PERF_CPU_SLEEP_1
  58                                                 &PERF_CLUSTER_SLEEP_0
  59                                                 &PERF_CLUSTER_SLEEP_1
  60                                                 &PERF_CLUSTER_SLEEP_2>;
  61                         capacity-dmips-mhz = <1126>;
  62                         #cooling-cells = <2>;
  63                         next-level-cache = <&L2_1>;
  64                         L2_1: l2-cache {
  65                                 compatible = "cache";
  66                                 cache-level = <2>;
  67                                 cache-unified;
  68                         };
  69                 };
  70
  71                 CPU1: cpu@101 {
  72                         device_type = "cpu";
  73                         compatible = "arm,cortex-a53";
  74                         reg = <0x0 0x101>;
  75                         enable-method = "psci";
  76                         cpu-idle-states = <&PERF_CPU_SLEEP_0
  77                                                 &PERF_CPU_SLEEP_1
  78                                                 &PERF_CLUSTER_SLEEP_0
  79                                                 &PERF_CLUSTER_SLEEP_1
  80                                                 &PERF_CLUSTER_SLEEP_2>;
  81                         capacity-dmips-mhz = <1126>;
  82                         #cooling-cells = <2>;
  83                         next-level-cache = <&L2_1>;
  84                 };
  85
  86                 CPU2: cpu@102 {
  87                         device_type = "cpu";
  88                         compatible = "arm,cortex-a53";
  89                         reg = <0x0 0x102>;
  90                         enable-method = "psci";
  91                         cpu-idle-states = <&PERF_CPU_SLEEP_0
  92                                                 &PERF_CPU_SLEEP_1
  93                                                 &PERF_CLUSTER_SLEEP_0
  94                                                 &PERF_CLUSTER_SLEEP_1
  95                                                 &PERF_CLUSTER_SLEEP_2>;
  96                         capacity-dmips-mhz = <1126>;
  97                         #cooling-cells = <2>;
  98                         next-level-cache = <&L2_1>;
  99                 };
 100
 101                 CPU3: cpu@103 {
 102                         device_type = "cpu";
 103                         compatible = "arm,cortex-a53";
 104                         reg = <0x0 0x103>;
 105                         enable-method = "psci";
 106                         cpu-idle-states = <&PERF_CPU_SLEEP_0
 107                                                 &PERF_CPU_SLEEP_1
 108                                                 &PERF_CLUSTER_SLEEP_0
 109                                                 &PERF_CLUSTER_SLEEP_1
 110                                                 &PERF_CLUSTER_SLEEP_2>;
 111                         capacity-dmips-mhz = <1126>;
 112                         #cooling-cells = <2>;
 113                         next-level-cache = <&L2_1>;
 114                 };
 115
 116                 CPU4: cpu@0 {
 117                         device_type = "cpu";
 118                         compatible = "arm,cortex-a53";
 119                         reg = <0x0 0x0>;
 120                         enable-method = "psci";
 121                         cpu-idle-states = <&PWR_CPU_SLEEP_0
 122                                                 &PWR_CPU_SLEEP_1
 123                                                 &PWR_CLUSTER_SLEEP_0
 124                                                 &PWR_CLUSTER_SLEEP_1
 125                                                 &PWR_CLUSTER_SLEEP_2>;
 126                         capacity-dmips-mhz = <1024>;
 127                         #cooling-cells = <2>;
 128                         next-level-cache = <&L2_0>;
 129                         L2_0: l2-cache {
 130                                 compatible = "cache";
 131                                 cache-level = <2>;
 132                                 cache-unified;
 133                         };
 134                 };
 135
 136                 CPU5: cpu@1 {
 137                         device_type = "cpu";
 138                         compatible = "arm,cortex-a53";
 139                         reg = <0x0 0x1>;
 140                         enable-method = "psci";
 141                         cpu-idle-states = <&PWR_CPU_SLEEP_0
 142                                                 &PWR_CPU_SLEEP_1
 143                                                 &PWR_CLUSTER_SLEEP_0
 144                                                 &PWR_CLUSTER_SLEEP_1
 145                                                 &PWR_CLUSTER_SLEEP_2>;
 146                         capacity-dmips-mhz = <1024>;
 147                         #cooling-cells = <2>;
 148                         next-level-cache = <&L2_0>;
 149                 };
 150
 151                 CPU6: cpu@2 {
 152                         device_type = "cpu";
 153                         compatible = "arm,cortex-a53";
 154                         reg = <0x0 0x2>;
 155                         enable-method = "psci";
 156                         cpu-idle-states = <&PWR_CPU_SLEEP_0
 157                                                 &PWR_CPU_SLEEP_1
 158                                                 &PWR_CLUSTER_SLEEP_0
 159                                                 &PWR_CLUSTER_SLEEP_1
 160                                                 &PWR_CLUSTER_SLEEP_2>;
 161                         capacity-dmips-mhz = <1024>;
 162                         #cooling-cells = <2>;
 163                         next-level-cache = <&L2_0>;
 164                 };
 165
 166                 CPU7: cpu@3 {
 167                         device_type = "cpu";
 168                         compatible = "arm,cortex-a53";
 169                         reg = <0x0 0x3>;
 170                         enable-method = "psci";
 171                         cpu-idle-states = <&PWR_CPU_SLEEP_0
 172                                                 &PWR_CPU_SLEEP_1
 173                                                 &PWR_CLUSTER_SLEEP_0
 174                                                 &PWR_CLUSTER_SLEEP_1
 175                                                 &PWR_CLUSTER_SLEEP_2>;
 176                         capacity-dmips-mhz = <1024>;
 177                         #cooling-cells = <2>;
 178                         next-level-cache = <&L2_0>;
 179                 };
 180
 181                 cpu-map {
 182                         cluster0 {
 183                                 core0 {
 184                                         cpu = <&CPU4>;
 185                                 };
 186
 187                                 core1 {
 188                                         cpu = <&CPU5>;
 189                                 };
 190
 191                                 core2 {
 192                                         cpu = <&CPU6>;
 193                                 };
 194
 195                                 core3 {
 196                                         cpu = <&CPU7>;
 197                                 };
 198                         };
 199
 200                         cluster1 {
 201                                 core0 {
 202                                         cpu = <&CPU0>;
 203                                 };
 204
 205                                 core1 {
 206                                         cpu = <&CPU1>;
 207                                 };
 208
 209                                 core2 {
 210                                         cpu = <&CPU2>;
 211                                 };
 212
 213                                 core3 {
 214                                         cpu = <&CPU3>;
 215                                 };
 216                         };
 217                 };
 218
 219                 idle-states {
 220                         entry-method = "psci";
 221
 222                         PWR_CPU_SLEEP_0: cpu-sleep-0-0 {
 223                                 compatible = "arm,idle-state";
 224                                 idle-state-name = "pwr-retention";
 225                                 arm,psci-suspend-param = <0x40000002>;
 226                                 entry-latency-us = <338>;
 227                                 exit-latency-us = <423>;
 228                                 min-residency-us = <200>;
 229                         };
 230
 231                         PWR_CPU_SLEEP_1: cpu-sleep-0-1 {
 232                                 compatible = "arm,idle-state";
 233                                 idle-state-name = "pwr-power-collapse";
 234                                 arm,psci-suspend-param = <0x40000003>;
 235                                 entry-latency-us = <515>;
 236                                 exit-latency-us = <1821>;
 237                                 min-residency-us = <1000>;
 238                                 local-timer-stop;
 239                         };
 240
 241                         PERF_CPU_SLEEP_0: cpu-sleep-1-0 {
 242                                 compatible = "arm,idle-state";
 243                                 idle-state-name = "perf-retention";
 244                                 arm,psci-suspend-param = <0x40000002>;
 245                                 entry-latency-us = <154>;
 246                                 exit-latency-us = <87>;
 247                                 min-residency-us = <200>;
 248                         };
 249
 250                         PERF_CPU_SLEEP_1: cpu-sleep-1-1 {
 251                                 compatible = "arm,idle-state";
 252                                 idle-state-name = "perf-power-collapse";
 253                                 arm,psci-suspend-param = <0x40000003>;
 254                                 entry-latency-us = <262>;
 255                                 exit-latency-us = <301>;
 256                                 min-residency-us = <1000>;
 257                                 local-timer-stop;
 258                         };
 259
 260                         PWR_CLUSTER_SLEEP_0: cluster-sleep-0-0 {
 261                                 compatible = "arm,idle-state";
 262                                 idle-state-name = "pwr-cluster-dynamic-retention";
 263                                 arm,psci-suspend-param = <0x400000F2>;
 264                                 entry-latency-us = <284>;
 265                                 exit-latency-us = <384>;
 266                                 min-residency-us = <9987>;
 267                                 local-timer-stop;
 268                         };
 269
 270                         PWR_CLUSTER_SLEEP_1: cluster-sleep-0-1 {
 271                                 compatible = "arm,idle-state";
 272                                 idle-state-name = "pwr-cluster-retention";
 273                                 arm,psci-suspend-param = <0x400000F3>;
 274                                 entry-latency-us = <338>;
 275                                 exit-latency-us = <423>;
 276                                 min-residency-us = <9987>;
 277                                 local-timer-stop;
 278                         };
 279
 280                         PWR_CLUSTER_SLEEP_2: cluster-sleep-0-2 {
 281                                 compatible = "arm,idle-state";
 282                                 idle-state-name = "pwr-cluster-retention";
 283                                 arm,psci-suspend-param = <0x400000F4>;
 284                                 entry-latency-us = <515>;
 285                                 exit-latency-us = <1821>;
 286                                 min-residency-us = <9987>;
 287                                 local-timer-stop;
 288                         };
 289
 290                         PERF_CLUSTER_SLEEP_0: cluster-sleep-1-0 {
 291                                 compatible = "arm,idle-state";
 292                                 idle-state-name = "perf-cluster-dynamic-retention";
 293                                 arm,psci-suspend-param = <0x400000F2>;
 294                                 entry-latency-us = <272>;
 295                                 exit-latency-us = <329>;
 296                                 min-residency-us = <9987>;
 297                                 local-timer-stop;
 298                         };
 299
 300                         PERF_CLUSTER_SLEEP_1: cluster-sleep-1-1 {
 301                                 compatible = "arm,idle-state";
 302                                 idle-state-name = "perf-cluster-retention";
 303                                 arm,psci-suspend-param = <0x400000F3>;
 304                                 entry-latency-us = <332>;
 305                                 exit-latency-us = <368>;
 306                                 min-residency-us = <9987>;
 307                                 local-timer-stop;
 308                         };
 309
 310                         PERF_CLUSTER_SLEEP_2: cluster-sleep-1-2 {
 311                                 compatible = "arm,idle-state";
 312                                 idle-state-name = "perf-cluster-retention";
 313                                 arm,psci-suspend-param = <0x400000F4>;
 314                                 entry-latency-us = <545>;
 315                                 exit-latency-us = <1609>;
 316                                 min-residency-us = <9987>;
 317                                 local-timer-stop;
 318                         };
 319                 };
 320         };
 321
 322         firmware {
 323                 scm {
 324                         compatible = "qcom,scm-msm8998", "qcom,scm";
 325                 };
 326         };
 327
 328         memory@80000000 {
 329                 device_type = "memory";
 330                 /* We expect the bootloader to fill in the reg */
 331                 reg = <0x0 0x80000000 0x0 0x0>;
 332         };
 333
 334         dsi_opp_table: opp-table-dsi {
 335                 compatible = "operating-points-v2";
 336
 337                 opp-131250000 {
 338                         opp-hz = /bits/ 64 <131250000>;
 339                         required-opps = <&rpmpd_opp_svs>;
 340                 };
 341
 342                 opp-210000000 {
 343                         opp-hz = /bits/ 64 <210000000>;
 344                         required-opps = <&rpmpd_opp_svs_plus>;
 345                 };
 346
 347                 opp-262500000 {
 348                         opp-hz = /bits/ 64 <262500000>;
 349                         required-opps = <&rpmpd_opp_nom>;
 350                 };
 351         };
 352
 353         pmu {
 354                 compatible = "arm,armv8-pmuv3";
 355                 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
 356         };
 357
 358         psci {
 359                 compatible = "arm,psci-1.0";
 360                 method = "smc";
 361         };
 362
 363         rpm: remoteproc {
 364                 compatible = "qcom,sdm660-rpm-proc", "qcom,rpm-proc";
 365
 366                 glink-edge {
 367                         compatible = "qcom,glink-rpm";
 368
 369                         interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
 370                         qcom,rpm-msg-ram = <&rpm_msg_ram>;
 371                         mboxes = <&apcs_glb 0>;
 372
 373                         rpm_requests: rpm-requests {
 374                                 compatible = "qcom,rpm-sdm660";
 375                                 qcom,glink-channels = "rpm_requests";
 376
 377                                 rpmcc: clock-controller {
 378                                         compatible = "qcom,rpmcc-sdm660", "qcom,rpmcc";
 379                                         #clock-cells = <1>;
 380                                 };
 381
 382                                 rpmpd: power-controller {
 383                                         compatible = "qcom,sdm660-rpmpd";
 384                                         #power-domain-cells = <1>;
 385                                         operating-points-v2 = <&rpmpd_opp_table>;
 386
 387                                         rpmpd_opp_table: opp-table {
 388                                                 compatible = "operating-points-v2";
 389
 390                                                 rpmpd_opp_ret: opp1 {
 391                                                         opp-level = <RPM_SMD_LEVEL_RETENTION>;
 392                                                 };
 393
 394                                                 rpmpd_opp_ret_plus: opp2 {
 395                                                         opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
 396                                                 };
 397
 398                                                 rpmpd_opp_min_svs: opp3 {
 399                                                         opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
 400                                                 };
 401
 402                                                 rpmpd_opp_low_svs: opp4 {
 403                                                         opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
 404                                                 };
 405
 406                                                 rpmpd_opp_svs: opp5 {
 407                                                         opp-level = <RPM_SMD_LEVEL_SVS>;
 408                                                 };
 409
 410                                                 rpmpd_opp_svs_plus: opp6 {
 411                                                         opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
 412                                                 };
 413
 414                                                 rpmpd_opp_nom: opp7 {
 415                                                         opp-level = <RPM_SMD_LEVEL_NOM>;
 416                                                 };
 417
 418                                                 rpmpd_opp_nom_plus: opp8 {
 419                                                         opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
 420                                                 };
 421
 422                                                 rpmpd_opp_turbo: opp9 {
 423                                                         opp-level = <RPM_SMD_LEVEL_TURBO>;
 424                                                 };
 425                                         };
 426                                 };
 427                         };
 428                 };
 429         };
 430
 431         reserved-memory {
 432                 #address-cells = <2>;
 433                 #size-cells = <2>;
 434                 ranges;
 435
 436                 wlan_msa_guard: wlan-msa-guard@85600000 {
 437                         reg = <0x0 0x85600000 0x0 0x100000>;
 438                         no-map;
 439                 };
 440
 441                 wlan_msa_mem: wlan-msa-mem@85700000 {
 442                         reg = <0x0 0x85700000 0x0 0x100000>;
 443                         no-map;
 444                 };
 445
 446                 qhee_code: qhee-code@85800000 {
 447                         reg = <0x0 0x85800000 0x0 0x600000>;
 448                         no-map;
 449                 };
 450
 451                 rmtfs_mem: memory@85e00000 {
 452                         compatible = "qcom,rmtfs-mem";
 453                         reg = <0x0 0x85e00000 0x0 0x200000>;
 454                         no-map;
 455
 456                         qcom,client-id = <1>;
 457                         qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
 458                 };
 459
 460                 smem_region: smem-mem@86000000 {
 461                         reg = <0 0x86000000 0 0x200000>;
 462                         no-map;
 463                 };
 464
 465                 tz_mem: memory@86200000 {
 466                         reg = <0x0 0x86200000 0x0 0x3300000>;
 467                         no-map;
 468                 };
 469
 470                 mpss_region: mpss@8ac00000 {
 471                         reg = <0x0 0x8ac00000 0x0 0x7e00000>;
 472                         no-map;
 473                 };
 474
 475                 adsp_region: adsp@92a00000 {
 476                         reg = <0x0 0x92a00000 0x0 0x1e00000>;
 477                         no-map;
 478                 };
 479
 480                 mba_region: mba@94800000 {
 481                         reg = <0x0 0x94800000 0x0 0x200000>;
 482                         no-map;
 483                 };
 484
 485                 buffer_mem: tzbuffer@94a00000 {
 486                         reg = <0x0 0x94a00000 0x0 0x100000>;
 487                         no-map;
 488                 };
 489
 490                 venus_region: venus@9f800000 {
 491                         reg = <0x0 0x9f800000 0x0 0x800000>;
 492                         no-map;
 493                 };
 494
 495                 adsp_mem: adsp-region@f6000000 {
 496                         reg = <0x0 0xf6000000 0x0 0x800000>;
 497                         no-map;
 498                 };
 499
 500                 qseecom_mem: qseecom-region@f6800000 {
 501                         reg = <0x0 0xf6800000 0x0 0x1400000>;
 502                         no-map;
 503                 };
 504
 505                 zap_shader_region: gpu@fed00000 {
 506                         compatible = "shared-dma-pool";
 507                         reg = <0x0 0xfed00000 0x0 0xa00000>;
 508                         no-map;
 509                 };
 510         };
 511
 512         smem: smem {
 513                 compatible = "qcom,smem";
 514                 memory-region = <&smem_region>;
 515                 hwlocks = <&tcsr_mutex 3>;
 516         };
 517
 518         smp2p-adsp {
 519                 compatible = "qcom,smp2p";
 520                 qcom,smem = <443>, <429>;
 521                 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
 522                 mboxes = <&apcs_glb 10>;
 523                 qcom,local-pid = <0>;
 524                 qcom,remote-pid = <2>;
 525
 526                 adsp_smp2p_out: master-kernel {
 527                         qcom,entry-name = "master-kernel";
 528                         #qcom,smem-state-cells = <1>;
 529                 };
 530
 531                 adsp_smp2p_in: slave-kernel {
 532                         qcom,entry-name = "slave-kernel";
 533                         interrupt-controller;
 534                         #interrupt-cells = <2>;
 535                 };
 536         };
 537
 538         smp2p-mpss {
 539                 compatible = "qcom,smp2p";
 540                 qcom,smem = <435>, <428>;
 541                 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
 542                 mboxes = <&apcs_glb 14>;
 543                 qcom,local-pid = <0>;
 544                 qcom,remote-pid = <1>;
 545
 546                 modem_smp2p_out: master-kernel {
 547                         qcom,entry-name = "master-kernel";
 548                         #qcom,smem-state-cells = <1>;
 549                 };
 550
 551                 modem_smp2p_in: slave-kernel {
 552                         qcom,entry-name = "slave-kernel";
 553                         interrupt-controller;
 554                         #interrupt-cells = <2>;
 555                 };
 556         };
 557
 558         soc@0 {
 559                 #address-cells = <1>;
 560                 #size-cells = <1>;
 561                 ranges = <0 0 0 0xffffffff>;
 562                 compatible = "simple-bus";
 563
 564                 gcc: clock-controller@100000 {
 565                         compatible = "qcom,gcc-sdm630";
 566                         #clock-cells = <1>;
 567                         #reset-cells = <1>;
 568                         #power-domain-cells = <1>;
 569                         reg = <0x00100000 0x94000>;
 570
 571                         clock-names = "xo", "sleep_clk";
 572                         clocks = <&xo_board>,
 573                                         <&sleep_clk>;
 574                 };
 575
 576                 rpm_msg_ram: sram@778000 {
 577                         compatible = "qcom,rpm-msg-ram";
 578                         reg = <0x00778000 0x7000>;
 579                 };
 580
 581                 qfprom: qfprom@780000 {
 582                         compatible = "qcom,sdm630-qfprom", "qcom,qfprom";
 583                         reg = <0x00780000 0x621c>;
 584                         #address-cells = <1>;
 585                         #size-cells = <1>;
 586
 587                         qusb2_hstx_trim: hstx-trim@240 {
 588                                 reg = <0x243 0x1>;
 589                                 bits = <1 3>;
 590                         };
 591
 592                         gpu_speed_bin: gpu-speed-bin@41a0 {
 593                                 reg = <0x41a2 0x1>;
 594                                 bits = <5 7>;
 595                         };
 596                 };
 597
 598                 rng: rng@793000 {
 599                         compatible = "qcom,prng-ee";
 600                         reg = <0x00793000 0x1000>;
 601                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 602                         clock-names = "core";
 603                 };
 604
 605                 bimc: interconnect@1008000 {
 606                         compatible = "qcom,sdm660-bimc";
 607                         reg = <0x01008000 0x78000>;
 608                         #interconnect-cells = <1>;
 609                         clock-names = "bus", "bus_a";
 610                         clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
 611                                  <&rpmcc RPM_SMD_BIMC_A_CLK>;
 612                 };
 613
 614                 restart@10ac000 {
 615                         compatible = "qcom,pshold";
 616                         reg = <0x010ac000 0x4>;
 617                 };
 618
 619                 cnoc: interconnect@1500000 {
 620                         compatible = "qcom,sdm660-cnoc";
 621                         reg = <0x01500000 0x10000>;
 622                         #interconnect-cells = <1>;
 623                         clock-names = "bus", "bus_a";
 624                         clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
 625                                  <&rpmcc RPM_SMD_CNOC_A_CLK>;
 626                 };
 627
 628                 snoc: interconnect@1626000 {
 629                         compatible = "qcom,sdm660-snoc";
 630                         reg = <0x01626000 0x7090>;
 631                         #interconnect-cells = <1>;
 632                         clock-names = "bus", "bus_a";
 633                         clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
 634                                  <&rpmcc RPM_SMD_SNOC_A_CLK>;
 635                 };
 636
 637                 anoc2_smmu: iommu@16c0000 {
 638                         compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
 639                         reg = <0x016c0000 0x40000>;
 640
 641                         assigned-clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
 642                         assigned-clock-rates = <1000>;
 643                         clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
 644                         clock-names = "bus";
 645                         #global-interrupts = <2>;
 646                         #iommu-cells = <1>;
 647
 648                         interrupts =
 649                                 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
 650                                 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
 651
 652                                 <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>,
 653                                 <GIC_SPI 374 IRQ_TYPE_LEVEL_LOW>,
 654                                 <GIC_SPI 375 IRQ_TYPE_LEVEL_LOW>,
 655                                 <GIC_SPI 376 IRQ_TYPE_LEVEL_LOW>,
 656                                 <GIC_SPI 377 IRQ_TYPE_LEVEL_LOW>,
 657                                 <GIC_SPI 378 IRQ_TYPE_LEVEL_LOW>,
 658                                 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
 659                                 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
 660                                 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
 661                                 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
 662                                 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
 663                                 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
 664                                 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
 665                                 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
 666                                 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
 667                                 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
 668                                 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
 669                                 <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
 670                                 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
 671                                 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
 672                                 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>,
 673                                 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>,
 674                                 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
 675                                 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
 676                                 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
 677                                 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
 678                                 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
 679                                 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
 680                                 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
 681
 682                         status = "disabled";
 683                 };
 684
 685                 a2noc: interconnect@1704000 {
 686                         compatible = "qcom,sdm660-a2noc";
 687                         reg = <0x01704000 0xc100>;
 688                         #interconnect-cells = <1>;
 689                         clock-names = "bus",
 690                                       "bus_a",
 691                                       "ipa",
 692                                       "ufs_axi",
 693                                       "aggre2_ufs_axi",
 694                                       "aggre2_usb3_axi",
 695                                       "cfg_noc_usb2_axi";
 696                         clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>,
 697                                  <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>,
 698                                  <&rpmcc RPM_SMD_IPA_CLK>,
 699                                  <&gcc GCC_UFS_AXI_CLK>,
 700                                  <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
 701                                  <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
 702                                  <&gcc GCC_CFG_NOC_USB2_AXI_CLK>;
 703                 };
 704
 705                 mnoc: interconnect@1745000 {
 706                         compatible = "qcom,sdm660-mnoc";
 707                         reg = <0x01745000 0xa010>;
 708                         #interconnect-cells = <1>;
 709                         clock-names = "bus", "bus_a", "iface";
 710                         clocks = <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK>,
 711                                  <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK_A>,
 712                                  <&mmcc AHB_CLK_SRC>;
 713                 };
 714
 715                 tsens: thermal-sensor@10ae000 {
 716                         compatible = "qcom,sdm630-tsens", "qcom,tsens-v2";
 717                         reg = <0x010ae000 0x1000>, /* TM */
 718                                   <0x010ad000 0x1000>; /* SROT */
 719                         #qcom,sensors = <12>;
 720                         interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
 721                                          <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
 722                         interrupt-names = "uplow", "critical";
 723                         #thermal-sensor-cells = <1>;
 724                 };
 725
 726                 tcsr_mutex: hwlock@1f40000 {
 727                         compatible = "qcom,tcsr-mutex";
 728                         reg = <0x01f40000 0x20000>;
 729                         #hwlock-cells = <1>;
 730                 };
 731
 732                 tcsr_regs_1: syscon@1f60000 {
 733                         compatible = "qcom,sdm630-tcsr", "syscon";
 734                         reg = <0x01f60000 0x20000>;
 735                 };
 736
 737                 tlmm: pinctrl@3100000 {
 738                         compatible = "qcom,sdm630-pinctrl";
 739                         reg = <0x03100000 0x400000>,
 740                                   <0x03500000 0x400000>,
 741                                   <0x03900000 0x400000>;
 742                         reg-names = "south", "center", "north";
 743                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 744                         gpio-controller;
 745                         gpio-ranges = <&tlmm 0 0 114>;
 746                         #gpio-cells = <2>;
 747                         interrupt-controller;
 748                         #interrupt-cells = <2>;
 749
 750                         blsp1_uart1_default: blsp1-uart1-default-state {
 751                                 pins = "gpio0", "gpio1", "gpio2", "gpio3";
 752                                 function = "blsp_uart1";
 753                                 drive-strength = <2>;
 754                                 bias-disable;
 755                         };
 756
 757                         blsp1_uart1_sleep: blsp1-uart1-sleep-state {
 758                                 pins = "gpio0", "gpio1", "gpio2", "gpio3";
 759                                 function = "gpio";
 760                                 drive-strength = <2>;
 761                                 bias-disable;
 762                         };
 763
 764                         blsp1_uart2_default: blsp1-uart2-default-state {
 765                                 pins = "gpio4", "gpio5";
 766                                 function = "blsp_uart2";
 767                                 drive-strength = <2>;
 768                                 bias-disable;
 769                         };
 770
 771                         blsp2_uart1_default: blsp2-uart1-active-state {
 772                                 tx-rts-pins {
 773                                         pins = "gpio16", "gpio19";
 774                                         function = "blsp_uart5";
 775                                         drive-strength = <2>;
 776                                         bias-disable;
 777                                 };
 778
 779                                 rx-pins {
 780                                         /*
 781                                          * Avoid garbage data while BT module
 782                                          * is powered off or not driving signal
 783                                          */
 784                                         pins = "gpio17";
 785                                         function = "blsp_uart5";
 786                                         drive-strength = <2>;
 787                                         bias-pull-up;
 788                                 };
 789
 790                                 cts-pins {
 791                                         /* Match the pull of the BT module */
 792                                         pins = "gpio18";
 793                                         function = "blsp_uart5";
 794                                         drive-strength = <2>;
 795                                         bias-pull-down;
 796                                 };
 797                         };
 798
 799                         blsp2_uart1_sleep: blsp2-uart1-sleep-state {
 800                                 tx-pins {
 801                                         pins = "gpio16";
 802                                         function = "gpio";
 803                                         drive-strength = <2>;
 804                                         bias-pull-up;
 805                                 };
 806
 807                                 rx-cts-rts-pins {
 808                                         pins = "gpio17", "gpio18", "gpio19";
 809                                         function = "gpio";
 810                                         drive-strength = <2>;
 811                                         bias-disable;
 812                                 };
 813                         };
 814
 815                         i2c1_default: i2c1-default-state {
 816                                 pins = "gpio2", "gpio3";
 817                                 function = "blsp_i2c1";
 818                                 drive-strength = <2>;
 819                                 bias-disable;
 820                         };
 821
 822                         i2c1_sleep: i2c1-sleep-state {
 823                                 pins = "gpio2", "gpio3";
 824                                 function = "blsp_i2c1";
 825                                 drive-strength = <2>;
 826                                 bias-pull-up;
 827                         };
 828
 829                         i2c2_default: i2c2-default-state {
 830                                 pins = "gpio6", "gpio7";
 831                                 function = "blsp_i2c2";
 832                                 drive-strength = <2>;
 833                                 bias-disable;
 834                         };
 835
 836                         i2c2_sleep: i2c2-sleep-state {
 837                                 pins = "gpio6", "gpio7";
 838                                 function = "blsp_i2c2";
 839                                 drive-strength = <2>;
 840                                 bias-pull-up;
 841                         };
 842
 843                         i2c3_default: i2c3-default-state {
 844                                 pins = "gpio10", "gpio11";
 845                                 function = "blsp_i2c3";
 846                                 drive-strength = <2>;
 847                                 bias-disable;
 848                         };
 849
 850                         i2c3_sleep: i2c3-sleep-state {
 851                                 pins = "gpio10", "gpio11";
 852                                 function = "blsp_i2c3";
 853                                 drive-strength = <2>;
 854                                 bias-pull-up;
 855                         };
 856
 857                         i2c4_default: i2c4-default-state {
 858                                 pins = "gpio14", "gpio15";
 859                                 function = "blsp_i2c4";
 860                                 drive-strength = <2>;
 861                                 bias-disable;
 862                         };
 863
 864                         i2c4_sleep: i2c4-sleep-state {
 865                                 pins = "gpio14", "gpio15";
 866                                 function = "blsp_i2c4";
 867                                 drive-strength = <2>;
 868                                 bias-pull-up;
 869                         };
 870
 871                         i2c5_default: i2c5-default-state {
 872                                 pins = "gpio18", "gpio19";
 873                                 function = "blsp_i2c5";
 874                                 drive-strength = <2>;
 875                                 bias-disable;
 876                         };
 877
 878                         i2c5_sleep: i2c5-sleep-state {
 879                                 pins = "gpio18", "gpio19";
 880                                 function = "blsp_i2c5";
 881                                 drive-strength = <2>;
 882                                 bias-pull-up;
 883                         };
 884
 885                         i2c6_default: i2c6-default-state {
 886                                 pins = "gpio22", "gpio23";
 887                                 function = "blsp_i2c6";
 888                                 drive-strength = <2>;
 889                                 bias-disable;
 890                         };
 891
 892                         i2c6_sleep: i2c6-sleep-state {
 893                                 pins = "gpio22", "gpio23";
 894                                 function = "blsp_i2c6";
 895                                 drive-strength = <2>;
 896                                 bias-pull-up;
 897                         };
 898
 899                         i2c7_default: i2c7-default-state {
 900                                 pins = "gpio26", "gpio27";
 901                                 function = "blsp_i2c7";
 902                                 drive-strength = <2>;
 903                                 bias-disable;
 904                         };
 905
 906                         i2c7_sleep: i2c7-sleep-state {
 907                                 pins = "gpio26", "gpio27";
 908                                 function = "blsp_i2c7";
 909                                 drive-strength = <2>;
 910                                 bias-pull-up;
 911                         };
 912
 913                         i2c8_default: i2c8-default-state {
 914                                 pins = "gpio30", "gpio31";
 915                                 function = "blsp_i2c8_a";
 916                                 drive-strength = <2>;
 917                                 bias-disable;
 918                         };
 919
 920                         i2c8_sleep: i2c8-sleep-state {
 921                                 pins = "gpio30", "gpio31";
 922                                 function = "blsp_i2c8_a";
 923                                 drive-strength = <2>;
 924                                 bias-pull-up;
 925                         };
 926
 927                         cci0_default: cci0-default-state {
 928                                 pins = "gpio36","gpio37";
 929                                 function = "cci_i2c";
 930                                 bias-pull-up;
 931                                 drive-strength = <2>;
 932                         };
 933
 934                         cci1_default: cci1-default-state {
 935                                 pins = "gpio38","gpio39";
 936                                 function = "cci_i2c";
 937                                 bias-pull-up;
 938                                 drive-strength = <2>;
 939                         };
 940
 941                         sdc1_state_on: sdc1-on-state {
 942                                 clk-pins {
 943                                         pins = "sdc1_clk";
 944                                         bias-disable;
 945                                         drive-strength = <16>;
 946                                 };
 947
 948                                 cmd-pins {
 949                                         pins = "sdc1_cmd";
 950                                         bias-pull-up;
 951                                         drive-strength = <10>;
 952                                 };
 953
 954                                 data-pins {
 955                                         pins = "sdc1_data";
 956                                         bias-pull-up;
 957                                         drive-strength = <10>;
 958                                 };
 959
 960                                 rclk-pins {
 961                                         pins = "sdc1_rclk";
 962                                         bias-pull-down;
 963                                 };
 964                         };
 965
 966                         sdc1_state_off: sdc1-off-state {
 967                                 clk-pins {
 968                                         pins = "sdc1_clk";
 969                                         bias-disable;
 970                                         drive-strength = <2>;
 971                                 };
 972
 973                                 cmd-pins {
 974                                         pins = "sdc1_cmd";
 975                                         bias-pull-up;
 976                                         drive-strength = <2>;
 977                                 };
 978
 979                                 data-pins {
 980                                         pins = "sdc1_data";
 981                                         bias-pull-up;
 982                                         drive-strength = <2>;
 983                                 };
 984
 985                                 rclk-pins {
 986                                         pins = "sdc1_rclk";
 987                                         bias-pull-down;
 988                                 };
 989                         };
 990
 991                         sdc2_state_on: sdc2-on-state {
 992                                 clk-pins {
 993                                         pins = "sdc2_clk";
 994                                         bias-disable;
 995                                         drive-strength = <16>;
 996                                 };
 997
 998                                 cmd-pins {
 999                                         pins = "sdc2_cmd";
1000                                         bias-pull-up;
1001                                         drive-strength = <10>;
1002                                 };
1003
1004                                 data-pins {
1005                                         pins = "sdc2_data";
1006                                         bias-pull-up;
1007                                         drive-strength = <10>;
1008                                 };
1009                         };
1010
1011                         sdc2_state_off: sdc2-off-state {
1012                                 clk-pins {
1013                                         pins = "sdc2_clk";
1014                                         bias-disable;
1015                                         drive-strength = <2>;
1016                                 };
1017
1018                                 cmd-pins {
1019                                         pins = "sdc2_cmd";
1020                                         bias-pull-up;
1021                                         drive-strength = <2>;
1022                                 };
1023
1024                                 data-pins {
1025                                         pins = "sdc2_data";
1026                                         bias-pull-up;
1027                                         drive-strength = <2>;
1028                                 };
1029                         };
1030                 };
1031
1032                 remoteproc_mss: remoteproc@4080000 {
1033                         compatible = "qcom,sdm660-mss-pil";
1034                         reg = <0x04080000 0x100>, <0x04180000 0x40>;
1035                         reg-names = "qdsp6", "rmb";
1036
1037                         interrupts-extended = <&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
1038                                               <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1039                                               <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1040                                               <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1041                                               <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
1042                                               <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
1043                         interrupt-names = "wdog",
1044                                           "fatal",
1045                                           "ready",
1046                                           "handover",
1047                                           "stop-ack",
1048                                           "shutdown-ack";
1049
1050                         clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1051                                  <&gcc GCC_BIMC_MSS_Q6_AXI_CLK>,
1052                                  <&gcc GCC_BOOT_ROM_AHB_CLK>,
1053                                  <&gcc GPLL0_OUT_MSSCC>,
1054                                  <&gcc GCC_MSS_SNOC_AXI_CLK>,
1055                                  <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
1056                                  <&rpmcc RPM_SMD_QDSS_CLK>,
1057                                  <&rpmcc RPM_SMD_XO_CLK_SRC>;
1058                         clock-names = "iface",
1059                                       "bus",
1060                                       "mem",
1061                                       "gpll0_mss",
1062                                       "snoc_axi",
1063                                       "mnoc_axi",
1064                                       "qdss",
1065                                       "xo";
1066
1067                         qcom,smem-states = <&modem_smp2p_out 0>;
1068                         qcom,smem-state-names = "stop";
1069
1070                         resets = <&gcc GCC_MSS_RESTART>;
1071                         reset-names = "mss_restart";
1072
1073                         qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
1074
1075                         power-domains = <&rpmpd SDM660_VDDCX>,
1076                                         <&rpmpd SDM660_VDDMX>;
1077                         power-domain-names = "cx", "mx";
1078
1079                         memory-region = <&mba_region>, <&mpss_region>;
1080
1081                         status = "disabled";
1082
1083                         glink-edge {
1084                                 interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>;
1085                                 label = "modem";
1086                                 qcom,remote-pid = <1>;
1087                                 mboxes = <&apcs_glb 15>;
1088                         };
1089                 };
1090
1091                 adreno_gpu: gpu@5000000 {
1092                         compatible = "qcom,adreno-508.0", "qcom,adreno";
1093
1094                         reg = <0x05000000 0x40000>;
1095                         reg-names = "kgsl_3d0_reg_memory";
1096
1097                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1098
1099                         clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
1100                                 <&gpucc GPUCC_RBBMTIMER_CLK>,
1101                                 <&gcc GCC_BIMC_GFX_CLK>,
1102                                 <&gcc GCC_GPU_BIMC_GFX_CLK>,
1103                                 <&gpucc GPUCC_RBCPR_CLK>,
1104                                 <&gpucc GPUCC_GFX3D_CLK>;
1105
1106                         clock-names = "iface",
1107                                 "rbbmtimer",
1108                                 "mem",
1109                                 "mem_iface",
1110                                 "rbcpr",
1111                                 "core";
1112
1113                         power-domains = <&rpmpd SDM660_VDDMX>;
1114                         iommus = <&kgsl_smmu 0>;
1115
1116                         nvmem-cells = <&gpu_speed_bin>;
1117                         nvmem-cell-names = "speed_bin";
1118
1119                         interconnects = <&bimc MASTER_OXILI &bimc SLAVE_EBI>;
1120                         interconnect-names = "gfx-mem";
1121
1122                         operating-points-v2 = <&gpu_sdm630_opp_table>;
1123
1124                         status = "disabled";
1125
1126                         gpu_sdm630_opp_table: opp-table {
1127                                 compatible = "operating-points-v2";
1128                                 opp-775000000 {
1129                                         opp-hz = /bits/ 64 <775000000>;
1130                                         opp-level = <RPM_SMD_LEVEL_TURBO>;
1131                                         opp-peak-kBps = <5412000>;
1132                                         opp-supported-hw = <0xa2>;
1133                                 };
1134                                 opp-647000000 {
1135                                         opp-hz = /bits/ 64 <647000000>;
1136                                         opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
1137                                         opp-peak-kBps = <4068000>;
1138                                         opp-supported-hw = <0xff>;
1139                                 };
1140                                 opp-588000000 {
1141                                         opp-hz = /bits/ 64 <588000000>;
1142                                         opp-level = <RPM_SMD_LEVEL_NOM>;
1143                                         opp-peak-kBps = <3072000>;
1144                                         opp-supported-hw = <0xff>;
1145                                 };
1146                                 opp-465000000 {
1147                                         opp-hz = /bits/ 64 <465000000>;
1148                                         opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
1149                                         opp-peak-kBps = <2724000>;
1150                                         opp-supported-hw = <0xff>;
1151                                 };
1152                                 opp-370000000 {
1153                                         opp-hz = /bits/ 64 <370000000>;
1154                                         opp-level = <RPM_SMD_LEVEL_SVS>;
1155                                         opp-peak-kBps = <2188000>;
1156                                         opp-supported-hw = <0xff>;
1157                                 };
1158                                 opp-240000000 {
1159                                         opp-hz = /bits/ 64 <240000000>;
1160                                         opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
1161                                         opp-peak-kBps = <1648000>;
1162                                         opp-supported-hw = <0xff>;
1163                                 };
1164                                 opp-160000000 {
1165                                         opp-hz = /bits/ 64 <160000000>;
1166                                         opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
1167                                         opp-peak-kBps = <1200000>;
1168                                         opp-supported-hw = <0xff>;
1169                                 };
1170                         };
1171                 };
1172
1173                 kgsl_smmu: iommu@5040000 {
1174                         compatible = "qcom,sdm630-smmu-v2",
1175                                      "qcom,adreno-smmu", "qcom,smmu-v2";
1176                         reg = <0x05040000 0x10000>;
1177
1178                         /*
1179                          * GX GDSC parent is CX. We need to bring up CX for SMMU
1180                          * but we need both up for Adreno. On the other hand, we
1181                          * need to manage the GX rpmpd domain in the adreno driver.
1182                          * Enable CX/GX GDSCs here so that we can manage just the GX
1183                          * RPM Power Domain in the Adreno driver.
1184                          */
1185                         power-domains = <&gpucc GPU_GX_GDSC>;
1186                         clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
1187                                  <&gcc GCC_BIMC_GFX_CLK>,
1188                                  <&gcc GCC_GPU_BIMC_GFX_CLK>;
1189                         clock-names = "iface", "mem", "mem_iface";
1190                         #global-interrupts = <2>;
1191                         #iommu-cells = <1>;
1192
1193                         interrupts =
1194                                 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
1195                                 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
1196
1197                                 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1198                                 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1199                                 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
1200                                 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
1201                                 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1202                                 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1203                                 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
1204                                 <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>;
1205
1206                         status = "disabled";
1207                 };
1208
1209                 gpucc: clock-controller@5065000 {
1210                         compatible = "qcom,gpucc-sdm630";
1211                         #clock-cells = <1>;
1212                         #reset-cells = <1>;
1213                         #power-domain-cells = <1>;
1214                         reg = <0x05065000 0x9038>;
1215
1216                         clocks = <&xo_board>,
1217                                  <&gcc GCC_GPU_GPLL0_CLK>,
1218                                  <&gcc GCC_GPU_GPLL0_DIV_CLK>;
1219                         clock-names = "xo",
1220                                       "gcc_gpu_gpll0_clk",
1221                                       "gcc_gpu_gpll0_div_clk";
1222                         status = "disabled";
1223                 };
1224
1225                 lpass_smmu: iommu@5100000 {
1226                         compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
1227                         reg = <0x05100000 0x40000>;
1228                         #iommu-cells = <1>;
1229
1230                         #global-interrupts = <2>;
1231                         interrupts =
1232                                 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
1233                                 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
1234
1235                                 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
1236                                 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
1237                                 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
1238                                 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
1239                                 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
1240                                 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
1241                                 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
1242                                 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
1243                                 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
1244                                 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
1245                                 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
1246                                 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
1247                                 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
1248                                 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
1249                                 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>,
1250                                 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
1251                                 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
1252
1253                         status = "disabled";
1254                 };
1255
1256                 sram@290000 {
1257                         compatible = "qcom,rpm-stats";
1258                         reg = <0x00290000 0x10000>;
1259                 };
1260
1261                 spmi_bus: spmi@800f000 {
1262                         compatible = "qcom,spmi-pmic-arb";
1263                         reg = <0x0800f000 0x1000>,
1264                               <0x08400000 0x1000000>,
1265                               <0x09400000 0x1000000>,
1266                               <0x0a400000 0x220000>,
1267                               <0x0800a000 0x3000>;
1268                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1269                         interrupt-names = "periph_irq";
1270                         interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
1271                         qcom,ee = <0>;
1272                         qcom,channel = <0>;
1273                         #address-cells = <2>;
1274                         #size-cells = <0>;
1275                         interrupt-controller;
1276                         #interrupt-cells = <4>;
1277                 };
1278
1279                 usb3: usb@a8f8800 {
1280                         compatible = "qcom,sdm660-dwc3", "qcom,dwc3";
1281                         reg = <0x0a8f8800 0x400>;
1282                         status = "disabled";
1283                         #address-cells = <1>;
1284                         #size-cells = <1>;
1285                         ranges;
1286
1287                         clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>,
1288                                  <&gcc GCC_USB30_MASTER_CLK>,
1289                                  <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
1290                                  <&gcc GCC_USB30_SLEEP_CLK>,
1291                                  <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1292                                  <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
1293                         clock-names = "cfg_noc",
1294                                       "core",
1295                                       "iface",
1296                                       "sleep",
1297                                       "mock_utmi",
1298                                       "bus";
1299
1300                         assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1301                                           <&gcc GCC_USB30_MASTER_CLK>,
1302                                           <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
1303                         assigned-clock-rates = <19200000>, <120000000>,
1304                                                <19200000>;
1305
1306                         interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
1307                                      <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
1308                         interrupt-names = "hs_phy_irq", "ss_phy_irq";
1309
1310                         power-domains = <&gcc USB_30_GDSC>;
1311                         qcom,select-utmi-as-pipe-clk;
1312
1313                         resets = <&gcc GCC_USB_30_BCR>;
1314
1315                         usb3_dwc3: usb@a800000 {
1316                                 compatible = "snps,dwc3";
1317                                 reg = <0x0a800000 0xc8d0>;
1318                                 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
1319                                 snps,dis_u2_susphy_quirk;
1320                                 snps,dis_enblslpm_quirk;
1321
1322                                 /*
1323                                  * SDM630 technically supports USB3 but I
1324                                  * haven't seen any devices making use of it.
1325                                  */
1326                                 maximum-speed = "high-speed";
1327                                 phys = <&qusb2phy0>;
1328                                 phy-names = "usb2-phy";
1329                                 snps,hird-threshold = /bits/ 8 <0>;
1330                         };
1331                 };
1332
1333                 qusb2phy0: phy@c012000 {
1334                         compatible = "qcom,sdm660-qusb2-phy";
1335                         reg = <0x0c012000 0x180>;
1336                         #phy-cells = <0>;
1337
1338                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1339                                  <&gcc GCC_RX0_USB2_CLKREF_CLK>;
1340                         clock-names = "cfg_ahb", "ref";
1341
1342                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
1343                         nvmem-cells = <&qusb2_hstx_trim>;
1344                         status = "disabled";
1345                 };
1346
1347                 qusb2phy1: phy@c014000 {
1348                         compatible = "qcom,sdm660-qusb2-phy";
1349                         reg = <0x0c014000 0x180>;
1350                         #phy-cells = <0>;
1351
1352                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1353                                  <&gcc GCC_RX1_USB2_CLKREF_CLK>;
1354                         clock-names = "cfg_ahb", "ref";
1355
1356                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
1357                         nvmem-cells = <&qusb2_hstx_trim>;
1358                         status = "disabled";
1359                 };
1360
1361                 sdhc_2: mmc@c084000 {
1362                         compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5";
1363                         reg = <0x0c084000 0x1000>;
1364                         reg-names = "hc";
1365
1366                         interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1367                                         <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1368                         interrupt-names = "hc_irq", "pwr_irq";
1369
1370                         bus-width = <4>;
1371
1372                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
1373                                         <&gcc GCC_SDCC2_APPS_CLK>,
1374                                         <&xo_board>;
1375                         clock-names = "iface", "core", "xo";
1376
1377
1378                         interconnects = <&a2noc 3 &a2noc 10>,
1379                                         <&gnoc 0 &cnoc 28>;
1380                         interconnect-names = "sdhc-ddr","cpu-sdhc";
1381                         operating-points-v2 = <&sdhc2_opp_table>;
1382
1383                         pinctrl-names = "default", "sleep";
1384                         pinctrl-0 = <&sdc2_state_on>;
1385                         pinctrl-1 = <&sdc2_state_off>;
1386                         power-domains = <&rpmpd SDM660_VDDCX>;
1387
1388                         status = "disabled";
1389
1390                         sdhc2_opp_table: opp-table {
1391                                  compatible = "operating-points-v2";
1392
1393                                  opp-50000000 {
1394                                         opp-hz = /bits/ 64 <50000000>;
1395                                         required-opps = <&rpmpd_opp_low_svs>;
1396                                         opp-peak-kBps = <200000 140000>;
1397                                         opp-avg-kBps = <130718 133320>;
1398                                  };
1399                                  opp-100000000 {
1400                                         opp-hz = /bits/ 64 <100000000>;
1401                                         required-opps = <&rpmpd_opp_svs>;
1402                                         opp-peak-kBps = <250000 160000>;
1403                                         opp-avg-kBps = <196078 150000>;
1404                                  };
1405                                  opp-200000000 {
1406                                         opp-hz = /bits/ 64 <200000000>;
1407                                         required-opps = <&rpmpd_opp_nom>;
1408                                         opp-peak-kBps = <4096000 4096000>;
1409                                         opp-avg-kBps = <1338562 1338562>;
1410                                  };
1411                         };
1412                 };
1413
1414                 sdhc_1: mmc@c0c4000 {
1415                         compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5";
1416                         reg = <0x0c0c4000 0x1000>,
1417                               <0x0c0c5000 0x1000>,
1418                               <0x0c0c8000 0x8000>;
1419                         reg-names = "hc", "cqhci", "ice";
1420
1421                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1422                                         <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1423                         interrupt-names = "hc_irq", "pwr_irq";
1424
1425                         clocks = <&gcc GCC_SDCC1_AHB_CLK>,
1426                                  <&gcc GCC_SDCC1_APPS_CLK>,
1427                                  <&xo_board>,
1428                                  <&gcc GCC_SDCC1_ICE_CORE_CLK>;
1429                         clock-names = "iface", "core", "xo", "ice";
1430
1431                         interconnects = <&a2noc 2 &a2noc 10>,
1432                                         <&gnoc 0 &cnoc 27>;
1433                         interconnect-names = "sdhc-ddr", "cpu-sdhc";
1434                         operating-points-v2 = <&sdhc1_opp_table>;
1435                         pinctrl-names = "default", "sleep";
1436                         pinctrl-0 = <&sdc1_state_on>;
1437                         pinctrl-1 = <&sdc1_state_off>;
1438                         power-domains = <&rpmpd SDM660_VDDCX>;
1439
1440                         bus-width = <8>;
1441                         non-removable;
1442
1443                         status = "disabled";
1444
1445                         sdhc1_opp_table: opp-table {
1446                                 compatible = "operating-points-v2";
1447
1448                                 opp-50000000 {
1449                                         opp-hz = /bits/ 64 <50000000>;
1450                                         required-opps = <&rpmpd_opp_low_svs>;
1451                                         opp-peak-kBps = <200000 140000>;
1452                                         opp-avg-kBps = <130718 133320>;
1453                                 };
1454                                 opp-100000000 {
1455                                         opp-hz = /bits/ 64 <100000000>;
1456                                         required-opps = <&rpmpd_opp_svs>;
1457                                         opp-peak-kBps = <250000 160000>;
1458                                         opp-avg-kBps = <196078 150000>;
1459                                 };
1460                                 opp-384000000 {
1461                                         opp-hz = /bits/ 64 <384000000>;
1462                                         required-opps = <&rpmpd_opp_nom>;
1463                                         opp-peak-kBps = <4096000 4096000>;
1464                                         opp-avg-kBps = <1338562 1338562>;
1465                                 };
1466                         };
1467                 };
1468
1469                 usb2: usb@c2f8800 {
1470                         compatible = "qcom,sdm660-dwc3", "qcom,dwc3";
1471                         reg = <0x0c2f8800 0x400>;
1472                         status = "disabled";
1473                         #address-cells = <1>;
1474                         #size-cells = <1>;
1475                         ranges;
1476
1477                         clocks = <&gcc GCC_CFG_NOC_USB2_AXI_CLK>,
1478                                  <&gcc GCC_USB20_MASTER_CLK>,
1479                                  <&gcc GCC_USB20_SLEEP_CLK>,
1480                                  <&gcc GCC_USB20_MOCK_UTMI_CLK>;
1481                         clock-names = "cfg_noc", "core",
1482                                       "sleep", "mock_utmi";
1483
1484                         assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
1485                                           <&gcc GCC_USB20_MASTER_CLK>;
1486                         assigned-clock-rates = <19200000>, <60000000>;
1487
1488                         interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>;
1489                         interrupt-names = "hs_phy_irq";
1490
1491                         qcom,select-utmi-as-pipe-clk;
1492
1493                         resets = <&gcc GCC_USB_20_BCR>;
1494
1495                         usb2_dwc3: usb@c200000 {
1496                                 compatible = "snps,dwc3";
1497                                 reg = <0x0c200000 0xc8d0>;
1498                                 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
1499                                 snps,dis_u2_susphy_quirk;
1500                                 snps,dis_enblslpm_quirk;
1501
1502                                 /* This is the HS-only host */
1503                                 maximum-speed = "high-speed";
1504                                 phys = <&qusb2phy1>;
1505                                 phy-names = "usb2-phy";
1506                                 snps,hird-threshold = /bits/ 8 <0>;
1507                         };
1508                 };
1509
1510                 mmcc: clock-controller@c8c0000 {
1511                         compatible = "qcom,mmcc-sdm630";
1512                         reg = <0x0c8c0000 0x40000>;
1513                         #clock-cells = <1>;
1514                         #reset-cells = <1>;
1515                         #power-domain-cells = <1>;
1516                         clock-names = "xo",
1517                                         "sleep_clk",
1518                                         "gpll0",
1519                                         "gpll0_div",
1520                                         "dsi0pll",
1521                                         "dsi0pllbyte",
1522                                         "dsi1pll",
1523                                         "dsi1pllbyte",
1524                                         "dp_link_2x_clk_divsel_five",
1525                                         "dp_vco_divided_clk_src_mux";
1526                         clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1527                                         <&sleep_clk>,
1528                                         <&gcc GCC_MMSS_GPLL0_CLK>,
1529                                         <&gcc GCC_MMSS_GPLL0_DIV_CLK>,
1530                                         <&mdss_dsi0_phy 1>,
1531                                         <&mdss_dsi0_phy 0>,
1532                                         <0>,
1533                                         <0>,
1534                                         <0>,
1535                                         <0>;
1536                 };
1537
1538                 mdss: display-subsystem@c900000 {
1539                         compatible = "qcom,mdss";
1540                         reg = <0x0c900000 0x1000>,
1541                               <0x0c9b0000 0x1040>;
1542                         reg-names = "mdss_phys", "vbif_phys";
1543
1544                         power-domains = <&mmcc MDSS_GDSC>;
1545
1546                         clocks = <&mmcc MDSS_AHB_CLK>,
1547                                  <&mmcc MDSS_AXI_CLK>,
1548                                  <&mmcc MDSS_VSYNC_CLK>,
1549                                  <&mmcc MDSS_MDP_CLK>;
1550                         clock-names = "iface",
1551                                       "bus",
1552                                       "vsync",
1553                                       "core";
1554
1555                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1556
1557                         interrupt-controller;
1558                         #interrupt-cells = <1>;
1559
1560                         #address-cells = <1>;
1561                         #size-cells = <1>;
1562                         ranges;
1563                         status = "disabled";
1564
1565                         mdp: display-controller@c901000 {
1566                                 compatible = "qcom,sdm630-mdp5", "qcom,mdp5";
1567                                 reg = <0x0c901000 0x89000>;
1568                                 reg-names = "mdp_phys";
1569
1570                                 interrupt-parent = <&mdss>;
1571                                 interrupts = <0>;
1572
1573                                 assigned-clocks = <&mmcc MDSS_MDP_CLK>,
1574                                                   <&mmcc MDSS_VSYNC_CLK>;
1575                                 assigned-clock-rates = <300000000>,
1576                                                        <19200000>;
1577                                 clocks = <&mmcc MDSS_AHB_CLK>,
1578                                          <&mmcc MDSS_AXI_CLK>,
1579                                          <&mmcc MDSS_MDP_CLK>,
1580                                          <&mmcc MDSS_VSYNC_CLK>;
1581                                 clock-names = "iface",
1582                                               "bus",
1583                                               "core",
1584                                               "vsync";
1585
1586                                 interconnects = <&mnoc 2 &bimc 5>,
1587                                                 <&mnoc 3 &bimc 5>,
1588                                                 <&gnoc 0 &mnoc 17>;
1589                                 interconnect-names = "mdp0-mem",
1590                                                      "mdp1-mem",
1591                                                      "rotator-mem";
1592                                 iommus = <&mmss_smmu 0>;
1593                                 operating-points-v2 = <&mdp_opp_table>;
1594                                 power-domains = <&rpmpd SDM660_VDDCX>;
1595
1596                                 ports {
1597                                         #address-cells = <1>;
1598                                         #size-cells = <0>;
1599
1600                                         port@0 {
1601                                                 reg = <0>;
1602                                                 mdp5_intf1_out: endpoint {
1603                                                         remote-endpoint = <&mdss_dsi0_in>;
1604                                                 };
1605                                         };
1606                                 };
1607
1608                                 mdp_opp_table: opp-table {
1609                                         compatible = "operating-points-v2";
1610
1611                                         opp-150000000 {
1612                                                 opp-hz = /bits/ 64 <150000000>;
1613                                                 opp-peak-kBps = <320000 320000 76800>;
1614                                                 required-opps = <&rpmpd_opp_low_svs>;
1615                                         };
1616                                         opp-275000000 {
1617                                                 opp-hz = /bits/ 64 <275000000>;
1618                                                 opp-peak-kBps = <6400000 6400000 160000>;
1619                                                 required-opps = <&rpmpd_opp_svs>;
1620                                         };
1621                                         opp-300000000 {
1622                                                 opp-hz = /bits/ 64 <300000000>;
1623                                                 opp-peak-kBps = <6400000 6400000 190000>;
1624                                                 required-opps = <&rpmpd_opp_svs_plus>;
1625                                         };
1626                                         opp-330000000 {
1627                                                 opp-hz = /bits/ 64 <330000000>;
1628                                                 opp-peak-kBps = <6400000 6400000 240000>;
1629                                                 required-opps = <&rpmpd_opp_nom>;
1630                                         };
1631                                         opp-412500000 {
1632                                                 opp-hz = /bits/ 64 <412500000>;
1633                                                 opp-peak-kBps = <6400000 6400000 320000>;
1634                                                 required-opps = <&rpmpd_opp_turbo>;
1635                                         };
1636                                 };
1637                         };
1638
1639                         mdss_dsi0: dsi@c994000 {
1640                                 compatible = "qcom,sdm660-dsi-ctrl",
1641                                              "qcom,mdss-dsi-ctrl";
1642                                 reg = <0x0c994000 0x400>;
1643                                 reg-names = "dsi_ctrl";
1644
1645                                 operating-points-v2 = <&dsi_opp_table>;
1646                                 power-domains = <&rpmpd SDM660_VDDCX>;
1647
1648                                 interrupt-parent = <&mdss>;
1649                                 interrupts = <4>;
1650
1651                                 assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
1652                                                   <&mmcc PCLK0_CLK_SRC>;
1653                                 assigned-clock-parents = <&mdss_dsi0_phy 0>,
1654                                                          <&mdss_dsi0_phy 1>;
1655
1656                                 clocks = <&mmcc MDSS_MDP_CLK>,
1657                                          <&mmcc MDSS_BYTE0_CLK>,
1658                                          <&mmcc MDSS_BYTE0_INTF_CLK>,
1659                                          <&mmcc MNOC_AHB_CLK>,
1660                                          <&mmcc MDSS_AHB_CLK>,
1661                                          <&mmcc MDSS_AXI_CLK>,
1662                                          <&mmcc MISC_AHB_CLK>,
1663                                          <&mmcc MDSS_PCLK0_CLK>,
1664                                          <&mmcc MDSS_ESC0_CLK>;
1665                                 clock-names = "mdp_core",
1666                                               "byte",
1667                                               "byte_intf",
1668                                               "mnoc",
1669                                               "iface",
1670                                               "bus",
1671                                               "core_mmss",
1672                                               "pixel",
1673                                               "core";
1674
1675                                 phys = <&mdss_dsi0_phy>;
1676
1677                                 status = "disabled";
1678
1679                                 ports {
1680                                         #address-cells = <1>;
1681                                         #size-cells = <0>;
1682
1683                                         port@0 {
1684                                                 reg = <0>;
1685                                                 mdss_dsi0_in: endpoint {
1686                                                         remote-endpoint = <&mdp5_intf1_out>;
1687                                                 };
1688                                         };
1689
1690                                         port@1 {
1691                                                 reg = <1>;
1692                                                 mdss_dsi0_out: endpoint {
1693                                                 };
1694                                         };
1695                                 };
1696                         };
1697
1698                         mdss_dsi0_phy: phy@c994400 {
1699                                 compatible = "qcom,dsi-phy-14nm-660";
1700                                 reg = <0x0c994400 0x100>,
1701                                       <0x0c994500 0x300>,
1702                                       <0x0c994800 0x188>;
1703                                 reg-names = "dsi_phy",
1704                                             "dsi_phy_lane",
1705                                             "dsi_pll";
1706
1707                                 #clock-cells = <1>;
1708                                 #phy-cells = <0>;
1709
1710                                 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
1711                                 clock-names = "iface", "ref";
1712                                 status = "disabled";
1713                         };
1714                 };
1715
1716                 blsp1_dma: dma-controller@c144000 {
1717                         compatible = "qcom,bam-v1.7.0";
1718                         reg = <0x0c144000 0x1f000>;
1719                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1720                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
1721                         clock-names = "bam_clk";
1722                         #dma-cells = <1>;
1723                         qcom,ee = <0>;
1724                         qcom,controlled-remotely;
1725                         num-channels = <18>;
1726                         qcom,num-ees = <4>;
1727                 };
1728
1729                 blsp1_uart1: serial@c16f000 {
1730                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1731                         reg = <0x0c16f000 0x200>;
1732                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1733                         clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
1734                                  <&gcc GCC_BLSP1_AHB_CLK>;
1735                         clock-names = "core", "iface";
1736                         dmas = <&blsp1_dma 0>, <&blsp1_dma 1>;
1737                         dma-names = "tx", "rx";
1738                         pinctrl-names = "default", "sleep";
1739                         pinctrl-0 = <&blsp1_uart1_default>;
1740                         pinctrl-1 = <&blsp1_uart1_sleep>;
1741                         status = "disabled";
1742                 };
1743
1744                 blsp1_uart2: serial@c170000 {
1745                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1746                         reg = <0x0c170000 0x1000>;
1747                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1748                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
1749                                  <&gcc GCC_BLSP1_AHB_CLK>;
1750                         clock-names = "core", "iface";
1751                         dmas = <&blsp1_dma 2>, <&blsp1_dma 3>;
1752                         dma-names = "tx", "rx";
1753                         pinctrl-names = "default";
1754                         pinctrl-0 = <&blsp1_uart2_default>;
1755                         status = "disabled";
1756                 };
1757
1758                 blsp_i2c1: i2c@c175000 {
1759                         compatible = "qcom,i2c-qup-v2.2.1";
1760                         reg = <0x0c175000 0x600>;
1761                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1762
1763                         clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
1764                                         <&gcc GCC_BLSP1_AHB_CLK>;
1765                         clock-names = "core", "iface";
1766                         clock-frequency = <400000>;
1767                         dmas = <&blsp1_dma 4>, <&blsp1_dma 5>;
1768                         dma-names = "tx", "rx";
1769
1770                         pinctrl-names = "default", "sleep";
1771                         pinctrl-0 = <&i2c1_default>;
1772                         pinctrl-1 = <&i2c1_sleep>;
1773                         #address-cells = <1>;
1774                         #size-cells = <0>;
1775                         status = "disabled";
1776                 };
1777
1778                 blsp_i2c2: i2c@c176000 {
1779                         compatible = "qcom,i2c-qup-v2.2.1";
1780                         reg = <0x0c176000 0x600>;
1781                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1782
1783                         clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
1784                                  <&gcc GCC_BLSP1_AHB_CLK>;
1785                         clock-names = "core", "iface";
1786                         clock-frequency = <400000>;
1787                         dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
1788                         dma-names = "tx", "rx";
1789
1790                         pinctrl-names = "default", "sleep";
1791                         pinctrl-0 = <&i2c2_default>;
1792                         pinctrl-1 = <&i2c2_sleep>;
1793                         #address-cells = <1>;
1794                         #size-cells = <0>;
1795                         status = "disabled";
1796                 };
1797
1798                 blsp_i2c3: i2c@c177000 {
1799                         compatible = "qcom,i2c-qup-v2.2.1";
1800                         reg = <0x0c177000 0x600>;
1801                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1802
1803                         clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
1804                                  <&gcc GCC_BLSP1_AHB_CLK>;
1805                         clock-names = "core", "iface";
1806                         clock-frequency = <400000>;
1807                         dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
1808                         dma-names = "tx", "rx";
1809
1810                         pinctrl-names = "default", "sleep";
1811                         pinctrl-0 = <&i2c3_default>;
1812                         pinctrl-1 = <&i2c3_sleep>;
1813                         #address-cells = <1>;
1814                         #size-cells = <0>;
1815                         status = "disabled";
1816                 };
1817
1818                 blsp_i2c4: i2c@c178000 {
1819                         compatible = "qcom,i2c-qup-v2.2.1";
1820                         reg = <0x0c178000 0x600>;
1821                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1822
1823                         clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
1824                                  <&gcc GCC_BLSP1_AHB_CLK>;
1825                         clock-names = "core", "iface";
1826                         clock-frequency = <400000>;
1827                         dmas = <&blsp1_dma 10>, <&blsp1_dma 11>;
1828                         dma-names = "tx", "rx";
1829
1830                         pinctrl-names = "default", "sleep";
1831                         pinctrl-0 = <&i2c4_default>;
1832                         pinctrl-1 = <&i2c4_sleep>;
1833                         #address-cells = <1>;
1834                         #size-cells = <0>;
1835                         status = "disabled";
1836                 };
1837
1838                 blsp2_dma: dma-controller@c184000 {
1839                         compatible = "qcom,bam-v1.7.0";
1840                         reg = <0x0c184000 0x1f000>;
1841                         interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
1842                         clocks = <&gcc GCC_BLSP2_AHB_CLK>;
1843                         clock-names = "bam_clk";
1844                         #dma-cells = <1>;
1845                         qcom,ee = <0>;
1846                         qcom,controlled-remotely;
1847                         num-channels = <18>;
1848                         qcom,num-ees = <4>;
1849                 };
1850
1851                 blsp2_uart1: serial@c1af000 {
1852                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1853                         reg = <0x0c1af000 0x200>;
1854                         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1855                         clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>,
1856                                  <&gcc GCC_BLSP2_AHB_CLK>;
1857                         clock-names = "core", "iface";
1858                         dmas = <&blsp2_dma 0>, <&blsp2_dma 1>;
1859                         dma-names = "tx", "rx";
1860                         pinctrl-names = "default", "sleep";
1861                         pinctrl-0 = <&blsp2_uart1_default>;
1862                         pinctrl-1 = <&blsp2_uart1_sleep>;
1863                         status = "disabled";
1864                 };
1865
1866                 blsp_i2c5: i2c@c1b5000 {
1867                         compatible = "qcom,i2c-qup-v2.2.1";
1868                         reg = <0x0c1b5000 0x600>;
1869                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1870
1871                         clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
1872                                  <&gcc GCC_BLSP2_AHB_CLK>;
1873                         clock-names = "core", "iface";
1874                         clock-frequency = <400000>;
1875                         dmas = <&blsp2_dma 4>, <&blsp2_dma 5>;
1876                         dma-names = "tx", "rx";
1877
1878                         pinctrl-names = "default", "sleep";
1879                         pinctrl-0 = <&i2c5_default>;
1880                         pinctrl-1 = <&i2c5_sleep>;
1881                         #address-cells = <1>;
1882                         #size-cells = <0>;
1883                         status = "disabled";
1884                 };
1885
1886                 blsp_i2c6: i2c@c1b6000 {
1887                         compatible = "qcom,i2c-qup-v2.2.1";
1888                         reg = <0x0c1b6000 0x600>;
1889                         interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1890
1891                         clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
1892                                  <&gcc GCC_BLSP2_AHB_CLK>;
1893                         clock-names = "core", "iface";
1894                         clock-frequency = <400000>;
1895                         dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
1896                         dma-names = "tx", "rx";
1897
1898                         pinctrl-names = "default", "sleep";
1899                         pinctrl-0 = <&i2c6_default>;
1900                         pinctrl-1 = <&i2c6_sleep>;
1901                         #address-cells = <1>;
1902                         #size-cells = <0>;
1903                         status = "disabled";
1904                 };
1905
1906                 blsp_i2c7: i2c@c1b7000 {
1907                         compatible = "qcom,i2c-qup-v2.2.1";
1908                         reg = <0x0c1b7000 0x600>;
1909                         interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1910
1911                         clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
1912                                  <&gcc GCC_BLSP2_AHB_CLK>;
1913                         clock-names = "core", "iface";
1914                         clock-frequency = <400000>;
1915                         dmas = <&blsp2_dma 8>, <&blsp2_dma 9>;
1916                         dma-names = "tx", "rx";
1917
1918                         pinctrl-names = "default", "sleep";
1919                         pinctrl-0 = <&i2c7_default>;
1920                         pinctrl-1 = <&i2c7_sleep>;
1921                         #address-cells = <1>;
1922                         #size-cells = <0>;
1923                         status = "disabled";
1924                 };
1925
1926                 blsp_i2c8: i2c@c1b8000 {
1927                         compatible = "qcom,i2c-qup-v2.2.1";
1928                         reg = <0x0c1b8000 0x600>;
1929                         interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1930
1931                         clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
1932                                  <&gcc GCC_BLSP2_AHB_CLK>;
1933                         clock-names = "core", "iface";
1934                         clock-frequency = <400000>;
1935                         dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
1936                         dma-names = "tx", "rx";
1937
1938                         pinctrl-names = "default", "sleep";
1939                         pinctrl-0 = <&i2c8_default>;
1940                         pinctrl-1 = <&i2c8_sleep>;
1941                         #address-cells = <1>;
1942                         #size-cells = <0>;
1943                         status = "disabled";
1944                 };
1945
1946                 sram@146bf000 {
1947                         compatible = "qcom,sdm630-imem", "syscon", "simple-mfd";
1948                         reg = <0x146bf000 0x1000>;
1949
1950                         #address-cells = <1>;
1951                         #size-cells = <1>;
1952
1953                         ranges = <0 0x146bf000 0x1000>;
1954
1955                         pil-reloc@94c {
1956                                 compatible = "qcom,pil-reloc-info";
1957                                 reg = <0x94c 0xc8>;
1958                         };
1959                 };
1960
1961                 camss: camss@ca00020 {
1962                         compatible = "qcom,sdm660-camss";
1963                         reg = <0x0ca00020 0x10>,
1964                               <0x0ca30000 0x100>,
1965                               <0x0ca30400 0x100>,
1966                               <0x0ca30800 0x100>,
1967                               <0x0ca30c00 0x100>,
1968                               <0x0c824000 0x1000>,
1969                               <0x0ca00120 0x4>,
1970                               <0x0c825000 0x1000>,
1971                               <0x0ca00124 0x4>,
1972                               <0x0c826000 0x1000>,
1973                               <0x0ca00128 0x4>,
1974                               <0x0ca31000 0x500>,
1975                               <0x0ca10000 0x1000>,
1976                               <0x0ca14000 0x1000>;
1977                         reg-names = "csi_clk_mux",
1978                                     "csid0",
1979                                     "csid1",
1980                                     "csid2",
1981                                     "csid3",
1982                                     "csiphy0",
1983                                     "csiphy0_clk_mux",
1984                                     "csiphy1",
1985                                     "csiphy1_clk_mux",
1986                                     "csiphy2",
1987                                     "csiphy2_clk_mux",
1988                                     "ispif",
1989                                     "vfe0",
1990                                     "vfe1";
1991                         interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
1992                                      <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
1993                                      <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
1994                                      <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
1995                                      <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
1996                                      <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
1997                                      <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
1998                                      <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
1999                                      <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
2000                                      <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>;
2001                         interrupt-names = "csid0",
2002                                           "csid1",
2003                                           "csid2",
2004                                           "csid3",
2005                                           "csiphy0",
2006                                           "csiphy1",
2007                                           "csiphy2",
2008                                           "ispif",
2009                                           "vfe0",
2010                                           "vfe1";
2011                         clocks = <&mmcc CAMSS_AHB_CLK>,
2012                                  <&mmcc CAMSS_CPHY_CSID0_CLK>,
2013                                  <&mmcc CAMSS_CPHY_CSID1_CLK>,
2014                                  <&mmcc CAMSS_CPHY_CSID2_CLK>,
2015                                  <&mmcc CAMSS_CPHY_CSID3_CLK>,
2016                                  <&mmcc CAMSS_CSI0_AHB_CLK>,
2017                                  <&mmcc CAMSS_CSI0_CLK>,
2018                                  <&mmcc CAMSS_CPHY_CSID0_CLK>,
2019                                  <&mmcc CAMSS_CSI0PIX_CLK>,
2020                                  <&mmcc CAMSS_CSI0RDI_CLK>,
2021                                  <&mmcc CAMSS_CSI1_AHB_CLK>,
2022                                  <&mmcc CAMSS_CSI1_CLK>,
2023                                  <&mmcc CAMSS_CPHY_CSID1_CLK>,
2024                                  <&mmcc CAMSS_CSI1PIX_CLK>,
2025                                  <&mmcc CAMSS_CSI1RDI_CLK>,
2026                                  <&mmcc CAMSS_CSI2_AHB_CLK>,
2027                                  <&mmcc CAMSS_CSI2_CLK>,
2028                                  <&mmcc CAMSS_CPHY_CSID2_CLK>,
2029                                  <&mmcc CAMSS_CSI2PIX_CLK>,
2030                                  <&mmcc CAMSS_CSI2RDI_CLK>,
2031                                  <&mmcc CAMSS_CSI3_AHB_CLK>,
2032                                  <&mmcc CAMSS_CSI3_CLK>,
2033                                  <&mmcc CAMSS_CPHY_CSID3_CLK>,
2034                                  <&mmcc CAMSS_CSI3PIX_CLK>,
2035                                  <&mmcc CAMSS_CSI3RDI_CLK>,
2036                                  <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
2037                                  <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
2038                                  <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
2039                                  <&mmcc CSIPHY_AHB2CRIF_CLK>,
2040                                  <&mmcc CAMSS_CSI_VFE0_CLK>,
2041                                  <&mmcc CAMSS_CSI_VFE1_CLK>,
2042                                  <&mmcc CAMSS_ISPIF_AHB_CLK>,
2043                                  <&mmcc THROTTLE_CAMSS_AXI_CLK>,
2044                                  <&mmcc CAMSS_TOP_AHB_CLK>,
2045                                  <&mmcc CAMSS_VFE0_AHB_CLK>,
2046                                  <&mmcc CAMSS_VFE0_CLK>,
2047                                  <&mmcc CAMSS_VFE0_STREAM_CLK>,
2048                                  <&mmcc CAMSS_VFE1_AHB_CLK>,
2049                                  <&mmcc CAMSS_VFE1_CLK>,
2050                                  <&mmcc CAMSS_VFE1_STREAM_CLK>,
2051                                  <&mmcc CAMSS_VFE_VBIF_AHB_CLK>,
2052                                  <&mmcc CAMSS_VFE_VBIF_AXI_CLK>;
2053                         clock-names = "ahb",
2054                                       "cphy_csid0",
2055                                       "cphy_csid1",
2056                                       "cphy_csid2",
2057                                       "cphy_csid3",
2058                                       "csi0_ahb",
2059                                       "csi0",
2060                                       "csi0_phy",
2061                                       "csi0_pix",
2062                                       "csi0_rdi",
2063                                       "csi1_ahb",
2064                                       "csi1",
2065                                       "csi1_phy",
2066                                       "csi1_pix",
2067                                       "csi1_rdi",
2068                                       "csi2_ahb",
2069                                       "csi2",
2070                                       "csi2_phy",
2071                                       "csi2_pix",
2072                                       "csi2_rdi",
2073                                       "csi3_ahb",
2074                                       "csi3",
2075                                       "csi3_phy",
2076                                       "csi3_pix",
2077                                       "csi3_rdi",
2078                                       "csiphy0_timer",
2079                                       "csiphy1_timer",
2080                                       "csiphy2_timer",
2081                                       "csiphy_ahb2crif",
2082                                       "csi_vfe0",
2083                                       "csi_vfe1",
2084                                       "ispif_ahb",
2085                                       "throttle_axi",
2086                                       "top_ahb",
2087                                       "vfe0_ahb",
2088                                       "vfe0",
2089                                       "vfe0_stream",
2090                                       "vfe1_ahb",
2091                                       "vfe1",
2092                                       "vfe1_stream",
2093                                       "vfe_ahb",
2094                                       "vfe_axi";
2095                         interconnects = <&mnoc 5 &bimc 5>;
2096                         interconnect-names = "vfe-mem";
2097                         iommus = <&mmss_smmu 0xc00>,
2098                                  <&mmss_smmu 0xc01>,
2099                                  <&mmss_smmu 0xc02>,
2100                                  <&mmss_smmu 0xc03>;
2101                         power-domains = <&mmcc CAMSS_VFE0_GDSC>,
2102                                         <&mmcc CAMSS_VFE1_GDSC>;
2103                         status = "disabled";
2104
2105                         ports {
2106                                 #address-cells = <1>;
2107                                 #size-cells = <0>;
2108                         };
2109                 };
2110
2111                 cci: cci@ca0c000 {
2112                         compatible = "qcom,msm8996-cci";
2113                         #address-cells = <1>;
2114                         #size-cells = <0>;
2115                         reg = <0x0ca0c000 0x1000>;
2116                         interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>;
2117
2118                         assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
2119                                           <&mmcc CAMSS_CCI_CLK>;
2120                         assigned-clock-rates = <80800000>, <37500000>;
2121                         clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
2122                                  <&mmcc CAMSS_CCI_AHB_CLK>,
2123                                  <&mmcc CAMSS_CCI_CLK>,
2124                                  <&mmcc CAMSS_AHB_CLK>;
2125                         clock-names = "camss_top_ahb",
2126                                       "cci_ahb",
2127                                       "cci",
2128                                       "camss_ahb";
2129
2130                         pinctrl-names = "default";
2131                         pinctrl-0 = <&cci0_default &cci1_default>;
2132                         power-domains = <&mmcc CAMSS_TOP_GDSC>;
2133                         status = "disabled";
2134
2135                         cci_i2c0: i2c-bus@0 {
2136                                 reg = <0>;
2137                                 clock-frequency = <400000>;
2138                                 #address-cells = <1>;
2139                                 #size-cells = <0>;
2140                         };
2141
2142                         cci_i2c1: i2c-bus@1 {
2143                                 reg = <1>;
2144                                 clock-frequency = <400000>;
2145                                 #address-cells = <1>;
2146                                 #size-cells = <0>;
2147                         };
2148                 };
2149
2150                 venus: video-codec@cc00000 {
2151                         compatible = "qcom,sdm660-venus";
2152                         reg = <0x0cc00000 0xff000>;
2153                         clocks = <&mmcc VIDEO_CORE_CLK>,
2154                                  <&mmcc VIDEO_AHB_CLK>,
2155                                  <&mmcc VIDEO_AXI_CLK>,
2156                                  <&mmcc THROTTLE_VIDEO_AXI_CLK>;
2157                         clock-names = "core", "iface", "bus", "bus_throttle";
2158                         interconnects = <&gnoc 0 &mnoc 13>,
2159                                         <&mnoc 4 &bimc 5>;
2160                         interconnect-names = "cpu-cfg", "video-mem";
2161                         interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
2162                         iommus = <&mmss_smmu 0x400>,
2163                                  <&mmss_smmu 0x401>,
2164                                  <&mmss_smmu 0x40a>,
2165                                  <&mmss_smmu 0x407>,
2166                                  <&mmss_smmu 0x40e>,
2167                                  <&mmss_smmu 0x40f>,
2168                                  <&mmss_smmu 0x408>,
2169                                  <&mmss_smmu 0x409>,
2170                                  <&mmss_smmu 0x40b>,
2171                                  <&mmss_smmu 0x40c>,
2172                                  <&mmss_smmu 0x40d>,
2173                                  <&mmss_smmu 0x410>,
2174                                  <&mmss_smmu 0x421>,
2175                                  <&mmss_smmu 0x428>,
2176                                  <&mmss_smmu 0x429>,
2177                                  <&mmss_smmu 0x42b>,
2178                                  <&mmss_smmu 0x42c>,
2179                                  <&mmss_smmu 0x42d>,
2180                                  <&mmss_smmu 0x411>,
2181                                  <&mmss_smmu 0x431>;
2182                         memory-region = <&venus_region>;
2183                         power-domains = <&mmcc VENUS_GDSC>;
2184                         status = "disabled";
2185
2186                         video-decoder {
2187                                 compatible = "venus-decoder";
2188                                 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
2189                                 clock-names = "vcodec0_core";
2190                                 power-domains = <&mmcc VENUS_CORE0_GDSC>;
2191                         };
2192
2193                         video-encoder {
2194                                 compatible = "venus-encoder";
2195                                 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
2196                                 clock-names = "vcodec0_core";
2197                                 power-domains = <&mmcc VENUS_CORE0_GDSC>;
2198                         };
2199                 };
2200
2201                 mmss_smmu: iommu@cd00000 {
2202                         compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2";
2203                         reg = <0x0cd00000 0x40000>;
2204
2205                         clocks = <&mmcc MNOC_AHB_CLK>,
2206                                  <&mmcc BIMC_SMMU_AHB_CLK>,
2207                                  <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK>,
2208                                  <&mmcc BIMC_SMMU_AXI_CLK>;
2209                         clock-names = "iface-mm", "iface-smmu",
2210                                       "bus-mm", "bus-smmu";
2211                         #global-interrupts = <2>;
2212                         #iommu-cells = <1>;
2213
2214                         interrupts =
2215                                 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
2216                                 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
2217
2218                                 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
2219                                 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
2220                                 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
2221                                 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
2222                                 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
2223                                 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
2224                                 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
2225                                 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
2226                                 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
2227                                 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
2228                                 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
2229                                 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
2230                                 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
2231                                 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
2232                                 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
2233                                 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
2234                                 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
2235                                 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
2236                                 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
2237                                 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
2238                                 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
2239                                 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
2240                                 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
2241                                 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
2242
2243                         status = "disabled";
2244                 };
2245
2246                 adsp_pil: remoteproc@15700000 {
2247                         compatible = "qcom,sdm660-adsp-pas";
2248                         reg = <0x15700000 0x4040>;
2249
2250                         interrupts-extended =
2251                                 <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
2252                                 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2253                                 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2254                                 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2255                                 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2256                         interrupt-names = "wdog", "fatal", "ready",
2257                                           "handover", "stop-ack";
2258
2259                         clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
2260                         clock-names = "xo";
2261
2262                         memory-region = <&adsp_region>;
2263                         power-domains = <&rpmpd SDM660_VDDCX>;
2264                         power-domain-names = "cx";
2265
2266                         qcom,smem-states = <&adsp_smp2p_out 0>;
2267                         qcom,smem-state-names = "stop";
2268
2269                         glink-edge {
2270                                 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
2271
2272                                 label = "lpass";
2273                                 mboxes = <&apcs_glb 9>;
2274                                 qcom,remote-pid = <2>;
2275
2276                                 apr {
2277                                         compatible = "qcom,apr-v2";
2278                                         qcom,glink-channels = "apr_audio_svc";
2279                                         qcom,domain = <APR_DOMAIN_ADSP>;
2280                                         #address-cells = <1>;
2281                                         #size-cells = <0>;
2282
2283                                         service@3 {
2284                                                 reg = <APR_SVC_ADSP_CORE>;
2285                                                 compatible = "qcom,q6core";
2286                                         };
2287
2288                                         q6afe: service@4 {
2289                                                 compatible = "qcom,q6afe";
2290                                                 reg = <APR_SVC_AFE>;
2291                                                 q6afedai: dais {
2292                                                         compatible = "qcom,q6afe-dais";
2293                                                         #address-cells = <1>;
2294                                                         #size-cells = <0>;
2295                                                         #sound-dai-cells = <1>;
2296                                                 };
2297                                         };
2298
2299                                         q6asm: service@7 {
2300                                                 compatible = "qcom,q6asm";
2301                                                 reg = <APR_SVC_ASM>;
2302                                                 q6asmdai: dais {
2303                                                         compatible = "qcom,q6asm-dais";
2304                                                         #address-cells = <1>;
2305                                                         #size-cells = <0>;
2306                                                         #sound-dai-cells = <1>;
2307                                                         iommus = <&lpass_smmu 1>;
2308                                                 };
2309                                         };
2310
2311                                         q6adm: service@8 {
2312                                                 compatible = "qcom,q6adm";
2313                                                 reg = <APR_SVC_ADM>;
2314                                                 q6routing: routing {
2315                                                         compatible = "qcom,q6adm-routing";
2316                                                         #sound-dai-cells = <0>;
2317                                                 };
2318                                         };
2319                                 };
2320                         };
2321                 };
2322
2323                 gnoc: interconnect@17900000 {
2324                         compatible = "qcom,sdm660-gnoc";
2325                         reg = <0x17900000 0xe000>;
2326                         #interconnect-cells = <1>;
2327                         /*
2328                          * This one apparently features no clocks,
2329                          * so let's not mess with the driver needlessly
2330                          */
2331                         clock-names = "bus", "bus_a";
2332                         clocks = <&xo_board>, <&xo_board>;
2333                 };
2334
2335                 apcs_glb: mailbox@17911000 {
2336                         compatible = "qcom,sdm660-apcs-hmss-global",
2337                                      "qcom,msm8994-apcs-kpss-global";
2338                         reg = <0x17911000 0x1000>;
2339
2340                         #mbox-cells = <1>;
2341                 };
2342
2343                 timer@17920000 {
2344                         #address-cells = <1>;
2345                         #size-cells = <1>;
2346                         ranges;
2347                         compatible = "arm,armv7-timer-mem";
2348                         reg = <0x17920000 0x1000>;
2349                         clock-frequency = <19200000>;
2350
2351                         frame@17921000 {
2352                                 frame-number = <0>;
2353                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
2354                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
2355                                 reg = <0x17921000 0x1000>,
2356                                         <0x17922000 0x1000>;
2357                         };
2358
2359                         frame@17923000 {
2360                                 frame-number = <1>;
2361                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
2362                                 reg = <0x17923000 0x1000>;
2363                                 status = "disabled";
2364                         };
2365
2366                         frame@17924000 {
2367                                 frame-number = <2>;
2368                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
2369                                 reg = <0x17924000 0x1000>;
2370                                 status = "disabled";
2371                         };
2372
2373                         frame@17925000 {
2374                                 frame-number = <3>;
2375                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
2376                                 reg = <0x17925000 0x1000>;
2377                                 status = "disabled";
2378                         };
2379
2380                         frame@17926000 {
2381                                 frame-number = <4>;
2382                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
2383                                 reg = <0x17926000 0x1000>;
2384                                 status = "disabled";
2385                         };
2386
2387                         frame@17927000 {
2388                                 frame-number = <5>;
2389                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
2390                                 reg = <0x17927000 0x1000>;
2391                                 status = "disabled";
2392                         };
2393
2394                         frame@17928000 {
2395                                 frame-number = <6>;
2396                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
2397                                 reg = <0x17928000 0x1000>;
2398                                 status = "disabled";
2399                         };
2400                 };
2401
2402                 intc: interrupt-controller@17a00000 {
2403                         compatible = "arm,gic-v3";
2404                         reg = <0x17a00000 0x10000>,        /* GICD */
2405                                   <0x17b00000 0x100000>;          /* GICR * 8 */
2406                         #interrupt-cells = <3>;
2407                         #address-cells = <1>;
2408                         #size-cells = <1>;
2409                         ranges;
2410                         interrupt-controller;
2411                         #redistributor-regions = <1>;
2412                         redistributor-stride = <0x0 0x20000>;
2413                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
2414                 };
2415         };
2416
2417         sound: sound {
2418         };
2419
2420         thermal-zones {
2421                 aoss-thermal {
2422                         polling-delay-passive = <250>;
2423                         polling-delay = <1000>;
2424
2425                         thermal-sensors = <&tsens 0>;
2426
2427                         trips {
2428                                 aoss_alert0: trip-point0 {
2429                                         temperature = <105000>;
2430                                         hysteresis = <1000>;
2431                                         type = "hot";
2432                                 };
2433                         };
2434                 };
2435
2436                 cpuss0-thermal {
2437                         polling-delay-passive = <250>;
2438                         polling-delay = <1000>;
2439
2440                         thermal-sensors = <&tsens 1>;
2441
2442                         trips {
2443                                 cpuss0_alert0: trip-point0 {
2444                                         temperature = <125000>;
2445                                         hysteresis = <1000>;
2446                                         type = "hot";
2447                                 };
2448                         };
2449                 };
2450
2451                 cpuss1-thermal {
2452                         polling-delay-passive = <250>;
2453                         polling-delay = <1000>;
2454
2455                         thermal-sensors = <&tsens 2>;
2456
2457                         trips {
2458                                 cpuss1_alert0: trip-point0 {
2459                                         temperature = <125000>;
2460                                         hysteresis = <1000>;
2461                                         type = "hot";
2462                                 };
2463                         };
2464                 };
2465
2466                 cpu0-thermal {
2467                         polling-delay-passive = <250>;
2468                         polling-delay = <1000>;
2469
2470                         thermal-sensors = <&tsens 3>;
2471
2472                         trips {
2473                                 cpu0_alert0: trip-point0 {
2474                                         temperature = <70000>;
2475                                         hysteresis = <1000>;
2476                                         type = "passive";
2477                                 };
2478
2479                                 cpu0_crit: cpu-crit {
2480                                         temperature = <110000>;
2481                                         hysteresis = <1000>;
2482                                         type = "critical";
2483                                 };
2484                         };
2485                 };
2486
2487                 cpu1-thermal {
2488                         polling-delay-passive = <250>;
2489                         polling-delay = <1000>;
2490
2491                         thermal-sensors = <&tsens 4>;
2492
2493                         trips {
2494                                 cpu1_alert0: trip-point0 {
2495                                         temperature = <70000>;
2496                                         hysteresis = <1000>;
2497                                         type = "passive";
2498                                 };
2499
2500                                 cpu1_crit: cpu-crit {
2501                                         temperature = <110000>;
2502                                         hysteresis = <1000>;
2503                                         type = "critical";
2504                                 };
2505                         };
2506                 };
2507
2508                 cpu2-thermal {
2509                         polling-delay-passive = <250>;
2510                         polling-delay = <1000>;
2511
2512                         thermal-sensors = <&tsens 5>;
2513
2514                         trips {
2515                                 cpu2_alert0: trip-point0 {
2516                                         temperature = <70000>;
2517                                         hysteresis = <1000>;
2518                                         type = "passive";
2519                                 };
2520
2521                                 cpu2_crit: cpu-crit {
2522                                         temperature = <110000>;
2523                                         hysteresis = <1000>;
2524                                         type = "critical";
2525                                 };
2526                         };
2527                 };
2528
2529                 cpu3-thermal {
2530                         polling-delay-passive = <250>;
2531                         polling-delay = <1000>;
2532
2533                         thermal-sensors = <&tsens 6>;
2534
2535                         trips {
2536                                 cpu3_alert0: trip-point0 {
2537                                         temperature = <70000>;
2538                                         hysteresis = <1000>;
2539                                         type = "passive";
2540                                 };
2541
2542                                 cpu3_crit: cpu-crit {
2543                                         temperature = <110000>;
2544                                         hysteresis = <1000>;
2545                                         type = "critical";
2546                                 };
2547                         };
2548                 };
2549
2550                 /*
2551                  * According to what downstream DTS says,
2552                  * the entire power efficient cluster has
2553                  * only a single thermal sensor.
2554                  */
2555
2556                 pwr-cluster-thermal {
2557                         polling-delay-passive = <250>;
2558                         polling-delay = <1000>;
2559
2560                         thermal-sensors = <&tsens 7>;
2561
2562                         trips {
2563                                 pwr_cluster_alert0: trip-point0 {
2564                                         temperature = <70000>;
2565                                         hysteresis = <1000>;
2566                                         type = "passive";
2567                                 };
2568
2569                                 pwr_cluster_crit: cpu-crit {
2570                                         temperature = <110000>;
2571                                         hysteresis = <1000>;
2572                                         type = "critical";
2573                                 };
2574                         };
2575                 };
2576
2577                 gpu-thermal {
2578                         polling-delay-passive = <250>;
2579                         polling-delay = <1000>;
2580
2581                         thermal-sensors = <&tsens 8>;
2582
2583                         trips {
2584                                 gpu_alert0: trip-point0 {
2585                                         temperature = <90000>;
2586                                         hysteresis = <1000>;
2587                                         type = "hot";
2588                                 };
2589                         };
2590                 };
2591         };
2592
2593         timer {
2594                 compatible = "arm,armv8-timer";
2595                 interrupts = <GIC_PPI 1 0xf08>,
2596                                  <GIC_PPI 2 0xf08>,
2597                                  <GIC_PPI 3 0xf08>,
2598                                  <GIC_PPI 0 0xf08>;
2599         };
2600 };
2601