arch/arm64/boot/dts/qcom/sc7180.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * SC7180 SoC device tree source
   4  *
   5  * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
   6  */
   7
   8 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
   9 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
  10 #include <dt-bindings/clock/qcom,gpucc-sc7180.h>
  11 #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
  12 #include <dt-bindings/clock/qcom,rpmh.h>
  13 #include <dt-bindings/clock/qcom,videocc-sc7180.h>
  14 #include <dt-bindings/interconnect/qcom,osm-l3.h>
  15 #include <dt-bindings/interconnect/qcom,sc7180.h>
  16 #include <dt-bindings/interrupt-controller/arm-gic.h>
  17 #include <dt-bindings/phy/phy-qcom-qusb2.h>
  18 #include <dt-bindings/power/qcom-rpmpd.h>
  19 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
  20 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
  21 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  22 #include <dt-bindings/thermal/thermal.h>
  23
  24 / {
  25         interrupt-parent = <&intc>;
  26
  27         #address-cells = <2>;
  28         #size-cells = <2>;
  29
  30         chosen { };
  31
  32         aliases {
  33                 mmc1 = &sdhc_1;
  34                 mmc2 = &sdhc_2;
  35                 i2c0 = &i2c0;
  36                 i2c1 = &i2c1;
  37                 i2c2 = &i2c2;
  38                 i2c3 = &i2c3;
  39                 i2c4 = &i2c4;
  40                 i2c5 = &i2c5;
  41                 i2c6 = &i2c6;
  42                 i2c7 = &i2c7;
  43                 i2c8 = &i2c8;
  44                 i2c9 = &i2c9;
  45                 i2c10 = &i2c10;
  46                 i2c11 = &i2c11;
  47                 spi0 = &spi0;
  48                 spi1 = &spi1;
  49                 spi3 = &spi3;
  50                 spi5 = &spi5;
  51                 spi6 = &spi6;
  52                 spi8 = &spi8;
  53                 spi10 = &spi10;
  54                 spi11 = &spi11;
  55         };
  56
  57         clocks {
  58                 xo_board: xo-board {
  59                         compatible = "fixed-clock";
  60                         clock-frequency = <38400000>;
  61                         #clock-cells = <0>;
  62                 };
  63
  64                 sleep_clk: sleep-clk {
  65                         compatible = "fixed-clock";
  66                         clock-frequency = <32764>;
  67                         #clock-cells = <0>;
  68                 };
  69         };
  70
  71         reserved_memory: reserved-memory {
  72                 #address-cells = <2>;
  73                 #size-cells = <2>;
  74                 ranges;
  75
  76                 hyp_mem: memory@80000000 {
  77                         reg = <0x0 0x80000000 0x0 0x600000>;
  78                         no-map;
  79                 };
  80
  81                 xbl_mem: memory@80600000 {
  82                         reg = <0x0 0x80600000 0x0 0x200000>;
  83                         no-map;
  84                 };
  85
  86                 aop_mem: memory@80800000 {
  87                         reg = <0x0 0x80800000 0x0 0x20000>;
  88                         no-map;
  89                 };
  90
  91                 aop_cmd_db_mem: memory@80820000 {
  92                         reg = <0x0 0x80820000 0x0 0x20000>;
  93                         compatible = "qcom,cmd-db";
  94                         no-map;
  95                 };
  96
  97                 sec_apps_mem: memory@808ff000 {
  98                         reg = <0x0 0x808ff000 0x0 0x1000>;
  99                         no-map;
 100                 };
 101
 102                 smem_mem: memory@80900000 {
 103                         reg = <0x0 0x80900000 0x0 0x200000>;
 104                         no-map;
 105                 };
 106
 107                 tz_mem: memory@80b00000 {
 108                         reg = <0x0 0x80b00000 0x0 0x3900000>;
 109                         no-map;
 110                 };
 111
 112                 ipa_fw_mem: memory@8b700000 {
 113                         reg = <0 0x8b700000 0 0x10000>;
 114                         no-map;
 115                 };
 116
 117                 rmtfs_mem: memory@94600000 {
 118                         compatible = "qcom,rmtfs-mem";
 119                         reg = <0x0 0x94600000 0x0 0x200000>;
 120                         no-map;
 121
 122                         qcom,client-id = <1>;
 123                         qcom,vmid = <15>;
 124                 };
 125         };
 126
 127         cpus {
 128                 #address-cells = <2>;
 129                 #size-cells = <0>;
 130
 131                 CPU0: cpu@0 {
 132                         device_type = "cpu";
 133                         compatible = "qcom,kryo468";
 134                         reg = <0x0 0x0>;
 135                         enable-method = "psci";
 136                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 137                                            &LITTLE_CPU_SLEEP_1
 138                                            &CLUSTER_SLEEP_0>;
 139                         capacity-dmips-mhz = <415>;
 140                         dynamic-power-coefficient = <137>;
 141                         operating-points-v2 = <&cpu0_opp_table>;
 142                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 143                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 144                         next-level-cache = <&L2_0>;
 145                         #cooling-cells = <2>;
 146                         qcom,freq-domain = <&cpufreq_hw 0>;
 147                         L2_0: l2-cache {
 148                                 compatible = "cache";
 149                                 next-level-cache = <&L3_0>;
 150                                 L3_0: l3-cache {
 151                                         compatible = "cache";
 152                                 };
 153                         };
 154                 };
 155
 156                 CPU1: cpu@100 {
 157                         device_type = "cpu";
 158                         compatible = "qcom,kryo468";
 159                         reg = <0x0 0x100>;
 160                         enable-method = "psci";
 161                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 162                                            &LITTLE_CPU_SLEEP_1
 163                                            &CLUSTER_SLEEP_0>;
 164                         capacity-dmips-mhz = <415>;
 165                         dynamic-power-coefficient = <137>;
 166                         next-level-cache = <&L2_100>;
 167                         operating-points-v2 = <&cpu0_opp_table>;
 168                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 169                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 170                         #cooling-cells = <2>;
 171                         qcom,freq-domain = <&cpufreq_hw 0>;
 172                         L2_100: l2-cache {
 173                                 compatible = "cache";
 174                                 next-level-cache = <&L3_0>;
 175                         };
 176                 };
 177
 178                 CPU2: cpu@200 {
 179                         device_type = "cpu";
 180                         compatible = "qcom,kryo468";
 181                         reg = <0x0 0x200>;
 182                         enable-method = "psci";
 183                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 184                                            &LITTLE_CPU_SLEEP_1
 185                                            &CLUSTER_SLEEP_0>;
 186                         capacity-dmips-mhz = <415>;
 187                         dynamic-power-coefficient = <137>;
 188                         next-level-cache = <&L2_200>;
 189                         operating-points-v2 = <&cpu0_opp_table>;
 190                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 191                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 192                         #cooling-cells = <2>;
 193                         qcom,freq-domain = <&cpufreq_hw 0>;
 194                         L2_200: l2-cache {
 195                                 compatible = "cache";
 196                                 next-level-cache = <&L3_0>;
 197                         };
 198                 };
 199
 200                 CPU3: cpu@300 {
 201                         device_type = "cpu";
 202                         compatible = "qcom,kryo468";
 203                         reg = <0x0 0x300>;
 204                         enable-method = "psci";
 205                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 206                                            &LITTLE_CPU_SLEEP_1
 207                                            &CLUSTER_SLEEP_0>;
 208                         capacity-dmips-mhz = <415>;
 209                         dynamic-power-coefficient = <137>;
 210                         next-level-cache = <&L2_300>;
 211                         operating-points-v2 = <&cpu0_opp_table>;
 212                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 213                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 214                         #cooling-cells = <2>;
 215                         qcom,freq-domain = <&cpufreq_hw 0>;
 216                         L2_300: l2-cache {
 217                                 compatible = "cache";
 218                                 next-level-cache = <&L3_0>;
 219                         };
 220                 };
 221
 222                 CPU4: cpu@400 {
 223                         device_type = "cpu";
 224                         compatible = "qcom,kryo468";
 225                         reg = <0x0 0x400>;
 226                         enable-method = "psci";
 227                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 228                                            &LITTLE_CPU_SLEEP_1
 229                                            &CLUSTER_SLEEP_0>;
 230                         capacity-dmips-mhz = <415>;
 231                         dynamic-power-coefficient = <137>;
 232                         next-level-cache = <&L2_400>;
 233                         operating-points-v2 = <&cpu0_opp_table>;
 234                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 235                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 236                         #cooling-cells = <2>;
 237                         qcom,freq-domain = <&cpufreq_hw 0>;
 238                         L2_400: l2-cache {
 239                                 compatible = "cache";
 240                                 next-level-cache = <&L3_0>;
 241                         };
 242                 };
 243
 244                 CPU5: cpu@500 {
 245                         device_type = "cpu";
 246                         compatible = "qcom,kryo468";
 247                         reg = <0x0 0x500>;
 248                         enable-method = "psci";
 249                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 250                                            &LITTLE_CPU_SLEEP_1
 251                                            &CLUSTER_SLEEP_0>;
 252                         capacity-dmips-mhz = <415>;
 253                         dynamic-power-coefficient = <137>;
 254                         next-level-cache = <&L2_500>;
 255                         operating-points-v2 = <&cpu0_opp_table>;
 256                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 257                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 258                         #cooling-cells = <2>;
 259                         qcom,freq-domain = <&cpufreq_hw 0>;
 260                         L2_500: l2-cache {
 261                                 compatible = "cache";
 262                                 next-level-cache = <&L3_0>;
 263                         };
 264                 };
 265
 266                 CPU6: cpu@600 {
 267                         device_type = "cpu";
 268                         compatible = "qcom,kryo468";
 269                         reg = <0x0 0x600>;
 270                         enable-method = "psci";
 271                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 272                                            &BIG_CPU_SLEEP_1
 273                                            &CLUSTER_SLEEP_0>;
 274                         capacity-dmips-mhz = <1024>;
 275                         dynamic-power-coefficient = <480>;
 276                         next-level-cache = <&L2_600>;
 277                         operating-points-v2 = <&cpu6_opp_table>;
 278                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 279                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 280                         #cooling-cells = <2>;
 281                         qcom,freq-domain = <&cpufreq_hw 1>;
 282                         L2_600: l2-cache {
 283                                 compatible = "cache";
 284                                 next-level-cache = <&L3_0>;
 285                         };
 286                 };
 287
 288                 CPU7: cpu@700 {
 289                         device_type = "cpu";
 290                         compatible = "qcom,kryo468";
 291                         reg = <0x0 0x700>;
 292                         enable-method = "psci";
 293                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 294                                            &BIG_CPU_SLEEP_1
 295                                            &CLUSTER_SLEEP_0>;
 296                         capacity-dmips-mhz = <1024>;
 297                         dynamic-power-coefficient = <480>;
 298                         next-level-cache = <&L2_700>;
 299                         operating-points-v2 = <&cpu6_opp_table>;
 300                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 301                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 302                         #cooling-cells = <2>;
 303                         qcom,freq-domain = <&cpufreq_hw 1>;
 304                         L2_700: l2-cache {
 305                                 compatible = "cache";
 306                                 next-level-cache = <&L3_0>;
 307                         };
 308                 };
 309
 310                 cpu-map {
 311                         cluster0 {
 312                                 core0 {
 313                                         cpu = <&CPU0>;
 314                                 };
 315
 316                                 core1 {
 317                                         cpu = <&CPU1>;
 318                                 };
 319
 320                                 core2 {
 321                                         cpu = <&CPU2>;
 322                                 };
 323
 324                                 core3 {
 325                                         cpu = <&CPU3>;
 326                                 };
 327
 328                                 core4 {
 329                                         cpu = <&CPU4>;
 330                                 };
 331
 332                                 core5 {
 333                                         cpu = <&CPU5>;
 334                                 };
 335
 336                                 core6 {
 337                                         cpu = <&CPU6>;
 338                                 };
 339
 340                                 core7 {
 341                                         cpu = <&CPU7>;
 342                                 };
 343                         };
 344                 };
 345
 346                 idle-states {
 347                         entry-method = "psci";
 348
 349                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 350                                 compatible = "arm,idle-state";
 351                                 idle-state-name = "little-power-down";
 352                                 arm,psci-suspend-param = <0x40000003>;
 353                                 entry-latency-us = <549>;
 354                                 exit-latency-us = <901>;
 355                                 min-residency-us = <1774>;
 356                                 local-timer-stop;
 357                         };
 358
 359                         LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
 360                                 compatible = "arm,idle-state";
 361                                 idle-state-name = "little-rail-power-down";
 362                                 arm,psci-suspend-param = <0x40000004>;
 363                                 entry-latency-us = <702>;
 364                                 exit-latency-us = <915>;
 365                                 min-residency-us = <4001>;
 366                                 local-timer-stop;
 367                         };
 368
 369                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 370                                 compatible = "arm,idle-state";
 371                                 idle-state-name = "big-power-down";
 372                                 arm,psci-suspend-param = <0x40000003>;
 373                                 entry-latency-us = <523>;
 374                                 exit-latency-us = <1244>;
 375                                 min-residency-us = <2207>;
 376                                 local-timer-stop;
 377                         };
 378
 379                         BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
 380                                 compatible = "arm,idle-state";
 381                                 idle-state-name = "big-rail-power-down";
 382                                 arm,psci-suspend-param = <0x40000004>;
 383                                 entry-latency-us = <526>;
 384                                 exit-latency-us = <1854>;
 385                                 min-residency-us = <5555>;
 386                                 local-timer-stop;
 387                         };
 388
 389                         CLUSTER_SLEEP_0: cluster-sleep-0 {
 390                                 compatible = "arm,idle-state";
 391                                 idle-state-name = "cluster-power-down";
 392                                 arm,psci-suspend-param = <0x40003444>;
 393                                 entry-latency-us = <3263>;
 394                                 exit-latency-us = <6562>;
 395                                 min-residency-us = <9926>;
 396                                 local-timer-stop;
 397                         };
 398                 };
 399         };
 400
 401         cpu0_opp_table: opp-table-cpu0 {
 402                 compatible = "operating-points-v2";
 403                 opp-shared;
 404
 405                 cpu0_opp1: opp-300000000 {
 406                         opp-hz = /bits/ 64 <300000000>;
 407                         opp-peak-kBps = <1200000 4800000>;
 408                 };
 409
 410                 cpu0_opp2: opp-576000000 {
 411                         opp-hz = /bits/ 64 <576000000>;
 412                         opp-peak-kBps = <1200000 4800000>;
 413                 };
 414
 415                 cpu0_opp3: opp-768000000 {
 416                         opp-hz = /bits/ 64 <768000000>;
 417                         opp-peak-kBps = <1200000 4800000>;
 418                 };
 419
 420                 cpu0_opp4: opp-1017600000 {
 421                         opp-hz = /bits/ 64 <1017600000>;
 422                         opp-peak-kBps = <1804000 8908800>;
 423                 };
 424
 425                 cpu0_opp5: opp-1248000000 {
 426                         opp-hz = /bits/ 64 <1248000000>;
 427                         opp-peak-kBps = <2188000 12902400>;
 428                 };
 429
 430                 cpu0_opp6: opp-1324800000 {
 431                         opp-hz = /bits/ 64 <1324800000>;
 432                         opp-peak-kBps = <2188000 12902400>;
 433                 };
 434
 435                 cpu0_opp7: opp-1516800000 {
 436                         opp-hz = /bits/ 64 <1516800000>;
 437                         opp-peak-kBps = <3072000 15052800>;
 438                 };
 439
 440                 cpu0_opp8: opp-1612800000 {
 441                         opp-hz = /bits/ 64 <1612800000>;
 442                         opp-peak-kBps = <3072000 15052800>;
 443                 };
 444
 445                 cpu0_opp9: opp-1708800000 {
 446                         opp-hz = /bits/ 64 <1708800000>;
 447                         opp-peak-kBps = <3072000 15052800>;
 448                 };
 449
 450                 cpu0_opp10: opp-1804800000 {
 451                         opp-hz = /bits/ 64 <1804800000>;
 452                         opp-peak-kBps = <4068000 22425600>;
 453                 };
 454         };
 455
 456         cpu6_opp_table: opp-table-cpu6 {
 457                 compatible = "operating-points-v2";
 458                 opp-shared;
 459
 460                 cpu6_opp1: opp-300000000 {
 461                         opp-hz = /bits/ 64 <300000000>;
 462                         opp-peak-kBps = <2188000 8908800>;
 463                 };
 464
 465                 cpu6_opp2: opp-652800000 {
 466                         opp-hz = /bits/ 64 <652800000>;
 467                         opp-peak-kBps = <2188000 8908800>;
 468                 };
 469
 470                 cpu6_opp3: opp-825600000 {
 471                         opp-hz = /bits/ 64 <825600000>;
 472                         opp-peak-kBps = <2188000 8908800>;
 473                 };
 474
 475                 cpu6_opp4: opp-979200000 {
 476                         opp-hz = /bits/ 64 <979200000>;
 477                         opp-peak-kBps = <2188000 8908800>;
 478                 };
 479
 480                 cpu6_opp5: opp-1113600000 {
 481                         opp-hz = /bits/ 64 <1113600000>;
 482                         opp-peak-kBps = <2188000 8908800>;
 483                 };
 484
 485                 cpu6_opp6: opp-1267200000 {
 486                         opp-hz = /bits/ 64 <1267200000>;
 487                         opp-peak-kBps = <4068000 12902400>;
 488                 };
 489
 490                 cpu6_opp7: opp-1555200000 {
 491                         opp-hz = /bits/ 64 <1555200000>;
 492                         opp-peak-kBps = <4068000 15052800>;
 493                 };
 494
 495                 cpu6_opp8: opp-1708800000 {
 496                         opp-hz = /bits/ 64 <1708800000>;
 497                         opp-peak-kBps = <6220000 19353600>;
 498                 };
 499
 500                 cpu6_opp9: opp-1843200000 {
 501                         opp-hz = /bits/ 64 <1843200000>;
 502                         opp-peak-kBps = <6220000 19353600>;
 503                 };
 504
 505                 cpu6_opp10: opp-1900800000 {
 506                         opp-hz = /bits/ 64 <1900800000>;
 507                         opp-peak-kBps = <6220000 22425600>;
 508                 };
 509
 510                 cpu6_opp11: opp-1996800000 {
 511                         opp-hz = /bits/ 64 <1996800000>;
 512                         opp-peak-kBps = <6220000 22425600>;
 513                 };
 514
 515                 cpu6_opp12: opp-2112000000 {
 516                         opp-hz = /bits/ 64 <2112000000>;
 517                         opp-peak-kBps = <6220000 22425600>;
 518                 };
 519
 520                 cpu6_opp13: opp-2208000000 {
 521                         opp-hz = /bits/ 64 <2208000000>;
 522                         opp-peak-kBps = <7216000 22425600>;
 523                 };
 524
 525                 cpu6_opp14: opp-2323200000 {
 526                         opp-hz = /bits/ 64 <2323200000>;
 527                         opp-peak-kBps = <7216000 22425600>;
 528                 };
 529
 530                 cpu6_opp15: opp-2400000000 {
 531                         opp-hz = /bits/ 64 <2400000000>;
 532                         opp-peak-kBps = <8532000 23347200>;
 533                 };
 534
 535                 cpu6_opp16: opp-2553600000 {
 536                         opp-hz = /bits/ 64 <2553600000>;
 537                         opp-peak-kBps = <8532000 23347200>;
 538                 };
 539         };
 540
 541         memory@80000000 {
 542                 device_type = "memory";
 543                 /* We expect the bootloader to fill in the size */
 544                 reg = <0 0x80000000 0 0>;
 545         };
 546
 547         pmu {
 548                 compatible = "arm,armv8-pmuv3";
 549                 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
 550         };
 551
 552         firmware {
 553                 scm {
 554                         compatible = "qcom,scm-sc7180", "qcom,scm";
 555                 };
 556         };
 557
 558         smem {
 559                 compatible = "qcom,smem";
 560                 memory-region = <&smem_mem>;
 561                 hwlocks = <&tcsr_mutex 3>;
 562         };
 563
 564         smp2p-cdsp {
 565                 compatible = "qcom,smp2p";
 566                 qcom,smem = <94>, <432>;
 567
 568                 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
 569
 570                 mboxes = <&apss_shared 6>;
 571
 572                 qcom,local-pid = <0>;
 573                 qcom,remote-pid = <5>;
 574
 575                 cdsp_smp2p_out: master-kernel {
 576                         qcom,entry-name = "master-kernel";
 577                         #qcom,smem-state-cells = <1>;
 578                 };
 579
 580                 cdsp_smp2p_in: slave-kernel {
 581                         qcom,entry-name = "slave-kernel";
 582
 583                         interrupt-controller;
 584                         #interrupt-cells = <2>;
 585                 };
 586         };
 587
 588         smp2p-lpass {
 589                 compatible = "qcom,smp2p";
 590                 qcom,smem = <443>, <429>;
 591
 592                 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
 593
 594                 mboxes = <&apss_shared 10>;
 595
 596                 qcom,local-pid = <0>;
 597                 qcom,remote-pid = <2>;
 598
 599                 adsp_smp2p_out: master-kernel {
 600                         qcom,entry-name = "master-kernel";
 601                         #qcom,smem-state-cells = <1>;
 602                 };
 603
 604                 adsp_smp2p_in: slave-kernel {
 605                         qcom,entry-name = "slave-kernel";
 606
 607                         interrupt-controller;
 608                         #interrupt-cells = <2>;
 609                 };
 610         };
 611
 612         smp2p-mpss {
 613                 compatible = "qcom,smp2p";
 614                 qcom,smem = <435>, <428>;
 615                 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
 616                 mboxes = <&apss_shared 14>;
 617                 qcom,local-pid = <0>;
 618                 qcom,remote-pid = <1>;
 619
 620                 modem_smp2p_out: master-kernel {
 621                         qcom,entry-name = "master-kernel";
 622                         #qcom,smem-state-cells = <1>;
 623                 };
 624
 625                 modem_smp2p_in: slave-kernel {
 626                         qcom,entry-name = "slave-kernel";
 627                         interrupt-controller;
 628                         #interrupt-cells = <2>;
 629                 };
 630
 631                 ipa_smp2p_out: ipa-ap-to-modem {
 632                         qcom,entry-name = "ipa";
 633                         #qcom,smem-state-cells = <1>;
 634                 };
 635
 636                 ipa_smp2p_in: ipa-modem-to-ap {
 637                         qcom,entry-name = "ipa";
 638                         interrupt-controller;
 639                         #interrupt-cells = <2>;
 640                 };
 641         };
 642
 643         psci {
 644                 compatible = "arm,psci-1.0";
 645                 method = "smc";
 646         };
 647
 648         soc: soc@0 {
 649                 #address-cells = <2>;
 650                 #size-cells = <2>;
 651                 ranges = <0 0 0 0 0x10 0>;
 652                 dma-ranges = <0 0 0 0 0x10 0>;
 653                 compatible = "simple-bus";
 654
 655                 gcc: clock-controller@100000 {
 656                         compatible = "qcom,gcc-sc7180";
 657                         reg = <0 0x00100000 0 0x1f0000>;
 658                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 659                                  <&rpmhcc RPMH_CXO_CLK_A>,
 660                                  <&sleep_clk>;
 661                         clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
 662                         #clock-cells = <1>;
 663                         #reset-cells = <1>;
 664                         #power-domain-cells = <1>;
 665                         power-domains = <&rpmhpd SC7180_CX>;
 666                 };
 667
 668                 qfprom: efuse@784000 {
 669                         compatible = "qcom,sc7180-qfprom", "qcom,qfprom";
 670                         reg = <0 0x00784000 0 0x7a0>,
 671                               <0 0x00780000 0 0x7a0>,
 672                               <0 0x00782000 0 0x100>,
 673                               <0 0x00786000 0 0x1fff>;
 674
 675                         clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>;
 676                         clock-names = "core";
 677                         #address-cells = <1>;
 678                         #size-cells = <1>;
 679
 680                         qusb2p_hstx_trim: hstx-trim-primary@25b {
 681                                 reg = <0x25b 0x1>;
 682                                 bits = <1 3>;
 683                         };
 684
 685                         gpu_speed_bin: gpu_speed_bin@1d2 {
 686                                 reg = <0x1d2 0x2>;
 687                                 bits = <5 8>;
 688                         };
 689                 };
 690
 691                 sdhc_1: mmc@7c4000 {
 692                         compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
 693                         reg = <0 0x7c4000 0 0x1000>,
 694                                 <0 0x07c5000 0 0x1000>;
 695                         reg-names = "hc", "cqhci";
 696
 697                         iommus = <&apps_smmu 0x60 0x0>;
 698                         interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
 699                                         <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
 700                         interrupt-names = "hc_irq", "pwr_irq";
 701
 702                         clocks = <&gcc GCC_SDCC1_AHB_CLK>,
 703                                  <&gcc GCC_SDCC1_APPS_CLK>,
 704                                  <&rpmhcc RPMH_CXO_CLK>;
 705                         clock-names = "iface", "core", "xo";
 706                         interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>,
 707                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>;
 708                         interconnect-names = "sdhc-ddr","cpu-sdhc";
 709                         power-domains = <&rpmhpd SC7180_CX>;
 710                         operating-points-v2 = <&sdhc1_opp_table>;
 711
 712                         bus-width = <8>;
 713                         non-removable;
 714                         supports-cqe;
 715
 716                         mmc-ddr-1_8v;
 717                         mmc-hs200-1_8v;
 718                         mmc-hs400-1_8v;
 719                         mmc-hs400-enhanced-strobe;
 720
 721                         status = "disabled";
 722
 723                         sdhc1_opp_table: opp-table {
 724                                 compatible = "operating-points-v2";
 725
 726                                 opp-100000000 {
 727                                         opp-hz = /bits/ 64 <100000000>;
 728                                         required-opps = <&rpmhpd_opp_low_svs>;
 729                                         opp-peak-kBps = <1800000 600000>;
 730                                         opp-avg-kBps = <100000 0>;
 731                                 };
 732
 733                                 opp-384000000 {
 734                                         opp-hz = /bits/ 64 <384000000>;
 735                                         required-opps = <&rpmhpd_opp_nom>;
 736                                         opp-peak-kBps = <5400000 1600000>;
 737                                         opp-avg-kBps = <390000 0>;
 738                                 };
 739                         };
 740                 };
 741
 742                 qup_opp_table: opp-table-qup {
 743                         compatible = "operating-points-v2";
 744
 745                         opp-75000000 {
 746                                 opp-hz = /bits/ 64 <75000000>;
 747                                 required-opps = <&rpmhpd_opp_low_svs>;
 748                         };
 749
 750                         opp-100000000 {
 751                                 opp-hz = /bits/ 64 <100000000>;
 752                                 required-opps = <&rpmhpd_opp_svs>;
 753                         };
 754
 755                         opp-128000000 {
 756                                 opp-hz = /bits/ 64 <128000000>;
 757                                 required-opps = <&rpmhpd_opp_nom>;
 758                         };
 759                 };
 760
 761                 qupv3_id_0: geniqup@8c0000 {
 762                         compatible = "qcom,geni-se-qup";
 763                         reg = <0 0x008c0000 0 0x6000>;
 764                         clock-names = "m-ahb", "s-ahb";
 765                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
 766                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
 767                         #address-cells = <2>;
 768                         #size-cells = <2>;
 769                         ranges;
 770                         iommus = <&apps_smmu 0x43 0x0>;
 771                         status = "disabled";
 772
 773                         i2c0: i2c@880000 {
 774                                 compatible = "qcom,geni-i2c";
 775                                 reg = <0 0x00880000 0 0x4000>;
 776                                 clock-names = "se";
 777                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 778                                 pinctrl-names = "default";
 779                                 pinctrl-0 = <&qup_i2c0_default>;
 780                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 781                                 #address-cells = <1>;
 782                                 #size-cells = <0>;
 783                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 784                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
 785                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
 786                                 interconnect-names = "qup-core", "qup-config",
 787                                                         "qup-memory";
 788                                 power-domains = <&rpmhpd SC7180_CX>;
 789                                 required-opps = <&rpmhpd_opp_low_svs>;
 790                                 status = "disabled";
 791                         };
 792
 793                         spi0: spi@880000 {
 794                                 compatible = "qcom,geni-spi";
 795                                 reg = <0 0x00880000 0 0x4000>;
 796                                 clock-names = "se";
 797                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 798                                 pinctrl-names = "default";
 799                                 pinctrl-0 = <&qup_spi0_default>;
 800                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 801                                 #address-cells = <1>;
 802                                 #size-cells = <0>;
 803                                 power-domains = <&rpmhpd SC7180_CX>;
 804                                 operating-points-v2 = <&qup_opp_table>;
 805                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 806                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
 807                                 interconnect-names = "qup-core", "qup-config";
 808                                 status = "disabled";
 809                         };
 810
 811                         uart0: serial@880000 {
 812                                 compatible = "qcom,geni-uart";
 813                                 reg = <0 0x00880000 0 0x4000>;
 814                                 clock-names = "se";
 815                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 816                                 pinctrl-names = "default";
 817                                 pinctrl-0 = <&qup_uart0_default>;
 818                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 819                                 power-domains = <&rpmhpd SC7180_CX>;
 820                                 operating-points-v2 = <&qup_opp_table>;
 821                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 822                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
 823                                 interconnect-names = "qup-core", "qup-config";
 824                                 status = "disabled";
 825                         };
 826
 827                         i2c1: i2c@884000 {
 828                                 compatible = "qcom,geni-i2c";
 829                                 reg = <0 0x00884000 0 0x4000>;
 830                                 clock-names = "se";
 831                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 832                                 pinctrl-names = "default";
 833                                 pinctrl-0 = <&qup_i2c1_default>;
 834                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 835                                 #address-cells = <1>;
 836                                 #size-cells = <0>;
 837                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 838                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
 839                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
 840                                 interconnect-names = "qup-core", "qup-config",
 841                                                         "qup-memory";
 842                                 power-domains = <&rpmhpd SC7180_CX>;
 843                                 required-opps = <&rpmhpd_opp_low_svs>;
 844                                 status = "disabled";
 845                         };
 846
 847                         spi1: spi@884000 {
 848                                 compatible = "qcom,geni-spi";
 849                                 reg = <0 0x00884000 0 0x4000>;
 850                                 clock-names = "se";
 851                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 852                                 pinctrl-names = "default";
 853                                 pinctrl-0 = <&qup_spi1_default>;
 854                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 855                                 #address-cells = <1>;
 856                                 #size-cells = <0>;
 857                                 power-domains = <&rpmhpd SC7180_CX>;
 858                                 operating-points-v2 = <&qup_opp_table>;
 859                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 860                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
 861                                 interconnect-names = "qup-core", "qup-config";
 862                                 status = "disabled";
 863                         };
 864
 865                         uart1: serial@884000 {
 866                                 compatible = "qcom,geni-uart";
 867                                 reg = <0 0x00884000 0 0x4000>;
 868                                 clock-names = "se";
 869                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 870                                 pinctrl-names = "default";
 871                                 pinctrl-0 = <&qup_uart1_default>;
 872                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 873                                 power-domains = <&rpmhpd SC7180_CX>;
 874                                 operating-points-v2 = <&qup_opp_table>;
 875                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 876                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
 877                                 interconnect-names = "qup-core", "qup-config";
 878                                 status = "disabled";
 879                         };
 880
 881                         i2c2: i2c@888000 {
 882                                 compatible = "qcom,geni-i2c";
 883                                 reg = <0 0x00888000 0 0x4000>;
 884                                 clock-names = "se";
 885                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 886                                 pinctrl-names = "default";
 887                                 pinctrl-0 = <&qup_i2c2_default>;
 888                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
 889                                 #address-cells = <1>;
 890                                 #size-cells = <0>;
 891                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 892                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
 893                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
 894                                 interconnect-names = "qup-core", "qup-config",
 895                                                         "qup-memory";
 896                                 power-domains = <&rpmhpd SC7180_CX>;
 897                                 required-opps = <&rpmhpd_opp_low_svs>;
 898                                 status = "disabled";
 899                         };
 900
 901                         uart2: serial@888000 {
 902                                 compatible = "qcom,geni-uart";
 903                                 reg = <0 0x00888000 0 0x4000>;
 904                                 clock-names = "se";
 905                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 906                                 pinctrl-names = "default";
 907                                 pinctrl-0 = <&qup_uart2_default>;
 908                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
 909                                 power-domains = <&rpmhpd SC7180_CX>;
 910                                 operating-points-v2 = <&qup_opp_table>;
 911                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 912                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
 913                                 interconnect-names = "qup-core", "qup-config";
 914                                 status = "disabled";
 915                         };
 916
 917                         i2c3: i2c@88c000 {
 918                                 compatible = "qcom,geni-i2c";
 919                                 reg = <0 0x0088c000 0 0x4000>;
 920                                 clock-names = "se";
 921                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 922                                 pinctrl-names = "default";
 923                                 pinctrl-0 = <&qup_i2c3_default>;
 924                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 925                                 #address-cells = <1>;
 926                                 #size-cells = <0>;
 927                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 928                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
 929                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
 930                                 interconnect-names = "qup-core", "qup-config",
 931                                                         "qup-memory";
 932                                 power-domains = <&rpmhpd SC7180_CX>;
 933                                 required-opps = <&rpmhpd_opp_low_svs>;
 934                                 status = "disabled";
 935                         };
 936
 937                         spi3: spi@88c000 {
 938                                 compatible = "qcom,geni-spi";
 939                                 reg = <0 0x0088c000 0 0x4000>;
 940                                 clock-names = "se";
 941                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 942                                 pinctrl-names = "default";
 943                                 pinctrl-0 = <&qup_spi3_default>;
 944                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 945                                 #address-cells = <1>;
 946                                 #size-cells = <0>;
 947                                 power-domains = <&rpmhpd SC7180_CX>;
 948                                 operating-points-v2 = <&qup_opp_table>;
 949                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 950                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
 951                                 interconnect-names = "qup-core", "qup-config";
 952                                 status = "disabled";
 953                         };
 954
 955                         uart3: serial@88c000 {
 956                                 compatible = "qcom,geni-uart";
 957                                 reg = <0 0x0088c000 0 0x4000>;
 958                                 clock-names = "se";
 959                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 960                                 pinctrl-names = "default";
 961                                 pinctrl-0 = <&qup_uart3_default>;
 962                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 963                                 power-domains = <&rpmhpd SC7180_CX>;
 964                                 operating-points-v2 = <&qup_opp_table>;
 965                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 966                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
 967                                 interconnect-names = "qup-core", "qup-config";
 968                                 status = "disabled";
 969                         };
 970
 971                         i2c4: i2c@890000 {
 972                                 compatible = "qcom,geni-i2c";
 973                                 reg = <0 0x00890000 0 0x4000>;
 974                                 clock-names = "se";
 975                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
 976                                 pinctrl-names = "default";
 977                                 pinctrl-0 = <&qup_i2c4_default>;
 978                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
 979                                 #address-cells = <1>;
 980                                 #size-cells = <0>;
 981                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 982                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
 983                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
 984                                 interconnect-names = "qup-core", "qup-config",
 985                                                         "qup-memory";
 986                                 power-domains = <&rpmhpd SC7180_CX>;
 987                                 required-opps = <&rpmhpd_opp_low_svs>;
 988                                 status = "disabled";
 989                         };
 990
 991                         uart4: serial@890000 {
 992                                 compatible = "qcom,geni-uart";
 993                                 reg = <0 0x00890000 0 0x4000>;
 994                                 clock-names = "se";
 995                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
 996                                 pinctrl-names = "default";
 997                                 pinctrl-0 = <&qup_uart4_default>;
 998                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
 999                                 power-domains = <&rpmhpd SC7180_CX>;
1000                                 operating-points-v2 = <&qup_opp_table>;
1001                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1002                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1003                                 interconnect-names = "qup-core", "qup-config";
1004                                 status = "disabled";
1005                         };
1006
1007                         i2c5: i2c@894000 {
1008                                 compatible = "qcom,geni-i2c";
1009                                 reg = <0 0x00894000 0 0x4000>;
1010                                 clock-names = "se";
1011                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1012                                 pinctrl-names = "default";
1013                                 pinctrl-0 = <&qup_i2c5_default>;
1014                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1015                                 #address-cells = <1>;
1016                                 #size-cells = <0>;
1017                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1018                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1019                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1020                                 interconnect-names = "qup-core", "qup-config",
1021                                                         "qup-memory";
1022                                 power-domains = <&rpmhpd SC7180_CX>;
1023                                 required-opps = <&rpmhpd_opp_low_svs>;
1024                                 status = "disabled";
1025                         };
1026
1027                         spi5: spi@894000 {
1028                                 compatible = "qcom,geni-spi";
1029                                 reg = <0 0x00894000 0 0x4000>;
1030                                 clock-names = "se";
1031                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1032                                 pinctrl-names = "default";
1033                                 pinctrl-0 = <&qup_spi5_default>;
1034                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1035                                 #address-cells = <1>;
1036                                 #size-cells = <0>;
1037                                 power-domains = <&rpmhpd SC7180_CX>;
1038                                 operating-points-v2 = <&qup_opp_table>;
1039                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1040                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1041                                 interconnect-names = "qup-core", "qup-config";
1042                                 status = "disabled";
1043                         };
1044
1045                         uart5: serial@894000 {
1046                                 compatible = "qcom,geni-uart";
1047                                 reg = <0 0x00894000 0 0x4000>;
1048                                 clock-names = "se";
1049                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1050                                 pinctrl-names = "default";
1051                                 pinctrl-0 = <&qup_uart5_default>;
1052                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1053                                 power-domains = <&rpmhpd SC7180_CX>;
1054                                 operating-points-v2 = <&qup_opp_table>;
1055                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1056                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1057                                 interconnect-names = "qup-core", "qup-config";
1058                                 status = "disabled";
1059                         };
1060                 };
1061
1062                 qupv3_id_1: geniqup@ac0000 {
1063                         compatible = "qcom,geni-se-qup";
1064                         reg = <0 0x00ac0000 0 0x6000>;
1065                         clock-names = "m-ahb", "s-ahb";
1066                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1067                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1068                         #address-cells = <2>;
1069                         #size-cells = <2>;
1070                         ranges;
1071                         iommus = <&apps_smmu 0x4c3 0x0>;
1072                         status = "disabled";
1073
1074                         i2c6: i2c@a80000 {
1075                                 compatible = "qcom,geni-i2c";
1076                                 reg = <0 0x00a80000 0 0x4000>;
1077                                 clock-names = "se";
1078                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1079                                 pinctrl-names = "default";
1080                                 pinctrl-0 = <&qup_i2c6_default>;
1081                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1082                                 #address-cells = <1>;
1083                                 #size-cells = <0>;
1084                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1085                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1086                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1087                                 interconnect-names = "qup-core", "qup-config",
1088                                                         "qup-memory";
1089                                 power-domains = <&rpmhpd SC7180_CX>;
1090                                 required-opps = <&rpmhpd_opp_low_svs>;
1091                                 status = "disabled";
1092                         };
1093
1094                         spi6: spi@a80000 {
1095                                 compatible = "qcom,geni-spi";
1096                                 reg = <0 0x00a80000 0 0x4000>;
1097                                 clock-names = "se";
1098                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1099                                 pinctrl-names = "default";
1100                                 pinctrl-0 = <&qup_spi6_default>;
1101                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1102                                 #address-cells = <1>;
1103                                 #size-cells = <0>;
1104                                 power-domains = <&rpmhpd SC7180_CX>;
1105                                 operating-points-v2 = <&qup_opp_table>;
1106                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1107                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1108                                 interconnect-names = "qup-core", "qup-config";
1109                                 status = "disabled";
1110                         };
1111
1112                         uart6: serial@a80000 {
1113                                 compatible = "qcom,geni-uart";
1114                                 reg = <0 0x00a80000 0 0x4000>;
1115                                 clock-names = "se";
1116                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1117                                 pinctrl-names = "default";
1118                                 pinctrl-0 = <&qup_uart6_default>;
1119                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1120                                 power-domains = <&rpmhpd SC7180_CX>;
1121                                 operating-points-v2 = <&qup_opp_table>;
1122                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1123                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1124                                 interconnect-names = "qup-core", "qup-config";
1125                                 status = "disabled";
1126                         };
1127
1128                         i2c7: i2c@a84000 {
1129                                 compatible = "qcom,geni-i2c";
1130                                 reg = <0 0x00a84000 0 0x4000>;
1131                                 clock-names = "se";
1132                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1133                                 pinctrl-names = "default";
1134                                 pinctrl-0 = <&qup_i2c7_default>;
1135                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1136                                 #address-cells = <1>;
1137                                 #size-cells = <0>;
1138                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1139                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1140                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1141                                 interconnect-names = "qup-core", "qup-config",
1142                                                         "qup-memory";
1143                                 power-domains = <&rpmhpd SC7180_CX>;
1144                                 required-opps = <&rpmhpd_opp_low_svs>;
1145                                 status = "disabled";
1146                         };
1147
1148                         uart7: serial@a84000 {
1149                                 compatible = "qcom,geni-uart";
1150                                 reg = <0 0x00a84000 0 0x4000>;
1151                                 clock-names = "se";
1152                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1153                                 pinctrl-names = "default";
1154                                 pinctrl-0 = <&qup_uart7_default>;
1155                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1156                                 power-domains = <&rpmhpd SC7180_CX>;
1157                                 operating-points-v2 = <&qup_opp_table>;
1158                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1159                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1160                                 interconnect-names = "qup-core", "qup-config";
1161                                 status = "disabled";
1162                         };
1163
1164                         i2c8: i2c@a88000 {
1165                                 compatible = "qcom,geni-i2c";
1166                                 reg = <0 0x00a88000 0 0x4000>;
1167                                 clock-names = "se";
1168                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1169                                 pinctrl-names = "default";
1170                                 pinctrl-0 = <&qup_i2c8_default>;
1171                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1172                                 #address-cells = <1>;
1173                                 #size-cells = <0>;
1174                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1175                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1176                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1177                                 interconnect-names = "qup-core", "qup-config",
1178                                                         "qup-memory";
1179                                 power-domains = <&rpmhpd SC7180_CX>;
1180                                 required-opps = <&rpmhpd_opp_low_svs>;
1181                                 status = "disabled";
1182                         };
1183
1184                         spi8: spi@a88000 {
1185                                 compatible = "qcom,geni-spi";
1186                                 reg = <0 0x00a88000 0 0x4000>;
1187                                 clock-names = "se";
1188                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1189                                 pinctrl-names = "default";
1190                                 pinctrl-0 = <&qup_spi8_default>;
1191                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1192                                 #address-cells = <1>;
1193                                 #size-cells = <0>;
1194                                 power-domains = <&rpmhpd SC7180_CX>;
1195                                 operating-points-v2 = <&qup_opp_table>;
1196                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1197                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1198                                 interconnect-names = "qup-core", "qup-config";
1199                                 status = "disabled";
1200                         };
1201
1202                         uart8: serial@a88000 {
1203                                 compatible = "qcom,geni-debug-uart";
1204                                 reg = <0 0x00a88000 0 0x4000>;
1205                                 clock-names = "se";
1206                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1207                                 pinctrl-names = "default";
1208                                 pinctrl-0 = <&qup_uart8_default>;
1209                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1210                                 power-domains = <&rpmhpd SC7180_CX>;
1211                                 operating-points-v2 = <&qup_opp_table>;
1212                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1213                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1214                                 interconnect-names = "qup-core", "qup-config";
1215                                 status = "disabled";
1216                         };
1217
1218                         i2c9: i2c@a8c000 {
1219                                 compatible = "qcom,geni-i2c";
1220                                 reg = <0 0x00a8c000 0 0x4000>;
1221                                 clock-names = "se";
1222                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1223                                 pinctrl-names = "default";
1224                                 pinctrl-0 = <&qup_i2c9_default>;
1225                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1226                                 #address-cells = <1>;
1227                                 #size-cells = <0>;
1228                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1229                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1230                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1231                                 interconnect-names = "qup-core", "qup-config",
1232                                                         "qup-memory";
1233                                 power-domains = <&rpmhpd SC7180_CX>;
1234                                 required-opps = <&rpmhpd_opp_low_svs>;
1235                                 status = "disabled";
1236                         };
1237
1238                         uart9: serial@a8c000 {
1239                                 compatible = "qcom,geni-uart";
1240                                 reg = <0 0x00a8c000 0 0x4000>;
1241                                 clock-names = "se";
1242                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1243                                 pinctrl-names = "default";
1244                                 pinctrl-0 = <&qup_uart9_default>;
1245                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1246                                 power-domains = <&rpmhpd SC7180_CX>;
1247                                 operating-points-v2 = <&qup_opp_table>;
1248                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1249                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1250                                 interconnect-names = "qup-core", "qup-config";
1251                                 status = "disabled";
1252                         };
1253
1254                         i2c10: i2c@a90000 {
1255                                 compatible = "qcom,geni-i2c";
1256                                 reg = <0 0x00a90000 0 0x4000>;
1257                                 clock-names = "se";
1258                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1259                                 pinctrl-names = "default";
1260                                 pinctrl-0 = <&qup_i2c10_default>;
1261                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1262                                 #address-cells = <1>;
1263                                 #size-cells = <0>;
1264                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1265                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1266                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1267                                 interconnect-names = "qup-core", "qup-config",
1268                                                         "qup-memory";
1269                                 power-domains = <&rpmhpd SC7180_CX>;
1270                                 required-opps = <&rpmhpd_opp_low_svs>;
1271                                 status = "disabled";
1272                         };
1273
1274                         spi10: spi@a90000 {
1275                                 compatible = "qcom,geni-spi";
1276                                 reg = <0 0x00a90000 0 0x4000>;
1277                                 clock-names = "se";
1278                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1279                                 pinctrl-names = "default";
1280                                 pinctrl-0 = <&qup_spi10_default>;
1281                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1282                                 #address-cells = <1>;
1283                                 #size-cells = <0>;
1284                                 power-domains = <&rpmhpd SC7180_CX>;
1285                                 operating-points-v2 = <&qup_opp_table>;
1286                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1287                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1288                                 interconnect-names = "qup-core", "qup-config";
1289                                 status = "disabled";
1290                         };
1291
1292                         uart10: serial@a90000 {
1293                                 compatible = "qcom,geni-uart";
1294                                 reg = <0 0x00a90000 0 0x4000>;
1295                                 clock-names = "se";
1296                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1297                                 pinctrl-names = "default";
1298                                 pinctrl-0 = <&qup_uart10_default>;
1299                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1300                                 power-domains = <&rpmhpd SC7180_CX>;
1301                                 operating-points-v2 = <&qup_opp_table>;
1302                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1303                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1304                                 interconnect-names = "qup-core", "qup-config";
1305                                 status = "disabled";
1306                         };
1307
1308                         i2c11: i2c@a94000 {
1309                                 compatible = "qcom,geni-i2c";
1310                                 reg = <0 0x00a94000 0 0x4000>;
1311                                 clock-names = "se";
1312                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1313                                 pinctrl-names = "default";
1314                                 pinctrl-0 = <&qup_i2c11_default>;
1315                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1316                                 #address-cells = <1>;
1317                                 #size-cells = <0>;
1318                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1319                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1320                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1321                                 interconnect-names = "qup-core", "qup-config",
1322                                                         "qup-memory";
1323                                 power-domains = <&rpmhpd SC7180_CX>;
1324                                 required-opps = <&rpmhpd_opp_low_svs>;
1325                                 status = "disabled";
1326                         };
1327
1328                         spi11: spi@a94000 {
1329                                 compatible = "qcom,geni-spi";
1330                                 reg = <0 0x00a94000 0 0x4000>;
1331                                 clock-names = "se";
1332                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1333                                 pinctrl-names = "default";
1334                                 pinctrl-0 = <&qup_spi11_default>;
1335                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1336                                 #address-cells = <1>;
1337                                 #size-cells = <0>;
1338                                 power-domains = <&rpmhpd SC7180_CX>;
1339                                 operating-points-v2 = <&qup_opp_table>;
1340                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1341                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1342                                 interconnect-names = "qup-core", "qup-config";
1343                                 status = "disabled";
1344                         };
1345
1346                         uart11: serial@a94000 {
1347                                 compatible = "qcom,geni-uart";
1348                                 reg = <0 0x00a94000 0 0x4000>;
1349                                 clock-names = "se";
1350                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1351                                 pinctrl-names = "default";
1352                                 pinctrl-0 = <&qup_uart11_default>;
1353                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1354                                 power-domains = <&rpmhpd SC7180_CX>;
1355                                 operating-points-v2 = <&qup_opp_table>;
1356                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1357                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1358                                 interconnect-names = "qup-core", "qup-config";
1359                                 status = "disabled";
1360                         };
1361                 };
1362
1363                 config_noc: interconnect@1500000 {
1364                         compatible = "qcom,sc7180-config-noc";
1365                         reg = <0 0x01500000 0 0x28000>;
1366                         #interconnect-cells = <2>;
1367                         qcom,bcm-voters = <&apps_bcm_voter>;
1368                 };
1369
1370                 system_noc: interconnect@1620000 {
1371                         compatible = "qcom,sc7180-system-noc";
1372                         reg = <0 0x01620000 0 0x17080>;
1373                         #interconnect-cells = <2>;
1374                         qcom,bcm-voters = <&apps_bcm_voter>;
1375                 };
1376
1377                 mc_virt: interconnect@1638000 {
1378                         compatible = "qcom,sc7180-mc-virt";
1379                         reg = <0 0x01638000 0 0x1000>;
1380                         #interconnect-cells = <2>;
1381                         qcom,bcm-voters = <&apps_bcm_voter>;
1382                 };
1383
1384                 qup_virt: interconnect@1650000 {
1385                         compatible = "qcom,sc7180-qup-virt";
1386                         reg = <0 0x01650000 0 0x1000>;
1387                         #interconnect-cells = <2>;
1388                         qcom,bcm-voters = <&apps_bcm_voter>;
1389                 };
1390
1391                 aggre1_noc: interconnect@16e0000 {
1392                         compatible = "qcom,sc7180-aggre1-noc";
1393                         reg = <0 0x016e0000 0 0x15080>;
1394                         #interconnect-cells = <2>;
1395                         qcom,bcm-voters = <&apps_bcm_voter>;
1396                 };
1397
1398                 aggre2_noc: interconnect@1705000 {
1399                         compatible = "qcom,sc7180-aggre2-noc";
1400                         reg = <0 0x01705000 0 0x9000>;
1401                         #interconnect-cells = <2>;
1402                         qcom,bcm-voters = <&apps_bcm_voter>;
1403                 };
1404
1405                 compute_noc: interconnect@170e000 {
1406                         compatible = "qcom,sc7180-compute-noc";
1407                         reg = <0 0x0170e000 0 0x6000>;
1408                         #interconnect-cells = <2>;
1409                         qcom,bcm-voters = <&apps_bcm_voter>;
1410                 };
1411
1412                 mmss_noc: interconnect@1740000 {
1413                         compatible = "qcom,sc7180-mmss-noc";
1414                         reg = <0 0x01740000 0 0x1c100>;
1415                         #interconnect-cells = <2>;
1416                         qcom,bcm-voters = <&apps_bcm_voter>;
1417                 };
1418
1419                 ipa: ipa@1e40000 {
1420                         compatible = "qcom,sc7180-ipa";
1421
1422                         iommus = <&apps_smmu 0x440 0x0>,
1423                                  <&apps_smmu 0x442 0x0>;
1424                         reg = <0 0x1e40000 0 0x7000>,
1425                               <0 0x1e47000 0 0x2000>,
1426                               <0 0x1e04000 0 0x2c000>;
1427                         reg-names = "ipa-reg",
1428                                     "ipa-shared",
1429                                     "gsi";
1430
1431                         interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
1432                                               <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
1433                                               <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1434                                               <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
1435                         interrupt-names = "ipa",
1436                                           "gsi",
1437                                           "ipa-clock-query",
1438                                           "ipa-setup-ready";
1439
1440                         clocks = <&rpmhcc RPMH_IPA_CLK>;
1441                         clock-names = "core";
1442
1443                         interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
1444                                         <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
1445                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
1446                         interconnect-names = "memory",
1447                                              "imem",
1448                                              "config";
1449
1450                         qcom,qmp = <&aoss_qmp>;
1451
1452                         qcom,smem-states = <&ipa_smp2p_out 0>,
1453                                            <&ipa_smp2p_out 1>;
1454                         qcom,smem-state-names = "ipa-clock-enabled-valid",
1455                                                 "ipa-clock-enabled";
1456
1457                         status = "disabled";
1458                 };
1459
1460                 tcsr_mutex: hwlock@1f40000 {
1461                         compatible = "qcom,tcsr-mutex";
1462                         reg = <0 0x01f40000 0 0x20000>;
1463                         #hwlock-cells = <1>;
1464                 };
1465
1466                 tcsr_regs_1: syscon@1f60000 {
1467                         compatible = "qcom,sc7180-tcsr", "syscon";
1468                         reg = <0 0x01f60000 0 0x20000>;
1469                 };
1470
1471                 tcsr_regs_2: syscon@1fc0000 {
1472                         compatible = "qcom,sc7180-tcsr", "syscon";
1473                         reg = <0 0x01fc0000 0 0x40000>;
1474                 };
1475
1476                 tlmm: pinctrl@3500000 {
1477                         compatible = "qcom,sc7180-pinctrl";
1478                         reg = <0 0x03500000 0 0x300000>,
1479                               <0 0x03900000 0 0x300000>,
1480                               <0 0x03d00000 0 0x300000>;
1481                         reg-names = "west", "north", "south";
1482                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1483                         gpio-controller;
1484                         #gpio-cells = <2>;
1485                         interrupt-controller;
1486                         #interrupt-cells = <2>;
1487                         gpio-ranges = <&tlmm 0 0 120>;
1488                         wakeup-parent = <&pdc>;
1489
1490                         dp_hot_plug_det: dp-hot-plug-det {
1491                                 pinmux {
1492                                         pins = "gpio117";
1493                                         function = "dp_hot";
1494                                 };
1495                         };
1496
1497                         qspi_clk: qspi-clk {
1498                                 pinmux {
1499                                         pins = "gpio63";
1500                                         function = "qspi_clk";
1501                                 };
1502                         };
1503
1504                         qspi_cs0: qspi-cs0 {
1505                                 pinmux {
1506                                         pins = "gpio68";
1507                                         function = "qspi_cs";
1508                                 };
1509                         };
1510
1511                         qspi_cs1: qspi-cs1 {
1512                                 pinmux {
1513                                         pins = "gpio72";
1514                                         function = "qspi_cs";
1515                                 };
1516                         };
1517
1518                         qspi_data01: qspi-data01 {
1519                                 pinmux-data {
1520                                         pins = "gpio64", "gpio65";
1521                                         function = "qspi_data";
1522                                 };
1523                         };
1524
1525                         qspi_data12: qspi-data12 {
1526                                 pinmux-data {
1527                                         pins = "gpio66", "gpio67";
1528                                         function = "qspi_data";
1529                                 };
1530                         };
1531
1532                         qup_i2c0_default: qup-i2c0-default {
1533                                 pinmux {
1534                                         pins = "gpio34", "gpio35";
1535                                         function = "qup00";
1536                                 };
1537                         };
1538
1539                         qup_i2c1_default: qup-i2c1-default {
1540                                 pinmux {
1541                                         pins = "gpio0", "gpio1";
1542                                         function = "qup01";
1543                                 };
1544                         };
1545
1546                         qup_i2c2_default: qup-i2c2-default {
1547                                 pinmux {
1548                                         pins = "gpio15", "gpio16";
1549                                         function = "qup02_i2c";
1550                                 };
1551                         };
1552
1553                         qup_i2c3_default: qup-i2c3-default {
1554                                 pinmux {
1555                                         pins = "gpio38", "gpio39";
1556                                         function = "qup03";
1557                                 };
1558                         };
1559
1560                         qup_i2c4_default: qup-i2c4-default {
1561                                 pinmux {
1562                                         pins = "gpio115", "gpio116";
1563                                         function = "qup04_i2c";
1564                                 };
1565                         };
1566
1567                         qup_i2c5_default: qup-i2c5-default {
1568                                 pinmux {
1569                                         pins = "gpio25", "gpio26";
1570                                         function = "qup05";
1571                                 };
1572                         };
1573
1574                         qup_i2c6_default: qup-i2c6-default {
1575                                 pinmux {
1576                                         pins = "gpio59", "gpio60";
1577                                         function = "qup10";
1578                                 };
1579                         };
1580
1581                         qup_i2c7_default: qup-i2c7-default {
1582                                 pinmux {
1583                                         pins = "gpio6", "gpio7";
1584                                         function = "qup11_i2c";
1585                                 };
1586                         };
1587
1588                         qup_i2c8_default: qup-i2c8-default {
1589                                 pinmux {
1590                                         pins = "gpio42", "gpio43";
1591                                         function = "qup12";
1592                                 };
1593                         };
1594
1595                         qup_i2c9_default: qup-i2c9-default {
1596                                 pinmux {
1597                                         pins = "gpio46", "gpio47";
1598                                         function = "qup13_i2c";
1599                                 };
1600                         };
1601
1602                         qup_i2c10_default: qup-i2c10-default {
1603                                 pinmux {
1604                                         pins = "gpio86", "gpio87";
1605                                         function = "qup14";
1606                                 };
1607                         };
1608
1609                         qup_i2c11_default: qup-i2c11-default {
1610                                 pinmux {
1611                                         pins = "gpio53", "gpio54";
1612                                         function = "qup15";
1613                                 };
1614                         };
1615
1616                         qup_spi0_default: qup-spi0-default {
1617                                 pinmux {
1618                                         pins = "gpio34", "gpio35",
1619                                                "gpio36", "gpio37";
1620                                         function = "qup00";
1621                                 };
1622                         };
1623
1624                         qup_spi0_cs_gpio: qup-spi0-cs-gpio {
1625                                 pinmux {
1626                                         pins = "gpio34", "gpio35",
1627                                                "gpio36";
1628                                         function = "qup00";
1629                                 };
1630
1631                                 pinmux-cs {
1632                                         pins = "gpio37";
1633                                         function = "gpio";
1634                                 };
1635                         };
1636
1637                         qup_spi1_default: qup-spi1-default {
1638                                 pinmux {
1639                                         pins = "gpio0", "gpio1",
1640                                                "gpio2", "gpio3";
1641                                         function = "qup01";
1642                                 };
1643                         };
1644
1645                         qup_spi1_cs_gpio: qup-spi1-cs-gpio {
1646                                 pinmux {
1647                                         pins = "gpio0", "gpio1",
1648                                                "gpio2";
1649                                         function = "qup01";
1650                                 };
1651
1652                                 pinmux-cs {
1653                                         pins = "gpio3";
1654                                         function = "gpio";
1655                                 };
1656                         };
1657
1658                         qup_spi3_default: qup-spi3-default {
1659                                 pinmux {
1660                                         pins = "gpio38", "gpio39",
1661                                                "gpio40", "gpio41";
1662                                         function = "qup03";
1663                                 };
1664                         };
1665
1666                         qup_spi3_cs_gpio: qup-spi3-cs-gpio {
1667                                 pinmux {
1668                                         pins = "gpio38", "gpio39",
1669                                                "gpio40";
1670                                         function = "qup03";
1671                                 };
1672
1673                                 pinmux-cs {
1674                                         pins = "gpio41";
1675                                         function = "gpio";
1676                                 };
1677                         };
1678
1679                         qup_spi5_default: qup-spi5-default {
1680                                 pinmux {
1681                                         pins = "gpio25", "gpio26",
1682                                                "gpio27", "gpio28";
1683                                         function = "qup05";
1684                                 };
1685                         };
1686
1687                         qup_spi5_cs_gpio: qup-spi5-cs-gpio {
1688                                 pinmux {
1689                                         pins = "gpio25", "gpio26",
1690                                                "gpio27";
1691                                         function = "qup05";
1692                                 };
1693
1694                                 pinmux-cs {
1695                                         pins = "gpio28";
1696                                         function = "gpio";
1697                                 };
1698                         };
1699
1700                         qup_spi6_default: qup-spi6-default {
1701                                 pinmux {
1702                                         pins = "gpio59", "gpio60",
1703                                                "gpio61", "gpio62";
1704                                         function = "qup10";
1705                                 };
1706                         };
1707
1708                         qup_spi6_cs_gpio: qup-spi6-cs-gpio {
1709                                 pinmux {
1710                                         pins = "gpio59", "gpio60",
1711                                                "gpio61";
1712                                         function = "qup10";
1713                                 };
1714
1715                                 pinmux-cs {
1716                                         pins = "gpio62";
1717                                         function = "gpio";
1718                                 };
1719                         };
1720
1721                         qup_spi8_default: qup-spi8-default {
1722                                 pinmux {
1723                                         pins = "gpio42", "gpio43",
1724                                                "gpio44", "gpio45";
1725                                         function = "qup12";
1726                                 };
1727                         };
1728
1729                         qup_spi8_cs_gpio: qup-spi8-cs-gpio {
1730                                 pinmux {
1731                                         pins = "gpio42", "gpio43",
1732                                                "gpio44";
1733                                         function = "qup12";
1734                                 };
1735
1736                                 pinmux-cs {
1737                                         pins = "gpio45";
1738                                         function = "gpio";
1739                                 };
1740                         };
1741
1742                         qup_spi10_default: qup-spi10-default {
1743                                 pinmux {
1744                                         pins = "gpio86", "gpio87",
1745                                                "gpio88", "gpio89";
1746                                         function = "qup14";
1747                                 };
1748                         };
1749
1750                         qup_spi10_cs_gpio: qup-spi10-cs-gpio {
1751                                 pinmux {
1752                                         pins = "gpio86", "gpio87",
1753                                                "gpio88";
1754                                         function = "qup14";
1755                                 };
1756
1757                                 pinmux-cs {
1758                                         pins = "gpio89";
1759                                         function = "gpio";
1760                                 };
1761                         };
1762
1763                         qup_spi11_default: qup-spi11-default {
1764                                 pinmux {
1765                                         pins = "gpio53", "gpio54",
1766                                                "gpio55", "gpio56";
1767                                         function = "qup15";
1768                                 };
1769                         };
1770
1771                         qup_spi11_cs_gpio: qup-spi11-cs-gpio {
1772                                 pinmux {
1773                                         pins = "gpio53", "gpio54",
1774                                                "gpio55";
1775                                         function = "qup15";
1776                                 };
1777
1778                                 pinmux-cs {
1779                                         pins = "gpio56";
1780                                         function = "gpio";
1781                                 };
1782                         };
1783
1784                         qup_uart0_default: qup-uart0-default {
1785                                 pinmux {
1786                                         pins = "gpio34", "gpio35",
1787                                                "gpio36", "gpio37";
1788                                         function = "qup00";
1789                                 };
1790                         };
1791
1792                         qup_uart1_default: qup-uart1-default {
1793                                 pinmux {
1794                                         pins = "gpio0", "gpio1",
1795                                                "gpio2", "gpio3";
1796                                         function = "qup01";
1797                                 };
1798                         };
1799
1800                         qup_uart2_default: qup-uart2-default {
1801                                 pinmux {
1802                                         pins = "gpio15", "gpio16";
1803                                         function = "qup02_uart";
1804                                 };
1805                         };
1806
1807                         qup_uart3_default: qup-uart3-default {
1808                                 pinmux {
1809                                         pins = "gpio38", "gpio39",
1810                                                "gpio40", "gpio41";
1811                                         function = "qup03";
1812                                 };
1813                         };
1814
1815                         qup_uart4_default: qup-uart4-default {
1816                                 pinmux {
1817                                         pins = "gpio115", "gpio116";
1818                                         function = "qup04_uart";
1819                                 };
1820                         };
1821
1822                         qup_uart5_default: qup-uart5-default {
1823                                 pinmux {
1824                                         pins = "gpio25", "gpio26",
1825                                                "gpio27", "gpio28";
1826                                         function = "qup05";
1827                                 };
1828                         };
1829
1830                         qup_uart6_default: qup-uart6-default {
1831                                 pinmux {
1832                                         pins = "gpio59", "gpio60",
1833                                                "gpio61", "gpio62";
1834                                         function = "qup10";
1835                                 };
1836                         };
1837
1838                         qup_uart7_default: qup-uart7-default {
1839                                 pinmux {
1840                                         pins = "gpio6", "gpio7";
1841                                         function = "qup11_uart";
1842                                 };
1843                         };
1844
1845                         qup_uart8_default: qup-uart8-default {
1846                                 pinmux {
1847                                         pins = "gpio44", "gpio45";
1848                                         function = "qup12";
1849                                 };
1850                         };
1851
1852                         qup_uart9_default: qup-uart9-default {
1853                                 pinmux {
1854                                         pins = "gpio46", "gpio47";
1855                                         function = "qup13_uart";
1856                                 };
1857                         };
1858
1859                         qup_uart10_default: qup-uart10-default {
1860                                 pinmux {
1861                                         pins = "gpio86", "gpio87",
1862                                                "gpio88", "gpio89";
1863                                         function = "qup14";
1864                                 };
1865                         };
1866
1867                         qup_uart11_default: qup-uart11-default {
1868                                 pinmux {
1869                                         pins = "gpio53", "gpio54",
1870                                                "gpio55", "gpio56";
1871                                         function = "qup15";
1872                                 };
1873                         };
1874
1875                         sec_mi2s_active: sec-mi2s-active {
1876                                 pinmux {
1877                                         pins = "gpio49", "gpio50", "gpio51";
1878                                         function = "mi2s_1";
1879                                 };
1880                         };
1881
1882                         pri_mi2s_active: pri-mi2s-active {
1883                                 pinmux {
1884                                         pins = "gpio53", "gpio54", "gpio55", "gpio56";
1885                                         function = "mi2s_0";
1886                                 };
1887                         };
1888
1889                         pri_mi2s_mclk_active: pri-mi2s-mclk-active {
1890                                 pinmux {
1891                                         pins = "gpio57";
1892                                         function = "lpass_ext";
1893                                 };
1894                         };
1895                 };
1896
1897                 remoteproc_mpss: remoteproc@4080000 {
1898                         compatible = "qcom,sc7180-mpss-pas";
1899                         reg = <0 0x04080000 0 0x4040>, <0 0x04180000 0 0x48>;
1900                         reg-names = "qdsp6", "rmb";
1901
1902                         interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
1903                                               <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1904                                               <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1905                                               <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1906                                               <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
1907                                               <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
1908                         interrupt-names = "wdog", "fatal", "ready", "handover",
1909                                           "stop-ack", "shutdown-ack";
1910
1911                         clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1912                                  <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
1913                                  <&gcc GCC_MSS_NAV_AXI_CLK>,
1914                                  <&gcc GCC_MSS_SNOC_AXI_CLK>,
1915                                  <&gcc GCC_MSS_MFAB_AXIS_CLK>,
1916                                  <&rpmhcc RPMH_CXO_CLK>;
1917                         clock-names = "iface", "bus", "nav", "snoc_axi",
1918                                       "mnoc_axi", "xo";
1919
1920                         power-domains = <&rpmhpd SC7180_CX>,
1921                                         <&rpmhpd SC7180_MX>,
1922                                         <&rpmhpd SC7180_MSS>;
1923                         power-domain-names = "cx", "mx", "mss";
1924
1925                         memory-region = <&mpss_mem>;
1926
1927                         qcom,qmp = <&aoss_qmp>;
1928
1929                         qcom,smem-states = <&modem_smp2p_out 0>;
1930                         qcom,smem-state-names = "stop";
1931
1932                         resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
1933                                  <&pdc_reset PDC_MODEM_SYNC_RESET>;
1934                         reset-names = "mss_restart", "pdc_reset";
1935
1936                         qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
1937                         qcom,spare-regs = <&tcsr_regs_2 0xb3e4>;
1938
1939                         status = "disabled";
1940
1941                         glink-edge {
1942                                 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
1943                                 label = "modem";
1944                                 qcom,remote-pid = <1>;
1945                                 mboxes = <&apss_shared 12>;
1946                         };
1947                 };
1948
1949                 gpu: gpu@5000000 {
1950                         compatible = "qcom,adreno-618.0", "qcom,adreno";
1951                         reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>,
1952                                 <0 0x05061000 0 0x800>;
1953                         reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc";
1954                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1955                         iommus = <&adreno_smmu 0>;
1956                         operating-points-v2 = <&gpu_opp_table>;
1957                         qcom,gmu = <&gmu>;
1958
1959                         #cooling-cells = <2>;
1960
1961                         nvmem-cells = <&gpu_speed_bin>;
1962                         nvmem-cell-names = "speed_bin";
1963
1964                         interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
1965                         interconnect-names = "gfx-mem";
1966
1967                         gpu_opp_table: opp-table {
1968                                 compatible = "operating-points-v2";
1969
1970                                 opp-825000000 {
1971                                         opp-hz = /bits/ 64 <825000000>;
1972                                         opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1973                                         opp-peak-kBps = <8532000>;
1974                                         opp-supported-hw = <0x04>;
1975                                 };
1976
1977                                 opp-800000000 {
1978                                         opp-hz = /bits/ 64 <800000000>;
1979                                         opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1980                                         opp-peak-kBps = <8532000>;
1981                                         opp-supported-hw = <0x07>;
1982                                 };
1983
1984                                 opp-650000000 {
1985                                         opp-hz = /bits/ 64 <650000000>;
1986                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1987                                         opp-peak-kBps = <7216000>;
1988                                         opp-supported-hw = <0x07>;
1989                                 };
1990
1991                                 opp-565000000 {
1992                                         opp-hz = /bits/ 64 <565000000>;
1993                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1994                                         opp-peak-kBps = <5412000>;
1995                                         opp-supported-hw = <0x07>;
1996                                 };
1997
1998                                 opp-430000000 {
1999                                         opp-hz = /bits/ 64 <430000000>;
2000                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2001                                         opp-peak-kBps = <5412000>;
2002                                         opp-supported-hw = <0x07>;
2003                                 };
2004
2005                                 opp-355000000 {
2006                                         opp-hz = /bits/ 64 <355000000>;
2007                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2008                                         opp-peak-kBps = <3072000>;
2009                                         opp-supported-hw = <0x07>;
2010                                 };
2011
2012                                 opp-267000000 {
2013                                         opp-hz = /bits/ 64 <267000000>;
2014                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2015                                         opp-peak-kBps = <3072000>;
2016                                         opp-supported-hw = <0x07>;
2017                                 };
2018
2019                                 opp-180000000 {
2020                                         opp-hz = /bits/ 64 <180000000>;
2021                                         opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2022                                         opp-peak-kBps = <1804000>;
2023                                         opp-supported-hw = <0x07>;
2024                                 };
2025                         };
2026                 };
2027
2028                 adreno_smmu: iommu@5040000 {
2029                         compatible = "qcom,sc7180-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
2030                         reg = <0 0x05040000 0 0x10000>;
2031                         #iommu-cells = <1>;
2032                         #global-interrupts = <2>;
2033                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
2034                                         <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
2035                                         <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
2036                                         <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
2037                                         <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
2038                                         <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
2039                                         <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
2040                                         <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
2041                                         <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
2042                                         <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
2043
2044                         clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2045                                 <&gcc GCC_GPU_CFG_AHB_CLK>;
2046                         clock-names = "bus", "iface";
2047
2048                         power-domains = <&gpucc CX_GDSC>;
2049                 };
2050
2051                 gmu: gmu@506a000 {
2052                         compatible = "qcom,adreno-gmu-618.0", "qcom,adreno-gmu";
2053                         reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>,
2054                                 <0 0x0b490000 0 0x10000>;
2055                         reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2056                         interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2057                                    <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2058                         interrupt-names = "hfi", "gmu";
2059                         clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
2060                                <&gpucc GPU_CC_CXO_CLK>,
2061                                <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2062                                <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2063                         clock-names = "gmu", "cxo", "axi", "memnoc";
2064                         power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>;
2065                         power-domain-names = "cx", "gx";
2066                         iommus = <&adreno_smmu 5>;
2067                         operating-points-v2 = <&gmu_opp_table>;
2068
2069                         gmu_opp_table: opp-table {
2070                                 compatible = "operating-points-v2";
2071
2072                                 opp-200000000 {
2073                                         opp-hz = /bits/ 64 <200000000>;
2074                                         opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2075                                 };
2076                         };
2077                 };
2078
2079                 gpucc: clock-controller@5090000 {
2080                         compatible = "qcom,sc7180-gpucc";
2081                         reg = <0 0x05090000 0 0x9000>;
2082                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2083                                  <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2084                                  <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2085                         clock-names = "bi_tcxo",
2086                                       "gcc_gpu_gpll0_clk_src",
2087                                       "gcc_gpu_gpll0_div_clk_src";
2088                         #clock-cells = <1>;
2089                         #reset-cells = <1>;
2090                         #power-domain-cells = <1>;
2091                 };
2092
2093                 stm@6002000 {
2094                         compatible = "arm,coresight-stm", "arm,primecell";
2095                         reg = <0 0x06002000 0 0x1000>,
2096                               <0 0x16280000 0 0x180000>;
2097                         reg-names = "stm-base", "stm-stimulus-base";
2098
2099                         clocks = <&aoss_qmp>;
2100                         clock-names = "apb_pclk";
2101
2102                         out-ports {
2103                                 port {
2104                                         stm_out: endpoint {
2105                                                 remote-endpoint = <&funnel0_in7>;
2106                                         };
2107                                 };
2108                         };
2109                 };
2110
2111                 funnel@6041000 {
2112                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2113                         reg = <0 0x06041000 0 0x1000>;
2114
2115                         clocks = <&aoss_qmp>;
2116                         clock-names = "apb_pclk";
2117
2118                         out-ports {
2119                                 port {
2120                                         funnel0_out: endpoint {
2121                                                 remote-endpoint = <&merge_funnel_in0>;
2122                                         };
2123                                 };
2124                         };
2125
2126                         in-ports {
2127                                 #address-cells = <1>;
2128                                 #size-cells = <0>;
2129
2130                                 port@7 {
2131                                         reg = <7>;
2132                                         funnel0_in7: endpoint {
2133                                                 remote-endpoint = <&stm_out>;
2134                                         };
2135                                 };
2136                         };
2137                 };
2138
2139                 funnel@6042000 {
2140                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2141                         reg = <0 0x06042000 0 0x1000>;
2142
2143                         clocks = <&aoss_qmp>;
2144                         clock-names = "apb_pclk";
2145
2146                         out-ports {
2147                                 port {
2148                                         funnel1_out: endpoint {
2149                                                 remote-endpoint = <&merge_funnel_in1>;
2150                                         };
2151                                 };
2152                         };
2153
2154                         in-ports {
2155                                 #address-cells = <1>;
2156                                 #size-cells = <0>;
2157
2158                                 port@4 {
2159                                         reg = <4>;
2160                                         funnel1_in4: endpoint {
2161                                                 remote-endpoint = <&apss_merge_funnel_out>;
2162                                         };
2163                                 };
2164                         };
2165                 };
2166
2167                 funnel@6045000 {
2168                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2169                         reg = <0 0x06045000 0 0x1000>;
2170
2171                         clocks = <&aoss_qmp>;
2172                         clock-names = "apb_pclk";
2173
2174                         out-ports {
2175                                 port {
2176                                         merge_funnel_out: endpoint {
2177                                                 remote-endpoint = <&swao_funnel_in>;
2178                                         };
2179                                 };
2180                         };
2181
2182                         in-ports {
2183                                 #address-cells = <1>;
2184                                 #size-cells = <0>;
2185
2186                                 port@0 {
2187                                         reg = <0>;
2188                                         merge_funnel_in0: endpoint {
2189                                                 remote-endpoint = <&funnel0_out>;
2190                                         };
2191                                 };
2192
2193                                 port@1 {
2194                                         reg = <1>;
2195                                         merge_funnel_in1: endpoint {
2196                                                 remote-endpoint = <&funnel1_out>;
2197                                         };
2198                                 };
2199                         };
2200                 };
2201
2202                 replicator@6046000 {
2203                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2204                         reg = <0 0x06046000 0 0x1000>;
2205
2206                         clocks = <&aoss_qmp>;
2207                         clock-names = "apb_pclk";
2208
2209                         out-ports {
2210                                 port {
2211                                         replicator_out: endpoint {
2212                                                 remote-endpoint = <&etr_in>;
2213                                         };
2214                                 };
2215                         };
2216
2217                         in-ports {
2218                                 port {
2219                                         replicator_in: endpoint {
2220                                                 remote-endpoint = <&swao_replicator_out>;
2221                                         };
2222                                 };
2223                         };
2224                 };
2225
2226                 etr@6048000 {
2227                         compatible = "arm,coresight-tmc", "arm,primecell";
2228                         reg = <0 0x06048000 0 0x1000>;
2229                         iommus = <&apps_smmu 0x04a0 0x20>;
2230
2231                         clocks = <&aoss_qmp>;
2232                         clock-names = "apb_pclk";
2233                         arm,scatter-gather;
2234
2235                         in-ports {
2236                                 port {
2237                                         etr_in: endpoint {
2238                                                 remote-endpoint = <&replicator_out>;
2239                                         };
2240                                 };
2241                         };
2242                 };
2243
2244                 funnel@6b04000 {
2245                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2246                         reg = <0 0x06b04000 0 0x1000>;
2247
2248                         clocks = <&aoss_qmp>;
2249                         clock-names = "apb_pclk";
2250
2251                         out-ports {
2252                                 port {
2253                                         swao_funnel_out: endpoint {
2254                                                 remote-endpoint = <&etf_in>;
2255                                         };
2256                                 };
2257                         };
2258
2259                         in-ports {
2260                                 #address-cells = <1>;
2261                                 #size-cells = <0>;
2262
2263                                 port@7 {
2264                                         reg = <7>;
2265                                         swao_funnel_in: endpoint {
2266                                                 remote-endpoint = <&merge_funnel_out>;
2267                                         };
2268                                 };
2269                         };
2270                 };
2271
2272                 etf@6b05000 {
2273                         compatible = "arm,coresight-tmc", "arm,primecell";
2274                         reg = <0 0x06b05000 0 0x1000>;
2275
2276                         clocks = <&aoss_qmp>;
2277                         clock-names = "apb_pclk";
2278
2279                         out-ports {
2280                                 port {
2281                                         etf_out: endpoint {
2282                                                 remote-endpoint = <&swao_replicator_in>;
2283                                         };
2284                                 };
2285                         };
2286
2287                         in-ports {
2288                                 port {
2289                                         etf_in: endpoint {
2290                                                 remote-endpoint = <&swao_funnel_out>;
2291                                         };
2292                                 };
2293                         };
2294                 };
2295
2296                 replicator@6b06000 {
2297                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2298                         reg = <0 0x06b06000 0 0x1000>;
2299
2300                         clocks = <&aoss_qmp>;
2301                         clock-names = "apb_pclk";
2302                         qcom,replicator-loses-context;
2303
2304                         out-ports {
2305                                 port {
2306                                         swao_replicator_out: endpoint {
2307                                                 remote-endpoint = <&replicator_in>;
2308                                         };
2309                                 };
2310                         };
2311
2312                         in-ports {
2313                                 port {
2314                                         swao_replicator_in: endpoint {
2315                                                 remote-endpoint = <&etf_out>;
2316                                         };
2317                                 };
2318                         };
2319                 };
2320
2321                 etm@7040000 {
2322                         compatible = "arm,coresight-etm4x", "arm,primecell";
2323                         reg = <0 0x07040000 0 0x1000>;
2324
2325                         cpu = <&CPU0>;
2326
2327                         clocks = <&aoss_qmp>;
2328                         clock-names = "apb_pclk";
2329                         arm,coresight-loses-context-with-cpu;
2330                         qcom,skip-power-up;
2331
2332                         out-ports {
2333                                 port {
2334                                         etm0_out: endpoint {
2335                                                 remote-endpoint = <&apss_funnel_in0>;
2336                                         };
2337                                 };
2338                         };
2339                 };
2340
2341                 etm@7140000 {
2342                         compatible = "arm,coresight-etm4x", "arm,primecell";
2343                         reg = <0 0x07140000 0 0x1000>;
2344
2345                         cpu = <&CPU1>;
2346
2347                         clocks = <&aoss_qmp>;
2348                         clock-names = "apb_pclk";
2349                         arm,coresight-loses-context-with-cpu;
2350                         qcom,skip-power-up;
2351
2352                         out-ports {
2353                                 port {
2354                                         etm1_out: endpoint {
2355                                                 remote-endpoint = <&apss_funnel_in1>;
2356                                         };
2357                                 };
2358                         };
2359                 };
2360
2361                 etm@7240000 {
2362                         compatible = "arm,coresight-etm4x", "arm,primecell";
2363                         reg = <0 0x07240000 0 0x1000>;
2364
2365                         cpu = <&CPU2>;
2366
2367                         clocks = <&aoss_qmp>;
2368                         clock-names = "apb_pclk";
2369                         arm,coresight-loses-context-with-cpu;
2370                         qcom,skip-power-up;
2371
2372                         out-ports {
2373                                 port {
2374                                         etm2_out: endpoint {
2375                                                 remote-endpoint = <&apss_funnel_in2>;
2376                                         };
2377                                 };
2378                         };
2379                 };
2380
2381                 etm@7340000 {
2382                         compatible = "arm,coresight-etm4x", "arm,primecell";
2383                         reg = <0 0x07340000 0 0x1000>;
2384
2385                         cpu = <&CPU3>;
2386
2387                         clocks = <&aoss_qmp>;
2388                         clock-names = "apb_pclk";
2389                         arm,coresight-loses-context-with-cpu;
2390                         qcom,skip-power-up;
2391
2392                         out-ports {
2393                                 port {
2394                                         etm3_out: endpoint {
2395                                                 remote-endpoint = <&apss_funnel_in3>;
2396                                         };
2397                                 };
2398                         };
2399                 };
2400
2401                 etm@7440000 {
2402                         compatible = "arm,coresight-etm4x", "arm,primecell";
2403                         reg = <0 0x07440000 0 0x1000>;
2404
2405                         cpu = <&CPU4>;
2406
2407                         clocks = <&aoss_qmp>;
2408                         clock-names = "apb_pclk";
2409                         arm,coresight-loses-context-with-cpu;
2410                         qcom,skip-power-up;
2411
2412                         out-ports {
2413                                 port {
2414                                         etm4_out: endpoint {
2415                                                 remote-endpoint = <&apss_funnel_in4>;
2416                                         };
2417                                 };
2418                         };
2419                 };
2420
2421                 etm@7540000 {
2422                         compatible = "arm,coresight-etm4x", "arm,primecell";
2423                         reg = <0 0x07540000 0 0x1000>;
2424
2425                         cpu = <&CPU5>;
2426
2427                         clocks = <&aoss_qmp>;
2428                         clock-names = "apb_pclk";
2429                         arm,coresight-loses-context-with-cpu;
2430                         qcom,skip-power-up;
2431
2432                         out-ports {
2433                                 port {
2434                                         etm5_out: endpoint {
2435                                                 remote-endpoint = <&apss_funnel_in5>;
2436                                         };
2437                                 };
2438                         };
2439                 };
2440
2441                 etm@7640000 {
2442                         compatible = "arm,coresight-etm4x", "arm,primecell";
2443                         reg = <0 0x07640000 0 0x1000>;
2444
2445                         cpu = <&CPU6>;
2446
2447                         clocks = <&aoss_qmp>;
2448                         clock-names = "apb_pclk";
2449                         arm,coresight-loses-context-with-cpu;
2450                         qcom,skip-power-up;
2451
2452                         out-ports {
2453                                 port {
2454                                         etm6_out: endpoint {
2455                                                 remote-endpoint = <&apss_funnel_in6>;
2456                                         };
2457                                 };
2458                         };
2459                 };
2460
2461                 etm@7740000 {
2462                         compatible = "arm,coresight-etm4x", "arm,primecell";
2463                         reg = <0 0x07740000 0 0x1000>;
2464
2465                         cpu = <&CPU7>;
2466
2467                         clocks = <&aoss_qmp>;
2468                         clock-names = "apb_pclk";
2469                         arm,coresight-loses-context-with-cpu;
2470                         qcom,skip-power-up;
2471
2472                         out-ports {
2473                                 port {
2474                                         etm7_out: endpoint {
2475                                                 remote-endpoint = <&apss_funnel_in7>;
2476                                         };
2477                                 };
2478                         };
2479                 };
2480
2481                 funnel@7800000 { /* APSS Funnel */
2482                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2483                         reg = <0 0x07800000 0 0x1000>;
2484
2485                         clocks = <&aoss_qmp>;
2486                         clock-names = "apb_pclk";
2487
2488                         out-ports {
2489                                 port {
2490                                         apss_funnel_out: endpoint {
2491                                                 remote-endpoint = <&apss_merge_funnel_in>;
2492                                         };
2493                                 };
2494                         };
2495
2496                         in-ports {
2497                                 #address-cells = <1>;
2498                                 #size-cells = <0>;
2499
2500                                 port@0 {
2501                                         reg = <0>;
2502                                         apss_funnel_in0: endpoint {
2503                                                 remote-endpoint = <&etm0_out>;
2504                                         };
2505                                 };
2506
2507                                 port@1 {
2508                                         reg = <1>;
2509                                         apss_funnel_in1: endpoint {
2510                                                 remote-endpoint = <&etm1_out>;
2511                                         };
2512                                 };
2513
2514                                 port@2 {
2515                                         reg = <2>;
2516                                         apss_funnel_in2: endpoint {
2517                                                 remote-endpoint = <&etm2_out>;
2518                                         };
2519                                 };
2520
2521                                 port@3 {
2522                                         reg = <3>;
2523                                         apss_funnel_in3: endpoint {
2524                                                 remote-endpoint = <&etm3_out>;
2525                                         };
2526                                 };
2527
2528                                 port@4 {
2529                                         reg = <4>;
2530                                         apss_funnel_in4: endpoint {
2531                                                 remote-endpoint = <&etm4_out>;
2532                                         };
2533                                 };
2534
2535                                 port@5 {
2536                                         reg = <5>;
2537                                         apss_funnel_in5: endpoint {
2538                                                 remote-endpoint = <&etm5_out>;
2539                                         };
2540                                 };
2541
2542                                 port@6 {
2543                                         reg = <6>;
2544                                         apss_funnel_in6: endpoint {
2545                                                 remote-endpoint = <&etm6_out>;
2546                                         };
2547                                 };
2548
2549                                 port@7 {
2550                                         reg = <7>;
2551                                         apss_funnel_in7: endpoint {
2552                                                 remote-endpoint = <&etm7_out>;
2553                                         };
2554                                 };
2555                         };
2556                 };
2557
2558                 funnel@7810000 {
2559                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2560                         reg = <0 0x07810000 0 0x1000>;
2561
2562                         clocks = <&aoss_qmp>;
2563                         clock-names = "apb_pclk";
2564
2565                         out-ports {
2566                                 port {
2567                                         apss_merge_funnel_out: endpoint {
2568                                                 remote-endpoint = <&funnel1_in4>;
2569                                         };
2570                                 };
2571                         };
2572
2573                         in-ports {
2574                                 port {
2575                                         apss_merge_funnel_in: endpoint {
2576                                                 remote-endpoint = <&apss_funnel_out>;
2577                                         };
2578                                 };
2579                         };
2580                 };
2581
2582                 sdhc_2: mmc@8804000 {
2583                         compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
2584                         reg = <0 0x08804000 0 0x1000>;
2585
2586                         iommus = <&apps_smmu 0x80 0>;
2587                         interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
2588                                         <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
2589                         interrupt-names = "hc_irq", "pwr_irq";
2590
2591                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2592                                  <&gcc GCC_SDCC2_APPS_CLK>,
2593                                  <&rpmhcc RPMH_CXO_CLK>;
2594                         clock-names = "iface", "core", "xo";
2595
2596                         interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
2597                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
2598                         interconnect-names = "sdhc-ddr","cpu-sdhc";
2599                         power-domains = <&rpmhpd SC7180_CX>;
2600                         operating-points-v2 = <&sdhc2_opp_table>;
2601
2602                         bus-width = <4>;
2603
2604                         status = "disabled";
2605
2606                         sdhc2_opp_table: opp-table {
2607                                 compatible = "operating-points-v2";
2608
2609                                 opp-100000000 {
2610                                         opp-hz = /bits/ 64 <100000000>;
2611                                         required-opps = <&rpmhpd_opp_low_svs>;
2612                                         opp-peak-kBps = <1800000 600000>;
2613                                         opp-avg-kBps = <100000 0>;
2614                                 };
2615
2616                                 opp-202000000 {
2617                                         opp-hz = /bits/ 64 <202000000>;
2618                                         required-opps = <&rpmhpd_opp_nom>;
2619                                         opp-peak-kBps = <5400000 1600000>;
2620                                         opp-avg-kBps = <200000 0>;
2621                                 };
2622                         };
2623                 };
2624
2625                 qspi_opp_table: opp-table-qspi {
2626                         compatible = "operating-points-v2";
2627
2628                         opp-75000000 {
2629                                 opp-hz = /bits/ 64 <75000000>;
2630                                 required-opps = <&rpmhpd_opp_low_svs>;
2631                         };
2632
2633                         opp-150000000 {
2634                                 opp-hz = /bits/ 64 <150000000>;
2635                                 required-opps = <&rpmhpd_opp_svs>;
2636                         };
2637
2638                         opp-300000000 {
2639                                 opp-hz = /bits/ 64 <300000000>;
2640                                 required-opps = <&rpmhpd_opp_nom>;
2641                         };
2642                 };
2643
2644                 qspi: spi@88dc000 {
2645                         compatible = "qcom,sc7180-qspi", "qcom,qspi-v1";
2646                         reg = <0 0x088dc000 0 0x600>;
2647                         #address-cells = <1>;
2648                         #size-cells = <0>;
2649                         interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
2650                         clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
2651                                  <&gcc GCC_QSPI_CORE_CLK>;
2652                         clock-names = "iface", "core";
2653                         interconnects = <&gem_noc MASTER_APPSS_PROC 0
2654                                         &config_noc SLAVE_QSPI_0 0>;
2655                         interconnect-names = "qspi-config";
2656                         power-domains = <&rpmhpd SC7180_CX>;
2657                         operating-points-v2 = <&qspi_opp_table>;
2658                         status = "disabled";
2659                 };
2660
2661                 usb_1_hsphy: phy@88e3000 {
2662                         compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy";
2663                         reg = <0 0x088e3000 0 0x400>;
2664                         status = "disabled";
2665                         #phy-cells = <0>;
2666                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2667                                  <&rpmhcc RPMH_CXO_CLK>;
2668                         clock-names = "cfg_ahb", "ref";
2669                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2670
2671                         nvmem-cells = <&qusb2p_hstx_trim>;
2672                 };
2673
2674                 usb_1_qmpphy: phy-wrapper@88e9000 {
2675                         compatible = "qcom,sc7180-qmp-usb3-dp-phy";
2676                         reg = <0 0x088e9000 0 0x18c>,
2677                               <0 0x088e8000 0 0x3c>,
2678                               <0 0x088ea000 0 0x18c>;
2679                         status = "disabled";
2680                         #address-cells = <2>;
2681                         #size-cells = <2>;
2682                         ranges;
2683
2684                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2685                                  <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2686                                  <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
2687                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
2688                         clock-names = "aux", "cfg_ahb", "ref", "com_aux";
2689
2690                         resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
2691                                  <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
2692                         reset-names = "phy", "common";
2693
2694                         usb_1_ssphy: usb3-phy@88e9200 {
2695                                 reg = <0 0x088e9200 0 0x128>,
2696                                       <0 0x088e9400 0 0x200>,
2697                                       <0 0x088e9c00 0 0x218>,
2698                                       <0 0x088e9600 0 0x128>,
2699                                       <0 0x088e9800 0 0x200>,
2700                                       <0 0x088e9a00 0 0x18>;
2701                                 #clock-cells = <0>;
2702                                 #phy-cells = <0>;
2703                                 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2704                                 clock-names = "pipe0";
2705                                 clock-output-names = "usb3_phy_pipe_clk_src";
2706                         };
2707
2708                         dp_phy: dp-phy@88ea200 {
2709                                 reg = <0 0x088ea200 0 0x200>,
2710                                       <0 0x088ea400 0 0x200>,
2711                                       <0 0x088eaa00 0 0x200>,
2712                                       <0 0x088ea600 0 0x200>,
2713                                       <0 0x088ea800 0 0x200>;
2714                                 #clock-cells = <1>;
2715                                 #phy-cells = <0>;
2716                         };
2717                 };
2718
2719                 dc_noc: interconnect@9160000 {
2720                         compatible = "qcom,sc7180-dc-noc";
2721                         reg = <0 0x09160000 0 0x03200>;
2722                         #interconnect-cells = <2>;
2723                         qcom,bcm-voters = <&apps_bcm_voter>;
2724                 };
2725
2726                 system-cache-controller@9200000 {
2727                         compatible = "qcom,sc7180-llcc";
2728                         reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
2729                         reg-names = "llcc_base", "llcc_broadcast_base";
2730                         interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
2731                 };
2732
2733                 gem_noc: interconnect@9680000 {
2734                         compatible = "qcom,sc7180-gem-noc";
2735                         reg = <0 0x09680000 0 0x3e200>;
2736                         #interconnect-cells = <2>;
2737                         qcom,bcm-voters = <&apps_bcm_voter>;
2738                 };
2739
2740                 npu_noc: interconnect@9990000 {
2741                         compatible = "qcom,sc7180-npu-noc";
2742                         reg = <0 0x09990000 0 0x1600>;
2743                         #interconnect-cells = <2>;
2744                         qcom,bcm-voters = <&apps_bcm_voter>;
2745                 };
2746
2747                 usb_1: usb@a6f8800 {
2748                         compatible = "qcom,sc7180-dwc3", "qcom,dwc3";
2749                         reg = <0 0x0a6f8800 0 0x400>;
2750                         status = "disabled";
2751                         #address-cells = <2>;
2752                         #size-cells = <2>;
2753                         ranges;
2754                         dma-ranges;
2755
2756                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
2757                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
2758                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
2759                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
2760                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
2761                         clock-names = "cfg_noc",
2762                                       "core",
2763                                       "iface",
2764                                       "sleep",
2765                                       "mock_utmi";
2766
2767                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2768                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
2769                         assigned-clock-rates = <19200000>, <150000000>;
2770
2771                         interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
2772                                               <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
2773                                               <&pdc 8 IRQ_TYPE_LEVEL_HIGH>,
2774                                               <&pdc 9 IRQ_TYPE_LEVEL_HIGH>;
2775                         interrupt-names = "hs_phy_irq", "ss_phy_irq",
2776                                           "dm_hs_phy_irq", "dp_hs_phy_irq";
2777
2778                         power-domains = <&gcc USB30_PRIM_GDSC>;
2779                         required-opps = <&rpmhpd_opp_nom>;
2780
2781                         resets = <&gcc GCC_USB30_PRIM_BCR>;
2782
2783                         interconnects = <&aggre2_noc MASTER_USB3 0 &mc_virt SLAVE_EBI1 0>,
2784                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>;
2785                         interconnect-names = "usb-ddr", "apps-usb";
2786
2787                         wakeup-source;
2788
2789                         usb_1_dwc3: usb@a600000 {
2790                                 compatible = "snps,dwc3";
2791                                 reg = <0 0x0a600000 0 0xe000>;
2792                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
2793                                 iommus = <&apps_smmu 0x540 0>;
2794                                 snps,dis_u2_susphy_quirk;
2795                                 snps,dis_enblslpm_quirk;
2796                                 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
2797                                 phy-names = "usb2-phy", "usb3-phy";
2798                                 maximum-speed = "super-speed";
2799                         };
2800                 };
2801
2802                 venus: video-codec@aa00000 {
2803                         compatible = "qcom,sc7180-venus";
2804                         reg = <0 0x0aa00000 0 0xff000>;
2805                         interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
2806                         power-domains = <&videocc VENUS_GDSC>,
2807                                         <&videocc VCODEC0_GDSC>,
2808                                         <&rpmhpd SC7180_CX>;
2809                         power-domain-names = "venus", "vcodec0", "cx";
2810                         operating-points-v2 = <&venus_opp_table>;
2811                         clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
2812                                  <&videocc VIDEO_CC_VENUS_AHB_CLK>,
2813                                  <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
2814                                  <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
2815                                  <&videocc VIDEO_CC_VCODEC0_AXI_CLK>;
2816                         clock-names = "core", "iface", "bus",
2817                                       "vcodec0_core", "vcodec0_bus";
2818                         iommus = <&apps_smmu 0x0c00 0x60>;
2819                         memory-region = <&venus_mem>;
2820                         interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>,
2821                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
2822                         interconnect-names = "video-mem", "cpu-cfg";
2823
2824                         video-decoder {
2825                                 compatible = "venus-decoder";
2826                         };
2827
2828                         video-encoder {
2829                                 compatible = "venus-encoder";
2830                         };
2831
2832                         venus_opp_table: opp-table {
2833                                 compatible = "operating-points-v2";
2834
2835                                 opp-150000000 {
2836                                         opp-hz = /bits/ 64 <150000000>;
2837                                         required-opps = <&rpmhpd_opp_low_svs>;
2838                                 };
2839
2840                                 opp-270000000 {
2841                                         opp-hz = /bits/ 64 <270000000>;
2842                                         required-opps = <&rpmhpd_opp_svs>;
2843                                 };
2844
2845                                 opp-340000000 {
2846                                         opp-hz = /bits/ 64 <340000000>;
2847                                         required-opps = <&rpmhpd_opp_svs_l1>;
2848                                 };
2849
2850                                 opp-434000000 {
2851                                         opp-hz = /bits/ 64 <434000000>;
2852                                         required-opps = <&rpmhpd_opp_nom>;
2853                                 };
2854
2855                                 opp-500000097 {
2856                                         opp-hz = /bits/ 64 <500000097>;
2857                                         required-opps = <&rpmhpd_opp_turbo>;
2858                                 };
2859                         };
2860                 };
2861
2862                 videocc: clock-controller@ab00000 {
2863                         compatible = "qcom,sc7180-videocc";
2864                         reg = <0 0x0ab00000 0 0x10000>;
2865                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2866                         clock-names = "bi_tcxo";
2867                         #clock-cells = <1>;
2868                         #reset-cells = <1>;
2869                         #power-domain-cells = <1>;
2870                 };
2871
2872                 camnoc_virt: interconnect@ac00000 {
2873                         compatible = "qcom,sc7180-camnoc-virt";
2874                         reg = <0 0x0ac00000 0 0x1000>;
2875                         #interconnect-cells = <2>;
2876                         qcom,bcm-voters = <&apps_bcm_voter>;
2877                 };
2878
2879                 camcc: clock-controller@ad00000 {
2880                         compatible = "qcom,sc7180-camcc";
2881                         reg = <0 0x0ad00000 0 0x10000>;
2882                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2883                                <&gcc GCC_CAMERA_AHB_CLK>,
2884                                <&gcc GCC_CAMERA_XO_CLK>;
2885                         clock-names = "bi_tcxo", "iface", "xo";
2886                         #clock-cells = <1>;
2887                         #reset-cells = <1>;
2888                         #power-domain-cells = <1>;
2889                 };
2890
2891                 mdss: mdss@ae00000 {
2892                         compatible = "qcom,sc7180-mdss";
2893                         reg = <0 0x0ae00000 0 0x1000>;
2894                         reg-names = "mdss";
2895
2896                         power-domains = <&dispcc MDSS_GDSC>;
2897
2898                         clocks = <&gcc GCC_DISP_AHB_CLK>,
2899                                  <&dispcc DISP_CC_MDSS_AHB_CLK>,
2900                                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
2901                         clock-names = "iface", "ahb", "core";
2902
2903                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
2904                         interrupt-controller;
2905                         #interrupt-cells = <1>;
2906
2907                         interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>;
2908                         interconnect-names = "mdp0-mem";
2909
2910                         iommus = <&apps_smmu 0x800 0x2>;
2911
2912                         #address-cells = <2>;
2913                         #size-cells = <2>;
2914                         ranges;
2915
2916                         status = "disabled";
2917
2918                         mdp: display-controller@ae01000 {
2919                                 compatible = "qcom,sc7180-dpu";
2920                                 reg = <0 0x0ae01000 0 0x8f000>,
2921                                       <0 0x0aeb0000 0 0x2008>;
2922                                 reg-names = "mdp", "vbif";
2923
2924                                 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
2925                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
2926                                          <&dispcc DISP_CC_MDSS_ROT_CLK>,
2927                                          <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
2928                                          <&dispcc DISP_CC_MDSS_MDP_CLK>,
2929                                          <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2930                                 clock-names = "bus", "iface", "rot", "lut", "core",
2931                                               "vsync";
2932                                 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
2933                                                   <&dispcc DISP_CC_MDSS_ROT_CLK>,
2934                                                   <&dispcc DISP_CC_MDSS_AHB_CLK>;
2935                                 assigned-clock-rates = <19200000>,
2936                                                        <19200000>,
2937                                                        <19200000>;
2938                                 operating-points-v2 = <&mdp_opp_table>;
2939                                 power-domains = <&rpmhpd SC7180_CX>;
2940
2941                                 interrupt-parent = <&mdss>;
2942                                 interrupts = <0>;
2943
2944                                 status = "disabled";
2945
2946                                 ports {
2947                                         #address-cells = <1>;
2948                                         #size-cells = <0>;
2949
2950                                         port@0 {
2951                                                 reg = <0>;
2952                                                 dpu_intf1_out: endpoint {
2953                                                         remote-endpoint = <&dsi0_in>;
2954                                                 };
2955                                         };
2956
2957                                         port@2 {
2958                                                 reg = <2>;
2959                                                 dpu_intf0_out: endpoint {
2960                                                         remote-endpoint = <&dp_in>;
2961                                                 };
2962                                         };
2963                                 };
2964
2965                                 mdp_opp_table: opp-table {
2966                                         compatible = "operating-points-v2";
2967
2968                                         opp-200000000 {
2969                                                 opp-hz = /bits/ 64 <200000000>;
2970                                                 required-opps = <&rpmhpd_opp_low_svs>;
2971                                         };
2972
2973                                         opp-300000000 {
2974                                                 opp-hz = /bits/ 64 <300000000>;
2975                                                 required-opps = <&rpmhpd_opp_svs>;
2976                                         };
2977
2978                                         opp-345000000 {
2979                                                 opp-hz = /bits/ 64 <345000000>;
2980                                                 required-opps = <&rpmhpd_opp_svs_l1>;
2981                                         };
2982
2983                                         opp-460000000 {
2984                                                 opp-hz = /bits/ 64 <460000000>;
2985                                                 required-opps = <&rpmhpd_opp_nom>;
2986                                         };
2987                                 };
2988
2989                         };
2990
2991                         dsi0: dsi@ae94000 {
2992                                 compatible = "qcom,mdss-dsi-ctrl";
2993                                 reg = <0 0x0ae94000 0 0x400>;
2994                                 reg-names = "dsi_ctrl";
2995
2996                                 interrupt-parent = <&mdss>;
2997                                 interrupts = <4>;
2998
2999                                 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
3000                                          <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
3001                                          <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
3002                                          <&dispcc DISP_CC_MDSS_ESC0_CLK>,
3003                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
3004                                          <&gcc GCC_DISP_HF_AXI_CLK>;
3005                                 clock-names = "byte",
3006                                               "byte_intf",
3007                                               "pixel",
3008                                               "core",
3009                                               "iface",
3010                                               "bus";
3011
3012                                 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
3013                                 assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
3014
3015                                 operating-points-v2 = <&dsi_opp_table>;
3016                                 power-domains = <&rpmhpd SC7180_CX>;
3017
3018                                 phys = <&dsi_phy>;
3019
3020                                 #address-cells = <1>;
3021                                 #size-cells = <0>;
3022
3023                                 status = "disabled";
3024
3025                                 ports {
3026                                         #address-cells = <1>;
3027                                         #size-cells = <0>;
3028
3029                                         port@0 {
3030                                                 reg = <0>;
3031                                                 dsi0_in: endpoint {
3032                                                         remote-endpoint = <&dpu_intf1_out>;
3033                                                 };
3034                                         };
3035
3036                                         port@1 {
3037                                                 reg = <1>;
3038                                                 dsi0_out: endpoint {
3039                                                 };
3040                                         };
3041                                 };
3042
3043                                 dsi_opp_table: opp-table {
3044                                         compatible = "operating-points-v2";
3045
3046                                         opp-187500000 {
3047                                                 opp-hz = /bits/ 64 <187500000>;
3048                                                 required-opps = <&rpmhpd_opp_low_svs>;
3049                                         };
3050
3051                                         opp-300000000 {
3052                                                 opp-hz = /bits/ 64 <300000000>;
3053                                                 required-opps = <&rpmhpd_opp_svs>;
3054                                         };
3055
3056                                         opp-358000000 {
3057                                                 opp-hz = /bits/ 64 <358000000>;
3058                                                 required-opps = <&rpmhpd_opp_svs_l1>;
3059                                         };
3060                                 };
3061                         };
3062
3063                         dsi_phy: phy@ae94400 {
3064                                 compatible = "qcom,dsi-phy-10nm";
3065                                 reg = <0 0x0ae94400 0 0x200>,
3066                                       <0 0x0ae94600 0 0x280>,
3067                                       <0 0x0ae94a00 0 0x1e0>;
3068                                 reg-names = "dsi_phy",
3069                                             "dsi_phy_lane",
3070                                             "dsi_pll";
3071
3072                                 #clock-cells = <1>;
3073                                 #phy-cells = <0>;
3074
3075                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3076                                          <&rpmhcc RPMH_CXO_CLK>;
3077                                 clock-names = "iface", "ref";
3078
3079                                 status = "disabled";
3080                         };
3081
3082                         mdss_dp: displayport-controller@ae90000 {
3083                                 compatible = "qcom,sc7180-dp";
3084                                 status = "disabled";
3085
3086                                 reg = <0 0xae90000 0 0x200>,
3087                                       <0 0xae90200 0 0x200>,
3088                                       <0 0xae90400 0 0xc00>,
3089                                       <0 0xae91000 0 0x400>,
3090                                       <0 0xae91400 0 0x400>;
3091
3092                                 interrupt-parent = <&mdss>;
3093                                 interrupts = <12>;
3094
3095                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3096                                          <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
3097                                          <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
3098                                          <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
3099                                          <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
3100                                 clock-names = "core_iface", "core_aux", "ctrl_link",
3101                                               "ctrl_link_iface", "stream_pixel";
3102                                 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
3103                                                   <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
3104                                 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
3105                                 phys = <&dp_phy>;
3106                                 phy-names = "dp";
3107
3108                                 operating-points-v2 = <&dp_opp_table>;
3109                                 power-domains = <&rpmhpd SC7180_CX>;
3110
3111                                 #sound-dai-cells = <0>;
3112
3113                                 ports {
3114                                         #address-cells = <1>;
3115                                         #size-cells = <0>;
3116                                         port@0 {
3117                                                 reg = <0>;
3118                                                 dp_in: endpoint {
3119                                                         remote-endpoint = <&dpu_intf0_out>;
3120                                                 };
3121                                         };
3122
3123                                         port@1 {
3124                                                 reg = <1>;
3125                                                 dp_out: endpoint { };
3126                                         };
3127                                 };
3128
3129                                 dp_opp_table: opp-table {
3130                                         compatible = "operating-points-v2";
3131
3132                                         opp-160000000 {
3133                                                 opp-hz = /bits/ 64 <160000000>;
3134                                                 required-opps = <&rpmhpd_opp_low_svs>;
3135                                         };
3136
3137                                         opp-270000000 {
3138                                                 opp-hz = /bits/ 64 <270000000>;
3139                                                 required-opps = <&rpmhpd_opp_svs>;
3140                                         };
3141
3142                                         opp-540000000 {
3143                                                 opp-hz = /bits/ 64 <540000000>;
3144                                                 required-opps = <&rpmhpd_opp_svs_l1>;
3145                                         };
3146
3147                                         opp-810000000 {
3148                                                 opp-hz = /bits/ 64 <810000000>;
3149                                                 required-opps = <&rpmhpd_opp_nom>;
3150                                         };
3151                                 };
3152                         };
3153                 };
3154
3155                 dispcc: clock-controller@af00000 {
3156                         compatible = "qcom,sc7180-dispcc";
3157                         reg = <0 0x0af00000 0 0x200000>;
3158                         clocks = <&rpmhcc RPMH_CXO_CLK>,
3159                                  <&gcc GCC_DISP_GPLL0_CLK_SRC>,
3160                                  <&dsi_phy 0>,
3161                                  <&dsi_phy 1>,
3162                                  <&dp_phy 0>,
3163                                  <&dp_phy 1>;
3164                         clock-names = "bi_tcxo",
3165                                       "gcc_disp_gpll0_clk_src",
3166                                       "dsi0_phy_pll_out_byteclk",
3167                                       "dsi0_phy_pll_out_dsiclk",
3168                                       "dp_phy_pll_link_clk",
3169                                       "dp_phy_pll_vco_div_clk";
3170                         #clock-cells = <1>;
3171                         #reset-cells = <1>;
3172                         #power-domain-cells = <1>;
3173                 };
3174
3175                 pdc: interrupt-controller@b220000 {
3176                         compatible = "qcom,sc7180-pdc", "qcom,pdc";
3177                         reg = <0 0x0b220000 0 0x30000>;
3178                         qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
3179                         #interrupt-cells = <2>;
3180                         interrupt-parent = <&intc>;
3181                         interrupt-controller;
3182                 };
3183
3184                 pdc_reset: reset-controller@b2e0000 {
3185                         compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global";
3186                         reg = <0 0x0b2e0000 0 0x20000>;
3187                         #reset-cells = <1>;
3188                 };
3189
3190                 tsens0: thermal-sensor@c263000 {
3191                         compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3192                         reg = <0 0x0c263000 0 0x1ff>, /* TM */
3193                                 <0 0x0c222000 0 0x1ff>; /* SROT */
3194                         #qcom,sensors = <15>;
3195                         interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3196                                      <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
3197                         interrupt-names = "uplow","critical";
3198                         #thermal-sensor-cells = <1>;
3199                 };
3200
3201                 tsens1: thermal-sensor@c265000 {
3202                         compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3203                         reg = <0 0x0c265000 0 0x1ff>, /* TM */
3204                                 <0 0x0c223000 0 0x1ff>; /* SROT */
3205                         #qcom,sensors = <10>;
3206                         interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
3207                                      <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
3208                         interrupt-names = "uplow","critical";
3209                         #thermal-sensor-cells = <1>;
3210                 };
3211
3212                 aoss_reset: reset-controller@c2a0000 {
3213                         compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc";
3214                         reg = <0 0x0c2a0000 0 0x31000>;
3215                         #reset-cells = <1>;
3216                 };
3217
3218                 aoss_qmp: power-controller@c300000 {
3219                         compatible = "qcom,sc7180-aoss-qmp", "qcom,aoss-qmp";
3220                         reg = <0 0x0c300000 0 0x400>;
3221                         interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
3222                         mboxes = <&apss_shared 0>;
3223
3224                         #clock-cells = <0>;
3225                 };
3226
3227                 sram@c3f0000 {
3228                         compatible = "qcom,rpmh-stats";
3229                         reg = <0 0x0c3f0000 0 0x400>;
3230                 };
3231
3232                 spmi_bus: spmi@c440000 {
3233                         compatible = "qcom,spmi-pmic-arb";
3234                         reg = <0 0x0c440000 0 0x1100>,
3235                               <0 0x0c600000 0 0x2000000>,
3236                               <0 0x0e600000 0 0x100000>,
3237                               <0 0x0e700000 0 0xa0000>,
3238                               <0 0x0c40a000 0 0x26000>;
3239                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3240                         interrupt-names = "periph_irq";
3241                         interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3242                         qcom,ee = <0>;
3243                         qcom,channel = <0>;
3244                         #address-cells = <1>;
3245                         #size-cells = <1>;
3246                         interrupt-controller;
3247                         #interrupt-cells = <4>;
3248                         cell-index = <0>;
3249                 };
3250
3251                 sram@146aa000 {
3252                         compatible = "qcom,sc7180-imem", "syscon", "simple-mfd";
3253                         reg = <0 0x146aa000 0 0x2000>;
3254
3255                         #address-cells = <1>;
3256                         #size-cells = <1>;
3257
3258                         ranges = <0 0 0x146aa000 0x2000>;
3259
3260                         pil-reloc@94c {
3261                                 compatible = "qcom,pil-reloc-info";
3262                                 reg = <0x94c 0xc8>;
3263                         };
3264                 };
3265
3266                 apps_smmu: iommu@15000000 {
3267                         compatible = "qcom,sc7180-smmu-500", "arm,mmu-500";
3268                         reg = <0 0x15000000 0 0x100000>;
3269                         #iommu-cells = <2>;
3270                         #global-interrupts = <1>;
3271                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
3272                                      <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
3273                                      <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
3274                                      <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
3275                                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
3276                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
3277                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
3278                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
3279                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
3280                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3281                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3282                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3283                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3284                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3285                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3286                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3287                                      <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3288                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3289                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3290                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3291                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3292                                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3293                                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3294                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3295                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3296                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3297                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3298                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3299                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3300                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3301                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3302                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3303                                      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3304                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3305                                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3306                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3307                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3308                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3309                                      <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3310                                      <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3311                                      <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3312                                      <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3313                                      <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3314                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3315                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3316                                      <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3317                                      <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3318                                      <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3319                                      <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3320                                      <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3321                                      <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3322                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3323                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3324                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3325                                      <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3326                                      <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3327                                      <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3328                                      <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3329                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3330                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3331                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3332                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3333                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3334                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3335                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3336                                      <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3337                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
3338                                      <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
3339                                      <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
3340                                      <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
3341                                      <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
3342                                      <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
3343                                      <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
3344                                      <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
3345                                      <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
3346                                      <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
3347                                      <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
3348                                      <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
3349                                      <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
3350                                      <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
3351                                      <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
3352                 };
3353
3354                 intc: interrupt-controller@17a00000 {
3355                         compatible = "arm,gic-v3";
3356                         #address-cells = <2>;
3357                         #size-cells = <2>;
3358                         ranges;
3359                         #interrupt-cells = <3>;
3360                         interrupt-controller;
3361                         reg = <0 0x17a00000 0 0x10000>,     /* GICD */
3362                               <0 0x17a60000 0 0x100000>;    /* GICR * 8 */
3363                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3364
3365                         msi-controller@17a40000 {
3366                                 compatible = "arm,gic-v3-its";
3367                                 msi-controller;
3368                                 #msi-cells = <1>;
3369                                 reg = <0 0x17a40000 0 0x20000>;
3370                                 status = "disabled";
3371                         };
3372                 };
3373
3374                 apss_shared: mailbox@17c00000 {
3375                         compatible = "qcom,sc7180-apss-shared";
3376                         reg = <0 0x17c00000 0 0x10000>;
3377                         #mbox-cells = <1>;
3378                 };
3379
3380                 watchdog@17c10000 {
3381                         compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt";
3382                         reg = <0 0x17c10000 0 0x1000>;
3383                         clocks = <&sleep_clk>;
3384                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
3385                 };
3386
3387                 timer@17c20000{
3388                         #address-cells = <1>;
3389                         #size-cells = <1>;
3390                         ranges = <0 0 0 0x20000000>;
3391                         compatible = "arm,armv7-timer-mem";
3392                         reg = <0 0x17c20000 0 0x1000>;
3393
3394                         frame@17c21000 {
3395                                 frame-number = <0>;
3396                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3397                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
3398                                 reg = <0x17c21000 0x1000>,
3399                                       <0x17c22000 0x1000>;
3400                         };
3401
3402                         frame@17c23000 {
3403                                 frame-number = <1>;
3404                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3405                                 reg = <0x17c23000 0x1000>;
3406                                 status = "disabled";
3407                         };
3408
3409                         frame@17c25000 {
3410                                 frame-number = <2>;
3411                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3412                                 reg = <0x17c25000 0x1000>;
3413                                 status = "disabled";
3414                         };
3415
3416                         frame@17c27000 {
3417                                 frame-number = <3>;
3418                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3419                                 reg = <0x17c27000 0x1000>;
3420                                 status = "disabled";
3421                         };
3422
3423                         frame@17c29000 {
3424                                 frame-number = <4>;
3425                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3426                                 reg = <0x17c29000 0x1000>;
3427                                 status = "disabled";
3428                         };
3429
3430                         frame@17c2b000 {
3431                                 frame-number = <5>;
3432                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3433                                 reg = <0x17c2b000 0x1000>;
3434                                 status = "disabled";
3435                         };
3436
3437                         frame@17c2d000 {
3438                                 frame-number = <6>;
3439                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3440                                 reg = <0x17c2d000 0x1000>;
3441                                 status = "disabled";
3442                         };
3443                 };
3444
3445                 apps_rsc: rsc@18200000 {
3446                         compatible = "qcom,rpmh-rsc";
3447                         reg = <0 0x18200000 0 0x10000>,
3448                               <0 0x18210000 0 0x10000>,
3449                               <0 0x18220000 0 0x10000>;
3450                         reg-names = "drv-0", "drv-1", "drv-2";
3451                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
3452                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
3453                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
3454                         qcom,tcs-offset = <0xd00>;
3455                         qcom,drv-id = <2>;
3456                         qcom,tcs-config = <ACTIVE_TCS  2>,
3457                                           <SLEEP_TCS   3>,
3458                                           <WAKE_TCS    3>,
3459                                           <CONTROL_TCS 1>;
3460
3461                         rpmhcc: clock-controller {
3462                                 compatible = "qcom,sc7180-rpmh-clk";
3463                                 clocks = <&xo_board>;
3464                                 clock-names = "xo";
3465                                 #clock-cells = <1>;
3466                         };
3467
3468                         rpmhpd: power-controller {
3469                                 compatible = "qcom,sc7180-rpmhpd";
3470                                 #power-domain-cells = <1>;
3471                                 operating-points-v2 = <&rpmhpd_opp_table>;
3472
3473                                 rpmhpd_opp_table: opp-table {
3474                                         compatible = "operating-points-v2";
3475
3476                                         rpmhpd_opp_ret: opp1 {
3477                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3478                                         };
3479
3480                                         rpmhpd_opp_min_svs: opp2 {
3481                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3482                                         };
3483
3484                                         rpmhpd_opp_low_svs: opp3 {
3485                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3486                                         };
3487
3488                                         rpmhpd_opp_svs: opp4 {
3489                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3490                                         };
3491
3492                                         rpmhpd_opp_svs_l1: opp5 {
3493                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3494                                         };
3495
3496                                         rpmhpd_opp_svs_l2: opp6 {
3497                                                 opp-level = <224>;
3498                                         };
3499
3500                                         rpmhpd_opp_nom: opp7 {
3501                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3502                                         };
3503
3504                                         rpmhpd_opp_nom_l1: opp8 {
3505                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3506                                         };
3507
3508                                         rpmhpd_opp_nom_l2: opp9 {
3509                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3510                                         };
3511
3512                                         rpmhpd_opp_turbo: opp10 {
3513                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3514                                         };
3515
3516                                         rpmhpd_opp_turbo_l1: opp11 {
3517                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3518                                         };
3519                                 };
3520                         };
3521
3522                         apps_bcm_voter: bcm-voter {
3523                                 compatible = "qcom,bcm-voter";
3524                         };
3525                 };
3526
3527                 osm_l3: interconnect@18321000 {
3528                         compatible = "qcom,sc7180-osm-l3";
3529                         reg = <0 0x18321000 0 0x1400>;
3530
3531                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3532                         clock-names = "xo", "alternate";
3533
3534                         #interconnect-cells = <1>;
3535                 };
3536
3537                 cpufreq_hw: cpufreq@18323000 {
3538                         compatible = "qcom,cpufreq-hw";
3539                         reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
3540                         reg-names = "freq-domain0", "freq-domain1";
3541
3542                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3543                         clock-names = "xo", "alternate";
3544
3545                         #freq-domain-cells = <1>;
3546                 };
3547
3548                 wifi: wifi@18800000 {
3549                         compatible = "qcom,wcn3990-wifi";
3550                         reg = <0 0x18800000 0 0x800000>;
3551                         reg-names = "membase";
3552                         iommus = <&apps_smmu 0xc0 0x1>;
3553                         interrupts =
3554                                 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >,
3555                                 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >,
3556                                 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >,
3557                                 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >,
3558                                 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >,
3559                                 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >,
3560                                 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >,
3561                                 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >,
3562                                 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >,
3563                                 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >,
3564                                 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH /* CE10 */>,
3565                                 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH /* CE11 */>;
3566                         memory-region = <&wlan_mem>;
3567                         qcom,msa-fixed-perm;
3568                         status = "disabled";
3569                 };
3570
3571                 lpasscc: clock-controller@62d00000 {
3572                         compatible = "qcom,sc7180-lpasscorecc";
3573                         reg = <0 0x62d00000 0 0x50000>,
3574                               <0 0x62780000 0 0x30000>;
3575                         reg-names = "lpass_core_cc", "lpass_audio_cc";
3576                         clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
3577                                  <&rpmhcc RPMH_CXO_CLK>;
3578                         clock-names = "iface", "bi_tcxo";
3579                         power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
3580                         #clock-cells = <1>;
3581                         #power-domain-cells = <1>;
3582                 };
3583
3584                 lpass_cpu: lpass@62d87000 {
3585                         compatible = "qcom,sc7180-lpass-cpu";
3586
3587                         reg = <0 0x62d87000 0 0x68000>, <0 0x62f00000 0 0x29000>;
3588                         reg-names = "lpass-hdmiif", "lpass-lpaif";
3589
3590                         iommus = <&apps_smmu 0x1020 0>,
3591                                 <&apps_smmu 0x1021 0>,
3592                                 <&apps_smmu 0x1032 0>;
3593
3594                         power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
3595
3596                         status = "disabled";
3597
3598                         clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
3599                                  <&lpasscc LPASS_AUDIO_CORE_CORE_CLK>,
3600                                  <&lpasscc LPASS_AUDIO_CORE_EXT_MCLK0_CLK>,
3601                                  <&lpasscc LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK>,
3602                                  <&lpasscc LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK>,
3603                                  <&lpasscc LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK>;
3604
3605                         clock-names = "pcnoc-sway-clk", "audio-core",
3606                                         "mclk0", "pcnoc-mport-clk",
3607                                         "mi2s-bit-clk0", "mi2s-bit-clk1";
3608
3609
3610                         #sound-dai-cells = <1>;
3611                         #address-cells = <1>;
3612                         #size-cells = <0>;
3613
3614                         interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
3615                                         <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
3616                         interrupt-names = "lpass-irq-lpaif", "lpass-irq-hdmi";
3617                 };
3618
3619                 lpass_hm: clock-controller@63000000 {
3620                         compatible = "qcom,sc7180-lpasshm";
3621                         reg = <0 0x63000000 0 0x28>;
3622                         clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
3623                                  <&rpmhcc RPMH_CXO_CLK>;
3624                         clock-names = "iface", "bi_tcxo";
3625                         #clock-cells = <1>;
3626                         #power-domain-cells = <1>;
3627                 };
3628         };
3629
3630         thermal-zones {
3631                 cpu0_thermal: cpu0-thermal {
3632                         polling-delay-passive = <250>;
3633                         polling-delay = <0>;
3634
3635                         thermal-sensors = <&tsens0 1>;
3636                         sustainable-power = <1052>;
3637
3638                         trips {
3639                                 cpu0_alert0: trip-point0 {
3640                                         temperature = <90000>;
3641                                         hysteresis = <2000>;
3642                                         type = "passive";
3643                                 };
3644
3645                                 cpu0_alert1: trip-point1 {
3646                                         temperature = <95000>;
3647                                         hysteresis = <2000>;
3648                                         type = "passive";
3649                                 };
3650
3651                                 cpu0_crit: cpu_crit {
3652                                         temperature = <110000>;
3653                                         hysteresis = <1000>;
3654                                         type = "critical";
3655                                 };
3656                         };
3657
3658                         cooling-maps {
3659                                 map0 {
3660                                         trip = <&cpu0_alert0>;
3661                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3662                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3663                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3664                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3665                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3666                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3667                                 };
3668                                 map1 {
3669                                         trip = <&cpu0_alert1>;
3670                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3671                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3672                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3673                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3674                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3675                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3676                                 };
3677                         };
3678                 };
3679
3680                 cpu1_thermal: cpu1-thermal {
3681                         polling-delay-passive = <250>;
3682                         polling-delay = <0>;
3683
3684                         thermal-sensors = <&tsens0 2>;
3685                         sustainable-power = <1052>;
3686
3687                         trips {
3688                                 cpu1_alert0: trip-point0 {
3689                                         temperature = <90000>;
3690                                         hysteresis = <2000>;
3691                                         type = "passive";
3692                                 };
3693
3694                                 cpu1_alert1: trip-point1 {
3695                                         temperature = <95000>;
3696                                         hysteresis = <2000>;
3697                                         type = "passive";
3698                                 };
3699
3700                                 cpu1_crit: cpu_crit {
3701                                         temperature = <110000>;
3702                                         hysteresis = <1000>;
3703                                         type = "critical";
3704                                 };
3705                         };
3706
3707                         cooling-maps {
3708                                 map0 {
3709                                         trip = <&cpu1_alert0>;
3710                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3711                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3712                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3713                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3714                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3715                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3716                                 };
3717                                 map1 {
3718                                         trip = <&cpu1_alert1>;
3719                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3720                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3721                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3722                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3723                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3724                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3725                                 };
3726                         };
3727                 };
3728
3729                 cpu2_thermal: cpu2-thermal {
3730                         polling-delay-passive = <250>;
3731                         polling-delay = <0>;
3732
3733                         thermal-sensors = <&tsens0 3>;
3734                         sustainable-power = <1052>;
3735
3736                         trips {
3737                                 cpu2_alert0: trip-point0 {
3738                                         temperature = <90000>;
3739                                         hysteresis = <2000>;
3740                                         type = "passive";
3741                                 };
3742
3743                                 cpu2_alert1: trip-point1 {
3744                                         temperature = <95000>;
3745                                         hysteresis = <2000>;
3746                                         type = "passive";
3747                                 };
3748
3749                                 cpu2_crit: cpu_crit {
3750                                         temperature = <110000>;
3751                                         hysteresis = <1000>;
3752                                         type = "critical";
3753                                 };
3754                         };
3755
3756                         cooling-maps {
3757                                 map0 {
3758                                         trip = <&cpu2_alert0>;
3759                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3760                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3761                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3762                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3763                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3764                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3765                                 };
3766                                 map1 {
3767                                         trip = <&cpu2_alert1>;
3768                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3769                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3770                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3771                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3772                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3773                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3774                                 };
3775                         };
3776                 };
3777
3778                 cpu3_thermal: cpu3-thermal {
3779                         polling-delay-passive = <250>;
3780                         polling-delay = <0>;
3781
3782                         thermal-sensors = <&tsens0 4>;
3783                         sustainable-power = <1052>;
3784
3785                         trips {
3786                                 cpu3_alert0: trip-point0 {
3787                                         temperature = <90000>;
3788                                         hysteresis = <2000>;
3789                                         type = "passive";
3790                                 };
3791
3792                                 cpu3_alert1: trip-point1 {
3793                                         temperature = <95000>;
3794                                         hysteresis = <2000>;
3795                                         type = "passive";
3796                                 };
3797
3798                                 cpu3_crit: cpu_crit {
3799                                         temperature = <110000>;
3800                                         hysteresis = <1000>;
3801                                         type = "critical";
3802                                 };
3803                         };
3804
3805                         cooling-maps {
3806                                 map0 {
3807                                         trip = <&cpu3_alert0>;
3808                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3809                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3810                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3811                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3812                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3813                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3814                                 };
3815                                 map1 {
3816                                         trip = <&cpu3_alert1>;
3817                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3818                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3819                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3820                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3821                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3822                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3823                                 };
3824                         };
3825                 };
3826
3827                 cpu4_thermal: cpu4-thermal {
3828                         polling-delay-passive = <250>;
3829                         polling-delay = <0>;
3830
3831                         thermal-sensors = <&tsens0 5>;
3832                         sustainable-power = <1052>;
3833
3834                         trips {
3835                                 cpu4_alert0: trip-point0 {
3836                                         temperature = <90000>;
3837                                         hysteresis = <2000>;
3838                                         type = "passive";
3839                                 };
3840
3841                                 cpu4_alert1: trip-point1 {
3842                                         temperature = <95000>;
3843                                         hysteresis = <2000>;
3844                                         type = "passive";
3845                                 };
3846
3847                                 cpu4_crit: cpu_crit {
3848                                         temperature = <110000>;
3849                                         hysteresis = <1000>;
3850                                         type = "critical";
3851                                 };
3852                         };
3853
3854                         cooling-maps {
3855                                 map0 {
3856                                         trip = <&cpu4_alert0>;
3857                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3858                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3859                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3860                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3861                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3862                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3863                                 };
3864                                 map1 {
3865                                         trip = <&cpu4_alert1>;
3866                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3867                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3868                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3869                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3870                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3871                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3872                                 };
3873                         };
3874                 };
3875
3876                 cpu5_thermal: cpu5-thermal {
3877                         polling-delay-passive = <250>;
3878                         polling-delay = <0>;
3879
3880                         thermal-sensors = <&tsens0 6>;
3881                         sustainable-power = <1052>;
3882
3883                         trips {
3884                                 cpu5_alert0: trip-point0 {
3885                                         temperature = <90000>;
3886                                         hysteresis = <2000>;
3887                                         type = "passive";
3888                                 };
3889
3890                                 cpu5_alert1: trip-point1 {
3891                                         temperature = <95000>;
3892                                         hysteresis = <2000>;
3893                                         type = "passive";
3894                                 };
3895
3896                                 cpu5_crit: cpu_crit {
3897                                         temperature = <110000>;
3898                                         hysteresis = <1000>;
3899                                         type = "critical";
3900                                 };
3901                         };
3902
3903                         cooling-maps {
3904                                 map0 {
3905                                         trip = <&cpu5_alert0>;
3906                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3907                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3908                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3909                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3910                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3911                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3912                                 };
3913                                 map1 {
3914                                         trip = <&cpu5_alert1>;
3915                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3916                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3917                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3918                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3919                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3920                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3921                                 };
3922                         };
3923                 };
3924
3925                 cpu6_thermal: cpu6-thermal {
3926                         polling-delay-passive = <250>;
3927                         polling-delay = <0>;
3928
3929                         thermal-sensors = <&tsens0 9>;
3930                         sustainable-power = <1425>;
3931
3932                         trips {
3933                                 cpu6_alert0: trip-point0 {
3934                                         temperature = <90000>;
3935                                         hysteresis = <2000>;
3936                                         type = "passive";
3937                                 };
3938
3939                                 cpu6_alert1: trip-point1 {
3940                                         temperature = <95000>;
3941                                         hysteresis = <2000>;
3942                                         type = "passive";
3943                                 };
3944
3945                                 cpu6_crit: cpu_crit {
3946                                         temperature = <110000>;
3947                                         hysteresis = <1000>;
3948                                         type = "critical";
3949                                 };
3950                         };
3951
3952                         cooling-maps {
3953                                 map0 {
3954                                         trip = <&cpu6_alert0>;
3955                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3956                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3957                                 };
3958                                 map1 {
3959                                         trip = <&cpu6_alert1>;
3960                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3961                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3962                                 };
3963                         };
3964                 };
3965
3966                 cpu7_thermal: cpu7-thermal {
3967                         polling-delay-passive = <250>;
3968                         polling-delay = <0>;
3969
3970                         thermal-sensors = <&tsens0 10>;
3971                         sustainable-power = <1425>;
3972
3973                         trips {
3974                                 cpu7_alert0: trip-point0 {
3975                                         temperature = <90000>;
3976                                         hysteresis = <2000>;
3977                                         type = "passive";
3978                                 };
3979
3980                                 cpu7_alert1: trip-point1 {
3981                                         temperature = <95000>;
3982                                         hysteresis = <2000>;
3983                                         type = "passive";
3984                                 };
3985
3986                                 cpu7_crit: cpu_crit {
3987                                         temperature = <110000>;
3988                                         hysteresis = <1000>;
3989                                         type = "critical";
3990                                 };
3991                         };
3992
3993                         cooling-maps {
3994                                 map0 {
3995                                         trip = <&cpu7_alert0>;
3996                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3997                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3998                                 };
3999                                 map1 {
4000                                         trip = <&cpu7_alert1>;
4001                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4002                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4003                                 };
4004                         };
4005                 };
4006
4007                 cpu8_thermal: cpu8-thermal {
4008                         polling-delay-passive = <250>;
4009                         polling-delay = <0>;
4010
4011                         thermal-sensors = <&tsens0 11>;
4012                         sustainable-power = <1425>;
4013
4014                         trips {
4015                                 cpu8_alert0: trip-point0 {
4016                                         temperature = <90000>;
4017                                         hysteresis = <2000>;
4018                                         type = "passive";
4019                                 };
4020
4021                                 cpu8_alert1: trip-point1 {
4022                                         temperature = <95000>;
4023                                         hysteresis = <2000>;
4024                                         type = "passive";
4025                                 };
4026
4027                                 cpu8_crit: cpu_crit {
4028                                         temperature = <110000>;
4029                                         hysteresis = <1000>;
4030                                         type = "critical";
4031                                 };
4032                         };
4033
4034                         cooling-maps {
4035                                 map0 {
4036                                         trip = <&cpu8_alert0>;
4037                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4038                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4039                                 };
4040                                 map1 {
4041                                         trip = <&cpu8_alert1>;
4042                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4043                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4044                                 };
4045                         };
4046                 };
4047
4048                 cpu9_thermal: cpu9-thermal {
4049                         polling-delay-passive = <250>;
4050                         polling-delay = <0>;
4051
4052                         thermal-sensors = <&tsens0 12>;
4053                         sustainable-power = <1425>;
4054
4055                         trips {
4056                                 cpu9_alert0: trip-point0 {
4057                                         temperature = <90000>;
4058                                         hysteresis = <2000>;
4059                                         type = "passive";
4060                                 };
4061
4062                                 cpu9_alert1: trip-point1 {
4063                                         temperature = <95000>;
4064                                         hysteresis = <2000>;
4065                                         type = "passive";
4066                                 };
4067
4068                                 cpu9_crit: cpu_crit {
4069                                         temperature = <110000>;
4070                                         hysteresis = <1000>;
4071                                         type = "critical";
4072                                 };
4073                         };
4074
4075                         cooling-maps {
4076                                 map0 {
4077                                         trip = <&cpu9_alert0>;
4078                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4079                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4080                                 };
4081                                 map1 {
4082                                         trip = <&cpu9_alert1>;
4083                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4084                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4085                                 };
4086                         };
4087                 };
4088
4089                 aoss0-thermal {
4090                         polling-delay-passive = <250>;
4091                         polling-delay = <0>;
4092
4093                         thermal-sensors = <&tsens0 0>;
4094
4095                         trips {
4096                                 aoss0_alert0: trip-point0 {
4097                                         temperature = <90000>;
4098                                         hysteresis = <2000>;
4099                                         type = "hot";
4100                                 };
4101
4102                                 aoss0_crit: aoss0_crit {
4103                                         temperature = <110000>;
4104                                         hysteresis = <2000>;
4105                                         type = "critical";
4106                                 };
4107                         };
4108                 };
4109
4110                 cpuss0-thermal {
4111                         polling-delay-passive = <250>;
4112                         polling-delay = <0>;
4113
4114                         thermal-sensors = <&tsens0 7>;
4115
4116                         trips {
4117                                 cpuss0_alert0: trip-point0 {
4118                                         temperature = <90000>;
4119                                         hysteresis = <2000>;
4120                                         type = "hot";
4121                                 };
4122                                 cpuss0_crit: cluster0_crit {
4123                                         temperature = <110000>;
4124                                         hysteresis = <2000>;
4125                                         type = "critical";
4126                                 };
4127                         };
4128                 };
4129
4130                 cpuss1-thermal {
4131                         polling-delay-passive = <250>;
4132                         polling-delay = <0>;
4133
4134                         thermal-sensors = <&tsens0 8>;
4135
4136                         trips {
4137                                 cpuss1_alert0: trip-point0 {
4138                                         temperature = <90000>;
4139                                         hysteresis = <2000>;
4140                                         type = "hot";
4141                                 };
4142                                 cpuss1_crit: cluster0_crit {
4143                                         temperature = <110000>;
4144                                         hysteresis = <2000>;
4145                                         type = "critical";
4146                                 };
4147                         };
4148                 };
4149
4150                 gpuss0-thermal {
4151                         polling-delay-passive = <250>;
4152                         polling-delay = <0>;
4153
4154                         thermal-sensors = <&tsens0 13>;
4155
4156                         trips {
4157                                 gpuss0_alert0: trip-point0 {
4158                                         temperature = <95000>;
4159                                         hysteresis = <2000>;
4160                                         type = "passive";
4161                                 };
4162
4163                                 gpuss0_crit: gpuss0_crit {
4164                                         temperature = <110000>;
4165                                         hysteresis = <2000>;
4166                                         type = "critical";
4167                                 };
4168                         };
4169
4170                         cooling-maps {
4171                                 map0 {
4172                                         trip = <&gpuss0_alert0>;
4173                                         cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4174                                 };
4175                         };
4176                 };
4177
4178                 gpuss1-thermal {
4179                         polling-delay-passive = <250>;
4180                         polling-delay = <0>;
4181
4182                         thermal-sensors = <&tsens0 14>;
4183
4184                         trips {
4185                                 gpuss1_alert0: trip-point0 {
4186                                         temperature = <95000>;
4187                                         hysteresis = <2000>;
4188                                         type = "passive";
4189                                 };
4190
4191                                 gpuss1_crit: gpuss1_crit {
4192                                         temperature = <110000>;
4193                                         hysteresis = <2000>;
4194                                         type = "critical";
4195                                 };
4196                         };
4197
4198                         cooling-maps {
4199                                 map0 {
4200                                         trip = <&gpuss1_alert0>;
4201                                         cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4202                                 };
4203                         };
4204                 };
4205
4206                 aoss1-thermal {
4207                         polling-delay-passive = <250>;
4208                         polling-delay = <0>;
4209
4210                         thermal-sensors = <&tsens1 0>;
4211
4212                         trips {
4213                                 aoss1_alert0: trip-point0 {
4214                                         temperature = <90000>;
4215                                         hysteresis = <2000>;
4216                                         type = "hot";
4217                                 };
4218
4219                                 aoss1_crit: aoss1_crit {
4220                                         temperature = <110000>;
4221                                         hysteresis = <2000>;
4222                                         type = "critical";
4223                                 };
4224                         };
4225                 };
4226
4227                 cwlan-thermal {
4228                         polling-delay-passive = <250>;
4229                         polling-delay = <0>;
4230
4231                         thermal-sensors = <&tsens1 1>;
4232
4233                         trips {
4234                                 cwlan_alert0: trip-point0 {
4235                                         temperature = <90000>;
4236                                         hysteresis = <2000>;
4237                                         type = "hot";
4238                                 };
4239
4240                                 cwlan_crit: cwlan_crit {
4241                                         temperature = <110000>;
4242                                         hysteresis = <2000>;
4243                                         type = "critical";
4244                                 };
4245                         };
4246                 };
4247
4248                 audio-thermal {
4249                         polling-delay-passive = <250>;
4250                         polling-delay = <0>;
4251
4252                         thermal-sensors = <&tsens1 2>;
4253
4254                         trips {
4255                                 audio_alert0: trip-point0 {
4256                                         temperature = <90000>;
4257                                         hysteresis = <2000>;
4258                                         type = "hot";
4259                                 };
4260
4261                                 audio_crit: audio_crit {
4262                                         temperature = <110000>;
4263                                         hysteresis = <2000>;
4264                                         type = "critical";
4265                                 };
4266                         };
4267                 };
4268
4269                 ddr-thermal {
4270                         polling-delay-passive = <250>;
4271                         polling-delay = <0>;
4272
4273                         thermal-sensors = <&tsens1 3>;
4274
4275                         trips {
4276                                 ddr_alert0: trip-point0 {
4277                                         temperature = <90000>;
4278                                         hysteresis = <2000>;
4279                                         type = "hot";
4280                                 };
4281
4282                                 ddr_crit: ddr_crit {
4283                                         temperature = <110000>;
4284                                         hysteresis = <2000>;
4285                                         type = "critical";
4286                                 };
4287                         };
4288                 };
4289
4290                 q6-hvx-thermal {
4291                         polling-delay-passive = <250>;
4292                         polling-delay = <0>;
4293
4294                         thermal-sensors = <&tsens1 4>;
4295
4296                         trips {
4297                                 q6_hvx_alert0: trip-point0 {
4298                                         temperature = <90000>;
4299                                         hysteresis = <2000>;
4300                                         type = "hot";
4301                                 };
4302
4303                                 q6_hvx_crit: q6_hvx_crit {
4304                                         temperature = <110000>;
4305                                         hysteresis = <2000>;
4306                                         type = "critical";
4307                                 };
4308                         };
4309                 };
4310
4311                 camera-thermal {
4312                         polling-delay-passive = <250>;
4313                         polling-delay = <0>;
4314
4315                         thermal-sensors = <&tsens1 5>;
4316
4317                         trips {
4318                                 camera_alert0: trip-point0 {
4319                                         temperature = <90000>;
4320                                         hysteresis = <2000>;
4321                                         type = "hot";
4322                                 };
4323
4324                                 camera_crit: camera_crit {
4325                                         temperature = <110000>;
4326                                         hysteresis = <2000>;
4327                                         type = "critical";
4328                                 };
4329                         };
4330                 };
4331
4332                 mdm-core-thermal {
4333                         polling-delay-passive = <250>;
4334                         polling-delay = <0>;
4335
4336                         thermal-sensors = <&tsens1 6>;
4337
4338                         trips {
4339                                 mdm_alert0: trip-point0 {
4340                                         temperature = <90000>;
4341                                         hysteresis = <2000>;
4342                                         type = "hot";
4343                                 };
4344
4345                                 mdm_crit: mdm_crit {
4346                                         temperature = <110000>;
4347                                         hysteresis = <2000>;
4348                                         type = "critical";
4349                                 };
4350                         };
4351                 };
4352
4353                 mdm-dsp-thermal {
4354                         polling-delay-passive = <250>;
4355                         polling-delay = <0>;
4356
4357                         thermal-sensors = <&tsens1 7>;
4358
4359                         trips {
4360                                 mdm_dsp_alert0: trip-point0 {
4361                                         temperature = <90000>;
4362                                         hysteresis = <2000>;
4363                                         type = "hot";
4364                                 };
4365
4366                                 mdm_dsp_crit: mdm_dsp_crit {
4367                                         temperature = <110000>;
4368                                         hysteresis = <2000>;
4369                                         type = "critical";
4370                                 };
4371                         };
4372                 };
4373
4374                 npu-thermal {
4375                         polling-delay-passive = <250>;
4376                         polling-delay = <0>;
4377
4378                         thermal-sensors = <&tsens1 8>;
4379
4380                         trips {
4381                                 npu_alert0: trip-point0 {
4382                                         temperature = <90000>;
4383                                         hysteresis = <2000>;
4384                                         type = "hot";
4385                                 };
4386
4387                                 npu_crit: npu_crit {
4388                                         temperature = <110000>;
4389                                         hysteresis = <2000>;
4390                                         type = "critical";
4391                                 };
4392                         };
4393                 };
4394
4395                 video-thermal {
4396                         polling-delay-passive = <250>;
4397                         polling-delay = <0>;
4398
4399                         thermal-sensors = <&tsens1 9>;
4400
4401                         trips {
4402                                 video_alert0: trip-point0 {
4403                                         temperature = <90000>;
4404                                         hysteresis = <2000>;
4405                                         type = "hot";
4406                                 };
4407
4408                                 video_crit: video_crit {
4409                                         temperature = <110000>;
4410                                         hysteresis = <2000>;
4411                                         type = "critical";
4412                                 };
4413                         };
4414                 };
4415         };
4416
4417         timer {
4418                 compatible = "arm,armv8-timer";
4419                 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
4420                              <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
4421                              <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
4422                              <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
4423         };
4424 };