arch/arm64/boot/dts/qcom/msm8996.dtsi

   1 /* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
   2  *
   3  * This program is free software; you can redistribute it and/or modify
   4  * it under the terms of the GNU General Public License version 2 and
   5  * only version 2 as published by the Free Software Foundation.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  */
  12
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
  15 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
  16
  17 / {
  18         model = "Qualcomm Technologies, Inc. MSM8996";
  19
  20         interrupt-parent = <&intc>;
  21
  22         #address-cells = <2>;
  23         #size-cells = <2>;
  24
  25         chosen { };
  26
  27         memory {
  28                 device_type = "memory";
  29                 /* We expect the bootloader to fill in the reg */
  30                 reg = <0 0 0 0>;
  31         };
  32
  33         reserved-memory {
  34                 #address-cells = <2>;
  35                 #size-cells = <2>;
  36                 ranges;
  37
  38                 mba_region: mba@91500000 {
  39                         reg = <0x0 0x91500000 0x0 0x200000>;
  40                         no-map;
  41                 };
  42
  43                 slpi_region: slpi@90b00000 {
  44                         reg = <0x0 0x90b00000 0x0 0xa00000>;
  45                         no-map;
  46                 };
  47
  48                 venus_region: venus@90400000 {
  49                         reg = <0x0 0x90400000 0x0 0x700000>;
  50                         no-map;
  51                 };
  52
  53                 adsp_region: adsp@8ea00000 {
  54                         reg = <0x0 0x8ea00000 0x0 0x1a00000>;
  55                         no-map;
  56                 };
  57
  58                 mpss_region: mpss@88800000 {
  59                         reg = <0x0 0x88800000 0x0 0x6200000>;
  60                         no-map;
  61                 };
  62
  63                 smem_mem: smem-mem@86000000 {
  64                         reg = <0x0 0x86000000 0x0 0x200000>;
  65                         no-map;
  66                 };
  67         };
  68
  69         cpus {
  70                 #address-cells = <2>;
  71                 #size-cells = <0>;
  72
  73                 CPU0: cpu@0 {
  74                         device_type = "cpu";
  75                         compatible = "qcom,kryo";
  76                         reg = <0x0 0x0>;
  77                         enable-method = "psci";
  78                         next-level-cache = <&L2_0>;
  79                         L2_0: l2-cache {
  80                               compatible = "cache";
  81                               cache-level = <2>;
  82                         };
  83                 };
  84
  85                 CPU1: cpu@1 {
  86                         device_type = "cpu";
  87                         compatible = "qcom,kryo";
  88                         reg = <0x0 0x1>;
  89                         enable-method = "psci";
  90                         next-level-cache = <&L2_0>;
  91                 };
  92
  93                 CPU2: cpu@100 {
  94                         device_type = "cpu";
  95                         compatible = "qcom,kryo";
  96                         reg = <0x0 0x100>;
  97                         enable-method = "psci";
  98                         next-level-cache = <&L2_1>;
  99                         L2_1: l2-cache {
 100                               compatible = "cache";
 101                               cache-level = <2>;
 102                         };
 103                 };
 104
 105                 CPU3: cpu@101 {
 106                         device_type = "cpu";
 107                         compatible = "qcom,kryo";
 108                         reg = <0x0 0x101>;
 109                         enable-method = "psci";
 110                         next-level-cache = <&L2_1>;
 111                 };
 112
 113                 cpu-map {
 114                         cluster0 {
 115                                 core0 {
 116                                         cpu = <&CPU0>;
 117                                 };
 118
 119                                 core1 {
 120                                         cpu = <&CPU1>;
 121                                 };
 122                         };
 123
 124                         cluster1 {
 125                                 core0 {
 126                                         cpu = <&CPU2>;
 127                                 };
 128
 129                                 core1 {
 130                                         cpu = <&CPU3>;
 131                                 };
 132                         };
 133                 };
 134         };
 135
 136         thermal-zones {
 137                 cpu-thermal0 {
 138                         polling-delay-passive = <250>;
 139                         polling-delay = <1000>;
 140
 141                         thermal-sensors = <&tsens0 3>;
 142
 143                         trips {
 144                                 cpu_alert0: trip0 {
 145                                         temperature = <75000>;
 146                                         hysteresis = <2000>;
 147                                         type = "passive";
 148                                 };
 149
 150                                 cpu_crit0: trip1 {
 151                                         temperature = <110000>;
 152                                         hysteresis = <2000>;
 153                                         type = "critical";
 154                                 };
 155                         };
 156                 };
 157
 158                 cpu-thermal1 {
 159                         polling-delay-passive = <250>;
 160                         polling-delay = <1000>;
 161
 162                         thermal-sensors = <&tsens0 5>;
 163
 164                         trips {
 165                                 cpu_alert1: trip0 {
 166                                         temperature = <75000>;
 167                                         hysteresis = <2000>;
 168                                         type = "passive";
 169                                 };
 170
 171                                 cpu_crit1: trip1 {
 172                                         temperature = <110000>;
 173                                         hysteresis = <2000>;
 174                                         type = "critical";
 175                                 };
 176                         };
 177                 };
 178
 179                 cpu-thermal2 {
 180                         polling-delay-passive = <250>;
 181                         polling-delay = <1000>;
 182
 183                         thermal-sensors = <&tsens0 8>;
 184
 185                         trips {
 186                                 cpu_alert2: trip0 {
 187                                         temperature = <75000>;
 188                                         hysteresis = <2000>;
 189                                         type = "passive";
 190                                 };
 191
 192                                 cpu_crit2: trip1 {
 193                                         temperature = <110000>;
 194                                         hysteresis = <2000>;
 195                                         type = "critical";
 196                                 };
 197                         };
 198                 };
 199
 200                 cpu-thermal3 {
 201                         polling-delay-passive = <250>;
 202                         polling-delay = <1000>;
 203
 204                         thermal-sensors = <&tsens0 10>;
 205
 206                         trips {
 207                                 cpu_alert3: trip0 {
 208                                         temperature = <75000>;
 209                                         hysteresis = <2000>;
 210                                         type = "passive";
 211                                 };
 212
 213                                 cpu_crit3: trip1 {
 214                                         temperature = <110000>;
 215                                         hysteresis = <2000>;
 216                                         type = "critical";
 217                                 };
 218                         };
 219                 };
 220         };
 221
 222         timer {
 223                 compatible = "arm,armv8-timer";
 224                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 225                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 226                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 227                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 228         };
 229
 230         clocks {
 231                 xo_board: xo_board {
 232                         compatible = "fixed-clock";
 233                         #clock-cells = <0>;
 234                         clock-frequency = <19200000>;
 235                         clock-output-names = "xo_board";
 236                 };
 237
 238                 sleep_clk: sleep_clk {
 239                         compatible = "fixed-clock";
 240                         #clock-cells = <0>;
 241                         clock-frequency = <32764>;
 242                         clock-output-names = "sleep_clk";
 243                 };
 244         };
 245
 246         psci {
 247                 compatible = "arm,psci-1.0";
 248                 method = "smc";
 249         };
 250
 251         tcsr_mutex: hwlock {
 252                 compatible = "qcom,tcsr-mutex";
 253                 syscon = <&tcsr_mutex_regs 0 0x1000>;
 254                 #hwlock-cells = <1>;
 255         };
 256
 257         smem {
 258                 compatible = "qcom,smem";
 259                 memory-region = <&smem_mem>;
 260                 hwlocks = <&tcsr_mutex 3>;
 261         };
 262
 263         soc: soc {
 264                 #address-cells = <1>;
 265                 #size-cells = <1>;
 266                 ranges = <0 0 0 0xffffffff>;
 267                 compatible = "simple-bus";
 268
 269                 tcsr_mutex_regs: syscon@740000 {
 270                         compatible = "syscon";
 271                         reg = <0x740000 0x20000>;
 272                 };
 273
 274                 intc: interrupt-controller@9bc0000 {
 275                         compatible = "arm,gic-v3";
 276                         #interrupt-cells = <3>;
 277                         interrupt-controller;
 278                         #redistributor-regions = <1>;
 279                         redistributor-stride = <0x0 0x40000>;
 280                         reg = <0x09bc0000 0x10000>,
 281                               <0x09c00000 0x100000>;
 282                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 283                 };
 284
 285                 apcs: syscon@9820000 {
 286                         compatible = "syscon";
 287                         reg = <0x9820000 0x1000>;
 288                 };
 289
 290                 gcc: clock-controller@300000 {
 291                         compatible = "qcom,gcc-msm8996";
 292                         #clock-cells = <1>;
 293                         #reset-cells = <1>;
 294                         #power-domain-cells = <1>;
 295                         reg = <0x300000 0x90000>;
 296                 };
 297
 298                 blsp1_spi0: spi@07575000 {
 299                         compatible = "qcom,spi-qup-v2.2.1";
 300                         reg = <0x07575000 0x600>;
 301                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 302                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
 303                                  <&gcc GCC_BLSP1_AHB_CLK>;
 304                         clock-names = "core", "iface";
 305                         pinctrl-names = "default", "sleep";
 306                         pinctrl-0 = <&blsp1_spi0_default>;
 307                         pinctrl-1 = <&blsp1_spi0_sleep>;
 308                         #address-cells = <1>;
 309                         #size-cells = <0>;
 310                         status = "disabled";
 311                 };
 312
 313                 blsp2_i2c0: i2c@075b5000 {
 314                         compatible = "qcom,i2c-qup-v2.2.1";
 315                         reg = <0x075b5000 0x1000>;
 316                         interrupts = <GIC_SPI 101 0>;
 317                         clocks = <&gcc GCC_BLSP2_AHB_CLK>,
 318                                 <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
 319                         clock-names = "iface", "core";
 320                         pinctrl-names = "default", "sleep";
 321                         pinctrl-0 = <&blsp2_i2c0_default>;
 322                         pinctrl-1 = <&blsp2_i2c0_sleep>;
 323                         #address-cells = <1>;
 324                         #size-cells = <0>;
 325                         status = "disabled";
 326                 };
 327
 328                 tsens0: thermal-sensor@4a8000 {
 329                         compatible = "qcom,msm8996-tsens";
 330                         reg = <0x4a8000 0x2000>;
 331                         #thermal-sensor-cells = <1>;
 332                 };
 333
 334                 blsp2_uart1: serial@75b0000 {
 335                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 336                         reg = <0x75b0000 0x1000>;
 337                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 338                         clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
 339                                  <&gcc GCC_BLSP2_AHB_CLK>;
 340                         clock-names = "core", "iface";
 341                         status = "disabled";
 342                 };
 343
 344                 blsp2_i2c1: i2c@075b6000 {
 345                         compatible = "qcom,i2c-qup-v2.2.1";
 346                         reg = <0x075b6000 0x1000>;
 347                         interrupts = <GIC_SPI 102 0>;
 348                         clocks = <&gcc GCC_BLSP2_AHB_CLK>,
 349                                 <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
 350                         clock-names = "iface", "core";
 351                         pinctrl-names = "default", "sleep";
 352                         pinctrl-0 = <&blsp2_i2c1_default>;
 353                         pinctrl-1 = <&blsp2_i2c1_sleep>;
 354                         #address-cells = <1>;
 355                         #size-cells = <0>;
 356                         status = "disabled";
 357                 };
 358
 359                 blsp2_uart2: serial@75b1000 {
 360                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 361                         reg = <0x075b1000 0x1000>;
 362                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 363                         clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
 364                                  <&gcc GCC_BLSP2_AHB_CLK>;
 365                         clock-names = "core", "iface";
 366                         status = "disabled";
 367                 };
 368
 369                 blsp1_i2c2: i2c@07577000 {
 370                         compatible = "qcom,i2c-qup-v2.2.1";
 371                         reg = <0x07577000 0x1000>;
 372                         interrupts = <GIC_SPI 97 0>;
 373                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 374                                 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
 375                         clock-names = "iface", "core";
 376                         pinctrl-names = "default", "sleep";
 377                         pinctrl-0 = <&blsp1_i2c2_default>;
 378                         pinctrl-1 = <&blsp1_i2c2_sleep>;
 379                         #address-cells = <1>;
 380                         #size-cells = <0>;
 381                         status = "disabled";
 382                 };
 383
 384                 blsp2_spi5: spi@075ba000{
 385                         compatible = "qcom,spi-qup-v2.2.1";
 386                         reg = <0x075ba000 0x600>;
 387                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 388                         clocks = <&gcc GCC_BLSP2_QUP5_SPI_APPS_CLK>,
 389                                  <&gcc GCC_BLSP2_AHB_CLK>;
 390                         clock-names = "core", "iface";
 391                         pinctrl-names = "default", "sleep";
 392                         pinctrl-0 = <&blsp2_spi5_default>;
 393                         pinctrl-1 = <&blsp2_spi5_sleep>;
 394                         #address-cells = <1>;
 395                         #size-cells = <0>;
 396                         status = "disabled";
 397                 };
 398
 399                 sdhc2: sdhci@74a4900 {
 400                          status = "disabled";
 401                          compatible = "qcom,sdhci-msm-v4";
 402                          reg = <0x74a4900 0x314>, <0x74a4000 0x800>;
 403                          reg-names = "hc_mem", "core_mem";
 404
 405                          interrupts = <0 125 0>, <0 221 0>;
 406                          interrupt-names = "hc_irq", "pwr_irq";
 407
 408                          clock-names = "iface", "core", "xo";
 409                          clocks = <&gcc GCC_SDCC2_AHB_CLK>,
 410                          <&gcc GCC_SDCC2_APPS_CLK>,
 411                          <&xo_board>;
 412                          bus-width = <4>;
 413                  };
 414
 415                 msmgpio: pinctrl@1010000 {
 416                         compatible = "qcom,msm8996-pinctrl";
 417                         reg = <0x01010000 0x300000>;
 418                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 419                         gpio-controller;
 420                         #gpio-cells = <2>;
 421                         interrupt-controller;
 422                         #interrupt-cells = <2>;
 423                 };
 424
 425                 timer@09840000 {
 426                         #address-cells = <1>;
 427                         #size-cells = <1>;
 428                         ranges;
 429                         compatible = "arm,armv7-timer-mem";
 430                         reg = <0x09840000 0x1000>;
 431                         clock-frequency = <19200000>;
 432
 433                         frame@9850000 {
 434                                 frame-number = <0>;
 435                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
 436                                              <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 437                                 reg = <0x09850000 0x1000>,
 438                                       <0x09860000 0x1000>;
 439                         };
 440
 441                         frame@9870000 {
 442                                 frame-number = <1>;
 443                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 444                                 reg = <0x09870000 0x1000>;
 445                                 status = "disabled";
 446                         };
 447
 448                         frame@9880000 {
 449                                 frame-number = <2>;
 450                                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 451                                 reg = <0x09880000 0x1000>;
 452                                 status = "disabled";
 453                         };
 454
 455                         frame@9890000 {
 456                                 frame-number = <3>;
 457                                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 458                                 reg = <0x09890000 0x1000>;
 459                                 status = "disabled";
 460                         };
 461
 462                         frame@98a0000 {
 463                                 frame-number = <4>;
 464                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 465                                 reg = <0x098a0000 0x1000>;
 466                                 status = "disabled";
 467                         };
 468
 469                         frame@98b0000 {
 470                                 frame-number = <5>;
 471                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 472                                 reg = <0x098b0000 0x1000>;
 473                                 status = "disabled";
 474                         };
 475
 476                         frame@98c0000 {
 477                                 frame-number = <6>;
 478                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 479                                 reg = <0x098c0000 0x1000>;
 480                                 status = "disabled";
 481                         };
 482                 };
 483
 484                 spmi_bus: qcom,spmi@400f000 {
 485                         compatible = "qcom,spmi-pmic-arb";
 486                         reg = <0x400f000 0x1000>,
 487                               <0x4400000 0x800000>,
 488                               <0x4c00000 0x800000>,
 489                               <0x5800000 0x200000>,
 490                               <0x400a000 0x002100>;
 491                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
 492                         interrupt-names = "periph_irq";
 493                         interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
 494                         qcom,ee = <0>;
 495                         qcom,channel = <0>;
 496                         #address-cells = <2>;
 497                         #size-cells = <0>;
 498                         interrupt-controller;
 499                         #interrupt-cells = <4>;
 500                 };
 501
 502                 mmcc: clock-controller@8c0000 {
 503                         compatible = "qcom,mmcc-msm8996";
 504                         #clock-cells = <1>;
 505                         #reset-cells = <1>;
 506                         #power-domain-cells = <1>;
 507                         reg = <0x8c0000 0x40000>;
 508                         assigned-clocks = <&mmcc MMPLL9_PLL>,
 509                                           <&mmcc MMPLL1_PLL>,
 510                                           <&mmcc MMPLL3_PLL>,
 511                                           <&mmcc MMPLL4_PLL>,
 512                                           <&mmcc MMPLL5_PLL>;
 513                         assigned-clock-rates = <624000000>,
 514                                                <810000000>,
 515                                                <980000000>,
 516                                                <960000000>,
 517                                                <825000000>;
 518                 };
 519         };
 520
 521         adsp-smp2p {
 522                 compatible = "qcom,smp2p";
 523                 qcom,smem = <443>, <429>;
 524
 525                 interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
 526
 527                 qcom,ipc = <&apcs 16 10>;
 528
 529                 qcom,local-pid = <0>;
 530                 qcom,remote-pid = <2>;
 531
 532                 adsp_smp2p_out: master-kernel {
 533                         qcom,entry-name = "master-kernel";
 534                         #qcom,state-cells = <1>;
 535                 };
 536
 537                 adsp_smp2p_in: slave-kernel {
 538                         qcom,entry-name = "slave-kernel";
 539
 540                         interrupt-controller;
 541                         #interrupt-cells = <2>;
 542                 };
 543         };
 544 };
 545 #include "msm8996-pins.dtsi"