arch/arm64/boot/dts/qcom/msm8953.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /* Copyright (c) 2022, The Linux Foundation. All rights reserved. */
   3
   4 #include <dt-bindings/clock/qcom,gcc-msm8953.h>
   5 #include <dt-bindings/clock/qcom,rpmcc.h>
   6 #include <dt-bindings/gpio/gpio.h>
   7 #include <dt-bindings/interrupt-controller/arm-gic.h>
   8 #include <dt-bindings/power/qcom-rpmpd.h>
   9 #include <dt-bindings/soc/qcom,apr.h>
  10 #include <dt-bindings/sound/qcom,q6afe.h>
  11 #include <dt-bindings/sound/qcom,q6asm.h>
  12 #include <dt-bindings/thermal/thermal.h>
  13
  14 / {
  15         interrupt-parent = <&intc>;
  16
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         chosen { };
  21
  22         clocks {
  23                 sleep_clk: sleep-clk {
  24                         compatible = "fixed-clock";
  25                         #clock-cells = <0>;
  26                         clock-frequency = <32768>;
  27                 };
  28
  29                 xo_board: xo-board {
  30                         compatible = "fixed-clock";
  31                         #clock-cells = <0>;
  32                         clock-frequency = <19200000>;
  33                         clock-output-names = "xo";
  34                 };
  35         };
  36
  37         cpus {
  38                 #address-cells = <1>;
  39                 #size-cells = <0>;
  40
  41                 CPU0: cpu@0 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a53";
  44                         reg = <0x0>;
  45                         enable-method = "psci";
  46                         capacity-dmips-mhz = <1024>;
  47                         next-level-cache = <&L2_0>;
  48                         #cooling-cells = <2>;
  49                 };
  50
  51                 CPU1: cpu@1 {
  52                         device_type = "cpu";
  53                         compatible = "arm,cortex-a53";
  54                         reg = <0x1>;
  55                         enable-method = "psci";
  56                         capacity-dmips-mhz = <1024>;
  57                         next-level-cache = <&L2_0>;
  58                         #cooling-cells = <2>;
  59                 };
  60
  61                 CPU2: cpu@2 {
  62                         device_type = "cpu";
  63                         compatible = "arm,cortex-a53";
  64                         reg = <0x2>;
  65                         enable-method = "psci";
  66                         capacity-dmips-mhz = <1024>;
  67                         next-level-cache = <&L2_0>;
  68                         #cooling-cells = <2>;
  69                 };
  70
  71                 CPU3: cpu@3 {
  72                         device_type = "cpu";
  73                         compatible = "arm,cortex-a53";
  74                         reg = <0x3>;
  75                         enable-method = "psci";
  76                         capacity-dmips-mhz = <1024>;
  77                         next-level-cache = <&L2_0>;
  78                         #cooling-cells = <2>;
  79                 };
  80
  81                 CPU4: cpu@100 {
  82                         device_type = "cpu";
  83                         compatible = "arm,cortex-a53";
  84                         reg = <0x100>;
  85                         enable-method = "psci";
  86                         capacity-dmips-mhz = <1024>;
  87                         next-level-cache = <&L2_1>;
  88                         #cooling-cells = <2>;
  89                 };
  90
  91                 CPU5: cpu@101 {
  92                         device_type = "cpu";
  93                         compatible = "arm,cortex-a53";
  94                         reg = <0x101>;
  95                         enable-method = "psci";
  96                         capacity-dmips-mhz = <1024>;
  97                         next-level-cache = <&L2_1>;
  98                         #cooling-cells = <2>;
  99                 };
 100
 101                 CPU6: cpu@102 {
 102                         device_type = "cpu";
 103                         compatible = "arm,cortex-a53";
 104                         reg = <0x102>;
 105                         enable-method = "psci";
 106                         capacity-dmips-mhz = <1024>;
 107                         next-level-cache = <&L2_1>;
 108                         #cooling-cells = <2>;
 109                 };
 110
 111                 CPU7: cpu@103 {
 112                         device_type = "cpu";
 113                         compatible = "arm,cortex-a53";
 114                         reg = <0x103>;
 115                         enable-method = "psci";
 116                         capacity-dmips-mhz = <1024>;
 117                         next-level-cache = <&L2_1>;
 118                         #cooling-cells = <2>;
 119                 };
 120
 121                 cpu-map {
 122                         cluster0 {
 123                                 core0 {
 124                                         cpu = <&CPU0>;
 125                                 };
 126                                 core1 {
 127                                         cpu = <&CPU1>;
 128                                 };
 129                                 core2 {
 130                                         cpu = <&CPU2>;
 131                                 };
 132                                 core3 {
 133                                         cpu = <&CPU3>;
 134                                 };
 135                         };
 136
 137                         cluster1 {
 138                                 core0 {
 139                                         cpu = <&CPU4>;
 140                                 };
 141                                 core1 {
 142                                         cpu = <&CPU5>;
 143                                 };
 144                                 core2 {
 145                                         cpu = <&CPU6>;
 146                                 };
 147                                 core3 {
 148                                         cpu = <&CPU7>;
 149                                 };
 150                         };
 151                 };
 152
 153                 L2_0: l2-cache-0 {
 154                         compatible = "cache";
 155                         cache-level = <2>;
 156                         cache-unified;
 157                 };
 158
 159                 L2_1: l2-cache-1 {
 160                         compatible = "cache";
 161                         cache-level = <2>;
 162                         cache-unified;
 163                 };
 164         };
 165
 166         firmware {
 167                 scm: scm {
 168                         compatible = "qcom,scm-msm8953", "qcom,scm";
 169                         clocks = <&gcc GCC_CRYPTO_CLK>,
 170                                  <&gcc GCC_CRYPTO_AXI_CLK>,
 171                                  <&gcc GCC_CRYPTO_AHB_CLK>;
 172                         clock-names = "core", "bus", "iface";
 173                         #reset-cells = <1>;
 174                 };
 175         };
 176
 177         memory@10000000 {
 178                 device_type = "memory";
 179                 /* We expect the bootloader to fill in the reg */
 180                 reg = <0 0x10000000 0 0>;
 181         };
 182
 183         pmu {
 184                 compatible = "arm,cortex-a53-pmu";
 185                 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 186         };
 187
 188         psci {
 189                 compatible = "arm,psci-1.0";
 190                 method = "smc";
 191         };
 192
 193         rpm: remoteproc {
 194                 compatible = "qcom,msm8953-rpm-proc", "qcom,rpm-proc";
 195
 196                 smd-edge {
 197                         interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
 198                         qcom,ipc = <&apcs 8 0>;
 199                         qcom,smd-edge = <15>;
 200
 201                         rpm_requests: rpm-requests {
 202                                 compatible = "qcom,rpm-msm8953";
 203                                 qcom,smd-channels = "rpm_requests";
 204
 205                                 rpmcc: clock-controller {
 206                                         compatible = "qcom,rpmcc-msm8953", "qcom,rpmcc";
 207                                         clocks = <&xo_board>;
 208                                         clock-names = "xo";
 209                                         #clock-cells = <1>;
 210                                 };
 211
 212                                 rpmpd: power-controller {
 213                                         compatible = "qcom,msm8953-rpmpd";
 214                                         #power-domain-cells = <1>;
 215                                         operating-points-v2 = <&rpmpd_opp_table>;
 216
 217                                         rpmpd_opp_table: opp-table {
 218                                                 compatible = "operating-points-v2";
 219
 220                                                 rpmpd_opp_ret: opp1 {
 221                                                         opp-level = <RPM_SMD_LEVEL_RETENTION>;
 222                                                 };
 223
 224                                                 rpmpd_opp_ret_plus: opp2 {
 225                                                         opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
 226                                                 };
 227
 228                                                 rpmpd_opp_min_svs: opp3 {
 229                                                         opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
 230                                                 };
 231
 232                                                 rpmpd_opp_low_svs: opp4 {
 233                                                         opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
 234                                                 };
 235
 236                                                 rpmpd_opp_svs: opp5 {
 237                                                         opp-level = <RPM_SMD_LEVEL_SVS>;
 238                                                 };
 239
 240                                                 rpmpd_opp_svs_plus: opp6 {
 241                                                         opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
 242                                                 };
 243
 244                                                 rpmpd_opp_nom: opp7 {
 245                                                         opp-level = <RPM_SMD_LEVEL_NOM>;
 246                                                 };
 247
 248                                                 rpmpd_opp_nom_plus: opp8 {
 249                                                         opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
 250                                                 };
 251
 252                                                 rpmpd_opp_turbo: opp9 {
 253                                                         opp-level = <RPM_SMD_LEVEL_TURBO>;
 254                                                 };
 255                                         };
 256                                 };
 257                         };
 258                 };
 259         };
 260
 261         reserved-memory {
 262                 #address-cells = <2>;
 263                 #size-cells = <2>;
 264                 ranges;
 265
 266                 zap_shader_region: zap@81800000 {
 267                         compatible = "shared-dma-pool";
 268                         reg = <0x0 0x81800000 0x0 0x2000>;
 269                         no-map;
 270                 };
 271
 272                 qseecom_mem: qseecom@85b00000 {
 273                         reg = <0x0 0x85b00000 0x0 0x800000>;
 274                         no-map;
 275                 };
 276
 277                 smem_mem: smem@86300000 {
 278                         compatible = "qcom,smem";
 279                         reg = <0x0 0x86300000 0x0 0x100000>;
 280                         qcom,rpm-msg-ram = <&rpm_msg_ram>;
 281                         hwlocks = <&tcsr_mutex 3>;
 282                         no-map;
 283                 };
 284
 285                 reserved@86400000 {
 286                         reg = <0x0 0x86400000 0x0 0x400000>;
 287                         no-map;
 288                 };
 289
 290                 mpss_mem: mpss@86c00000 {
 291                         reg = <0x0 0x86c00000 0x0 0x6a00000>;
 292                         no-map;
 293                 };
 294
 295                 adsp_fw_mem: adsp@8d600000 {
 296                         reg = <0x0 0x8d600000 0x0 0x1100000>;
 297                         no-map;
 298                 };
 299
 300                 wcnss_fw_mem: wcnss@8e700000 {
 301                         reg = <0x0 0x8e700000 0x0 0x700000>;
 302                         no-map;
 303                 };
 304
 305                 dfps_data_mem: dfps-data@90000000 {
 306                         reg = <0 0x90000000 0 0x1000>;
 307                         no-map;
 308                 };
 309
 310                 cont_splash_mem: cont-splash@90001000 {
 311                         reg = <0x0 0x90001000 0x0 0x13ff000>;
 312                         no-map;
 313                 };
 314
 315                 venus_mem: venus@91400000 {
 316                         reg = <0x0 0x91400000 0x0 0x700000>;
 317                         no-map;
 318                 };
 319
 320                 mba_mem: mba@92000000 {
 321                         reg = <0x0 0x92000000 0x0 0x100000>;
 322                         no-map;
 323                 };
 324
 325                 rmtfs@f2d00000 {
 326                         compatible = "qcom,rmtfs-mem";
 327                         reg = <0x0 0xf2d00000 0x0 0x180000>;
 328                         no-map;
 329
 330                         qcom,client-id = <1>;
 331                 };
 332         };
 333
 334         smp2p-adsp {
 335                 compatible = "qcom,smp2p";
 336                 qcom,smem = <443>, <429>;
 337
 338                 interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>;
 339
 340                 mboxes = <&apcs 10>;
 341
 342                 qcom,local-pid = <0>;
 343                 qcom,remote-pid = <2>;
 344
 345                 smp2p_adsp_out: master-kernel {
 346                         qcom,entry-name = "master-kernel";
 347                         #qcom,smem-state-cells = <1>;
 348                 };
 349
 350                 smp2p_adsp_in: slave-kernel {
 351                         qcom,entry-name = "slave-kernel";
 352
 353                         interrupt-controller;
 354                         #interrupt-cells = <2>;
 355                 };
 356         };
 357
 358         smp2p-modem {
 359                 compatible = "qcom,smp2p";
 360                 qcom,smem = <435>, <428>;
 361
 362                 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
 363
 364                 qcom,ipc = <&apcs 8 14>;
 365
 366                 qcom,local-pid = <0>;
 367                 qcom,remote-pid = <1>;
 368
 369                 smp2p_modem_out: master-kernel {
 370                         qcom,entry-name = "master-kernel";
 371
 372                         #qcom,smem-state-cells = <1>;
 373                 };
 374
 375                 smp2p_modem_in: slave-kernel {
 376                         qcom,entry-name = "slave-kernel";
 377
 378                         interrupt-controller;
 379                         #interrupt-cells = <2>;
 380                 };
 381         };
 382
 383         smp2p-wcnss {
 384                 compatible = "qcom,smp2p";
 385                 qcom,smem = <451>, <431>;
 386
 387                 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
 388
 389                 qcom,ipc = <&apcs 8 18>;
 390
 391                 qcom,local-pid = <0>;
 392                 qcom,remote-pid = <4>;
 393
 394                 smp2p_wcnss_out: master-kernel {
 395                         qcom,entry-name = "master-kernel";
 396
 397                         #qcom,smem-state-cells = <1>;
 398                 };
 399
 400                 smp2p_wcnss_in: slave-kernel {
 401                         qcom,entry-name = "slave-kernel";
 402
 403                         interrupt-controller;
 404                         #interrupt-cells = <2>;
 405                 };
 406         };
 407
 408         smsm {
 409                 compatible = "qcom,smsm";
 410
 411                 #address-cells = <1>;
 412                 #size-cells = <0>;
 413
 414                 qcom,ipc-1 = <&apcs 8 13>;
 415                 qcom,ipc-3 = <&apcs 8 19>;
 416
 417                 apps_smsm: apps@0 {
 418                         reg = <0>;
 419
 420                         #qcom,smem-state-cells = <1>;
 421                 };
 422
 423                 modem_smsm: modem@1 {
 424                         reg = <1>;
 425                         interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
 426
 427                         interrupt-controller;
 428                         #interrupt-cells = <2>;
 429                 };
 430
 431                 wcnss_smsm: wcnss@6 {
 432                         reg = <6>;
 433                         interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
 434
 435                         interrupt-controller;
 436                         #interrupt-cells = <2>;
 437                 };
 438         };
 439
 440         soc: soc@0 {
 441                 #address-cells = <1>;
 442                 #size-cells = <1>;
 443                 ranges = <0 0 0 0xffffffff>;
 444                 compatible = "simple-bus";
 445
 446                 rpm_msg_ram: sram@60000 {
 447                         compatible = "qcom,rpm-msg-ram";
 448                         reg = <0x00060000 0x8000>;
 449                 };
 450
 451                 hsusb_phy: phy@79000 {
 452                         compatible = "qcom,msm8953-qusb2-phy";
 453                         reg = <0x00079000 0x180>;
 454                         #phy-cells = <0>;
 455
 456                         clocks = <&gcc GCC_USB_PHY_CFG_AHB_CLK>,
 457                                  <&gcc GCC_QUSB_REF_CLK>;
 458                         clock-names = "cfg_ahb", "ref";
 459
 460                         qcom,tcsr-syscon = <&tcsr_phy_clk_scheme_sel>;
 461
 462                         resets = <&gcc GCC_QUSB2_PHY_BCR>;
 463
 464                         status = "disabled";
 465                 };
 466
 467                 rng@e3000 {
 468                         compatible = "qcom,prng";
 469                         reg = <0x000e3000 0x1000>;
 470                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 471                         clock-names = "core";
 472                 };
 473
 474                 tsens0: thermal-sensor@4a9000 {
 475                         compatible = "qcom,msm8953-tsens", "qcom,tsens-v2";
 476                         reg = <0x004a9000 0x1000>, /* TM */
 477                               <0x004a8000 0x1000>; /* SROT */
 478                         #qcom,sensors = <16>;
 479                         interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
 480                                      <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>;
 481                         interrupt-names = "uplow", "critical";
 482                         #thermal-sensor-cells = <1>;
 483                 };
 484
 485                 restart@4ab000 {
 486                         compatible = "qcom,pshold";
 487                         reg = <0x004ab000 0x4>;
 488                 };
 489
 490                 tlmm: pinctrl@1000000 {
 491                         compatible = "qcom,msm8953-pinctrl";
 492                         reg = <0x01000000 0x300000>;
 493                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 494                         gpio-controller;
 495                         gpio-ranges = <&tlmm 0 0 142>;
 496                         #gpio-cells = <2>;
 497                         interrupt-controller;
 498                         #interrupt-cells = <2>;
 499
 500                         uart_console_active: uart-console-active-state {
 501                                 pins = "gpio4", "gpio5";
 502                                 function = "blsp_uart2";
 503                                 drive-strength = <2>;
 504                                 bias-disable;
 505                         };
 506
 507                         uart_console_sleep: uart-console-sleep-state {
 508                                 pins = "gpio4", "gpio5";
 509                                 function = "blsp_uart2";
 510                                 drive-strength = <2>;
 511                                 bias-pull-down;
 512                         };
 513
 514                         sdc1_clk_on: sdc1-clk-on-state {
 515                                 pins = "sdc1_clk";
 516                                 bias-disable;
 517                                 drive-strength = <16>;
 518                         };
 519
 520                         sdc1_clk_off: sdc1-clk-off-state {
 521                                 pins = "sdc1_clk";
 522                                 bias-disable;
 523                                 drive-strength = <2>;
 524                         };
 525
 526                         sdc1_cmd_on: sdc1-cmd-on-state {
 527                                 pins = "sdc1_cmd";
 528                                 bias-disable;
 529                                 drive-strength = <10>;
 530                         };
 531
 532                         sdc1_cmd_off: sdc1-cmd-off-state {
 533                                 pins = "sdc1_cmd";
 534                                 bias-disable;
 535                                 drive-strength = <2>;
 536                         };
 537
 538                         sdc1_data_on: sdc1-data-on-state {
 539                                 pins = "sdc1_data";
 540                                 bias-pull-up;
 541                                 drive-strength = <10>;
 542                         };
 543
 544                         sdc1_data_off: sdc1-data-off-state {
 545                                 pins = "sdc1_data";
 546                                 bias-pull-up;
 547                                 drive-strength = <2>;
 548                         };
 549
 550                         sdc1_rclk_on: sdc1-rclk-on-state {
 551                                 pins = "sdc1_rclk";
 552                                 bias-pull-down;
 553                         };
 554
 555                         sdc1_rclk_off: sdc1-rclk-off-state {
 556                                 pins = "sdc1_rclk";
 557                                 bias-pull-down;
 558                         };
 559
 560                         sdc2_clk_on: sdc2-clk-on-state {
 561                                 pins = "sdc2_clk";
 562                                 drive-strength = <16>;
 563                                 bias-disable;
 564                         };
 565
 566                         sdc2_clk_off: sdc2-clk-off-state {
 567                                 pins = "sdc2_clk";
 568                                 bias-disable;
 569                                 drive-strength = <2>;
 570                         };
 571
 572                         sdc2_cmd_on: sdc2-cmd-on-state {
 573                                 pins = "sdc2_cmd";
 574                                 bias-pull-up;
 575                                 drive-strength = <10>;
 576                         };
 577
 578                         sdc2_cmd_off: sdc2-cmd-off-state {
 579                                 pins = "sdc2_cmd";
 580                                 bias-pull-up;
 581                                 drive-strength = <2>;
 582                         };
 583
 584                         sdc2_data_on: sdc2-data-on-state {
 585                                 pins = "sdc2_data";
 586                                 bias-pull-up;
 587                                 drive-strength = <10>;
 588                         };
 589
 590                         sdc2_data_off: sdc2-data-off-state {
 591                                 pins = "sdc2_data";
 592                                 bias-pull-up;
 593                                 drive-strength = <2>;
 594                         };
 595
 596                         sdc2_cd_on: cd-on-state {
 597                                 pins = "gpio133";
 598                                 function = "gpio";
 599                                 drive-strength = <2>;
 600                                 bias-pull-up;
 601                         };
 602
 603                         sdc2_cd_off: cd-off-state {
 604                                 pins = "gpio133";
 605                                 function = "gpio";
 606                                 drive-strength = <2>;
 607                                 bias-disable;
 608                         };
 609
 610                         gpio_key_default: gpio-key-default-state {
 611                                 pins = "gpio85";
 612                                 function = "gpio";
 613                                 drive-strength = <2>;
 614                                 bias-pull-up;
 615                         };
 616
 617                         i2c_1_default: i2c-1-default-state {
 618                                 pins = "gpio2", "gpio3";
 619                                 function = "blsp_i2c1";
 620                                 drive-strength = <2>;
 621                                 bias-disable;
 622                         };
 623
 624                         i2c_1_sleep: i2c-1-sleep-state {
 625                                 pins = "gpio2", "gpio3";
 626                                 function = "gpio";
 627                                 drive-strength = <2>;
 628                                 bias-disable;
 629                         };
 630
 631                         i2c_2_default: i2c-2-default-state {
 632                                 pins = "gpio6", "gpio7";
 633                                 function = "blsp_i2c2";
 634                                 drive-strength = <2>;
 635                                 bias-disable;
 636                         };
 637
 638                         i2c_2_sleep: i2c-2-sleep-state {
 639                                 pins = "gpio6", "gpio7";
 640                                 function = "gpio";
 641                                 drive-strength = <2>;
 642                                 bias-disable;
 643                         };
 644
 645                         i2c_3_default: i2c-3-default-state {
 646                                 pins = "gpio10", "gpio11";
 647                                 function = "blsp_i2c3";
 648                                 drive-strength = <2>;
 649                                 bias-disable;
 650                         };
 651
 652                         i2c_3_sleep: i2c-3-sleep-state {
 653                                 pins = "gpio10", "gpio11";
 654                                 function = "gpio";
 655                                 drive-strength = <2>;
 656                                 bias-disable;
 657                         };
 658
 659                         i2c_4_default: i2c-4-default-state {
 660                                 pins = "gpio14", "gpio15";
 661                                 function = "blsp_i2c4";
 662                                 drive-strength = <2>;
 663                                 bias-disable;
 664                         };
 665
 666                         i2c_4_sleep: i2c-4-sleep-state {
 667                                 pins = "gpio14", "gpio15";
 668                                 function = "gpio";
 669                                 drive-strength = <2>;
 670                                 bias-disable;
 671                         };
 672
 673                         i2c_5_default: i2c-5-default-state {
 674                                 pins = "gpio18", "gpio19";
 675                                 function = "blsp_i2c5";
 676                                 drive-strength = <2>;
 677                                 bias-disable;
 678                         };
 679
 680                         i2c_5_sleep: i2c-5-sleep-state {
 681                                 pins = "gpio18", "gpio19";
 682                                 function = "gpio";
 683                                 drive-strength = <2>;
 684                                 bias-disable;
 685                         };
 686
 687                         i2c_6_default: i2c-6-default-state {
 688                                 pins = "gpio22", "gpio23";
 689                                 function = "blsp_i2c6";
 690                                 drive-strength = <2>;
 691                                 bias-disable;
 692                         };
 693
 694                         i2c_6_sleep: i2c-6-sleep-state {
 695                                 pins = "gpio22", "gpio23";
 696                                 function = "gpio";
 697                                 drive-strength = <2>;
 698                                 bias-disable;
 699                         };
 700
 701                         i2c_7_default: i2c-7-default-state {
 702                                 pins = "gpio135", "gpio136";
 703                                 function = "blsp_i2c7";
 704                                 drive-strength = <2>;
 705                                 bias-disable;
 706                         };
 707
 708                         i2c_7_sleep: i2c-7-sleep-state {
 709                                 pins = "gpio135", "gpio136";
 710                                 function = "gpio";
 711                                 drive-strength = <2>;
 712                                 bias-disable;
 713                         };
 714
 715                         i2c_8_default: i2c-8-default-state {
 716                                 pins = "gpio98", "gpio99";
 717                                 function = "blsp_i2c8";
 718                                 drive-strength = <2>;
 719                                 bias-disable;
 720                         };
 721
 722                         i2c_8_sleep: i2c-8-sleep-state {
 723                                 pins = "gpio98", "gpio99";
 724                                 function = "gpio";
 725                                 drive-strength = <2>;
 726                                 bias-disable;
 727                         };
 728
 729                         spi_3_default: spi-3-default-state {
 730                                 pins = "gpio10", "gpio11";
 731                                 function = "blsp_spi3";
 732                                 drive-strength = <2>;
 733                                 bias-disable;
 734                         };
 735
 736                         spi_3_sleep: spi-3-sleep-state {
 737                                 pins = "gpio10", "gpio11";
 738                                 function = "gpio";
 739                                 drive-strength = <2>;
 740                                 bias-disable;
 741                         };
 742
 743                         spi_5_default: spi-5-default-state {
 744                                 pins = "gpio18", "gpio19";
 745                                 function = "blsp_spi5";
 746                                 drive-strength = <2>;
 747                                 bias-disable;
 748                         };
 749
 750                         spi_5_sleep: spi-5-sleep-state {
 751                                 pins = "gpio18", "gpio19";
 752                                 function = "gpio";
 753                                 drive-strength = <2>;
 754                                 bias-disable;
 755                         };
 756
 757                         spi_6_default: spi-6-default-state {
 758                                 pins = "gpio22", "gpio23";
 759                                 function = "blsp_spi6";
 760                                 drive-strength = <2>;
 761                                 bias-disable;
 762                         };
 763
 764                         spi_6_sleep: spi-6-sleep-state {
 765                                 pins = "gpio22", "gpio23";
 766                                 function = "gpio";
 767                                 drive-strength = <2>;
 768                                 bias-disable;
 769                         };
 770
 771                         wcnss_pin_a: wcnss-active-state {
 772
 773                                 wcss-wlan2-pins {
 774                                         pins = "gpio76";
 775                                         function = "wcss_wlan2";
 776                                         drive-strength = <6>;
 777                                         bias-pull-up;
 778                                 };
 779
 780                                 wcss-wlan1-pins {
 781                                         pins = "gpio77";
 782                                         function = "wcss_wlan1";
 783                                         drive-strength = <6>;
 784                                         bias-pull-up;
 785                                 };
 786
 787                                 wcss-wlan0-pins {
 788                                         pins = "gpio78";
 789                                         function = "wcss_wlan0";
 790                                         drive-strength = <6>;
 791                                         bias-pull-up;
 792                                 };
 793
 794                                 wcss-wlan-pins {
 795                                         pins = "gpio79", "gpio80";
 796                                         function = "wcss_wlan";
 797                                         drive-strength = <6>;
 798                                         bias-pull-up;
 799                                 };
 800                         };
 801                 };
 802
 803                 gcc: clock-controller@1800000 {
 804                         compatible = "qcom,gcc-msm8953";
 805                         reg = <0x01800000 0x80000>;
 806                         #clock-cells = <1>;
 807                         #reset-cells = <1>;
 808                         #power-domain-cells = <1>;
 809                         clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
 810                                  <&sleep_clk>,
 811                                  <&mdss_dsi0_phy 1>,
 812                                  <&mdss_dsi0_phy 0>,
 813                                  <&mdss_dsi1_phy 1>,
 814                                  <&mdss_dsi1_phy 0>;
 815                         clock-names = "xo",
 816                                       "sleep",
 817                                       "dsi0pll",
 818                                       "dsi0pllbyte",
 819                                       "dsi1pll",
 820                                       "dsi1pllbyte";
 821                 };
 822
 823                 tcsr_mutex: hwlock@1905000 {
 824                         compatible = "qcom,tcsr-mutex";
 825                         reg = <0x01905000 0x20000>;
 826                         #hwlock-cells = <1>;
 827                 };
 828
 829                 tcsr: syscon@1937000 {
 830                         compatible = "qcom,tcsr-msm8953", "syscon";
 831                         reg = <0x01937000 0x30000>;
 832                 };
 833
 834                 tcsr_phy_clk_scheme_sel: syscon@193f044 {
 835                         compatible = "qcom,tcsr-msm8953", "syscon";
 836                         reg = <0x0193f044 0x4>;
 837                 };
 838
 839                 mdss: display-subsystem@1a00000 {
 840                         compatible = "qcom,mdss";
 841
 842                         reg = <0x01a00000 0x1000>,
 843                               <0x01ab0000 0x1040>;
 844                         reg-names = "mdss_phys",
 845                                     "vbif_phys";
 846
 847                         power-domains = <&gcc MDSS_GDSC>;
 848                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 849
 850                         interrupt-controller;
 851                         #interrupt-cells = <1>;
 852
 853                         clocks = <&gcc GCC_MDSS_AHB_CLK>,
 854                                  <&gcc GCC_MDSS_AXI_CLK>,
 855                                  <&gcc GCC_MDSS_VSYNC_CLK>,
 856                                  <&gcc GCC_MDSS_MDP_CLK>;
 857                         clock-names = "iface",
 858                                       "bus",
 859                                       "vsync",
 860                                       "core";
 861
 862                         resets = <&gcc GCC_MDSS_BCR>;
 863
 864                         #address-cells = <1>;
 865                         #size-cells = <1>;
 866                         ranges;
 867
 868                         status = "disabled";
 869
 870                         mdp: display-controller@1a01000 {
 871                                 compatible = "qcom,msm8953-mdp5", "qcom,mdp5";
 872                                 reg = <0x01a01000 0x89000>;
 873                                 reg-names = "mdp_phys";
 874
 875                                 interrupt-parent = <&mdss>;
 876                                 interrupts = <0>;
 877
 878                                 power-domains = <&gcc MDSS_GDSC>;
 879
 880                                 clocks = <&gcc GCC_MDSS_AHB_CLK>,
 881                                          <&gcc GCC_MDSS_AXI_CLK>,
 882                                          <&gcc GCC_MDSS_MDP_CLK>,
 883                                          <&gcc GCC_MDSS_VSYNC_CLK>;
 884                                 clock-names = "iface",
 885                                               "bus",
 886                                               "core",
 887                                               "vsync";
 888
 889                                 iommus = <&apps_iommu 0x15>;
 890
 891                                 ports {
 892                                         #address-cells = <1>;
 893                                         #size-cells = <0>;
 894
 895                                         port@0 {
 896                                                 reg = <0>;
 897                                                 mdp5_intf1_out: endpoint {
 898                                                         remote-endpoint = <&mdss_dsi0_in>;
 899                                                 };
 900                                         };
 901
 902                                         port@1 {
 903                                                 reg = <1>;
 904                                                 mdp5_intf2_out: endpoint {
 905                                                         remote-endpoint = <&mdss_dsi1_in>;
 906                                                 };
 907                                         };
 908                                 };
 909                         };
 910
 911                         mdss_dsi0: dsi@1a94000 {
 912                                 compatible = "qcom,msm8953-dsi-ctrl", "qcom,mdss-dsi-ctrl";
 913                                 reg = <0x01a94000 0x400>;
 914                                 reg-names = "dsi_ctrl";
 915
 916                                 interrupt-parent = <&mdss>;
 917                                 interrupts = <4>;
 918
 919                                 assigned-clocks = <&gcc BYTE0_CLK_SRC>,
 920                                                   <&gcc PCLK0_CLK_SRC>;
 921                                 assigned-clock-parents = <&mdss_dsi0_phy 0>,
 922                                                          <&mdss_dsi0_phy 1>;
 923
 924                                 clocks = <&gcc GCC_MDSS_MDP_CLK>,
 925                                          <&gcc GCC_MDSS_AHB_CLK>,
 926                                          <&gcc GCC_MDSS_AXI_CLK>,
 927                                          <&gcc GCC_MDSS_BYTE0_CLK>,
 928                                          <&gcc GCC_MDSS_PCLK0_CLK>,
 929                                          <&gcc GCC_MDSS_ESC0_CLK>;
 930                                 clock-names = "mdp_core",
 931                                               "iface",
 932                                               "bus",
 933                                               "byte",
 934                                               "pixel",
 935                                               "core";
 936
 937                                 phys = <&mdss_dsi0_phy>;
 938
 939                                 #address-cells = <1>;
 940                                 #size-cells = <0>;
 941
 942                                 status = "disabled";
 943
 944                                 ports {
 945                                         #address-cells = <1>;
 946                                         #size-cells = <0>;
 947
 948                                         port@0 {
 949                                                 reg = <0>;
 950                                                 mdss_dsi0_in: endpoint {
 951                                                         remote-endpoint = <&mdp5_intf1_out>;
 952                                                 };
 953                                         };
 954
 955                                         port@1 {
 956                                                 reg = <1>;
 957                                                 mdss_dsi0_out: endpoint {
 958                                                 };
 959                                         };
 960                                 };
 961                         };
 962
 963                         mdss_dsi0_phy: phy@1a94400 {
 964                                 compatible = "qcom,dsi-phy-14nm-8953";
 965                                 reg = <0x01a94400 0x100>,
 966                                       <0x01a94500 0x300>,
 967                                       <0x01a94800 0x188>;
 968                                 reg-names = "dsi_phy",
 969                                             "dsi_phy_lane",
 970                                             "dsi_pll";
 971
 972                                 #clock-cells = <1>;
 973                                 #phy-cells = <0>;
 974
 975                                 clocks = <&gcc GCC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
 976                                 clock-names = "iface", "ref";
 977
 978                                 status = "disabled";
 979                         };
 980
 981                         mdss_dsi1: dsi@1a96000 {
 982                                 compatible = "qcom,msm8953-dsi-ctrl", "qcom,mdss-dsi-ctrl";
 983                                 reg = <0x01a96000 0x400>;
 984                                 reg-names = "dsi_ctrl";
 985
 986                                 interrupt-parent = <&mdss>;
 987                                 interrupts = <5>;
 988
 989                                 assigned-clocks = <&gcc BYTE1_CLK_SRC>,
 990                                                   <&gcc PCLK1_CLK_SRC>;
 991                                 assigned-clock-parents = <&mdss_dsi1_phy 0>,
 992                                                          <&mdss_dsi1_phy 1>;
 993
 994                                 clocks = <&gcc GCC_MDSS_MDP_CLK>,
 995                                          <&gcc GCC_MDSS_AHB_CLK>,
 996                                          <&gcc GCC_MDSS_AXI_CLK>,
 997                                          <&gcc GCC_MDSS_BYTE1_CLK>,
 998                                          <&gcc GCC_MDSS_PCLK1_CLK>,
 999                                          <&gcc GCC_MDSS_ESC1_CLK>;
1000                                 clock-names = "mdp_core",
1001                                               "iface",
1002                                               "bus",
1003                                               "byte",
1004                                               "pixel",
1005                                               "core";
1006
1007                                 phys = <&mdss_dsi1_phy>;
1008
1009                                 status = "disabled";
1010
1011                                 ports {
1012                                         #address-cells = <1>;
1013                                         #size-cells = <0>;
1014
1015                                         port@0 {
1016                                                 reg = <0>;
1017                                                 mdss_dsi1_in: endpoint {
1018                                                         remote-endpoint = <&mdp5_intf2_out>;
1019                                                 };
1020                                         };
1021
1022                                         port@1 {
1023                                                 reg = <1>;
1024                                                 mdss_dsi1_out: endpoint {
1025                                                 };
1026                                         };
1027                                 };
1028                         };
1029
1030                         mdss_dsi1_phy: phy@1a96400 {
1031                                 compatible = "qcom,dsi-phy-14nm-8953";
1032                                 reg = <0x01a96400 0x100>,
1033                                       <0x01a96500 0x300>,
1034                                       <0x01a96800 0x188>;
1035                                 reg-names = "dsi_phy",
1036                                             "dsi_phy_lane",
1037                                             "dsi_pll";
1038
1039                                 #clock-cells = <1>;
1040                                 #phy-cells = <0>;
1041
1042                                 clocks = <&gcc GCC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
1043                                 clock-names = "iface", "ref";
1044
1045                                 status = "disabled";
1046                         };
1047                 };
1048
1049                 gpu: gpu@1c00000 {
1050                         compatible = "qcom,adreno-506.0", "qcom,adreno";
1051                         reg = <0x01c00000 0x40000>;
1052                         reg-names = "kgsl_3d0_reg_memory";
1053                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1054
1055                         clocks = <&gcc GCC_OXILI_GFX3D_CLK>,
1056                                  <&gcc GCC_OXILI_AHB_CLK>,
1057                                  <&gcc GCC_BIMC_GFX_CLK>,
1058                                  <&gcc GCC_BIMC_GPU_CLK>,
1059                                  <&gcc GCC_OXILI_TIMER_CLK>,
1060                                  <&gcc GCC_OXILI_AON_CLK>;
1061                         clock-names = "core",
1062                                       "iface",
1063                                       "mem_iface",
1064                                       "alt_mem_iface",
1065                                       "rbbmtimer",
1066                                       "alwayson";
1067                         power-domains = <&gcc OXILI_GX_GDSC>;
1068
1069                         iommus = <&gpu_iommu 0>;
1070                         operating-points-v2 = <&gpu_opp_table>;
1071
1072                         #cooling-cells = <2>;
1073
1074                         status = "disabled";
1075
1076                         zap-shader {
1077                                 memory-region = <&zap_shader_region>;
1078                         };
1079
1080                         gpu_opp_table: opp-table {
1081                                 compatible = "operating-points-v2";
1082
1083                                 opp-19200000 {
1084                                         opp-hz = /bits/ 64 <19200000>;
1085                                         opp-supported-hw = <0xff>;
1086                                         required-opps = <&rpmpd_opp_min_svs>;
1087                                 };
1088
1089                                 opp-133300000 {
1090                                         opp-hz = /bits/ 64 <133300000>;
1091                                         opp-supported-hw = <0xff>;
1092                                         required-opps = <&rpmpd_opp_min_svs>;
1093                                 };
1094
1095                                 opp-216000000 {
1096                                         opp-hz = /bits/ 64 <216000000>;
1097                                         opp-supported-hw = <0xff>;
1098                                         required-opps = <&rpmpd_opp_low_svs>;
1099                                 };
1100
1101                                 opp-320000000 {
1102                                         opp-hz = /bits/ 64 <320000000>;
1103                                         opp-supported-hw = <0xff>;
1104                                         required-opps = <&rpmpd_opp_svs>;
1105                                 };
1106
1107                                 opp-400000000 {
1108                                         opp-hz = /bits/ 64 <400000000>;
1109                                         opp-supported-hw = <0xff>;
1110                                         required-opps = <&rpmpd_opp_svs_plus>;
1111                                 };
1112
1113                                 opp-510000000 {
1114                                         opp-hz = /bits/ 64 <510000000>;
1115                                         opp-supported-hw = <0xff>;
1116                                         required-opps = <&rpmpd_opp_nom>;
1117                                 };
1118
1119                                 opp-560000000 {
1120                                         opp-hz = /bits/ 64 <560000000>;
1121                                         opp-supported-hw = <0xff>;
1122                                         required-opps = <&rpmpd_opp_nom_plus>;
1123                                 };
1124
1125                                 /*
1126                                  * This opp is only available on msm8953 and
1127                                  * sdm632, the max for sdm450 is 600MHz.
1128                                  */
1129                                 opp-650000000 {
1130                                         opp-hz = /bits/ 64 <650000000>;
1131                                         opp-supported-hw = <0xff>;
1132                                         required-opps = <&rpmpd_opp_turbo>;
1133                                 };
1134                         };
1135                 };
1136
1137                 gpu_iommu: iommu@1c48000 {
1138                         compatible = "qcom,msm8953-iommu", "qcom,msm-iommu-v2";
1139                         ranges = <0 0x01c48000 0x8000>;
1140
1141                         clocks = <&gcc GCC_OXILI_AHB_CLK>,
1142                                  <&gcc GCC_BIMC_GFX_CLK>;
1143                         clock-names = "iface", "bus";
1144
1145                         power-domains = <&gcc OXILI_CX_GDSC>;
1146
1147                         qcom,iommu-secure-id = <18>;
1148
1149                         #address-cells = <1>;
1150                         #iommu-cells = <1>;
1151                         #size-cells = <1>;
1152
1153                         /* gfx3d_user */
1154                         iommu-ctx@0 {
1155                                 compatible = "qcom,msm-iommu-v2-ns";
1156                                 reg = <0x0000 0x1000>;
1157                                 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1158                         };
1159
1160                         /* gfx3d_secure */
1161                         iommu-ctx@2000 {
1162                                 compatible = "qcom,msm-iommu-v2-sec";
1163                                 reg = <0x2000 0x1000>;
1164                                 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
1165                         };
1166                 };
1167
1168                 apps_iommu: iommu@1e20000 {
1169                         compatible = "qcom,msm8953-iommu", "qcom,msm-iommu-v1";
1170                         ranges = <0 0x01e20000 0x20000>;
1171
1172                         clocks = <&gcc GCC_SMMU_CFG_CLK>,
1173                                  <&gcc GCC_APSS_TCU_ASYNC_CLK>;
1174                         clock-names = "iface", "bus";
1175
1176                         qcom,iommu-secure-id = <17>;
1177
1178                         #address-cells = <1>;
1179                         #iommu-cells = <1>;
1180                         #size-cells = <1>;
1181
1182                         /* VFE */
1183                         iommu-ctx@14000 {
1184                                 compatible = "qcom,msm-iommu-v1-ns";
1185                                 reg = <0x14000 0x1000>;
1186                                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1187                         };
1188
1189                         /* MDP_0 */
1190                         iommu-ctx@15000 {
1191                                 compatible = "qcom,msm-iommu-v1-ns";
1192                                 reg = <0x15000 0x1000>;
1193                                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1194                         };
1195
1196                         /* VENUS_NS */
1197                         iommu-ctx@16000 {
1198                                 compatible = "qcom,msm-iommu-v1-ns";
1199                                 reg = <0x16000 0x1000>;
1200                                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1201                         };
1202                 };
1203
1204                 spmi_bus: spmi@200f000 {
1205                         compatible = "qcom,spmi-pmic-arb";
1206                         reg = <0x0200f000 0x1000>,
1207                               <0x02400000 0x800000>,
1208                               <0x02c00000 0x800000>,
1209                               <0x03800000 0x200000>,
1210                               <0x0200a000 0x2100>;
1211                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1212                         interrupt-names = "periph_irq";
1213                         interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1214                         qcom,ee = <0>;
1215                         qcom,channel = <0>;
1216                         interrupt-controller;
1217
1218                         #interrupt-cells = <4>;
1219                         #address-cells = <2>;
1220                         #size-cells = <0>;
1221                 };
1222
1223                 mpss: remoteproc@4080000 {
1224                         compatible = "qcom,msm8953-mss-pil";
1225                         reg = <0x04080000 0x100>,
1226                               <0x04020000 0x040>;
1227                         reg-names = "qdsp6", "rmb";
1228
1229                         interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
1230                                               <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
1231                                               <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
1232                                               <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
1233                                               <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>;
1234                         interrupt-names = "wdog", "fatal", "ready",
1235                                           "handover", "stop-ack";
1236
1237                         power-domains = <&rpmpd MSM8953_VDDCX>,
1238                                         <&rpmpd MSM8953_VDDMX>,
1239                                         <&rpmpd MSM8953_VDDMD>;
1240                         power-domain-names = "cx", "mx","mss";
1241
1242                         clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1243                                  <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
1244                                  <&gcc GCC_BOOT_ROM_AHB_CLK>,
1245                                  <&rpmcc RPM_SMD_XO_CLK_SRC>;
1246                         clock-names = "iface", "bus", "mem", "xo";
1247
1248                         qcom,smem-states = <&smp2p_modem_out 0>;
1249                         qcom,smem-state-names = "stop";
1250
1251                         resets = <&gcc GCC_MSS_BCR>;
1252                         reset-names = "mss_restart";
1253
1254                         qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
1255
1256                         status = "disabled";
1257
1258                         mba {
1259                                 memory-region = <&mba_mem>;
1260                         };
1261
1262                         mpss {
1263                                 memory-region = <&mpss_mem>;
1264                         };
1265
1266                         smd-edge {
1267                                 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
1268
1269                                 qcom,smd-edge = <0>;
1270                                 qcom,ipc = <&apcs 8 12>;
1271                                 qcom,remote-pid = <1>;
1272
1273                                 label = "modem";
1274                         };
1275                 };
1276
1277                 usb3: usb@70f8800 {
1278                         compatible = "qcom,msm8953-dwc3", "qcom,dwc3";
1279                         reg = <0x070f8800 0x400>;
1280                         #address-cells = <1>;
1281                         #size-cells = <1>;
1282                         ranges;
1283
1284                         interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
1285                                      <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
1286                                      <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
1287                         interrupt-names = "pwr_event",
1288                                           "qusb2_phy",
1289                                           "ss_phy_irq";
1290
1291                         clocks = <&gcc GCC_USB_PHY_CFG_AHB_CLK>,
1292                                  <&gcc GCC_USB30_MASTER_CLK>,
1293                                  <&gcc GCC_PCNOC_USB3_AXI_CLK>,
1294                                  <&gcc GCC_USB30_SLEEP_CLK>,
1295                                  <&gcc GCC_USB30_MOCK_UTMI_CLK>;
1296                         clock-names = "cfg_noc",
1297                                       "core",
1298                                       "iface",
1299                                       "sleep",
1300                                       "mock_utmi";
1301
1302                         assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1303                                           <&gcc GCC_USB30_MASTER_CLK>;
1304                         assigned-clock-rates = <19200000>, <133330000>;
1305
1306                         power-domains = <&gcc USB30_GDSC>;
1307
1308                         qcom,select-utmi-as-pipe-clk;
1309
1310                         status = "disabled";
1311
1312                         usb3_dwc3: usb@7000000 {
1313                                 compatible = "snps,dwc3";
1314                                 reg = <0x07000000 0xcc00>;
1315                                 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
1316                                 phys = <&hsusb_phy>;
1317                                 phy-names = "usb2-phy";
1318
1319                                 snps,usb2-gadget-lpm-disable;
1320                                 snps,dis-u1-entry-quirk;
1321                                 snps,dis-u2-entry-quirk;
1322                                 snps,is-utmi-l1-suspend;
1323                                 snps,hird-threshold = /bits/ 8 <0x00>;
1324
1325                                 maximum-speed = "high-speed";
1326                         };
1327                 };
1328
1329                 sdhc_1: mmc@7824900 {
1330                         compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4";
1331
1332                         reg = <0x07824900 0x500>, <0x07824000 0x800>;
1333                         reg-names = "hc", "core";
1334
1335                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1336                                      <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
1337                         interrupt-names = "hc_irq", "pwr_irq";
1338
1339                         clocks = <&gcc GCC_SDCC1_AHB_CLK>,
1340                                  <&gcc GCC_SDCC1_APPS_CLK>,
1341                                  <&rpmcc RPM_SMD_XO_CLK_SRC>;
1342                         clock-names = "iface", "core", "xo";
1343
1344                         power-domains = <&rpmpd MSM8953_VDDCX>;
1345                         operating-points-v2 = <&sdhc1_opp_table>;
1346
1347                         pinctrl-names = "default", "sleep";
1348                         pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
1349                         pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
1350
1351                         mmc-hs400-1_8v;
1352                         mmc-hs200-1_8v;
1353                         mmc-ddr-1_8v;
1354                         bus-width = <8>;
1355                         non-removable;
1356
1357                         status = "disabled";
1358
1359                         sdhc1_opp_table: opp-table-sdhc1 {
1360                                 compatible = "operating-points-v2";
1361
1362                                 opp-25000000 {
1363                                         opp-hz = /bits/ 64 <25000000>;
1364                                         required-opps = <&rpmpd_opp_low_svs>;
1365                                 };
1366
1367                                 opp-50000000 {
1368                                         opp-hz = /bits/ 64 <50000000>;
1369                                         required-opps = <&rpmpd_opp_svs>;
1370                                 };
1371
1372                                 opp-100000000 {
1373                                         opp-hz = /bits/ 64 <100000000>;
1374                                         required-opps = <&rpmpd_opp_svs>;
1375                                 };
1376
1377                                 opp-192000000 {
1378                                         opp-hz = /bits/ 64 <192000000>;
1379                                         required-opps = <&rpmpd_opp_nom>;
1380                                 };
1381
1382                                 opp-384000000 {
1383                                         opp-hz = /bits/ 64 <384000000>;
1384                                         required-opps = <&rpmpd_opp_nom>;
1385                                 };
1386                         };
1387                 };
1388
1389                 sdhc_2: mmc@7864900 {
1390                         compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4";
1391
1392                         reg = <0x07864900 0x500>, <0x07864000 0x800>;
1393                         reg-names = "hc", "core";
1394
1395                         interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1396                                      <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1397                         interrupt-names = "hc_irq", "pwr_irq";
1398
1399                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
1400                                  <&gcc GCC_SDCC2_APPS_CLK>,
1401                                  <&rpmcc RPM_SMD_XO_CLK_SRC>;
1402                         clock-names = "iface", "core", "xo";
1403
1404                         power-domains = <&rpmpd MSM8953_VDDCX>;
1405                         operating-points-v2 = <&sdhc2_opp_table>;
1406
1407                         pinctrl-names = "default", "sleep";
1408                         pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>;
1409                         pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;
1410
1411                         bus-width = <4>;
1412
1413                         status = "disabled";
1414
1415                         sdhc2_opp_table: opp-table-sdhc2 {
1416                                 compatible = "operating-points-v2";
1417
1418                                 opp-25000000 {
1419                                         opp-hz = /bits/ 64 <25000000>;
1420                                         required-opps = <&rpmpd_opp_low_svs>;
1421                                 };
1422
1423                                 opp-50000000 {
1424                                         opp-hz = /bits/ 64 <50000000>;
1425                                         required-opps = <&rpmpd_opp_svs>;
1426                                 };
1427
1428                                 opp-100000000 {
1429                                         opp-hz = /bits/ 64 <100000000>;
1430                                         required-opps = <&rpmpd_opp_svs>;
1431                                 };
1432
1433                                 opp-177770000 {
1434                                         opp-hz = /bits/ 64 <177770000>;
1435                                         required-opps = <&rpmpd_opp_nom>;
1436                                 };
1437
1438                                 opp-200000000 {
1439                                         opp-hz = /bits/ 64 <200000000>;
1440                                         required-opps = <&rpmpd_opp_nom>;
1441                                 };
1442                         };
1443                 };
1444
1445                 blsp1_dma: dma-controller@7884000 {
1446                         compatible = "qcom,bam-v1.7.0";
1447                         reg = <0x07884000 0x1f000>;
1448                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1449                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
1450                         clock-names = "bam_clk";
1451                         num-channels = <12>;
1452                         #dma-cells = <1>;
1453                         qcom,ee = <0>;
1454                         qcom,num-ees = <4>;
1455                         qcom,controlled-remotely;
1456                 };
1457
1458                 uart_0: serial@78af000 {
1459                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1460                         reg = <0x078af000 0x200>;
1461                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1462                         clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
1463                                  <&gcc GCC_BLSP1_AHB_CLK>;
1464                         clock-names = "core", "iface";
1465
1466                         status = "disabled";
1467                 };
1468
1469                 i2c_1: i2c@78b5000 {
1470                         compatible = "qcom,i2c-qup-v2.2.1";
1471                         reg = <0x078b5000 0x600>;
1472                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1473                         clock-names = "core", "iface";
1474                         clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
1475                                  <&gcc GCC_BLSP1_AHB_CLK>;
1476                         dmas = <&blsp1_dma 4>, <&blsp1_dma 5>;
1477                         dma-names = "tx", "rx";
1478
1479                         pinctrl-names = "default", "sleep";
1480                         pinctrl-0 = <&i2c_1_default>;
1481                         pinctrl-1 = <&i2c_1_sleep>;
1482
1483                         #address-cells = <1>;
1484                         #size-cells = <0>;
1485
1486                         status = "disabled";
1487                 };
1488
1489                 i2c_2: i2c@78b6000 {
1490                         compatible = "qcom,i2c-qup-v2.2.1";
1491                         reg = <0x078b6000 0x600>;
1492                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1493                         clock-names = "core", "iface";
1494                         clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
1495                                  <&gcc GCC_BLSP1_AHB_CLK>;
1496                         dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
1497                         dma-names = "tx", "rx";
1498
1499                         pinctrl-names = "default", "sleep";
1500                         pinctrl-0 = <&i2c_2_default>;
1501                         pinctrl-1 = <&i2c_2_sleep>;
1502
1503                         #address-cells = <1>;
1504                         #size-cells = <0>;
1505
1506                         status = "disabled";
1507                 };
1508
1509                 i2c_3: i2c@78b7000 {
1510                         compatible = "qcom,i2c-qup-v2.2.1";
1511                         reg = <0x078b7000 0x600>;
1512                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1513                         clock-names = "core", "iface";
1514                         clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
1515                                  <&gcc GCC_BLSP1_AHB_CLK>;
1516                         dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
1517                         dma-names = "tx", "rx";
1518
1519                         pinctrl-names = "default", "sleep";
1520                         pinctrl-0 = <&i2c_3_default>;
1521                         pinctrl-1 = <&i2c_3_sleep>;
1522
1523                         #address-cells = <1>;
1524                         #size-cells = <0>;
1525
1526                         status = "disabled";
1527                 };
1528
1529                 spi_3: spi@78b7000 {
1530                         compatible = "qcom,spi-qup-v2.2.1";
1531                         reg = <0x078b7000 0x600>;
1532                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1533                         clock-names = "core", "iface";
1534                         clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
1535                                  <&gcc GCC_BLSP1_AHB_CLK>;
1536                         dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
1537                         dma-names = "tx", "rx";
1538
1539                         pinctrl-names = "default", "sleep";
1540                         pinctrl-0 = <&spi_3_default>;
1541                         pinctrl-1 = <&spi_3_sleep>;
1542
1543                         #address-cells = <1>;
1544                         #size-cells = <0>;
1545
1546                         status = "disabled";
1547                 };
1548
1549                 i2c_4: i2c@78b8000 {
1550                         compatible = "qcom,i2c-qup-v2.2.1";
1551                         reg = <0x078b8000 0x600>;
1552                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1553                         clock-names = "core", "iface";
1554                         clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
1555                                  <&gcc GCC_BLSP1_AHB_CLK>;
1556                         dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
1557                         dma-names = "tx", "rx";
1558
1559                         pinctrl-names = "default", "sleep";
1560                         pinctrl-0 = <&i2c_4_default>;
1561                         pinctrl-1 = <&i2c_4_sleep>;
1562
1563                         #address-cells = <1>;
1564                         #size-cells = <0>;
1565
1566                         status = "disabled";
1567                 };
1568
1569                 blsp2_dma: dma-controller@7ac4000 {
1570                         compatible = "qcom,bam-v1.7.0";
1571                         reg = <0x07ac4000 0x1f000>;
1572                         interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
1573                         clocks = <&gcc GCC_BLSP2_AHB_CLK>;
1574                         clock-names = "bam_clk";
1575                         num-channels = <12>;
1576                         #dma-cells = <1>;
1577                         qcom,ee = <0>;
1578                         qcom,num-ees = <4>;
1579                         qcom,controlled-remotely;
1580                 };
1581
1582                 i2c_5: i2c@7af5000 {
1583                         compatible = "qcom,i2c-qup-v2.2.1";
1584                         reg = <0x07af5000 0x600>;
1585                         interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
1586                         clock-names = "core", "iface";
1587                         clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
1588                                  <&gcc GCC_BLSP2_AHB_CLK>;
1589                         dmas = <&blsp2_dma 4>, <&blsp2_dma 5>;
1590                         dma-names = "tx", "rx";
1591
1592                         pinctrl-names = "default", "sleep";
1593                         pinctrl-0 = <&i2c_5_default>;
1594                         pinctrl-1 = <&i2c_5_sleep>;
1595
1596                         #address-cells = <1>;
1597                         #size-cells = <0>;
1598
1599                         status = "disabled";
1600                 };
1601
1602                 spi_5: spi@7af5000 {
1603                         compatible = "qcom,spi-qup-v2.2.1";
1604                         reg = <0x07af5000 0x600>;
1605                         interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
1606                         clock-names = "core", "iface";
1607                         clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
1608                                 <&gcc GCC_BLSP2_AHB_CLK>;
1609                         dmas = <&blsp2_dma 4>, <&blsp2_dma 5>;
1610                         dma-names = "tx", "rx";
1611
1612                         pinctrl-names = "default", "sleep";
1613                         pinctrl-0 = <&spi_5_default>;
1614                         pinctrl-1 = <&spi_5_sleep>;
1615
1616                         #address-cells = <1>;
1617                         #size-cells = <0>;
1618
1619                         status = "disabled";
1620                 };
1621
1622                 i2c_6: i2c@7af6000 {
1623                         compatible = "qcom,i2c-qup-v2.2.1";
1624                         reg = <0x07af6000 0x600>;
1625                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1626                         clock-names = "core", "iface";
1627                         clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
1628                                  <&gcc GCC_BLSP2_AHB_CLK>;
1629                         dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
1630                         dma-names = "tx", "rx";
1631
1632                         pinctrl-names = "default", "sleep";
1633                         pinctrl-0 = <&i2c_6_default>;
1634                         pinctrl-1 = <&i2c_6_sleep>;
1635
1636                         #address-cells = <1>;
1637                         #size-cells = <0>;
1638
1639                         status = "disabled";
1640                 };
1641
1642                 spi_6: spi@7af6000 {
1643                         compatible = "qcom,spi-qup-v2.2.1";
1644                         reg = <0x07af6000 0x600>;
1645                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1646                         clock-names = "core", "iface";
1647                         clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
1648                                  <&gcc GCC_BLSP2_AHB_CLK>;
1649                         dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
1650                         dma-names = "tx", "rx";
1651
1652                         pinctrl-names = "default", "sleep";
1653                         pinctrl-0 = <&spi_6_default>;
1654                         pinctrl-1 = <&spi_6_sleep>;
1655
1656                         #address-cells = <1>;
1657                         #size-cells = <0>;
1658
1659                         status = "disabled";
1660                 };
1661
1662                 i2c_7: i2c@7af7000 {
1663                         compatible = "qcom,i2c-qup-v2.2.1";
1664                         reg = <0x07af7000 0x600>;
1665                         interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>;
1666                         clock-names = "core", "iface";
1667                         clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
1668                                  <&gcc GCC_BLSP2_AHB_CLK>;
1669                         dmas = <&blsp2_dma 8>, <&blsp2_dma 9>;
1670                         dma-names = "tx", "rx";
1671
1672                         pinctrl-names = "default", "sleep";
1673                         pinctrl-0 = <&i2c_7_default>;
1674                         pinctrl-1 = <&i2c_7_sleep>;
1675
1676                         #address-cells = <1>;
1677                         #size-cells = <0>;
1678
1679                         status = "disabled";
1680                 };
1681
1682                 i2c_8: i2c@7af8000 {
1683                         compatible = "qcom,i2c-qup-v2.2.1";
1684                         reg = <0x07af8000 0x600>;
1685                         interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>;
1686                         clock-names = "core", "iface";
1687                         clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
1688                                  <&gcc GCC_BLSP2_AHB_CLK>;
1689                         dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
1690                         dma-names = "tx", "rx";
1691
1692                         pinctrl-names = "default", "sleep";
1693                         pinctrl-0 = <&i2c_8_default>;
1694                         pinctrl-1 = <&i2c_8_sleep>;
1695
1696                         #address-cells = <1>;
1697                         #size-cells = <0>;
1698
1699                         status = "disabled";
1700                 };
1701
1702                 wcnss: remoteproc@a204000 {
1703                         compatible = "qcom,pronto-v3-pil", "qcom,pronto";
1704                         reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>;
1705                         reg-names = "ccu", "dxe", "pmu";
1706
1707                         memory-region = <&wcnss_fw_mem>;
1708
1709                         interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
1710                                               <&smp2p_wcnss_in 0 IRQ_TYPE_EDGE_RISING>,
1711                                               <&smp2p_wcnss_in 1 IRQ_TYPE_EDGE_RISING>,
1712                                               <&smp2p_wcnss_in 2 IRQ_TYPE_EDGE_RISING>,
1713                                               <&smp2p_wcnss_in 3 IRQ_TYPE_EDGE_RISING>;
1714                         interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
1715
1716                         power-domains = <&rpmpd MSM8953_VDDCX>,
1717                                         <&rpmpd MSM8953_VDDMX>;
1718                         power-domain-names = "cx", "mx";
1719
1720                         qcom,smem-states = <&smp2p_wcnss_out 0>;
1721                         qcom,smem-state-names = "stop";
1722
1723                         pinctrl-names = "default";
1724                         pinctrl-0 = <&wcnss_pin_a>;
1725
1726                         status = "disabled";
1727
1728                         wcnss_iris: iris {
1729                                 /* Separate chip, compatible is board-specific */
1730                                 clocks = <&rpmcc RPM_SMD_RF_CLK2>;
1731                                 clock-names = "xo";
1732                         };
1733
1734                         smd-edge {
1735                                 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
1736
1737                                 qcom,ipc = <&apcs 8 17>;
1738                                 qcom,smd-edge = <6>;
1739                                 qcom,remote-pid = <4>;
1740
1741                                 label = "pronto";
1742
1743                                 wcnss_ctrl: wcnss {
1744                                         compatible = "qcom,wcnss";
1745                                         qcom,smd-channels = "WCNSS_CTRL";
1746
1747                                         qcom,mmio = <&wcnss>;
1748
1749                                         wcnss_bt: bluetooth {
1750                                                 compatible = "qcom,wcnss-bt";
1751                                         };
1752
1753                                         wcnss_wifi: wifi {
1754                                                 compatible = "qcom,wcnss-wlan";
1755
1756                                                 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1757                                                              <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
1758                                                 interrupt-names = "tx", "rx";
1759
1760                                                 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
1761                                                 qcom,smem-state-names = "tx-enable",
1762                                                                         "tx-rings-empty";
1763                                         };
1764                                 };
1765                         };
1766                 };
1767
1768                 intc: interrupt-controller@b000000 {
1769                         compatible = "qcom,msm-qgic2";
1770                         interrupt-controller;
1771                         #interrupt-cells = <3>;
1772                         reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
1773                 };
1774
1775                 apcs: mailbox@b011000 {
1776                         compatible = "qcom,msm8953-apcs-kpss-global", "syscon";
1777                         reg = <0x0b011000 0x1000>;
1778                         #mbox-cells = <1>;
1779                 };
1780
1781                 timer@b120000 {
1782                         compatible = "arm,armv7-timer-mem";
1783                         reg = <0x0b120000 0x1000>;
1784                         #address-cells = <1>;
1785                         #size-cells = <1>;
1786                         ranges;
1787
1788                         frame@b121000 {
1789                                 frame-number = <0>;
1790                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1791                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1792                                 reg = <0x0b121000 0x1000>,
1793                                       <0x0b122000 0x1000>;
1794                         };
1795
1796                         frame@b123000 {
1797                                 frame-number = <1>;
1798                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1799                                 reg = <0x0b123000 0x1000>;
1800                                 status = "disabled";
1801                         };
1802
1803                         frame@b124000 {
1804                                 frame-number = <2>;
1805                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1806                                 reg = <0x0b124000 0x1000>;
1807                                 status = "disabled";
1808                         };
1809
1810                         frame@b125000 {
1811                                 frame-number = <3>;
1812                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1813                                 reg = <0x0b125000 0x1000>;
1814                                 status = "disabled";
1815                         };
1816
1817                         frame@b126000 {
1818                                 frame-number = <4>;
1819                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1820                                 reg = <0x0b126000 0x1000>;
1821                                 status = "disabled";
1822                         };
1823
1824                         frame@b127000 {
1825                                 frame-number = <5>;
1826                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1827                                 reg = <0x0b127000 0x1000>;
1828                                 status = "disabled";
1829                         };
1830
1831                         frame@b128000 {
1832                                 frame-number = <6>;
1833                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1834                                 reg = <0x0b128000 0x1000>;
1835                                 status = "disabled";
1836                         };
1837                 };
1838
1839                 lpass: remoteproc@c200000 {
1840                         compatible = "qcom,msm8953-adsp-pil";
1841                         reg = <0x0c200000 0x100>;
1842
1843                         interrupts-extended = <&intc 0 293 IRQ_TYPE_EDGE_RISING>,
1844                                               <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
1845                                               <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
1846                                               <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
1847                                               <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
1848                         interrupt-names = "wdog", "fatal", "ready",
1849                                           "handover", "stop-ack";
1850                         clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
1851                         clock-names = "xo";
1852
1853                         power-domains = <&rpmpd MSM8953_VDDCX>;
1854                         power-domain-names = "cx";
1855
1856                         memory-region = <&adsp_fw_mem>;
1857
1858                         qcom,smem-states = <&smp2p_adsp_out 0>;
1859                         qcom,smem-state-names = "stop";
1860
1861                         status = "disabled";
1862
1863                         smd-edge {
1864                                 interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>;
1865
1866                                 label = "lpass";
1867                                 mboxes = <&apcs 8>;
1868                                 qcom,smd-edge = <1>;
1869                                 qcom,remote-pid = <2>;
1870
1871                                 apr {
1872                                         compatible = "qcom,apr-v2";
1873                                         qcom,smd-channels = "apr_audio_svc";
1874                                         qcom,domain = <APR_DOMAIN_ADSP>;
1875                                         #address-cells = <1>;
1876                                         #size-cells = <0>;
1877
1878                                         q6core: service@3 {
1879                                                 reg = <APR_SVC_ADSP_CORE>;
1880                                                 compatible = "qcom,q6core";
1881                                         };
1882
1883                                         q6afe: service@4 {
1884                                                 compatible = "qcom,q6afe";
1885                                                 reg = <APR_SVC_AFE>;
1886                                                 q6afedai: dais {
1887                                                         compatible = "qcom,q6afe-dais";
1888                                                         #address-cells = <1>;
1889                                                         #size-cells = <0>;
1890                                                         #sound-dai-cells = <1>;
1891
1892                                                         dai@16 {
1893                                                                 reg = <PRIMARY_MI2S_RX>;
1894                                                                 qcom,sd-lines = <0 1>;
1895                                                         };
1896                                                         dai@20 {
1897                                                                 reg = <TERTIARY_MI2S_TX>;
1898                                                                 qcom,sd-lines = <0 1>;
1899                                                         };
1900                                                         dai@127 {
1901                                                                 reg = <QUINARY_MI2S_RX>;
1902                                                                 qcom,sd-lines = <0>;
1903                                                         };
1904                                                 };
1905
1906                                                 q6afecc: clock-controller {
1907                                                         compatible = "qcom,q6afe-clocks";
1908                                                         #clock-cells = <2>;
1909                                                 };
1910                                         };
1911
1912                                         q6asm: service@7 {
1913                                                 compatible = "qcom,q6asm";
1914                                                 reg = <APR_SVC_ASM>;
1915                                                 q6asmdai: dais {
1916                                                         compatible = "qcom,q6asm-dais";
1917                                                         #address-cells = <1>;
1918                                                         #size-cells = <0>;
1919                                                         #sound-dai-cells = <1>;
1920
1921                                                         dai@0 {
1922                                                                 reg = <0>;
1923                                                                 direction = <Q6ASM_DAI_RX>;
1924                                                         };
1925                                                         dai@1 {
1926                                                                 reg = <1>;
1927                                                                 direction = <Q6ASM_DAI_TX>;
1928                                                         };
1929                                                         dai@2 {
1930                                                                 reg = <2>;
1931                                                                 direction = <Q6ASM_DAI_RX>;
1932                                                         };
1933                                                         dai@3 {
1934                                                                 reg = <3>;
1935                                                                 direction = <Q6ASM_DAI_RX>;
1936                                                                 is-compress-dai;
1937                                                         };
1938                                                 };
1939                                         };
1940
1941                                         q6adm: service@8 {
1942                                                 compatible = "qcom,q6adm";
1943                                                 reg = <APR_SVC_ADM>;
1944                                                 q6routing: routing {
1945                                                         compatible = "qcom,q6adm-routing";
1946                                                         #sound-dai-cells = <0>;
1947                                                 };
1948                                         };
1949                                 };
1950                         };
1951                 };
1952         };
1953
1954         thermal-zones {
1955                 cpu0-thermal {
1956                         polling-delay-passive = <250>;
1957                         polling-delay = <1000>;
1958                         thermal-sensors = <&tsens0 9>;
1959                         trips {
1960                                 cpu0_alert: trip-point0 {
1961                                         temperature = <80000>;
1962                                         hysteresis = <2000>;
1963                                         type = "passive";
1964                                 };
1965                                 cpu0_crit: crit {
1966                                         temperature = <100000>;
1967                                         hysteresis = <2000>;
1968                                         type = "critical";
1969                                 };
1970                         };
1971                         cooling-maps {
1972                                 map0 {
1973                                         trip = <&cpu0_alert>;
1974                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1975                                 };
1976                         };
1977                 };
1978                 cpu1-thermal {
1979                         polling-delay-passive = <250>;
1980                         polling-delay = <1000>;
1981                         thermal-sensors = <&tsens0 10>;
1982                         trips {
1983                                 cpu1_alert: trip-point0 {
1984                                         temperature = <80000>;
1985                                         hysteresis = <2000>;
1986                                         type = "passive";
1987                                 };
1988                                 cpu1_crit: crit {
1989                                         temperature = <100000>;
1990                                         hysteresis = <2000>;
1991                                         type = "critical";
1992                                 };
1993                         };
1994                         cooling-maps {
1995                                 map0 {
1996                                         trip = <&cpu1_alert>;
1997                                         cooling-device = <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1998                                 };
1999                         };
2000                 };
2001                 cpu2-thermal {
2002                         polling-delay-passive = <250>;
2003                         polling-delay = <1000>;
2004                         thermal-sensors = <&tsens0 11>;
2005                         trips {
2006                                 cpu2_alert: trip-point0 {
2007                                         temperature = <80000>;
2008                                         hysteresis = <2000>;
2009                                         type = "passive";
2010                                 };
2011                                 cpu2_crit: crit {
2012                                         temperature = <100000>;
2013                                         hysteresis = <2000>;
2014                                         type = "critical";
2015                                 };
2016                         };
2017                         cooling-maps {
2018                                 map0 {
2019                                         trip = <&cpu2_alert>;
2020                                         cooling-device = <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2021                                 };
2022                         };
2023                 };
2024                 cpu3-thermal {
2025                         polling-delay-passive = <250>;
2026                         polling-delay = <1000>;
2027                         thermal-sensors = <&tsens0 12>;
2028                         trips {
2029                                 cpu3_alert: trip-point0 {
2030                                         temperature = <80000>;
2031                                         hysteresis = <2000>;
2032                                         type = "passive";
2033                                 };
2034                                 cpu3_crit: crit {
2035                                         temperature = <100000>;
2036                                         hysteresis = <2000>;
2037                                         type = "critical";
2038                                 };
2039                         };
2040                         cooling-maps {
2041                                 map0 {
2042                                         trip = <&cpu3_alert>;
2043                                         cooling-device = <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2044                                 };
2045                         };
2046                 };
2047                 cpu4-thermal {
2048                         polling-delay-passive = <250>;
2049                         polling-delay = <1000>;
2050                         thermal-sensors = <&tsens0 4>;
2051                         trips {
2052                                 cpu4_alert: trip-point0 {
2053                                         temperature = <80000>;
2054                                         hysteresis = <2000>;
2055                                         type = "passive";
2056                                 };
2057                                 cpu4_crit: crit {
2058                                         temperature = <100000>;
2059                                         hysteresis = <2000>;
2060                                         type = "critical";
2061                                 };
2062                         };
2063                         cooling-maps {
2064                                 map0 {
2065                                         trip = <&cpu4_alert>;
2066                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2067                                 };
2068                         };
2069                 };
2070                 cpu5-thermal {
2071                         polling-delay-passive = <250>;
2072                         polling-delay = <1000>;
2073                         thermal-sensors = <&tsens0 5>;
2074                         trips {
2075                                 cpu5_alert: trip-point0 {
2076                                         temperature = <80000>;
2077                                         hysteresis = <2000>;
2078                                         type = "passive";
2079                                 };
2080                                 cpu5_crit: crit {
2081                                         temperature = <100000>;
2082                                         hysteresis = <2000>;
2083                                         type = "critical";
2084                                 };
2085                         };
2086                         cooling-maps {
2087                                 map0 {
2088                                         trip = <&cpu5_alert>;
2089                                         cooling-device = <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2090                                 };
2091                         };
2092                 };
2093                 cpu6-thermal {
2094                         polling-delay-passive = <250>;
2095                         polling-delay = <1000>;
2096                         thermal-sensors = <&tsens0 6>;
2097                         trips {
2098                                 cpu6_alert: trip-point0 {
2099                                         temperature = <80000>;
2100                                         hysteresis = <2000>;
2101                                         type = "passive";
2102                                 };
2103                                 cpu6_crit: crit {
2104                                         temperature = <100000>;
2105                                         hysteresis = <2000>;
2106                                         type = "critical";
2107                                 };
2108                         };
2109                         cooling-maps {
2110                                 map0 {
2111                                         trip = <&cpu6_alert>;
2112                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2113                                 };
2114                         };
2115                 };
2116                 cpu7-thermal {
2117                         polling-delay-passive = <250>;
2118                         polling-delay = <1000>;
2119                         thermal-sensors = <&tsens0 7>;
2120                         trips {
2121                                 cpu7_alert: trip-point0 {
2122                                         temperature = <80000>;
2123                                         hysteresis = <2000>;
2124                                         type = "passive";
2125                                 };
2126                                 cpu7_crit: crit {
2127                                         temperature = <100000>;
2128                                         hysteresis = <2000>;
2129                                         type = "critical";
2130                                 };
2131                         };
2132                         cooling-maps {
2133                                 map0 {
2134                                         trip = <&cpu7_alert>;
2135                                         cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2136                                 };
2137                         };
2138                 };
2139
2140                 gpu-thermal {
2141                         polling-delay-passive = <250>;
2142                         polling-delay = <1000>;
2143                         thermal-sensors = <&tsens0 15>;
2144
2145                         trips {
2146                                 gpu_alert: trip-point0 {
2147                                         temperature = <70000>;
2148                                         hysteresis = <2000>;
2149                                         type = "passive";
2150                                 };
2151
2152                                 gpu_crit: crit {
2153                                         temperature = <90000>;
2154                                         hysteresis = <2000>;
2155                                         type = "critical";
2156                                 };
2157                         };
2158
2159                         cooling-maps {
2160                                 map0 {
2161                                         trip = <&gpu_alert>;
2162                                         cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2163                                 };
2164                         };
2165                 };
2166         };
2167
2168         timer {
2169                 compatible = "arm,armv8-timer";
2170                 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2171                              <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2172                              <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2173                              <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
2174         };
2175 };