1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
6 #include <dt-bindings/arm/coresight-cti-dt.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/interconnect/qcom,msm8916.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/power/qcom-rpmpd.h>
12 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
13 #include <dt-bindings/soc/qcom,apr.h>
14 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&intc>;
25 device_type = "memory";
26 /* We expect the bootloader to fill in the reg */
27 reg = <0 0x80000000 0 0>;
36 reg = <0x0 0x86000000 0x0 0x300000>;
41 compatible = "qcom,smem";
42 reg = <0x0 0x86300000 0x0 0x100000>;
45 hwlocks = <&tcsr_mutex 3>;
46 qcom,rpm-msg-ram = <&rpm_msg_ram>;
50 reg = <0x0 0x86400000 0x0 0x100000>;
55 reg = <0x0 0x86500000 0x0 0x180000>;
60 reg = <0x0 0x86680000 0x0 0x80000>;
65 compatible = "qcom,rmtfs-mem";
66 reg = <0x0 0x86700000 0x0 0xe0000>;
73 reg = <0x0 0x867e0000 0x0 0x20000>;
77 mpss_mem: mpss@86800000 {
79 * The memory region for the mpss firmware is generally
80 * relocatable and could be allocated dynamically.
81 * However, many firmware versions tend to fail when
82 * loaded to some special addresses, so it is hard to
83 * define reliable alloc-ranges.
85 * alignment = <0x0 0x400000>;
86 * alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
88 reg = <0x0 0x86800000 0x0 0>; /* size is device-specific */
94 size = <0x0 0x600000>;
95 alignment = <0x0 0x100000>;
96 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
102 size = <0x0 0x500000>;
103 alignment = <0x0 0x100000>;
104 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
110 size = <0x0 0x100000>;
111 alignment = <0x0 0x100000>;
112 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
120 compatible = "fixed-clock";
122 clock-frequency = <19200000>;
125 sleep_clk: sleep-clk {
126 compatible = "fixed-clock";
128 clock-frequency = <32768>;
133 #address-cells = <1>;
138 compatible = "arm,cortex-a53";
140 next-level-cache = <&L2_0>;
141 enable-method = "psci";
143 operating-points-v2 = <&cpu_opp_table>;
144 #cooling-cells = <2>;
145 power-domains = <&CPU_PD0>;
146 power-domain-names = "psci";
147 qcom,acc = <&cpu0_acc>;
148 qcom,saw = <&cpu0_saw>;
153 compatible = "arm,cortex-a53";
155 next-level-cache = <&L2_0>;
156 enable-method = "psci";
158 operating-points-v2 = <&cpu_opp_table>;
159 #cooling-cells = <2>;
160 power-domains = <&CPU_PD1>;
161 power-domain-names = "psci";
162 qcom,acc = <&cpu1_acc>;
163 qcom,saw = <&cpu1_saw>;
168 compatible = "arm,cortex-a53";
170 next-level-cache = <&L2_0>;
171 enable-method = "psci";
173 operating-points-v2 = <&cpu_opp_table>;
174 #cooling-cells = <2>;
175 power-domains = <&CPU_PD2>;
176 power-domain-names = "psci";
177 qcom,acc = <&cpu2_acc>;
178 qcom,saw = <&cpu2_saw>;
183 compatible = "arm,cortex-a53";
185 next-level-cache = <&L2_0>;
186 enable-method = "psci";
188 operating-points-v2 = <&cpu_opp_table>;
189 #cooling-cells = <2>;
190 power-domains = <&CPU_PD3>;
191 power-domain-names = "psci";
192 qcom,acc = <&cpu3_acc>;
193 qcom,saw = <&cpu3_saw>;
197 compatible = "cache";
203 entry-method = "psci";
205 CPU_SLEEP_0: cpu-sleep-0 {
206 compatible = "arm,idle-state";
207 idle-state-name = "standalone-power-collapse";
208 arm,psci-suspend-param = <0x40000002>;
209 entry-latency-us = <130>;
210 exit-latency-us = <150>;
211 min-residency-us = <2000>;
218 CLUSTER_RET: cluster-retention {
219 compatible = "domain-idle-state";
220 arm,psci-suspend-param = <0x41000012>;
221 entry-latency-us = <500>;
222 exit-latency-us = <500>;
223 min-residency-us = <2000>;
226 CLUSTER_PWRDN: cluster-gdhs {
227 compatible = "domain-idle-state";
228 arm,psci-suspend-param = <0x41000032>;
229 entry-latency-us = <2000>;
230 exit-latency-us = <2000>;
231 min-residency-us = <6000>;
236 cpu_opp_table: opp-table-cpu {
237 compatible = "operating-points-v2";
241 opp-hz = /bits/ 64 <200000000>;
244 opp-hz = /bits/ 64 <400000000>;
247 opp-hz = /bits/ 64 <800000000>;
250 opp-hz = /bits/ 64 <998400000>;
256 compatible = "qcom,scm-msm8916", "qcom,scm";
257 clocks = <&gcc GCC_CRYPTO_CLK>,
258 <&gcc GCC_CRYPTO_AXI_CLK>,
259 <&gcc GCC_CRYPTO_AHB_CLK>;
260 clock-names = "core", "bus", "iface";
263 qcom,dload-mode = <&tcsr 0x6100>;
268 compatible = "arm,cortex-a53-pmu";
269 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
273 compatible = "arm,psci-1.0";
276 CPU_PD0: power-domain-cpu0 {
277 #power-domain-cells = <0>;
278 power-domains = <&CLUSTER_PD>;
279 domain-idle-states = <&CPU_SLEEP_0>;
282 CPU_PD1: power-domain-cpu1 {
283 #power-domain-cells = <0>;
284 power-domains = <&CLUSTER_PD>;
285 domain-idle-states = <&CPU_SLEEP_0>;
288 CPU_PD2: power-domain-cpu2 {
289 #power-domain-cells = <0>;
290 power-domains = <&CLUSTER_PD>;
291 domain-idle-states = <&CPU_SLEEP_0>;
294 CPU_PD3: power-domain-cpu3 {
295 #power-domain-cells = <0>;
296 power-domains = <&CLUSTER_PD>;
297 domain-idle-states = <&CPU_SLEEP_0>;
300 CLUSTER_PD: power-domain-cluster {
301 #power-domain-cells = <0>;
302 domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>;
307 compatible = "qcom,msm8916-rpm-proc", "qcom,rpm-proc";
310 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
311 qcom,ipc = <&apcs 8 0>;
312 qcom,smd-edge = <15>;
314 rpm_requests: rpm-requests {
315 compatible = "qcom,rpm-msm8916";
316 qcom,smd-channels = "rpm_requests";
318 rpmcc: clock-controller {
319 compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc";
321 clocks = <&xo_board>;
325 rpmpd: power-controller {
326 compatible = "qcom,msm8916-rpmpd";
327 #power-domain-cells = <1>;
328 operating-points-v2 = <&rpmpd_opp_table>;
330 rpmpd_opp_table: opp-table {
331 compatible = "operating-points-v2";
333 rpmpd_opp_ret: opp1 {
336 rpmpd_opp_svs_krait: opp2 {
339 rpmpd_opp_svs_soc: opp3 {
342 rpmpd_opp_nom: opp4 {
345 rpmpd_opp_turbo: opp5 {
348 rpmpd_opp_super_turbo: opp6 {
358 compatible = "qcom,smp2p";
359 qcom,smem = <435>, <428>;
361 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
363 qcom,ipc = <&apcs 8 14>;
365 qcom,local-pid = <0>;
366 qcom,remote-pid = <1>;
368 hexagon_smp2p_out: master-kernel {
369 qcom,entry-name = "master-kernel";
371 #qcom,smem-state-cells = <1>;
374 hexagon_smp2p_in: slave-kernel {
375 qcom,entry-name = "slave-kernel";
377 interrupt-controller;
378 #interrupt-cells = <2>;
383 compatible = "qcom,smp2p";
384 qcom,smem = <451>, <431>;
386 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
388 qcom,ipc = <&apcs 8 18>;
390 qcom,local-pid = <0>;
391 qcom,remote-pid = <4>;
393 wcnss_smp2p_out: master-kernel {
394 qcom,entry-name = "master-kernel";
396 #qcom,smem-state-cells = <1>;
399 wcnss_smp2p_in: slave-kernel {
400 qcom,entry-name = "slave-kernel";
402 interrupt-controller;
403 #interrupt-cells = <2>;
408 compatible = "qcom,smsm";
410 #address-cells = <1>;
413 qcom,ipc-1 = <&apcs 8 13>;
414 qcom,ipc-3 = <&apcs 8 19>;
419 #qcom,smem-state-cells = <1>;
422 hexagon_smsm: hexagon@1 {
424 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
426 interrupt-controller;
427 #interrupt-cells = <2>;
430 wcnss_smsm: wcnss@6 {
432 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
434 interrupt-controller;
435 #interrupt-cells = <2>;
440 #address-cells = <1>;
442 ranges = <0 0 0 0xffffffff>;
443 compatible = "simple-bus";
446 compatible = "qcom,prng";
447 reg = <0x00022000 0x200>;
448 clocks = <&gcc GCC_PRNG_AHB_CLK>;
449 clock-names = "core";
453 compatible = "qcom,pshold";
454 reg = <0x004ab000 0x4>;
457 qfprom: qfprom@5c000 {
458 compatible = "qcom,msm8916-qfprom", "qcom,qfprom";
459 reg = <0x0005c000 0x1000>;
460 #address-cells = <1>;
463 tsens_base1: base1@d0 {
468 tsens_s0_p1: s0-p1@d0 {
473 tsens_s0_p2: s0-p2@d1 {
478 tsens_s1_p1: s1-p1@d2 {
482 tsens_s1_p2: s1-p2@d2 {
486 tsens_s2_p1: s2-p1@d3 {
491 tsens_s2_p2: s2-p2@d4 {
496 // no tsens with hw_id 3
498 tsens_s4_p1: s4-p1@d4 {
503 tsens_s4_p2: s4-p2@d5 {
508 tsens_s5_p1: s5-p1@d5 {
513 tsens_s5_p2: s5-p2@d6 {
518 tsens_base2: base2@d7 {
523 tsens_mode: mode@ef {
529 rpm_msg_ram: sram@60000 {
530 compatible = "qcom,rpm-msg-ram";
531 reg = <0x00060000 0x8000>;
535 compatible = "qcom,msm8916-rpm-stats";
536 reg = <0x00290000 0x10000>;
539 bimc: interconnect@400000 {
540 compatible = "qcom,msm8916-bimc";
541 reg = <0x00400000 0x62000>;
542 #interconnect-cells = <1>;
543 clock-names = "bus", "bus_a";
544 clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
545 <&rpmcc RPM_SMD_BIMC_A_CLK>;
548 tsens: thermal-sensor@4a9000 {
549 compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1";
550 reg = <0x004a9000 0x1000>, /* TM */
551 <0x004a8000 0x1000>; /* SROT */
554 nvmem-cells = <&tsens_mode>,
555 <&tsens_base1>, <&tsens_base2>,
556 <&tsens_s0_p1>, <&tsens_s0_p2>,
557 <&tsens_s1_p1>, <&tsens_s1_p2>,
558 <&tsens_s2_p1>, <&tsens_s2_p2>,
559 <&tsens_s4_p1>, <&tsens_s4_p2>,
560 <&tsens_s5_p1>, <&tsens_s5_p2>;
561 nvmem-cell-names = "mode",
569 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
570 interrupt-names = "uplow";
571 #thermal-sensor-cells = <1>;
574 pcnoc: interconnect@500000 {
575 compatible = "qcom,msm8916-pcnoc";
576 reg = <0x00500000 0x11000>;
577 #interconnect-cells = <1>;
578 clock-names = "bus", "bus_a";
579 clocks = <&rpmcc RPM_SMD_PCNOC_CLK>,
580 <&rpmcc RPM_SMD_PCNOC_A_CLK>;
583 snoc: interconnect@580000 {
584 compatible = "qcom,msm8916-snoc";
585 reg = <0x00580000 0x14000>;
586 #interconnect-cells = <1>;
587 clock-names = "bus", "bus_a";
588 clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
589 <&rpmcc RPM_SMD_SNOC_A_CLK>;
593 compatible = "arm,coresight-stm", "arm,primecell";
594 reg = <0x00802000 0x1000>,
595 <0x09280000 0x180000>;
596 reg-names = "stm-base", "stm-stimulus-base";
598 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
599 clock-names = "apb_pclk", "atclk";
606 remote-endpoint = <&funnel0_in7>;
613 /* CTI 0 - TMC connections */
615 compatible = "arm,coresight-cti", "arm,primecell";
616 reg = <0x00810000 0x1000>;
618 clocks = <&rpmcc RPM_QDSS_CLK>;
619 clock-names = "apb_pclk";
624 /* CTI 1 - TPIU connections */
626 compatible = "arm,coresight-cti", "arm,primecell";
627 reg = <0x00811000 0x1000>;
629 clocks = <&rpmcc RPM_QDSS_CLK>;
630 clock-names = "apb_pclk";
635 /* CTIs 2-11 - no information - not instantiated */
638 compatible = "arm,coresight-tpiu", "arm,primecell";
639 reg = <0x00820000 0x1000>;
641 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
642 clock-names = "apb_pclk", "atclk";
649 remote-endpoint = <&replicator_out1>;
655 funnel0: funnel@821000 {
656 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
657 reg = <0x00821000 0x1000>;
659 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
660 clock-names = "apb_pclk", "atclk";
665 #address-cells = <1>;
669 * Not described input ports:
670 * 0 - connected to Resource and Power Manger CPU ETM
672 * 2 - connected to Modem CPU ETM
675 * 6 - connected trought funnel to Wireless CPU ETM
676 * 7 - connected to STM component
681 funnel0_in4: endpoint {
682 remote-endpoint = <&funnel1_out>;
688 funnel0_in7: endpoint {
689 remote-endpoint = <&stm_out>;
696 funnel0_out: endpoint {
697 remote-endpoint = <&etf_in>;
703 replicator: replicator@824000 {
704 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
705 reg = <0x00824000 0x1000>;
707 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
708 clock-names = "apb_pclk", "atclk";
713 #address-cells = <1>;
718 replicator_out0: endpoint {
719 remote-endpoint = <&etr_in>;
724 replicator_out1: endpoint {
725 remote-endpoint = <&tpiu_in>;
732 replicator_in: endpoint {
733 remote-endpoint = <&etf_out>;
740 compatible = "arm,coresight-tmc", "arm,primecell";
741 reg = <0x00825000 0x1000>;
743 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
744 clock-names = "apb_pclk", "atclk";
751 remote-endpoint = <&funnel0_out>;
759 remote-endpoint = <&replicator_in>;
766 compatible = "arm,coresight-tmc", "arm,primecell";
767 reg = <0x00826000 0x1000>;
769 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
770 clock-names = "apb_pclk", "atclk";
777 remote-endpoint = <&replicator_out0>;
783 funnel1: funnel@841000 { /* APSS funnel only 4 inputs are used */
784 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
785 reg = <0x00841000 0x1000>;
787 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
788 clock-names = "apb_pclk", "atclk";
793 #address-cells = <1>;
798 funnel1_in0: endpoint {
799 remote-endpoint = <&etm0_out>;
804 funnel1_in1: endpoint {
805 remote-endpoint = <&etm1_out>;
810 funnel1_in2: endpoint {
811 remote-endpoint = <&etm2_out>;
816 funnel1_in3: endpoint {
817 remote-endpoint = <&etm3_out>;
824 funnel1_out: endpoint {
825 remote-endpoint = <&funnel0_in4>;
831 debug0: debug@850000 {
832 compatible = "arm,coresight-cpu-debug", "arm,primecell";
833 reg = <0x00850000 0x1000>;
834 clocks = <&rpmcc RPM_QDSS_CLK>;
835 clock-names = "apb_pclk";
840 debug1: debug@852000 {
841 compatible = "arm,coresight-cpu-debug", "arm,primecell";
842 reg = <0x00852000 0x1000>;
843 clocks = <&rpmcc RPM_QDSS_CLK>;
844 clock-names = "apb_pclk";
849 debug2: debug@854000 {
850 compatible = "arm,coresight-cpu-debug", "arm,primecell";
851 reg = <0x00854000 0x1000>;
852 clocks = <&rpmcc RPM_QDSS_CLK>;
853 clock-names = "apb_pclk";
858 debug3: debug@856000 {
859 compatible = "arm,coresight-cpu-debug", "arm,primecell";
860 reg = <0x00856000 0x1000>;
861 clocks = <&rpmcc RPM_QDSS_CLK>;
862 clock-names = "apb_pclk";
867 /* Core CTIs; CTIs 12-15 */
870 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
872 reg = <0x00858000 0x1000>;
874 clocks = <&rpmcc RPM_QDSS_CLK>;
875 clock-names = "apb_pclk";
878 arm,cs-dev-assoc = <&etm0>;
885 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
887 reg = <0x00859000 0x1000>;
889 clocks = <&rpmcc RPM_QDSS_CLK>;
890 clock-names = "apb_pclk";
893 arm,cs-dev-assoc = <&etm1>;
900 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
902 reg = <0x0085a000 0x1000>;
904 clocks = <&rpmcc RPM_QDSS_CLK>;
905 clock-names = "apb_pclk";
908 arm,cs-dev-assoc = <&etm2>;
915 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
917 reg = <0x0085b000 0x1000>;
919 clocks = <&rpmcc RPM_QDSS_CLK>;
920 clock-names = "apb_pclk";
923 arm,cs-dev-assoc = <&etm3>;
929 compatible = "arm,coresight-etm4x", "arm,primecell";
930 reg = <0x0085c000 0x1000>;
932 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
933 clock-names = "apb_pclk", "atclk";
934 arm,coresight-loses-context-with-cpu;
943 remote-endpoint = <&funnel1_in0>;
950 compatible = "arm,coresight-etm4x", "arm,primecell";
951 reg = <0x0085d000 0x1000>;
953 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
954 clock-names = "apb_pclk", "atclk";
955 arm,coresight-loses-context-with-cpu;
964 remote-endpoint = <&funnel1_in1>;
971 compatible = "arm,coresight-etm4x", "arm,primecell";
972 reg = <0x0085e000 0x1000>;
974 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
975 clock-names = "apb_pclk", "atclk";
976 arm,coresight-loses-context-with-cpu;
985 remote-endpoint = <&funnel1_in2>;
992 compatible = "arm,coresight-etm4x", "arm,primecell";
993 reg = <0x0085f000 0x1000>;
995 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
996 clock-names = "apb_pclk", "atclk";
997 arm,coresight-loses-context-with-cpu;
1001 status = "disabled";
1005 etm3_out: endpoint {
1006 remote-endpoint = <&funnel1_in3>;
1012 tlmm: pinctrl@1000000 {
1013 compatible = "qcom,msm8916-pinctrl";
1014 reg = <0x01000000 0x300000>;
1015 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1017 gpio-ranges = <&tlmm 0 0 122>;
1019 interrupt-controller;
1020 #interrupt-cells = <2>;
1022 blsp_i2c1_default: blsp-i2c1-default-state {
1023 pins = "gpio2", "gpio3";
1024 function = "blsp_i2c1";
1025 drive-strength = <2>;
1029 blsp_i2c1_sleep: blsp-i2c1-sleep-state {
1030 pins = "gpio2", "gpio3";
1032 drive-strength = <2>;
1036 blsp_i2c2_default: blsp-i2c2-default-state {
1037 pins = "gpio6", "gpio7";
1038 function = "blsp_i2c2";
1039 drive-strength = <2>;
1043 blsp_i2c2_sleep: blsp-i2c2-sleep-state {
1044 pins = "gpio6", "gpio7";
1046 drive-strength = <2>;
1050 blsp_i2c3_default: blsp-i2c3-default-state {
1051 pins = "gpio10", "gpio11";
1052 function = "blsp_i2c3";
1053 drive-strength = <2>;
1057 blsp_i2c3_sleep: blsp-i2c3-sleep-state {
1058 pins = "gpio10", "gpio11";
1060 drive-strength = <2>;
1064 blsp_i2c4_default: blsp-i2c4-default-state {
1065 pins = "gpio14", "gpio15";
1066 function = "blsp_i2c4";
1067 drive-strength = <2>;
1071 blsp_i2c4_sleep: blsp-i2c4-sleep-state {
1072 pins = "gpio14", "gpio15";
1074 drive-strength = <2>;
1078 blsp_i2c5_default: blsp-i2c5-default-state {
1079 pins = "gpio18", "gpio19";
1080 function = "blsp_i2c5";
1081 drive-strength = <2>;
1085 blsp_i2c5_sleep: blsp-i2c5-sleep-state {
1086 pins = "gpio18", "gpio19";
1088 drive-strength = <2>;
1092 blsp_i2c6_default: blsp-i2c6-default-state {
1093 pins = "gpio22", "gpio23";
1094 function = "blsp_i2c6";
1095 drive-strength = <2>;
1099 blsp_i2c6_sleep: blsp-i2c6-sleep-state {
1100 pins = "gpio22", "gpio23";
1102 drive-strength = <2>;
1106 blsp_spi1_default: blsp-spi1-default-state {
1108 pins = "gpio0", "gpio1", "gpio3";
1109 function = "blsp_spi1";
1110 drive-strength = <12>;
1116 drive-strength = <16>;
1122 blsp_spi1_sleep: blsp-spi1-sleep-state {
1123 pins = "gpio0", "gpio1", "gpio2", "gpio3";
1125 drive-strength = <2>;
1129 blsp_spi2_default: blsp-spi2-default-state {
1131 pins = "gpio4", "gpio5", "gpio7";
1132 function = "blsp_spi2";
1133 drive-strength = <12>;
1139 drive-strength = <16>;
1145 blsp_spi2_sleep: blsp-spi2-sleep-state {
1146 pins = "gpio4", "gpio5", "gpio6", "gpio7";
1148 drive-strength = <2>;
1152 blsp_spi3_default: blsp-spi3-default-state {
1154 pins = "gpio8", "gpio9", "gpio11";
1155 function = "blsp_spi3";
1156 drive-strength = <12>;
1162 drive-strength = <16>;
1168 blsp_spi3_sleep: blsp-spi3-sleep-state {
1169 pins = "gpio8", "gpio9", "gpio10", "gpio11";
1171 drive-strength = <2>;
1175 blsp_spi4_default: blsp-spi4-default-state {
1177 pins = "gpio12", "gpio13", "gpio15";
1178 function = "blsp_spi4";
1179 drive-strength = <12>;
1185 drive-strength = <16>;
1191 blsp_spi4_sleep: blsp-spi4-sleep-state {
1192 pins = "gpio12", "gpio13", "gpio14", "gpio15";
1194 drive-strength = <2>;
1198 blsp_spi5_default: blsp-spi5-default-state {
1200 pins = "gpio16", "gpio17", "gpio19";
1201 function = "blsp_spi5";
1202 drive-strength = <12>;
1208 drive-strength = <16>;
1214 blsp_spi5_sleep: blsp-spi5-sleep-state {
1215 pins = "gpio16", "gpio17", "gpio18", "gpio19";
1217 drive-strength = <2>;
1221 blsp_spi6_default: blsp-spi6-default-state {
1223 pins = "gpio20", "gpio21", "gpio23";
1224 function = "blsp_spi6";
1225 drive-strength = <12>;
1231 drive-strength = <16>;
1237 blsp_spi6_sleep: blsp-spi6-sleep-state {
1238 pins = "gpio20", "gpio21", "gpio22", "gpio23";
1240 drive-strength = <2>;
1244 blsp_uart1_default: blsp-uart1-default-state {
1245 /* TX, RX, CTS_N, RTS_N */
1246 pins = "gpio0", "gpio1", "gpio2", "gpio3";
1247 function = "blsp_uart1";
1248 drive-strength = <16>;
1252 blsp_uart1_sleep: blsp-uart1-sleep-state {
1253 pins = "gpio0", "gpio1", "gpio2", "gpio3";
1255 drive-strength = <2>;
1259 blsp_uart2_default: blsp-uart2-default-state {
1260 pins = "gpio4", "gpio5";
1261 function = "blsp_uart2";
1262 drive-strength = <16>;
1266 blsp_uart2_sleep: blsp-uart2-sleep-state {
1267 pins = "gpio4", "gpio5";
1269 drive-strength = <2>;
1273 camera_front_default: camera-front-default-state {
1277 drive-strength = <16>;
1283 drive-strength = <16>;
1288 function = "cam_mclk1";
1289 drive-strength = <16>;
1294 camera_rear_default: camera-rear-default-state {
1298 drive-strength = <16>;
1304 drive-strength = <16>;
1309 function = "cam_mclk0";
1310 drive-strength = <16>;
1315 cci0_default: cci0-default-state {
1316 pins = "gpio29", "gpio30";
1317 function = "cci_i2c";
1318 drive-strength = <16>;
1322 cdc_dmic_default: cdc-dmic-default-state {
1325 function = "dmic0_clk";
1326 drive-strength = <8>;
1330 function = "dmic0_data";
1331 drive-strength = <8>;
1335 cdc_dmic_sleep: cdc-dmic-sleep-state {
1338 function = "dmic0_clk";
1339 drive-strength = <2>;
1344 function = "dmic0_data";
1345 drive-strength = <2>;
1350 cdc_pdm_default: cdc-pdm-default-state {
1351 pins = "gpio63", "gpio64", "gpio65", "gpio66",
1353 function = "cdc_pdm0";
1354 drive-strength = <8>;
1358 cdc_pdm_sleep: cdc-pdm-sleep-state {
1359 pins = "gpio63", "gpio64", "gpio65", "gpio66",
1361 function = "cdc_pdm0";
1362 drive-strength = <2>;
1366 pri_mi2s_default: mi2s-pri-default-state {
1367 pins = "gpio113", "gpio114", "gpio115", "gpio116";
1368 function = "pri_mi2s";
1369 drive-strength = <8>;
1373 pri_mi2s_sleep: mi2s-pri-sleep-state {
1374 pins = "gpio113", "gpio114", "gpio115", "gpio116";
1375 function = "pri_mi2s";
1376 drive-strength = <2>;
1380 pri_mi2s_mclk_default: mi2s-pri-mclk-default-state {
1382 function = "pri_mi2s";
1383 drive-strength = <8>;
1387 pri_mi2s_mclk_sleep: mi2s-pri-mclk-sleep-state {
1389 function = "pri_mi2s";
1390 drive-strength = <2>;
1394 pri_mi2s_ws_default: mi2s-pri-ws-default-state {
1396 function = "pri_mi2s_ws";
1397 drive-strength = <8>;
1401 pri_mi2s_ws_sleep: mi2s-pri-ws-sleep-state {
1403 function = "pri_mi2s_ws";
1404 drive-strength = <2>;
1408 sec_mi2s_default: mi2s-sec-default-state {
1409 pins = "gpio112", "gpio117", "gpio118", "gpio119";
1410 function = "sec_mi2s";
1411 drive-strength = <8>;
1415 sec_mi2s_sleep: mi2s-sec-sleep-state {
1416 pins = "gpio112", "gpio117", "gpio118", "gpio119";
1417 function = "sec_mi2s";
1418 drive-strength = <2>;
1422 sdc1_default: sdc1-default-state {
1426 drive-strength = <16>;
1431 drive-strength = <10>;
1436 drive-strength = <10>;
1440 sdc1_sleep: sdc1-sleep-state {
1444 drive-strength = <2>;
1449 drive-strength = <2>;
1454 drive-strength = <2>;
1458 sdc2_default: sdc2-default-state {
1462 drive-strength = <16>;
1467 drive-strength = <10>;
1472 drive-strength = <10>;
1476 sdc2_sleep: sdc2-sleep-state {
1480 drive-strength = <2>;
1485 drive-strength = <2>;
1490 drive-strength = <2>;
1494 wcss_wlan_default: wcss-wlan-default-state {
1495 pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44";
1496 function = "wcss_wlan";
1497 drive-strength = <6>;
1502 gcc: clock-controller@1800000 {
1503 compatible = "qcom,gcc-msm8916";
1506 #power-domain-cells = <1>;
1507 reg = <0x01800000 0x80000>;
1508 clocks = <&xo_board>,
1524 tcsr_mutex: hwlock@1905000 {
1525 compatible = "qcom,tcsr-mutex";
1526 reg = <0x01905000 0x20000>;
1527 #hwlock-cells = <1>;
1530 tcsr: syscon@1937000 {
1531 compatible = "qcom,tcsr-msm8916", "syscon";
1532 reg = <0x01937000 0x30000>;
1535 mdss: display-subsystem@1a00000 {
1536 status = "disabled";
1537 compatible = "qcom,mdss";
1538 reg = <0x01a00000 0x1000>,
1539 <0x01ac8000 0x3000>;
1540 reg-names = "mdss_phys", "vbif_phys";
1542 power-domains = <&gcc MDSS_GDSC>;
1544 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1545 <&gcc GCC_MDSS_AXI_CLK>,
1546 <&gcc GCC_MDSS_VSYNC_CLK>;
1547 clock-names = "iface",
1551 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1553 interrupt-controller;
1554 #interrupt-cells = <1>;
1556 #address-cells = <1>;
1560 mdss_mdp: display-controller@1a01000 {
1561 compatible = "qcom,msm8916-mdp5", "qcom,mdp5";
1562 reg = <0x01a01000 0x89000>;
1563 reg-names = "mdp_phys";
1565 interrupt-parent = <&mdss>;
1568 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1569 <&gcc GCC_MDSS_AXI_CLK>,
1570 <&gcc GCC_MDSS_MDP_CLK>,
1571 <&gcc GCC_MDSS_VSYNC_CLK>;
1572 clock-names = "iface",
1577 iommus = <&apps_iommu 4>;
1580 #address-cells = <1>;
1585 mdss_mdp_intf1_out: endpoint {
1586 remote-endpoint = <&mdss_dsi0_in>;
1592 mdss_dsi0: dsi@1a98000 {
1593 compatible = "qcom,msm8916-dsi-ctrl",
1594 "qcom,mdss-dsi-ctrl";
1595 reg = <0x01a98000 0x25c>;
1596 reg-names = "dsi_ctrl";
1598 interrupt-parent = <&mdss>;
1601 assigned-clocks = <&gcc BYTE0_CLK_SRC>,
1602 <&gcc PCLK0_CLK_SRC>;
1603 assigned-clock-parents = <&mdss_dsi0_phy 0>,
1606 clocks = <&gcc GCC_MDSS_MDP_CLK>,
1607 <&gcc GCC_MDSS_AHB_CLK>,
1608 <&gcc GCC_MDSS_AXI_CLK>,
1609 <&gcc GCC_MDSS_BYTE0_CLK>,
1610 <&gcc GCC_MDSS_PCLK0_CLK>,
1611 <&gcc GCC_MDSS_ESC0_CLK>;
1612 clock-names = "mdp_core",
1618 phys = <&mdss_dsi0_phy>;
1620 #address-cells = <1>;
1624 #address-cells = <1>;
1629 mdss_dsi0_in: endpoint {
1630 remote-endpoint = <&mdss_mdp_intf1_out>;
1636 mdss_dsi0_out: endpoint {
1642 mdss_dsi0_phy: phy@1a98300 {
1643 compatible = "qcom,dsi-phy-28nm-lp";
1644 reg = <0x01a98300 0xd4>,
1647 reg-names = "dsi_pll",
1649 "dsi_phy_regulator";
1654 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1656 clock-names = "iface", "ref";
1660 camss: camss@1b0ac00 {
1661 compatible = "qcom,msm8916-camss";
1662 reg = <0x01b0ac00 0x200>,
1670 <0x01b10000 0x1000>;
1671 reg-names = "csiphy0",
1680 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
1681 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
1682 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
1683 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
1684 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
1685 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
1686 interrupt-names = "csiphy0",
1692 power-domains = <&gcc VFE_GDSC>;
1693 clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
1694 <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
1695 <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
1696 <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
1697 <&gcc GCC_CAMSS_CSI0_AHB_CLK>,
1698 <&gcc GCC_CAMSS_CSI0_CLK>,
1699 <&gcc GCC_CAMSS_CSI0PHY_CLK>,
1700 <&gcc GCC_CAMSS_CSI0PIX_CLK>,
1701 <&gcc GCC_CAMSS_CSI0RDI_CLK>,
1702 <&gcc GCC_CAMSS_CSI1_AHB_CLK>,
1703 <&gcc GCC_CAMSS_CSI1_CLK>,
1704 <&gcc GCC_CAMSS_CSI1PHY_CLK>,
1705 <&gcc GCC_CAMSS_CSI1PIX_CLK>,
1706 <&gcc GCC_CAMSS_CSI1RDI_CLK>,
1707 <&gcc GCC_CAMSS_AHB_CLK>,
1708 <&gcc GCC_CAMSS_VFE0_CLK>,
1709 <&gcc GCC_CAMSS_CSI_VFE0_CLK>,
1710 <&gcc GCC_CAMSS_VFE_AHB_CLK>,
1711 <&gcc GCC_CAMSS_VFE_AXI_CLK>;
1712 clock-names = "top_ahb",
1731 iommus = <&apps_iommu 3>;
1732 status = "disabled";
1734 #address-cells = <1>;
1748 compatible = "qcom,msm8916-cci", "qcom,msm8226-cci";
1749 #address-cells = <1>;
1751 reg = <0x01b0c000 0x1000>;
1752 interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
1753 clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
1754 <&gcc GCC_CAMSS_CCI_AHB_CLK>,
1755 <&gcc GCC_CAMSS_CCI_CLK>,
1756 <&gcc GCC_CAMSS_AHB_CLK>;
1757 clock-names = "camss_top_ahb", "cci_ahb",
1759 assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>,
1760 <&gcc GCC_CAMSS_CCI_CLK>;
1761 assigned-clock-rates = <80000000>, <19200000>;
1762 pinctrl-names = "default";
1763 pinctrl-0 = <&cci0_default>;
1764 status = "disabled";
1766 cci_i2c0: i2c-bus@0 {
1768 clock-frequency = <400000>;
1769 #address-cells = <1>;
1775 compatible = "qcom,adreno-306.0", "qcom,adreno";
1776 reg = <0x01c00000 0x20000>;
1777 reg-names = "kgsl_3d0_reg_memory";
1778 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1779 interrupt-names = "kgsl_3d0_irq";
1788 <&gcc GCC_OXILI_GFX3D_CLK>,
1789 <&gcc GCC_OXILI_AHB_CLK>,
1790 <&gcc GCC_OXILI_GMEM_CLK>,
1791 <&gcc GCC_BIMC_GFX_CLK>,
1792 <&gcc GCC_BIMC_GPU_CLK>,
1793 <&gcc GFX3D_CLK_SRC>;
1794 power-domains = <&gcc OXILI_GDSC>;
1795 operating-points-v2 = <&gpu_opp_table>;
1796 iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
1797 status = "disabled";
1799 gpu_opp_table: opp-table {
1800 compatible = "operating-points-v2";
1803 opp-hz = /bits/ 64 <400000000>;
1806 opp-hz = /bits/ 64 <19200000>;
1811 venus: video-codec@1d00000 {
1812 compatible = "qcom,msm8916-venus";
1813 reg = <0x01d00000 0xff000>;
1814 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1815 power-domains = <&gcc VENUS_GDSC>;
1816 clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>,
1817 <&gcc GCC_VENUS0_AHB_CLK>,
1818 <&gcc GCC_VENUS0_AXI_CLK>;
1819 clock-names = "core", "iface", "bus";
1820 iommus = <&apps_iommu 5>;
1821 memory-region = <&venus_mem>;
1822 status = "disabled";
1825 compatible = "venus-decoder";
1829 compatible = "venus-encoder";
1833 apps_iommu: iommu@1ef0000 {
1834 #address-cells = <1>;
1837 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
1838 ranges = <0 0x01e20000 0x20000>;
1839 reg = <0x01ef0000 0x3000>;
1840 clocks = <&gcc GCC_SMMU_CFG_CLK>,
1841 <&gcc GCC_APSS_TCU_CLK>;
1842 clock-names = "iface", "bus";
1843 qcom,iommu-secure-id = <17>;
1847 compatible = "qcom,msm-iommu-v1-sec";
1848 reg = <0x3000 0x1000>;
1849 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1854 compatible = "qcom,msm-iommu-v1-ns";
1855 reg = <0x4000 0x1000>;
1856 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1861 compatible = "qcom,msm-iommu-v1-sec";
1862 reg = <0x5000 0x1000>;
1863 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1867 gpu_iommu: iommu@1f08000 {
1868 #address-cells = <1>;
1871 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
1872 ranges = <0 0x01f08000 0x10000>;
1873 clocks = <&gcc GCC_SMMU_CFG_CLK>,
1874 <&gcc GCC_GFX_TCU_CLK>;
1875 clock-names = "iface", "bus";
1876 qcom,iommu-secure-id = <18>;
1880 compatible = "qcom,msm-iommu-v1-ns";
1881 reg = <0x1000 0x1000>;
1882 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
1887 compatible = "qcom,msm-iommu-v1-ns";
1888 reg = <0x2000 0x1000>;
1889 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
1893 spmi_bus: spmi@200f000 {
1894 compatible = "qcom,spmi-pmic-arb";
1895 reg = <0x0200f000 0x001000>,
1896 <0x02400000 0x400000>,
1897 <0x02c00000 0x400000>,
1898 <0x03800000 0x200000>,
1899 <0x0200a000 0x002100>;
1900 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1901 interrupt-names = "periph_irq";
1902 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1905 #address-cells = <2>;
1907 interrupt-controller;
1908 #interrupt-cells = <4>;
1911 bam_dmux_dma: dma-controller@4044000 {
1912 compatible = "qcom,bam-v1.7.0";
1913 reg = <0x04044000 0x19000>;
1914 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1920 qcom,powered-remotely;
1922 status = "disabled";
1925 mpss: remoteproc@4080000 {
1926 compatible = "qcom,msm8916-mss-pil";
1927 reg = <0x04080000 0x100>,
1930 reg-names = "qdsp6", "rmb";
1932 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
1933 <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1934 <&hexagon_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1935 <&hexagon_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1936 <&hexagon_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1937 interrupt-names = "wdog", "fatal", "ready",
1938 "handover", "stop-ack";
1940 power-domains = <&rpmpd MSM8916_VDDCX>,
1941 <&rpmpd MSM8916_VDDMX>;
1942 power-domain-names = "cx", "mx";
1944 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1945 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
1946 <&gcc GCC_BOOT_ROM_AHB_CLK>,
1948 clock-names = "iface", "bus", "mem", "xo";
1950 qcom,smem-states = <&hexagon_smp2p_out 0>;
1951 qcom,smem-state-names = "stop";
1954 reset-names = "mss_restart";
1956 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
1958 status = "disabled";
1961 memory-region = <&mba_mem>;
1965 memory-region = <&mpss_mem>;
1968 bam_dmux: bam-dmux {
1969 compatible = "qcom,bam-dmux";
1971 interrupt-parent = <&hexagon_smsm>;
1972 interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>;
1973 interrupt-names = "pc", "pc-ack";
1975 qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>;
1976 qcom,smem-state-names = "pc", "pc-ack";
1978 dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>;
1979 dma-names = "tx", "rx";
1981 status = "disabled";
1985 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
1987 qcom,smd-edge = <0>;
1988 qcom,ipc = <&apcs 8 12>;
1989 qcom,remote-pid = <1>;
1994 compatible = "qcom,apr-v2";
1995 qcom,smd-channels = "apr_audio_svc";
1996 qcom,domain = <APR_DOMAIN_ADSP>;
1997 #address-cells = <1>;
1999 status = "disabled";
2002 compatible = "qcom,q6core";
2003 reg = <APR_SVC_ADSP_CORE>;
2007 compatible = "qcom,q6afe";
2008 reg = <APR_SVC_AFE>;
2011 compatible = "qcom,q6afe-dais";
2012 #address-cells = <1>;
2014 #sound-dai-cells = <1>;
2019 compatible = "qcom,q6asm";
2020 reg = <APR_SVC_ASM>;
2023 compatible = "qcom,q6asm-dais";
2024 #address-cells = <1>;
2026 #sound-dai-cells = <1>;
2031 compatible = "qcom,q6adm";
2032 reg = <APR_SVC_ADM>;
2034 q6routing: routing {
2035 compatible = "qcom,q6adm-routing";
2036 #sound-dai-cells = <0>;
2042 compatible = "qcom,fastrpc";
2043 qcom,smd-channels = "fastrpcsmd-apps-dsp";
2045 qcom,non-secure-domain;
2047 #address-cells = <1>;
2051 compatible = "qcom,fastrpc-compute-cb";
2058 sound: sound@7702000 {
2059 status = "disabled";
2060 compatible = "qcom,apq8016-sbc-sndcard";
2061 reg = <0x07702000 0x4>, <0x07702004 0x4>;
2062 reg-names = "mic-iomux", "spkr-iomux";
2065 lpass: audio-controller@7708000 {
2066 status = "disabled";
2067 compatible = "qcom,apq8016-lpass-cpu";
2070 * Note: Unlike the name would suggest, the SEC_I2S_CLK
2071 * is actually only used by Tertiary MI2S while
2072 * Primary/Secondary MI2S both use the PRI_I2S_CLK.
2074 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
2075 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
2076 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
2077 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
2078 <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>,
2079 <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
2080 <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>;
2082 clock-names = "ahbix-clk",
2089 #sound-dai-cells = <1>;
2091 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
2092 interrupt-names = "lpass-irq-lpaif";
2093 reg = <0x07708000 0x10000>;
2094 reg-names = "lpass-lpaif";
2096 #address-cells = <1>;
2100 lpass_codec: audio-codec@771c000 {
2101 compatible = "qcom,msm8916-wcd-digital-codec";
2102 reg = <0x0771c000 0x400>;
2103 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
2104 <&gcc GCC_CODEC_DIGCODEC_CLK>;
2105 clock-names = "ahbix-clk", "mclk";
2106 #sound-dai-cells = <1>;
2107 status = "disabled";
2110 sdhc_1: mmc@7824900 {
2111 compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
2112 reg = <0x07824900 0x11c>, <0x07824000 0x800>;
2113 reg-names = "hc", "core";
2115 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
2116 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
2117 interrupt-names = "hc_irq", "pwr_irq";
2118 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
2119 <&gcc GCC_SDCC1_APPS_CLK>,
2121 clock-names = "iface", "core", "xo";
2122 pinctrl-0 = <&sdc1_default>;
2123 pinctrl-1 = <&sdc1_sleep>;
2124 pinctrl-names = "default", "sleep";
2128 status = "disabled";
2131 sdhc_2: mmc@7864900 {
2132 compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
2133 reg = <0x07864900 0x11c>, <0x07864000 0x800>;
2134 reg-names = "hc", "core";
2136 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
2137 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
2138 interrupt-names = "hc_irq", "pwr_irq";
2139 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2140 <&gcc GCC_SDCC2_APPS_CLK>,
2142 clock-names = "iface", "core", "xo";
2143 pinctrl-0 = <&sdc2_default>;
2144 pinctrl-1 = <&sdc2_sleep>;
2145 pinctrl-names = "default", "sleep";
2147 status = "disabled";
2150 blsp_dma: dma-controller@7884000 {
2151 compatible = "qcom,bam-v1.7.0";
2152 reg = <0x07884000 0x23000>;
2153 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
2154 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
2155 clock-names = "bam_clk";
2160 blsp_uart1: serial@78af000 {
2161 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2162 reg = <0x078af000 0x200>;
2163 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
2164 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
2165 clock-names = "core", "iface";
2166 dmas = <&blsp_dma 0>, <&blsp_dma 1>;
2167 dma-names = "tx", "rx";
2168 pinctrl-names = "default", "sleep";
2169 pinctrl-0 = <&blsp_uart1_default>;
2170 pinctrl-1 = <&blsp_uart1_sleep>;
2171 status = "disabled";
2174 blsp_uart2: serial@78b0000 {
2175 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2176 reg = <0x078b0000 0x200>;
2177 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2178 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
2179 clock-names = "core", "iface";
2180 dmas = <&blsp_dma 2>, <&blsp_dma 3>;
2181 dma-names = "tx", "rx";
2182 pinctrl-names = "default", "sleep";
2183 pinctrl-0 = <&blsp_uart2_default>;
2184 pinctrl-1 = <&blsp_uart2_sleep>;
2185 status = "disabled";
2188 blsp_i2c1: i2c@78b5000 {
2189 compatible = "qcom,i2c-qup-v2.2.1";
2190 reg = <0x078b5000 0x500>;
2191 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
2192 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
2193 <&gcc GCC_BLSP1_AHB_CLK>;
2194 clock-names = "core", "iface";
2195 dmas = <&blsp_dma 4>, <&blsp_dma 5>;
2196 dma-names = "tx", "rx";
2197 pinctrl-names = "default", "sleep";
2198 pinctrl-0 = <&blsp_i2c1_default>;
2199 pinctrl-1 = <&blsp_i2c1_sleep>;
2200 #address-cells = <1>;
2202 status = "disabled";
2205 blsp_spi1: spi@78b5000 {
2206 compatible = "qcom,spi-qup-v2.2.1";
2207 reg = <0x078b5000 0x500>;
2208 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
2209 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
2210 <&gcc GCC_BLSP1_AHB_CLK>;
2211 clock-names = "core", "iface";
2212 dmas = <&blsp_dma 4>, <&blsp_dma 5>;
2213 dma-names = "tx", "rx";
2214 pinctrl-names = "default", "sleep";
2215 pinctrl-0 = <&blsp_spi1_default>;
2216 pinctrl-1 = <&blsp_spi1_sleep>;
2217 #address-cells = <1>;
2219 status = "disabled";
2222 blsp_i2c2: i2c@78b6000 {
2223 compatible = "qcom,i2c-qup-v2.2.1";
2224 reg = <0x078b6000 0x500>;
2225 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
2226 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
2227 <&gcc GCC_BLSP1_AHB_CLK>;
2228 clock-names = "core", "iface";
2229 dmas = <&blsp_dma 6>, <&blsp_dma 7>;
2230 dma-names = "tx", "rx";
2231 pinctrl-names = "default", "sleep";
2232 pinctrl-0 = <&blsp_i2c2_default>;
2233 pinctrl-1 = <&blsp_i2c2_sleep>;
2234 #address-cells = <1>;
2236 status = "disabled";
2239 blsp_spi2: spi@78b6000 {
2240 compatible = "qcom,spi-qup-v2.2.1";
2241 reg = <0x078b6000 0x500>;
2242 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
2243 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
2244 <&gcc GCC_BLSP1_AHB_CLK>;
2245 clock-names = "core", "iface";
2246 dmas = <&blsp_dma 6>, <&blsp_dma 7>;
2247 dma-names = "tx", "rx";
2248 pinctrl-names = "default", "sleep";
2249 pinctrl-0 = <&blsp_spi2_default>;
2250 pinctrl-1 = <&blsp_spi2_sleep>;
2251 #address-cells = <1>;
2253 status = "disabled";
2256 blsp_i2c3: i2c@78b7000 {
2257 compatible = "qcom,i2c-qup-v2.2.1";
2258 reg = <0x078b7000 0x500>;
2259 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
2260 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
2261 <&gcc GCC_BLSP1_AHB_CLK>;
2262 clock-names = "core", "iface";
2263 dmas = <&blsp_dma 8>, <&blsp_dma 9>;
2264 dma-names = "tx", "rx";
2265 pinctrl-names = "default", "sleep";
2266 pinctrl-0 = <&blsp_i2c3_default>;
2267 pinctrl-1 = <&blsp_i2c3_sleep>;
2268 #address-cells = <1>;
2270 status = "disabled";
2273 blsp_spi3: spi@78b7000 {
2274 compatible = "qcom,spi-qup-v2.2.1";
2275 reg = <0x078b7000 0x500>;
2276 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
2277 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
2278 <&gcc GCC_BLSP1_AHB_CLK>;
2279 clock-names = "core", "iface";
2280 dmas = <&blsp_dma 8>, <&blsp_dma 9>;
2281 dma-names = "tx", "rx";
2282 pinctrl-names = "default", "sleep";
2283 pinctrl-0 = <&blsp_spi3_default>;
2284 pinctrl-1 = <&blsp_spi3_sleep>;
2285 #address-cells = <1>;
2287 status = "disabled";
2290 blsp_i2c4: i2c@78b8000 {
2291 compatible = "qcom,i2c-qup-v2.2.1";
2292 reg = <0x078b8000 0x500>;
2293 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
2294 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
2295 <&gcc GCC_BLSP1_AHB_CLK>;
2296 clock-names = "core", "iface";
2297 dmas = <&blsp_dma 10>, <&blsp_dma 11>;
2298 dma-names = "tx", "rx";
2299 pinctrl-names = "default", "sleep";
2300 pinctrl-0 = <&blsp_i2c4_default>;
2301 pinctrl-1 = <&blsp_i2c4_sleep>;
2302 #address-cells = <1>;
2304 status = "disabled";
2307 blsp_spi4: spi@78b8000 {
2308 compatible = "qcom,spi-qup-v2.2.1";
2309 reg = <0x078b8000 0x500>;
2310 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
2311 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
2312 <&gcc GCC_BLSP1_AHB_CLK>;
2313 clock-names = "core", "iface";
2314 dmas = <&blsp_dma 10>, <&blsp_dma 11>;
2315 dma-names = "tx", "rx";
2316 pinctrl-names = "default", "sleep";
2317 pinctrl-0 = <&blsp_spi4_default>;
2318 pinctrl-1 = <&blsp_spi4_sleep>;
2319 #address-cells = <1>;
2321 status = "disabled";
2324 blsp_i2c5: i2c@78b9000 {
2325 compatible = "qcom,i2c-qup-v2.2.1";
2326 reg = <0x078b9000 0x500>;
2327 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
2328 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
2329 <&gcc GCC_BLSP1_AHB_CLK>;
2330 clock-names = "core", "iface";
2331 dmas = <&blsp_dma 12>, <&blsp_dma 13>;
2332 dma-names = "tx", "rx";
2333 pinctrl-names = "default", "sleep";
2334 pinctrl-0 = <&blsp_i2c5_default>;
2335 pinctrl-1 = <&blsp_i2c5_sleep>;
2336 #address-cells = <1>;
2338 status = "disabled";
2341 blsp_spi5: spi@78b9000 {
2342 compatible = "qcom,spi-qup-v2.2.1";
2343 reg = <0x078b9000 0x500>;
2344 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
2345 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
2346 <&gcc GCC_BLSP1_AHB_CLK>;
2347 clock-names = "core", "iface";
2348 dmas = <&blsp_dma 12>, <&blsp_dma 13>;
2349 dma-names = "tx", "rx";
2350 pinctrl-names = "default", "sleep";
2351 pinctrl-0 = <&blsp_spi5_default>;
2352 pinctrl-1 = <&blsp_spi5_sleep>;
2353 #address-cells = <1>;
2355 status = "disabled";
2358 blsp_i2c6: i2c@78ba000 {
2359 compatible = "qcom,i2c-qup-v2.2.1";
2360 reg = <0x078ba000 0x500>;
2361 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
2362 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
2363 <&gcc GCC_BLSP1_AHB_CLK>;
2364 clock-names = "core", "iface";
2365 dmas = <&blsp_dma 14>, <&blsp_dma 15>;
2366 dma-names = "tx", "rx";
2367 pinctrl-names = "default", "sleep";
2368 pinctrl-0 = <&blsp_i2c6_default>;
2369 pinctrl-1 = <&blsp_i2c6_sleep>;
2370 #address-cells = <1>;
2372 status = "disabled";
2375 blsp_spi6: spi@78ba000 {
2376 compatible = "qcom,spi-qup-v2.2.1";
2377 reg = <0x078ba000 0x500>;
2378 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
2379 clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
2380 <&gcc GCC_BLSP1_AHB_CLK>;
2381 clock-names = "core", "iface";
2382 dmas = <&blsp_dma 14>, <&blsp_dma 15>;
2383 dma-names = "tx", "rx";
2384 pinctrl-names = "default", "sleep";
2385 pinctrl-0 = <&blsp_spi6_default>;
2386 pinctrl-1 = <&blsp_spi6_sleep>;
2387 #address-cells = <1>;
2389 status = "disabled";
2393 compatible = "qcom,ci-hdrc";
2394 reg = <0x078d9000 0x200>,
2396 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
2397 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
2398 clocks = <&gcc GCC_USB_HS_AHB_CLK>,
2399 <&gcc GCC_USB_HS_SYSTEM_CLK>;
2400 clock-names = "iface", "core";
2401 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
2402 assigned-clock-rates = <80000000>;
2403 resets = <&gcc GCC_USB_HS_BCR>;
2404 reset-names = "core";
2410 ahb-burst-config = <0>;
2411 phy-names = "usb-phy";
2412 phys = <&usb_hs_phy>;
2413 status = "disabled";
2418 compatible = "qcom,usb-hs-phy-msm8916",
2421 clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
2422 clock-names = "ref", "sleep";
2423 resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
2424 reset-names = "phy", "por";
2425 qcom,init-seq = /bits/ 8 <0x0 0x44>,
2433 wcnss: remoteproc@a204000 {
2434 compatible = "qcom,pronto-v2-pil", "qcom,pronto";
2435 reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>;
2436 reg-names = "ccu", "dxe", "pmu";
2438 memory-region = <&wcnss_mem>;
2440 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
2441 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2442 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2443 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2444 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2445 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
2447 power-domains = <&rpmpd MSM8916_VDDCX>,
2448 <&rpmpd MSM8916_VDDMX>;
2449 power-domain-names = "cx", "mx";
2451 qcom,smem-states = <&wcnss_smp2p_out 0>;
2452 qcom,smem-state-names = "stop";
2454 pinctrl-names = "default";
2455 pinctrl-0 = <&wcss_wlan_default>;
2457 status = "disabled";
2460 /* Separate chip, compatible is board-specific */
2461 clocks = <&rpmcc RPM_SMD_RF_CLK2>;
2466 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
2468 qcom,ipc = <&apcs 8 17>;
2469 qcom,smd-edge = <6>;
2470 qcom,remote-pid = <4>;
2475 compatible = "qcom,wcnss";
2476 qcom,smd-channels = "WCNSS_CTRL";
2478 qcom,mmio = <&wcnss>;
2480 wcnss_bt: bluetooth {
2481 compatible = "qcom,wcnss-bt";
2485 compatible = "qcom,wcnss-wlan";
2487 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
2488 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
2489 interrupt-names = "tx", "rx";
2491 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
2492 qcom,smem-state-names = "tx-enable", "tx-rings-empty";
2498 intc: interrupt-controller@b000000 {
2499 compatible = "qcom,msm-qgic2";
2500 interrupt-controller;
2501 #interrupt-cells = <3>;
2502 reg = <0x0b000000 0x1000>, <0x0b002000 0x2000>,
2503 <0x0b001000 0x1000>, <0x0b004000 0x2000>;
2504 interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
2507 apcs: mailbox@b011000 {
2508 compatible = "qcom,msm8916-apcs-kpss-global", "syscon";
2509 reg = <0x0b011000 0x1000>;
2511 clocks = <&a53pll>, <&gcc GPLL0_VOTE>;
2512 clock-names = "pll", "aux";
2516 a53pll: clock@b016000 {
2517 compatible = "qcom,msm8916-a53pll";
2518 reg = <0x0b016000 0x40>;
2520 clocks = <&xo_board>;
2525 #address-cells = <1>;
2528 compatible = "arm,armv7-timer-mem";
2529 reg = <0x0b020000 0x1000>;
2530 clock-frequency = <19200000>;
2534 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
2535 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
2536 reg = <0x0b021000 0x1000>,
2537 <0x0b022000 0x1000>;
2542 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
2543 reg = <0x0b023000 0x1000>;
2544 status = "disabled";
2549 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
2550 reg = <0x0b024000 0x1000>;
2551 status = "disabled";
2556 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
2557 reg = <0x0b025000 0x1000>;
2558 status = "disabled";
2563 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
2564 reg = <0x0b026000 0x1000>;
2565 status = "disabled";
2570 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
2571 reg = <0x0b027000 0x1000>;
2572 status = "disabled";
2577 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
2578 reg = <0x0b028000 0x1000>;
2579 status = "disabled";
2583 cpu0_acc: power-manager@b088000 {
2584 compatible = "qcom,msm8916-acc";
2585 reg = <0x0b088000 0x1000>;
2586 status = "reserved"; /* Controlled by PSCI firmware */
2589 cpu0_saw: power-manager@b089000 {
2590 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
2591 reg = <0x0b089000 0x1000>;
2592 status = "reserved"; /* Controlled by PSCI firmware */
2595 cpu1_acc: power-manager@b098000 {
2596 compatible = "qcom,msm8916-acc";
2597 reg = <0x0b098000 0x1000>;
2598 status = "reserved"; /* Controlled by PSCI firmware */
2601 cpu1_saw: power-manager@b099000 {
2602 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
2603 reg = <0x0b099000 0x1000>;
2604 status = "reserved"; /* Controlled by PSCI firmware */
2607 cpu2_acc: power-manager@b0a8000 {
2608 compatible = "qcom,msm8916-acc";
2609 reg = <0x0b0a8000 0x1000>;
2610 status = "reserved"; /* Controlled by PSCI firmware */
2613 cpu2_saw: power-manager@b0a9000 {
2614 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
2615 reg = <0x0b0a9000 0x1000>;
2616 status = "reserved"; /* Controlled by PSCI firmware */
2619 cpu3_acc: power-manager@b0b8000 {
2620 compatible = "qcom,msm8916-acc";
2621 reg = <0x0b0b8000 0x1000>;
2622 status = "reserved"; /* Controlled by PSCI firmware */
2625 cpu3_saw: power-manager@b0b9000 {
2626 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
2627 reg = <0x0b0b9000 0x1000>;
2628 status = "reserved"; /* Controlled by PSCI firmware */
2634 polling-delay-passive = <250>;
2635 polling-delay = <1000>;
2637 thermal-sensors = <&tsens 5>;
2640 cpu0_1_alert0: trip-point0 {
2641 temperature = <75000>;
2642 hysteresis = <2000>;
2645 cpu0_1_crit: cpu-crit {
2646 temperature = <110000>;
2647 hysteresis = <2000>;
2654 trip = <&cpu0_1_alert0>;
2655 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2656 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2657 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2658 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2664 polling-delay-passive = <250>;
2665 polling-delay = <1000>;
2667 thermal-sensors = <&tsens 4>;
2670 cpu2_3_alert0: trip-point0 {
2671 temperature = <75000>;
2672 hysteresis = <2000>;
2675 cpu2_3_crit: cpu-crit {
2676 temperature = <110000>;
2677 hysteresis = <2000>;
2684 trip = <&cpu2_3_alert0>;
2685 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2686 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2687 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2688 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2694 polling-delay-passive = <250>;
2695 polling-delay = <1000>;
2697 thermal-sensors = <&tsens 2>;
2700 gpu_alert0: trip-point0 {
2701 temperature = <75000>;
2702 hysteresis = <2000>;
2705 gpu_crit: gpu-crit {
2706 temperature = <95000>;
2707 hysteresis = <2000>;
2714 polling-delay-passive = <250>;
2715 polling-delay = <1000>;
2717 thermal-sensors = <&tsens 1>;
2720 cam_alert0: trip-point0 {
2721 temperature = <75000>;
2722 hysteresis = <2000>;
2729 polling-delay-passive = <250>;
2730 polling-delay = <1000>;
2732 thermal-sensors = <&tsens 0>;
2735 modem_alert0: trip-point0 {
2736 temperature = <85000>;
2737 hysteresis = <2000>;
2745 compatible = "arm,armv8-timer";
2746 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2747 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2748 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2749 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;