1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
6 #include <dt-bindings/arm/coresight-cti-dt.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/interconnect/qcom,msm8916.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/power/qcom-rpmpd.h>
12 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
13 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&intc>;
22 mmc0 = &sdhc_1; /* SDC1 eMMC slot */
23 mmc1 = &sdhc_2; /* SDC2 SD card slot */
29 device_type = "memory";
30 /* We expect the bootloader to fill in the reg */
31 reg = <0 0x80000000 0 0>;
40 reg = <0x0 0x86000000 0x0 0x300000>;
45 compatible = "qcom,smem";
46 reg = <0x0 0x86300000 0x0 0x100000>;
49 hwlocks = <&tcsr_mutex 3>;
50 qcom,rpm-msg-ram = <&rpm_msg_ram>;
54 reg = <0x0 0x86400000 0x0 0x100000>;
59 reg = <0x0 0x86500000 0x0 0x180000>;
64 reg = <0x0 0x86680000 0x0 0x80000>;
69 compatible = "qcom,rmtfs-mem";
70 reg = <0x0 0x86700000 0x0 0xe0000>;
77 reg = <0x0 0x867e0000 0x0 0x20000>;
81 mpss_mem: mpss@86800000 {
82 reg = <0x0 0x86800000 0x0 0x2b00000>;
86 wcnss_mem: wcnss@89300000 {
87 reg = <0x0 0x89300000 0x0 0x600000>;
91 venus_mem: venus@89900000 {
92 reg = <0x0 0x89900000 0x0 0x600000>;
96 mba_mem: mba@8ea00000 {
98 reg = <0 0x8ea00000 0 0x100000>;
104 compatible = "fixed-clock";
106 clock-frequency = <19200000>;
109 sleep_clk: sleep-clk {
110 compatible = "fixed-clock";
112 clock-frequency = <32768>;
117 #address-cells = <1>;
122 compatible = "arm,cortex-a53";
124 next-level-cache = <&L2_0>;
125 enable-method = "psci";
127 operating-points-v2 = <&cpu_opp_table>;
128 #cooling-cells = <2>;
129 power-domains = <&CPU_PD0>;
130 power-domain-names = "psci";
131 qcom,acc = <&cpu0_acc>;
132 qcom,saw = <&cpu0_saw>;
137 compatible = "arm,cortex-a53";
139 next-level-cache = <&L2_0>;
140 enable-method = "psci";
142 operating-points-v2 = <&cpu_opp_table>;
143 #cooling-cells = <2>;
144 power-domains = <&CPU_PD1>;
145 power-domain-names = "psci";
146 qcom,acc = <&cpu1_acc>;
147 qcom,saw = <&cpu1_saw>;
152 compatible = "arm,cortex-a53";
154 next-level-cache = <&L2_0>;
155 enable-method = "psci";
157 operating-points-v2 = <&cpu_opp_table>;
158 #cooling-cells = <2>;
159 power-domains = <&CPU_PD2>;
160 power-domain-names = "psci";
161 qcom,acc = <&cpu2_acc>;
162 qcom,saw = <&cpu2_saw>;
167 compatible = "arm,cortex-a53";
169 next-level-cache = <&L2_0>;
170 enable-method = "psci";
172 operating-points-v2 = <&cpu_opp_table>;
173 #cooling-cells = <2>;
174 power-domains = <&CPU_PD3>;
175 power-domain-names = "psci";
176 qcom,acc = <&cpu3_acc>;
177 qcom,saw = <&cpu3_saw>;
181 compatible = "cache";
187 entry-method = "psci";
189 CPU_SLEEP_0: cpu-sleep-0 {
190 compatible = "arm,idle-state";
191 idle-state-name = "standalone-power-collapse";
192 arm,psci-suspend-param = <0x40000002>;
193 entry-latency-us = <130>;
194 exit-latency-us = <150>;
195 min-residency-us = <2000>;
202 CLUSTER_RET: cluster-retention {
203 compatible = "domain-idle-state";
204 arm,psci-suspend-param = <0x41000012>;
205 entry-latency-us = <500>;
206 exit-latency-us = <500>;
207 min-residency-us = <2000>;
210 CLUSTER_PWRDN: cluster-gdhs {
211 compatible = "domain-idle-state";
212 arm,psci-suspend-param = <0x41000032>;
213 entry-latency-us = <2000>;
214 exit-latency-us = <2000>;
215 min-residency-us = <6000>;
220 cpu_opp_table: opp-table-cpu {
221 compatible = "operating-points-v2";
225 opp-hz = /bits/ 64 <200000000>;
228 opp-hz = /bits/ 64 <400000000>;
231 opp-hz = /bits/ 64 <800000000>;
234 opp-hz = /bits/ 64 <998400000>;
240 compatible = "qcom,scm-msm8916", "qcom,scm";
241 clocks = <&gcc GCC_CRYPTO_CLK>,
242 <&gcc GCC_CRYPTO_AXI_CLK>,
243 <&gcc GCC_CRYPTO_AHB_CLK>;
244 clock-names = "core", "bus", "iface";
247 qcom,dload-mode = <&tcsr 0x6100>;
252 compatible = "arm,cortex-a53-pmu";
253 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
257 compatible = "arm,psci-1.0";
260 CPU_PD0: power-domain-cpu0 {
261 #power-domain-cells = <0>;
262 power-domains = <&CLUSTER_PD>;
263 domain-idle-states = <&CPU_SLEEP_0>;
266 CPU_PD1: power-domain-cpu1 {
267 #power-domain-cells = <0>;
268 power-domains = <&CLUSTER_PD>;
269 domain-idle-states = <&CPU_SLEEP_0>;
272 CPU_PD2: power-domain-cpu2 {
273 #power-domain-cells = <0>;
274 power-domains = <&CLUSTER_PD>;
275 domain-idle-states = <&CPU_SLEEP_0>;
278 CPU_PD3: power-domain-cpu3 {
279 #power-domain-cells = <0>;
280 power-domains = <&CLUSTER_PD>;
281 domain-idle-states = <&CPU_SLEEP_0>;
284 CLUSTER_PD: power-domain-cluster {
285 #power-domain-cells = <0>;
286 domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>;
291 compatible = "qcom,smd";
294 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
295 qcom,ipc = <&apcs 8 0>;
296 qcom,smd-edge = <15>;
298 rpm_requests: rpm-requests {
299 compatible = "qcom,rpm-msm8916";
300 qcom,smd-channels = "rpm_requests";
302 rpmcc: clock-controller {
303 compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc";
305 clocks = <&xo_board>;
309 rpmpd: power-controller {
310 compatible = "qcom,msm8916-rpmpd";
311 #power-domain-cells = <1>;
312 operating-points-v2 = <&rpmpd_opp_table>;
314 rpmpd_opp_table: opp-table {
315 compatible = "operating-points-v2";
317 rpmpd_opp_ret: opp1 {
320 rpmpd_opp_svs_krait: opp2 {
323 rpmpd_opp_svs_soc: opp3 {
326 rpmpd_opp_nom: opp4 {
329 rpmpd_opp_turbo: opp5 {
332 rpmpd_opp_super_turbo: opp6 {
342 compatible = "qcom,smp2p";
343 qcom,smem = <435>, <428>;
345 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
347 qcom,ipc = <&apcs 8 14>;
349 qcom,local-pid = <0>;
350 qcom,remote-pid = <1>;
352 hexagon_smp2p_out: master-kernel {
353 qcom,entry-name = "master-kernel";
355 #qcom,smem-state-cells = <1>;
358 hexagon_smp2p_in: slave-kernel {
359 qcom,entry-name = "slave-kernel";
361 interrupt-controller;
362 #interrupt-cells = <2>;
367 compatible = "qcom,smp2p";
368 qcom,smem = <451>, <431>;
370 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
372 qcom,ipc = <&apcs 8 18>;
374 qcom,local-pid = <0>;
375 qcom,remote-pid = <4>;
377 wcnss_smp2p_out: master-kernel {
378 qcom,entry-name = "master-kernel";
380 #qcom,smem-state-cells = <1>;
383 wcnss_smp2p_in: slave-kernel {
384 qcom,entry-name = "slave-kernel";
386 interrupt-controller;
387 #interrupt-cells = <2>;
392 compatible = "qcom,smsm";
394 #address-cells = <1>;
397 qcom,ipc-1 = <&apcs 8 13>;
398 qcom,ipc-3 = <&apcs 8 19>;
403 #qcom,smem-state-cells = <1>;
406 hexagon_smsm: hexagon@1 {
408 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
410 interrupt-controller;
411 #interrupt-cells = <2>;
414 wcnss_smsm: wcnss@6 {
416 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
418 interrupt-controller;
419 #interrupt-cells = <2>;
424 #address-cells = <1>;
426 ranges = <0 0 0 0xffffffff>;
427 compatible = "simple-bus";
430 compatible = "qcom,prng";
431 reg = <0x00022000 0x200>;
432 clocks = <&gcc GCC_PRNG_AHB_CLK>;
433 clock-names = "core";
437 compatible = "qcom,pshold";
438 reg = <0x004ab000 0x4>;
441 qfprom: qfprom@5c000 {
442 compatible = "qcom,msm8916-qfprom", "qcom,qfprom";
443 reg = <0x0005c000 0x1000>;
444 #address-cells = <1>;
447 tsens_base1: base1@d0 {
452 tsens_s0_p1: s0-p1@d0 {
457 tsens_s0_p2: s0-p2@d1 {
462 tsens_s1_p1: s1-p1@d2 {
466 tsens_s1_p2: s1-p2@d2 {
470 tsens_s2_p1: s2-p1@d3 {
475 tsens_s2_p2: s2-p2@d4 {
480 // no tsens with hw_id 3
482 tsens_s4_p1: s4-p1@d4 {
487 tsens_s4_p2: s4-p2@d5 {
492 tsens_s5_p1: s5-p1@d5 {
497 tsens_s5_p2: s5-p2@d6 {
502 tsens_base2: base2@d7 {
507 tsens_mode: mode@ef {
513 rpm_msg_ram: sram@60000 {
514 compatible = "qcom,rpm-msg-ram";
515 reg = <0x00060000 0x8000>;
519 compatible = "qcom,msm8916-rpm-stats";
520 reg = <0x00290000 0x10000>;
523 bimc: interconnect@400000 {
524 compatible = "qcom,msm8916-bimc";
525 reg = <0x00400000 0x62000>;
526 #interconnect-cells = <1>;
527 clock-names = "bus", "bus_a";
528 clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
529 <&rpmcc RPM_SMD_BIMC_A_CLK>;
532 tsens: thermal-sensor@4a9000 {
533 compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1";
534 reg = <0x004a9000 0x1000>, /* TM */
535 <0x004a8000 0x1000>; /* SROT */
538 nvmem-cells = <&tsens_mode>,
539 <&tsens_base1>, <&tsens_base2>,
540 <&tsens_s0_p1>, <&tsens_s0_p2>,
541 <&tsens_s1_p1>, <&tsens_s1_p2>,
542 <&tsens_s2_p1>, <&tsens_s2_p2>,
543 <&tsens_s4_p1>, <&tsens_s4_p2>,
544 <&tsens_s5_p1>, <&tsens_s5_p2>;
545 nvmem-cell-names = "mode",
553 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
554 interrupt-names = "uplow";
555 #thermal-sensor-cells = <1>;
558 pcnoc: interconnect@500000 {
559 compatible = "qcom,msm8916-pcnoc";
560 reg = <0x00500000 0x11000>;
561 #interconnect-cells = <1>;
562 clock-names = "bus", "bus_a";
563 clocks = <&rpmcc RPM_SMD_PCNOC_CLK>,
564 <&rpmcc RPM_SMD_PCNOC_A_CLK>;
567 snoc: interconnect@580000 {
568 compatible = "qcom,msm8916-snoc";
569 reg = <0x00580000 0x14000>;
570 #interconnect-cells = <1>;
571 clock-names = "bus", "bus_a";
572 clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
573 <&rpmcc RPM_SMD_SNOC_A_CLK>;
577 compatible = "arm,coresight-stm", "arm,primecell";
578 reg = <0x00802000 0x1000>,
579 <0x09280000 0x180000>;
580 reg-names = "stm-base", "stm-stimulus-base";
582 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
583 clock-names = "apb_pclk", "atclk";
590 remote-endpoint = <&funnel0_in7>;
597 /* CTI 0 - TMC connections */
599 compatible = "arm,coresight-cti", "arm,primecell";
600 reg = <0x00810000 0x1000>;
602 clocks = <&rpmcc RPM_QDSS_CLK>;
603 clock-names = "apb_pclk";
608 /* CTI 1 - TPIU connections */
610 compatible = "arm,coresight-cti", "arm,primecell";
611 reg = <0x00811000 0x1000>;
613 clocks = <&rpmcc RPM_QDSS_CLK>;
614 clock-names = "apb_pclk";
619 /* CTIs 2-11 - no information - not instantiated */
622 compatible = "arm,coresight-tpiu", "arm,primecell";
623 reg = <0x00820000 0x1000>;
625 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
626 clock-names = "apb_pclk", "atclk";
633 remote-endpoint = <&replicator_out1>;
639 funnel0: funnel@821000 {
640 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
641 reg = <0x00821000 0x1000>;
643 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
644 clock-names = "apb_pclk", "atclk";
649 #address-cells = <1>;
653 * Not described input ports:
654 * 0 - connected to Resource and Power Manger CPU ETM
656 * 2 - connected to Modem CPU ETM
659 * 6 - connected trought funnel to Wireless CPU ETM
660 * 7 - connected to STM component
665 funnel0_in4: endpoint {
666 remote-endpoint = <&funnel1_out>;
672 funnel0_in7: endpoint {
673 remote-endpoint = <&stm_out>;
680 funnel0_out: endpoint {
681 remote-endpoint = <&etf_in>;
687 replicator: replicator@824000 {
688 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
689 reg = <0x00824000 0x1000>;
691 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
692 clock-names = "apb_pclk", "atclk";
697 #address-cells = <1>;
702 replicator_out0: endpoint {
703 remote-endpoint = <&etr_in>;
708 replicator_out1: endpoint {
709 remote-endpoint = <&tpiu_in>;
716 replicator_in: endpoint {
717 remote-endpoint = <&etf_out>;
724 compatible = "arm,coresight-tmc", "arm,primecell";
725 reg = <0x00825000 0x1000>;
727 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
728 clock-names = "apb_pclk", "atclk";
735 remote-endpoint = <&funnel0_out>;
743 remote-endpoint = <&replicator_in>;
750 compatible = "arm,coresight-tmc", "arm,primecell";
751 reg = <0x00826000 0x1000>;
753 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
754 clock-names = "apb_pclk", "atclk";
761 remote-endpoint = <&replicator_out0>;
767 funnel1: funnel@841000 { /* APSS funnel only 4 inputs are used */
768 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
769 reg = <0x00841000 0x1000>;
771 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
772 clock-names = "apb_pclk", "atclk";
777 #address-cells = <1>;
782 funnel1_in0: endpoint {
783 remote-endpoint = <&etm0_out>;
788 funnel1_in1: endpoint {
789 remote-endpoint = <&etm1_out>;
794 funnel1_in2: endpoint {
795 remote-endpoint = <&etm2_out>;
800 funnel1_in3: endpoint {
801 remote-endpoint = <&etm3_out>;
808 funnel1_out: endpoint {
809 remote-endpoint = <&funnel0_in4>;
815 debug0: debug@850000 {
816 compatible = "arm,coresight-cpu-debug", "arm,primecell";
817 reg = <0x00850000 0x1000>;
818 clocks = <&rpmcc RPM_QDSS_CLK>;
819 clock-names = "apb_pclk";
824 debug1: debug@852000 {
825 compatible = "arm,coresight-cpu-debug", "arm,primecell";
826 reg = <0x00852000 0x1000>;
827 clocks = <&rpmcc RPM_QDSS_CLK>;
828 clock-names = "apb_pclk";
833 debug2: debug@854000 {
834 compatible = "arm,coresight-cpu-debug", "arm,primecell";
835 reg = <0x00854000 0x1000>;
836 clocks = <&rpmcc RPM_QDSS_CLK>;
837 clock-names = "apb_pclk";
842 debug3: debug@856000 {
843 compatible = "arm,coresight-cpu-debug", "arm,primecell";
844 reg = <0x00856000 0x1000>;
845 clocks = <&rpmcc RPM_QDSS_CLK>;
846 clock-names = "apb_pclk";
851 /* Core CTIs; CTIs 12-15 */
854 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
856 reg = <0x00858000 0x1000>;
858 clocks = <&rpmcc RPM_QDSS_CLK>;
859 clock-names = "apb_pclk";
862 arm,cs-dev-assoc = <&etm0>;
869 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
871 reg = <0x00859000 0x1000>;
873 clocks = <&rpmcc RPM_QDSS_CLK>;
874 clock-names = "apb_pclk";
877 arm,cs-dev-assoc = <&etm1>;
884 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
886 reg = <0x0085a000 0x1000>;
888 clocks = <&rpmcc RPM_QDSS_CLK>;
889 clock-names = "apb_pclk";
892 arm,cs-dev-assoc = <&etm2>;
899 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
901 reg = <0x0085b000 0x1000>;
903 clocks = <&rpmcc RPM_QDSS_CLK>;
904 clock-names = "apb_pclk";
907 arm,cs-dev-assoc = <&etm3>;
913 compatible = "arm,coresight-etm4x", "arm,primecell";
914 reg = <0x0085c000 0x1000>;
916 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
917 clock-names = "apb_pclk", "atclk";
918 arm,coresight-loses-context-with-cpu;
927 remote-endpoint = <&funnel1_in0>;
934 compatible = "arm,coresight-etm4x", "arm,primecell";
935 reg = <0x0085d000 0x1000>;
937 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
938 clock-names = "apb_pclk", "atclk";
939 arm,coresight-loses-context-with-cpu;
948 remote-endpoint = <&funnel1_in1>;
955 compatible = "arm,coresight-etm4x", "arm,primecell";
956 reg = <0x0085e000 0x1000>;
958 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
959 clock-names = "apb_pclk", "atclk";
960 arm,coresight-loses-context-with-cpu;
969 remote-endpoint = <&funnel1_in2>;
976 compatible = "arm,coresight-etm4x", "arm,primecell";
977 reg = <0x0085f000 0x1000>;
979 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
980 clock-names = "apb_pclk", "atclk";
981 arm,coresight-loses-context-with-cpu;
990 remote-endpoint = <&funnel1_in3>;
996 msmgpio: pinctrl@1000000 {
997 compatible = "qcom,msm8916-pinctrl";
998 reg = <0x01000000 0x300000>;
999 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1001 gpio-ranges = <&msmgpio 0 0 122>;
1003 interrupt-controller;
1004 #interrupt-cells = <2>;
1007 gcc: clock-controller@1800000 {
1008 compatible = "qcom,gcc-msm8916";
1011 #power-domain-cells = <1>;
1012 reg = <0x01800000 0x80000>;
1013 clocks = <&xo_board>,
1029 tcsr_mutex: hwlock@1905000 {
1030 compatible = "qcom,tcsr-mutex";
1031 reg = <0x01905000 0x20000>;
1032 #hwlock-cells = <1>;
1035 tcsr: syscon@1937000 {
1036 compatible = "qcom,tcsr-msm8916", "syscon";
1037 reg = <0x01937000 0x30000>;
1040 mdss: display-subsystem@1a00000 {
1041 status = "disabled";
1042 compatible = "qcom,mdss";
1043 reg = <0x01a00000 0x1000>,
1044 <0x01ac8000 0x3000>;
1045 reg-names = "mdss_phys", "vbif_phys";
1047 power-domains = <&gcc MDSS_GDSC>;
1049 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1050 <&gcc GCC_MDSS_AXI_CLK>,
1051 <&gcc GCC_MDSS_VSYNC_CLK>;
1052 clock-names = "iface",
1056 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1058 interrupt-controller;
1059 #interrupt-cells = <1>;
1061 #address-cells = <1>;
1065 mdp: display-controller@1a01000 {
1066 compatible = "qcom,msm8916-mdp5", "qcom,mdp5";
1067 reg = <0x01a01000 0x89000>;
1068 reg-names = "mdp_phys";
1070 interrupt-parent = <&mdss>;
1073 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1074 <&gcc GCC_MDSS_AXI_CLK>,
1075 <&gcc GCC_MDSS_MDP_CLK>,
1076 <&gcc GCC_MDSS_VSYNC_CLK>;
1077 clock-names = "iface",
1082 iommus = <&apps_iommu 4>;
1085 #address-cells = <1>;
1090 mdp5_intf1_out: endpoint {
1091 remote-endpoint = <&dsi0_in>;
1098 compatible = "qcom,msm8916-dsi-ctrl",
1099 "qcom,mdss-dsi-ctrl";
1100 reg = <0x01a98000 0x25c>;
1101 reg-names = "dsi_ctrl";
1103 interrupt-parent = <&mdss>;
1106 assigned-clocks = <&gcc BYTE0_CLK_SRC>,
1107 <&gcc PCLK0_CLK_SRC>;
1108 assigned-clock-parents = <&dsi_phy0 0>,
1111 clocks = <&gcc GCC_MDSS_MDP_CLK>,
1112 <&gcc GCC_MDSS_AHB_CLK>,
1113 <&gcc GCC_MDSS_AXI_CLK>,
1114 <&gcc GCC_MDSS_BYTE0_CLK>,
1115 <&gcc GCC_MDSS_PCLK0_CLK>,
1116 <&gcc GCC_MDSS_ESC0_CLK>;
1117 clock-names = "mdp_core",
1125 #address-cells = <1>;
1129 #address-cells = <1>;
1135 remote-endpoint = <&mdp5_intf1_out>;
1141 dsi0_out: endpoint {
1147 dsi_phy0: phy@1a98300 {
1148 compatible = "qcom,dsi-phy-28nm-lp";
1149 reg = <0x01a98300 0xd4>,
1152 reg-names = "dsi_pll",
1154 "dsi_phy_regulator";
1159 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1161 clock-names = "iface", "ref";
1165 camss: camss@1b00000 {
1166 compatible = "qcom,msm8916-camss";
1167 reg = <0x01b0ac00 0x200>,
1175 <0x01b10000 0x1000>;
1176 reg-names = "csiphy0",
1185 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
1186 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
1187 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
1188 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
1189 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
1190 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
1191 interrupt-names = "csiphy0",
1197 power-domains = <&gcc VFE_GDSC>;
1198 clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
1199 <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
1200 <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
1201 <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
1202 <&gcc GCC_CAMSS_CSI0_AHB_CLK>,
1203 <&gcc GCC_CAMSS_CSI0_CLK>,
1204 <&gcc GCC_CAMSS_CSI0PHY_CLK>,
1205 <&gcc GCC_CAMSS_CSI0PIX_CLK>,
1206 <&gcc GCC_CAMSS_CSI0RDI_CLK>,
1207 <&gcc GCC_CAMSS_CSI1_AHB_CLK>,
1208 <&gcc GCC_CAMSS_CSI1_CLK>,
1209 <&gcc GCC_CAMSS_CSI1PHY_CLK>,
1210 <&gcc GCC_CAMSS_CSI1PIX_CLK>,
1211 <&gcc GCC_CAMSS_CSI1RDI_CLK>,
1212 <&gcc GCC_CAMSS_AHB_CLK>,
1213 <&gcc GCC_CAMSS_VFE0_CLK>,
1214 <&gcc GCC_CAMSS_CSI_VFE0_CLK>,
1215 <&gcc GCC_CAMSS_VFE_AHB_CLK>,
1216 <&gcc GCC_CAMSS_VFE_AXI_CLK>;
1217 clock-names = "top_ahb",
1236 iommus = <&apps_iommu 3>;
1237 status = "disabled";
1239 #address-cells = <1>;
1245 compatible = "qcom,msm8916-cci", "qcom,msm8226-cci";
1246 #address-cells = <1>;
1248 reg = <0x01b0c000 0x1000>;
1249 interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
1250 clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
1251 <&gcc GCC_CAMSS_CCI_AHB_CLK>,
1252 <&gcc GCC_CAMSS_CCI_CLK>,
1253 <&gcc GCC_CAMSS_AHB_CLK>;
1254 clock-names = "camss_top_ahb", "cci_ahb",
1256 assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>,
1257 <&gcc GCC_CAMSS_CCI_CLK>;
1258 assigned-clock-rates = <80000000>, <19200000>;
1259 pinctrl-names = "default";
1260 pinctrl-0 = <&cci0_default>;
1261 status = "disabled";
1263 cci_i2c0: i2c-bus@0 {
1265 clock-frequency = <400000>;
1266 #address-cells = <1>;
1272 compatible = "qcom,adreno-306.0", "qcom,adreno";
1273 reg = <0x01c00000 0x20000>;
1274 reg-names = "kgsl_3d0_reg_memory";
1275 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1276 interrupt-names = "kgsl_3d0_irq";
1285 <&gcc GCC_OXILI_GFX3D_CLK>,
1286 <&gcc GCC_OXILI_AHB_CLK>,
1287 <&gcc GCC_OXILI_GMEM_CLK>,
1288 <&gcc GCC_BIMC_GFX_CLK>,
1289 <&gcc GCC_BIMC_GPU_CLK>,
1290 <&gcc GFX3D_CLK_SRC>;
1291 power-domains = <&gcc OXILI_GDSC>;
1292 operating-points-v2 = <&gpu_opp_table>;
1293 iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
1295 gpu_opp_table: opp-table {
1296 compatible = "operating-points-v2";
1299 opp-hz = /bits/ 64 <400000000>;
1302 opp-hz = /bits/ 64 <19200000>;
1307 venus: video-codec@1d00000 {
1308 compatible = "qcom,msm8916-venus";
1309 reg = <0x01d00000 0xff000>;
1310 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1311 power-domains = <&gcc VENUS_GDSC>;
1312 clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>,
1313 <&gcc GCC_VENUS0_AHB_CLK>,
1314 <&gcc GCC_VENUS0_AXI_CLK>;
1315 clock-names = "core", "iface", "bus";
1316 iommus = <&apps_iommu 5>;
1317 memory-region = <&venus_mem>;
1321 compatible = "venus-decoder";
1325 compatible = "venus-encoder";
1329 apps_iommu: iommu@1ef0000 {
1330 #address-cells = <1>;
1333 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
1334 ranges = <0 0x01e20000 0x40000>;
1335 reg = <0x01ef0000 0x3000>;
1336 clocks = <&gcc GCC_SMMU_CFG_CLK>,
1337 <&gcc GCC_APSS_TCU_CLK>;
1338 clock-names = "iface", "bus";
1339 qcom,iommu-secure-id = <17>;
1343 compatible = "qcom,msm-iommu-v1-sec";
1344 reg = <0x3000 0x1000>;
1345 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1350 compatible = "qcom,msm-iommu-v1-ns";
1351 reg = <0x4000 0x1000>;
1352 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1357 compatible = "qcom,msm-iommu-v1-sec";
1358 reg = <0x5000 0x1000>;
1359 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1363 gpu_iommu: iommu@1f08000 {
1364 #address-cells = <1>;
1367 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
1368 ranges = <0 0x01f08000 0x10000>;
1369 clocks = <&gcc GCC_SMMU_CFG_CLK>,
1370 <&gcc GCC_GFX_TCU_CLK>;
1371 clock-names = "iface", "bus";
1372 qcom,iommu-secure-id = <18>;
1376 compatible = "qcom,msm-iommu-v1-ns";
1377 reg = <0x1000 0x1000>;
1378 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
1383 compatible = "qcom,msm-iommu-v1-ns";
1384 reg = <0x2000 0x1000>;
1385 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
1389 spmi_bus: spmi@200f000 {
1390 compatible = "qcom,spmi-pmic-arb";
1391 reg = <0x0200f000 0x001000>,
1392 <0x02400000 0x400000>,
1393 <0x02c00000 0x400000>,
1394 <0x03800000 0x200000>,
1395 <0x0200a000 0x002100>;
1396 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1397 interrupt-names = "periph_irq";
1398 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1401 #address-cells = <2>;
1403 interrupt-controller;
1404 #interrupt-cells = <4>;
1407 bam_dmux_dma: dma-controller@4044000 {
1408 compatible = "qcom,bam-v1.7.0";
1409 reg = <0x04044000 0x19000>;
1410 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1416 qcom,powered-remotely;
1418 status = "disabled";
1421 mpss: remoteproc@4080000 {
1422 compatible = "qcom,msm8916-mss-pil";
1423 reg = <0x04080000 0x100>,
1426 reg-names = "qdsp6", "rmb";
1428 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
1429 <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1430 <&hexagon_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1431 <&hexagon_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1432 <&hexagon_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1433 interrupt-names = "wdog", "fatal", "ready",
1434 "handover", "stop-ack";
1436 power-domains = <&rpmpd MSM8916_VDDCX>,
1437 <&rpmpd MSM8916_VDDMX>;
1438 power-domain-names = "cx", "mx";
1440 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1441 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
1442 <&gcc GCC_BOOT_ROM_AHB_CLK>,
1444 clock-names = "iface", "bus", "mem", "xo";
1446 qcom,smem-states = <&hexagon_smp2p_out 0>;
1447 qcom,smem-state-names = "stop";
1450 reset-names = "mss_restart";
1452 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
1454 status = "disabled";
1457 memory-region = <&mba_mem>;
1461 memory-region = <&mpss_mem>;
1464 bam_dmux: bam-dmux {
1465 compatible = "qcom,bam-dmux";
1467 interrupt-parent = <&hexagon_smsm>;
1468 interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>;
1469 interrupt-names = "pc", "pc-ack";
1471 qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>;
1472 qcom,smem-state-names = "pc", "pc-ack";
1474 dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>;
1475 dma-names = "tx", "rx";
1477 status = "disabled";
1481 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
1483 qcom,smd-edge = <0>;
1484 qcom,ipc = <&apcs 8 12>;
1485 qcom,remote-pid = <1>;
1490 compatible = "qcom,fastrpc";
1491 qcom,smd-channels = "fastrpcsmd-apps-dsp";
1493 qcom,non-secure-domain;
1495 #address-cells = <1>;
1499 compatible = "qcom,fastrpc-compute-cb";
1506 sound: sound@7702000 {
1507 status = "disabled";
1508 compatible = "qcom,apq8016-sbc-sndcard";
1509 reg = <0x07702000 0x4>, <0x07702004 0x4>;
1510 reg-names = "mic-iomux", "spkr-iomux";
1513 lpass: audio-controller@7708000 {
1514 status = "disabled";
1515 compatible = "qcom,apq8016-lpass-cpu";
1518 * Note: Unlike the name would suggest, the SEC_I2S_CLK
1519 * is actually only used by Tertiary MI2S while
1520 * Primary/Secondary MI2S both use the PRI_I2S_CLK.
1522 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
1523 <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
1524 <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>,
1525 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
1526 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
1527 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
1528 <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>;
1530 clock-names = "ahbix-clk",
1537 #sound-dai-cells = <1>;
1539 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
1540 interrupt-names = "lpass-irq-lpaif";
1541 reg = <0x07708000 0x10000>;
1542 reg-names = "lpass-lpaif";
1544 #address-cells = <1>;
1548 lpass_codec: audio-codec@771c000 {
1549 compatible = "qcom,msm8916-wcd-digital-codec";
1550 reg = <0x0771c000 0x400>;
1551 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
1552 <&gcc GCC_CODEC_DIGCODEC_CLK>;
1553 clock-names = "ahbix-clk", "mclk";
1554 #sound-dai-cells = <1>;
1557 sdhc_1: mmc@7824000 {
1558 compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
1559 reg = <0x07824900 0x11c>, <0x07824000 0x800>;
1560 reg-names = "hc", "core";
1562 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1563 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
1564 interrupt-names = "hc_irq", "pwr_irq";
1565 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
1566 <&gcc GCC_SDCC1_APPS_CLK>,
1568 clock-names = "iface", "core", "xo";
1572 status = "disabled";
1575 sdhc_2: mmc@7864000 {
1576 compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
1577 reg = <0x07864900 0x11c>, <0x07864000 0x800>;
1578 reg-names = "hc", "core";
1580 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1581 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1582 interrupt-names = "hc_irq", "pwr_irq";
1583 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
1584 <&gcc GCC_SDCC2_APPS_CLK>,
1586 clock-names = "iface", "core", "xo";
1588 status = "disabled";
1591 blsp_dma: dma-controller@7884000 {
1592 compatible = "qcom,bam-v1.7.0";
1593 reg = <0x07884000 0x23000>;
1594 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1595 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
1596 clock-names = "bam_clk";
1601 blsp1_uart1: serial@78af000 {
1602 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1603 reg = <0x078af000 0x200>;
1604 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1605 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
1606 clock-names = "core", "iface";
1607 dmas = <&blsp_dma 0>, <&blsp_dma 1>;
1608 dma-names = "tx", "rx";
1609 pinctrl-names = "default", "sleep";
1610 pinctrl-0 = <&blsp1_uart1_default>;
1611 pinctrl-1 = <&blsp1_uart1_sleep>;
1612 status = "disabled";
1615 blsp1_uart2: serial@78b0000 {
1616 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1617 reg = <0x078b0000 0x200>;
1618 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1619 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
1620 clock-names = "core", "iface";
1621 dmas = <&blsp_dma 2>, <&blsp_dma 3>;
1622 dma-names = "tx", "rx";
1623 pinctrl-names = "default", "sleep";
1624 pinctrl-0 = <&blsp1_uart2_default>;
1625 pinctrl-1 = <&blsp1_uart2_sleep>;
1626 status = "disabled";
1629 blsp_i2c1: i2c@78b5000 {
1630 compatible = "qcom,i2c-qup-v2.2.1";
1631 reg = <0x078b5000 0x500>;
1632 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1633 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
1634 <&gcc GCC_BLSP1_AHB_CLK>;
1635 clock-names = "core", "iface";
1636 dmas = <&blsp_dma 4>, <&blsp_dma 5>;
1637 dma-names = "tx", "rx";
1638 pinctrl-names = "default", "sleep";
1639 pinctrl-0 = <&i2c1_default>;
1640 pinctrl-1 = <&i2c1_sleep>;
1641 #address-cells = <1>;
1643 status = "disabled";
1646 blsp_spi1: spi@78b5000 {
1647 compatible = "qcom,spi-qup-v2.2.1";
1648 reg = <0x078b5000 0x500>;
1649 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1650 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
1651 <&gcc GCC_BLSP1_AHB_CLK>;
1652 clock-names = "core", "iface";
1653 dmas = <&blsp_dma 4>, <&blsp_dma 5>;
1654 dma-names = "tx", "rx";
1655 pinctrl-names = "default", "sleep";
1656 pinctrl-0 = <&spi1_default>;
1657 pinctrl-1 = <&spi1_sleep>;
1658 #address-cells = <1>;
1660 status = "disabled";
1663 blsp_i2c2: i2c@78b6000 {
1664 compatible = "qcom,i2c-qup-v2.2.1";
1665 reg = <0x078b6000 0x500>;
1666 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1667 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
1668 <&gcc GCC_BLSP1_AHB_CLK>;
1669 clock-names = "core", "iface";
1670 dmas = <&blsp_dma 6>, <&blsp_dma 7>;
1671 dma-names = "tx", "rx";
1672 pinctrl-names = "default", "sleep";
1673 pinctrl-0 = <&i2c2_default>;
1674 pinctrl-1 = <&i2c2_sleep>;
1675 #address-cells = <1>;
1677 status = "disabled";
1680 blsp_spi2: spi@78b6000 {
1681 compatible = "qcom,spi-qup-v2.2.1";
1682 reg = <0x078b6000 0x500>;
1683 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1684 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
1685 <&gcc GCC_BLSP1_AHB_CLK>;
1686 clock-names = "core", "iface";
1687 dmas = <&blsp_dma 6>, <&blsp_dma 7>;
1688 dma-names = "tx", "rx";
1689 pinctrl-names = "default", "sleep";
1690 pinctrl-0 = <&spi2_default>;
1691 pinctrl-1 = <&spi2_sleep>;
1692 #address-cells = <1>;
1694 status = "disabled";
1697 blsp_i2c3: i2c@78b7000 {
1698 compatible = "qcom,i2c-qup-v2.2.1";
1699 reg = <0x078b7000 0x500>;
1700 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1701 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
1702 <&gcc GCC_BLSP1_AHB_CLK>;
1703 clock-names = "core", "iface";
1704 dmas = <&blsp_dma 8>, <&blsp_dma 9>;
1705 dma-names = "tx", "rx";
1706 pinctrl-names = "default", "sleep";
1707 pinctrl-0 = <&i2c3_default>;
1708 pinctrl-1 = <&i2c3_sleep>;
1709 #address-cells = <1>;
1711 status = "disabled";
1714 blsp_spi3: spi@78b7000 {
1715 compatible = "qcom,spi-qup-v2.2.1";
1716 reg = <0x078b7000 0x500>;
1717 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1718 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
1719 <&gcc GCC_BLSP1_AHB_CLK>;
1720 clock-names = "core", "iface";
1721 dmas = <&blsp_dma 8>, <&blsp_dma 9>;
1722 dma-names = "tx", "rx";
1723 pinctrl-names = "default", "sleep";
1724 pinctrl-0 = <&spi3_default>;
1725 pinctrl-1 = <&spi3_sleep>;
1726 #address-cells = <1>;
1728 status = "disabled";
1731 blsp_i2c4: i2c@78b8000 {
1732 compatible = "qcom,i2c-qup-v2.2.1";
1733 reg = <0x078b8000 0x500>;
1734 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1735 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
1736 <&gcc GCC_BLSP1_AHB_CLK>;
1737 clock-names = "core", "iface";
1738 dmas = <&blsp_dma 10>, <&blsp_dma 11>;
1739 dma-names = "tx", "rx";
1740 pinctrl-names = "default", "sleep";
1741 pinctrl-0 = <&i2c4_default>;
1742 pinctrl-1 = <&i2c4_sleep>;
1743 #address-cells = <1>;
1745 status = "disabled";
1748 blsp_spi4: spi@78b8000 {
1749 compatible = "qcom,spi-qup-v2.2.1";
1750 reg = <0x078b8000 0x500>;
1751 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1752 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
1753 <&gcc GCC_BLSP1_AHB_CLK>;
1754 clock-names = "core", "iface";
1755 dmas = <&blsp_dma 10>, <&blsp_dma 11>;
1756 dma-names = "tx", "rx";
1757 pinctrl-names = "default", "sleep";
1758 pinctrl-0 = <&spi4_default>;
1759 pinctrl-1 = <&spi4_sleep>;
1760 #address-cells = <1>;
1762 status = "disabled";
1765 blsp_i2c5: i2c@78b9000 {
1766 compatible = "qcom,i2c-qup-v2.2.1";
1767 reg = <0x078b9000 0x500>;
1768 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1769 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
1770 <&gcc GCC_BLSP1_AHB_CLK>;
1771 clock-names = "core", "iface";
1772 dmas = <&blsp_dma 12>, <&blsp_dma 13>;
1773 dma-names = "tx", "rx";
1774 pinctrl-names = "default", "sleep";
1775 pinctrl-0 = <&i2c5_default>;
1776 pinctrl-1 = <&i2c5_sleep>;
1777 #address-cells = <1>;
1779 status = "disabled";
1782 blsp_spi5: spi@78b9000 {
1783 compatible = "qcom,spi-qup-v2.2.1";
1784 reg = <0x078b9000 0x500>;
1785 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1786 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
1787 <&gcc GCC_BLSP1_AHB_CLK>;
1788 clock-names = "core", "iface";
1789 dmas = <&blsp_dma 12>, <&blsp_dma 13>;
1790 dma-names = "tx", "rx";
1791 pinctrl-names = "default", "sleep";
1792 pinctrl-0 = <&spi5_default>;
1793 pinctrl-1 = <&spi5_sleep>;
1794 #address-cells = <1>;
1796 status = "disabled";
1799 blsp_i2c6: i2c@78ba000 {
1800 compatible = "qcom,i2c-qup-v2.2.1";
1801 reg = <0x078ba000 0x500>;
1802 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1803 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
1804 <&gcc GCC_BLSP1_AHB_CLK>;
1805 clock-names = "core", "iface";
1806 dmas = <&blsp_dma 14>, <&blsp_dma 15>;
1807 dma-names = "tx", "rx";
1808 pinctrl-names = "default", "sleep";
1809 pinctrl-0 = <&i2c6_default>;
1810 pinctrl-1 = <&i2c6_sleep>;
1811 #address-cells = <1>;
1813 status = "disabled";
1816 blsp_spi6: spi@78ba000 {
1817 compatible = "qcom,spi-qup-v2.2.1";
1818 reg = <0x078ba000 0x500>;
1819 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1820 clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
1821 <&gcc GCC_BLSP1_AHB_CLK>;
1822 clock-names = "core", "iface";
1823 dmas = <&blsp_dma 14>, <&blsp_dma 15>;
1824 dma-names = "tx", "rx";
1825 pinctrl-names = "default", "sleep";
1826 pinctrl-0 = <&spi6_default>;
1827 pinctrl-1 = <&spi6_sleep>;
1828 #address-cells = <1>;
1830 status = "disabled";
1834 compatible = "qcom,ci-hdrc";
1835 reg = <0x078d9000 0x200>,
1837 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
1838 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
1839 clocks = <&gcc GCC_USB_HS_AHB_CLK>,
1840 <&gcc GCC_USB_HS_SYSTEM_CLK>;
1841 clock-names = "iface", "core";
1842 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
1843 assigned-clock-rates = <80000000>;
1844 resets = <&gcc GCC_USB_HS_BCR>;
1845 reset-names = "core";
1851 ahb-burst-config = <0>;
1852 phy-names = "usb-phy";
1853 phys = <&usb_hs_phy>;
1854 status = "disabled";
1859 compatible = "qcom,usb-hs-phy-msm8916",
1862 clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
1863 clock-names = "ref", "sleep";
1864 resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
1865 reset-names = "phy", "por";
1866 qcom,init-seq = /bits/ 8 <0x0 0x44>,
1874 wcnss: remoteproc@a21b000 {
1875 compatible = "qcom,pronto-v2-pil", "qcom,pronto";
1876 reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>;
1877 reg-names = "ccu", "dxe", "pmu";
1879 memory-region = <&wcnss_mem>;
1881 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
1882 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1883 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1884 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1885 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1886 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
1888 power-domains = <&rpmpd MSM8916_VDDCX>,
1889 <&rpmpd MSM8916_VDDMX>;
1890 power-domain-names = "cx", "mx";
1892 qcom,smem-states = <&wcnss_smp2p_out 0>;
1893 qcom,smem-state-names = "stop";
1895 pinctrl-names = "default";
1896 pinctrl-0 = <&wcnss_pin_a>;
1898 status = "disabled";
1901 /* Separate chip, compatible is board-specific */
1902 clocks = <&rpmcc RPM_SMD_RF_CLK2>;
1907 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
1909 qcom,ipc = <&apcs 8 17>;
1910 qcom,smd-edge = <6>;
1911 qcom,remote-pid = <4>;
1916 compatible = "qcom,wcnss";
1917 qcom,smd-channels = "WCNSS_CTRL";
1919 qcom,mmio = <&wcnss>;
1921 wcnss_bt: bluetooth {
1922 compatible = "qcom,wcnss-bt";
1926 compatible = "qcom,wcnss-wlan";
1928 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1929 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
1930 interrupt-names = "tx", "rx";
1932 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
1933 qcom,smem-state-names = "tx-enable", "tx-rings-empty";
1939 intc: interrupt-controller@b000000 {
1940 compatible = "qcom,msm-qgic2";
1941 interrupt-controller;
1942 #interrupt-cells = <3>;
1943 reg = <0x0b000000 0x1000>, <0x0b002000 0x2000>,
1944 <0x0b001000 0x1000>, <0x0b004000 0x2000>;
1945 interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1948 apcs: mailbox@b011000 {
1949 compatible = "qcom,msm8916-apcs-kpss-global", "syscon";
1950 reg = <0x0b011000 0x1000>;
1952 clocks = <&a53pll>, <&gcc GPLL0_VOTE>;
1953 clock-names = "pll", "aux";
1957 a53pll: clock@b016000 {
1958 compatible = "qcom,msm8916-a53pll";
1959 reg = <0x0b016000 0x40>;
1961 clocks = <&xo_board>;
1966 #address-cells = <1>;
1969 compatible = "arm,armv7-timer-mem";
1970 reg = <0x0b020000 0x1000>;
1971 clock-frequency = <19200000>;
1975 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1976 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1977 reg = <0x0b021000 0x1000>,
1978 <0x0b022000 0x1000>;
1983 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1984 reg = <0x0b023000 0x1000>;
1985 status = "disabled";
1990 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1991 reg = <0x0b024000 0x1000>;
1992 status = "disabled";
1997 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1998 reg = <0x0b025000 0x1000>;
1999 status = "disabled";
2004 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
2005 reg = <0x0b026000 0x1000>;
2006 status = "disabled";
2011 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
2012 reg = <0x0b027000 0x1000>;
2013 status = "disabled";
2018 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
2019 reg = <0x0b028000 0x1000>;
2020 status = "disabled";
2024 cpu0_acc: power-manager@b088000 {
2025 compatible = "qcom,msm8916-acc";
2026 reg = <0x0b088000 0x1000>;
2027 status = "reserved"; /* Controlled by PSCI firmware */
2030 cpu0_saw: power-manager@b089000 {
2031 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
2032 reg = <0x0b089000 0x1000>;
2033 status = "reserved"; /* Controlled by PSCI firmware */
2036 cpu1_acc: power-manager@b098000 {
2037 compatible = "qcom,msm8916-acc";
2038 reg = <0x0b098000 0x1000>;
2039 status = "reserved"; /* Controlled by PSCI firmware */
2042 cpu1_saw: power-manager@b099000 {
2043 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
2044 reg = <0x0b099000 0x1000>;
2045 status = "reserved"; /* Controlled by PSCI firmware */
2048 cpu2_acc: power-manager@b0a8000 {
2049 compatible = "qcom,msm8916-acc";
2050 reg = <0x0b0a8000 0x1000>;
2051 status = "reserved"; /* Controlled by PSCI firmware */
2054 cpu2_saw: power-manager@b0a9000 {
2055 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
2056 reg = <0x0b0a9000 0x1000>;
2057 status = "reserved"; /* Controlled by PSCI firmware */
2060 cpu3_acc: power-manager@b0b8000 {
2061 compatible = "qcom,msm8916-acc";
2062 reg = <0x0b0b8000 0x1000>;
2063 status = "reserved"; /* Controlled by PSCI firmware */
2066 cpu3_saw: power-manager@b0b9000 {
2067 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
2068 reg = <0x0b0b9000 0x1000>;
2069 status = "reserved"; /* Controlled by PSCI firmware */
2075 polling-delay-passive = <250>;
2076 polling-delay = <1000>;
2078 thermal-sensors = <&tsens 5>;
2081 cpu0_1_alert0: trip-point0 {
2082 temperature = <75000>;
2083 hysteresis = <2000>;
2086 cpu0_1_crit: cpu-crit {
2087 temperature = <110000>;
2088 hysteresis = <2000>;
2095 trip = <&cpu0_1_alert0>;
2096 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2097 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2098 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2099 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2105 polling-delay-passive = <250>;
2106 polling-delay = <1000>;
2108 thermal-sensors = <&tsens 4>;
2111 cpu2_3_alert0: trip-point0 {
2112 temperature = <75000>;
2113 hysteresis = <2000>;
2116 cpu2_3_crit: cpu-crit {
2117 temperature = <110000>;
2118 hysteresis = <2000>;
2125 trip = <&cpu2_3_alert0>;
2126 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2127 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2128 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2129 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2135 polling-delay-passive = <250>;
2136 polling-delay = <1000>;
2138 thermal-sensors = <&tsens 2>;
2141 gpu_alert0: trip-point0 {
2142 temperature = <75000>;
2143 hysteresis = <2000>;
2146 gpu_crit: gpu-crit {
2147 temperature = <95000>;
2148 hysteresis = <2000>;
2155 polling-delay-passive = <250>;
2156 polling-delay = <1000>;
2158 thermal-sensors = <&tsens 1>;
2161 cam_alert0: trip-point0 {
2162 temperature = <75000>;
2163 hysteresis = <2000>;
2170 polling-delay-passive = <250>;
2171 polling-delay = <1000>;
2173 thermal-sensors = <&tsens 0>;
2176 modem_alert0: trip-point0 {
2177 temperature = <85000>;
2178 hysteresis = <2000>;
2186 compatible = "arm,armv8-timer";
2187 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2188 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2189 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2190 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
2194 #include "msm8916-pins.dtsi"