arch/arm64/boot/dts/qcom/msm8916.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <dt-bindings/arm/coresight-cti-dt.h>
   7 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
   8 #include <dt-bindings/clock/qcom,rpmcc.h>
   9 #include <dt-bindings/interconnect/qcom,msm8916.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/power/qcom-rpmpd.h>
  12 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
  13 #include <dt-bindings/thermal/thermal.h>
  14
  15 / {
  16         interrupt-parent = <&intc>;
  17
  18         #address-cells = <2>;
  19         #size-cells = <2>;
  20
  21         chosen { };
  22
  23         memory@80000000 {
  24                 device_type = "memory";
  25                 /* We expect the bootloader to fill in the reg */
  26                 reg = <0 0x80000000 0 0>;
  27         };
  28
  29         reserved-memory {
  30                 #address-cells = <2>;
  31                 #size-cells = <2>;
  32                 ranges;
  33
  34                 tz-apps@86000000 {
  35                         reg = <0x0 0x86000000 0x0 0x300000>;
  36                         no-map;
  37                 };
  38
  39                 smem@86300000 {
  40                         compatible = "qcom,smem";
  41                         reg = <0x0 0x86300000 0x0 0x100000>;
  42                         no-map;
  43
  44                         hwlocks = <&tcsr_mutex 3>;
  45                         qcom,rpm-msg-ram = <&rpm_msg_ram>;
  46                 };
  47
  48                 hypervisor@86400000 {
  49                         reg = <0x0 0x86400000 0x0 0x100000>;
  50                         no-map;
  51                 };
  52
  53                 tz@86500000 {
  54                         reg = <0x0 0x86500000 0x0 0x180000>;
  55                         no-map;
  56                 };
  57
  58                 reserved@86680000 {
  59                         reg = <0x0 0x86680000 0x0 0x80000>;
  60                         no-map;
  61                 };
  62
  63                 rmtfs@86700000 {
  64                         compatible = "qcom,rmtfs-mem";
  65                         reg = <0x0 0x86700000 0x0 0xe0000>;
  66                         no-map;
  67
  68                         qcom,client-id = <1>;
  69                 };
  70
  71                 rfsa@867e0000 {
  72                         reg = <0x0 0x867e0000 0x0 0x20000>;
  73                         no-map;
  74                 };
  75
  76                 mpss_mem: mpss@86800000 {
  77                         /*
  78                          * The memory region for the mpss firmware is generally
  79                          * relocatable and could be allocated dynamically.
  80                          * However, many firmware versions tend to fail when
  81                          * loaded to some special addresses, so it is hard to
  82                          * define reliable alloc-ranges.
  83                          *
  84                          * alignment = <0x0 0x400000>;
  85                          * alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
  86                          */
  87                         reg = <0x0 0x86800000 0x0 0>; /* size is device-specific */
  88                         no-map;
  89                         status = "disabled";
  90                 };
  91
  92                 wcnss_mem: wcnss {
  93                         size = <0x0 0x600000>;
  94                         alignment = <0x0 0x100000>;
  95                         alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
  96                         no-map;
  97                         status = "disabled";
  98                 };
  99
 100                 venus_mem: venus {
 101                         size = <0x0 0x500000>;
 102                         alignment = <0x0 0x100000>;
 103                         alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
 104                         no-map;
 105                         status = "disabled";
 106                 };
 107
 108                 mba_mem: mba {
 109                         size = <0x0 0x100000>;
 110                         alignment = <0x0 0x100000>;
 111                         alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
 112                         no-map;
 113                         status = "disabled";
 114                 };
 115         };
 116
 117         clocks {
 118                 xo_board: xo-board {
 119                         compatible = "fixed-clock";
 120                         #clock-cells = <0>;
 121                         clock-frequency = <19200000>;
 122                 };
 123
 124                 sleep_clk: sleep-clk {
 125                         compatible = "fixed-clock";
 126                         #clock-cells = <0>;
 127                         clock-frequency = <32768>;
 128                 };
 129         };
 130
 131         cpus {
 132                 #address-cells = <1>;
 133                 #size-cells = <0>;
 134
 135                 CPU0: cpu@0 {
 136                         device_type = "cpu";
 137                         compatible = "arm,cortex-a53";
 138                         reg = <0x0>;
 139                         next-level-cache = <&L2_0>;
 140                         enable-method = "psci";
 141                         clocks = <&apcs>;
 142                         operating-points-v2 = <&cpu_opp_table>;
 143                         #cooling-cells = <2>;
 144                         power-domains = <&CPU_PD0>;
 145                         power-domain-names = "psci";
 146                         qcom,acc = <&cpu0_acc>;
 147                         qcom,saw = <&cpu0_saw>;
 148                 };
 149
 150                 CPU1: cpu@1 {
 151                         device_type = "cpu";
 152                         compatible = "arm,cortex-a53";
 153                         reg = <0x1>;
 154                         next-level-cache = <&L2_0>;
 155                         enable-method = "psci";
 156                         clocks = <&apcs>;
 157                         operating-points-v2 = <&cpu_opp_table>;
 158                         #cooling-cells = <2>;
 159                         power-domains = <&CPU_PD1>;
 160                         power-domain-names = "psci";
 161                         qcom,acc = <&cpu1_acc>;
 162                         qcom,saw = <&cpu1_saw>;
 163                 };
 164
 165                 CPU2: cpu@2 {
 166                         device_type = "cpu";
 167                         compatible = "arm,cortex-a53";
 168                         reg = <0x2>;
 169                         next-level-cache = <&L2_0>;
 170                         enable-method = "psci";
 171                         clocks = <&apcs>;
 172                         operating-points-v2 = <&cpu_opp_table>;
 173                         #cooling-cells = <2>;
 174                         power-domains = <&CPU_PD2>;
 175                         power-domain-names = "psci";
 176                         qcom,acc = <&cpu2_acc>;
 177                         qcom,saw = <&cpu2_saw>;
 178                 };
 179
 180                 CPU3: cpu@3 {
 181                         device_type = "cpu";
 182                         compatible = "arm,cortex-a53";
 183                         reg = <0x3>;
 184                         next-level-cache = <&L2_0>;
 185                         enable-method = "psci";
 186                         clocks = <&apcs>;
 187                         operating-points-v2 = <&cpu_opp_table>;
 188                         #cooling-cells = <2>;
 189                         power-domains = <&CPU_PD3>;
 190                         power-domain-names = "psci";
 191                         qcom,acc = <&cpu3_acc>;
 192                         qcom,saw = <&cpu3_saw>;
 193                 };
 194
 195                 L2_0: l2-cache {
 196                         compatible = "cache";
 197                         cache-level = <2>;
 198                         cache-unified;
 199                 };
 200
 201                 idle-states {
 202                         entry-method = "psci";
 203
 204                         CPU_SLEEP_0: cpu-sleep-0 {
 205                                 compatible = "arm,idle-state";
 206                                 idle-state-name = "standalone-power-collapse";
 207                                 arm,psci-suspend-param = <0x40000002>;
 208                                 entry-latency-us = <130>;
 209                                 exit-latency-us = <150>;
 210                                 min-residency-us = <2000>;
 211                                 local-timer-stop;
 212                         };
 213                 };
 214
 215                 domain-idle-states {
 216
 217                         CLUSTER_RET: cluster-retention {
 218                                 compatible = "domain-idle-state";
 219                                 arm,psci-suspend-param = <0x41000012>;
 220                                 entry-latency-us = <500>;
 221                                 exit-latency-us = <500>;
 222                                 min-residency-us = <2000>;
 223                         };
 224
 225                         CLUSTER_PWRDN: cluster-gdhs {
 226                                 compatible = "domain-idle-state";
 227                                 arm,psci-suspend-param = <0x41000032>;
 228                                 entry-latency-us = <2000>;
 229                                 exit-latency-us = <2000>;
 230                                 min-residency-us = <6000>;
 231                         };
 232                 };
 233         };
 234
 235         cpu_opp_table: opp-table-cpu {
 236                 compatible = "operating-points-v2";
 237                 opp-shared;
 238
 239                 opp-200000000 {
 240                         opp-hz = /bits/ 64 <200000000>;
 241                 };
 242                 opp-400000000 {
 243                         opp-hz = /bits/ 64 <400000000>;
 244                 };
 245                 opp-800000000 {
 246                         opp-hz = /bits/ 64 <800000000>;
 247                 };
 248                 opp-998400000 {
 249                         opp-hz = /bits/ 64 <998400000>;
 250                 };
 251         };
 252
 253         firmware {
 254                 scm: scm {
 255                         compatible = "qcom,scm-msm8916", "qcom,scm";
 256                         clocks = <&gcc GCC_CRYPTO_CLK>,
 257                                  <&gcc GCC_CRYPTO_AXI_CLK>,
 258                                  <&gcc GCC_CRYPTO_AHB_CLK>;
 259                         clock-names = "core", "bus", "iface";
 260                         #reset-cells = <1>;
 261
 262                         qcom,dload-mode = <&tcsr 0x6100>;
 263                 };
 264         };
 265
 266         pmu {
 267                 compatible = "arm,cortex-a53-pmu";
 268                 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 269         };
 270
 271         psci {
 272                 compatible = "arm,psci-1.0";
 273                 method = "smc";
 274
 275                 CPU_PD0: power-domain-cpu0 {
 276                         #power-domain-cells = <0>;
 277                         power-domains = <&CLUSTER_PD>;
 278                         domain-idle-states = <&CPU_SLEEP_0>;
 279                 };
 280
 281                 CPU_PD1: power-domain-cpu1 {
 282                         #power-domain-cells = <0>;
 283                         power-domains = <&CLUSTER_PD>;
 284                         domain-idle-states = <&CPU_SLEEP_0>;
 285                 };
 286
 287                 CPU_PD2: power-domain-cpu2 {
 288                         #power-domain-cells = <0>;
 289                         power-domains = <&CLUSTER_PD>;
 290                         domain-idle-states = <&CPU_SLEEP_0>;
 291                 };
 292
 293                 CPU_PD3: power-domain-cpu3 {
 294                         #power-domain-cells = <0>;
 295                         power-domains = <&CLUSTER_PD>;
 296                         domain-idle-states = <&CPU_SLEEP_0>;
 297                 };
 298
 299                 CLUSTER_PD: power-domain-cluster {
 300                         #power-domain-cells = <0>;
 301                         domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>;
 302                 };
 303         };
 304
 305         rpm: remoteproc {
 306                 compatible = "qcom,msm8916-rpm-proc", "qcom,rpm-proc";
 307
 308                 smd-edge {
 309                         interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
 310                         qcom,ipc = <&apcs 8 0>;
 311                         qcom,smd-edge = <15>;
 312
 313                         rpm_requests: rpm-requests {
 314                                 compatible = "qcom,rpm-msm8916";
 315                                 qcom,smd-channels = "rpm_requests";
 316
 317                                 rpmcc: clock-controller {
 318                                         compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc";
 319                                         #clock-cells = <1>;
 320                                         clocks = <&xo_board>;
 321                                         clock-names = "xo";
 322                                 };
 323
 324                                 rpmpd: power-controller {
 325                                         compatible = "qcom,msm8916-rpmpd";
 326                                         #power-domain-cells = <1>;
 327                                         operating-points-v2 = <&rpmpd_opp_table>;
 328
 329                                         rpmpd_opp_table: opp-table {
 330                                                 compatible = "operating-points-v2";
 331
 332                                                 rpmpd_opp_ret: opp1 {
 333                                                         opp-level = <1>;
 334                                                 };
 335                                                 rpmpd_opp_svs_krait: opp2 {
 336                                                         opp-level = <2>;
 337                                                 };
 338                                                 rpmpd_opp_svs_soc: opp3 {
 339                                                         opp-level = <3>;
 340                                                 };
 341                                                 rpmpd_opp_nom: opp4 {
 342                                                         opp-level = <4>;
 343                                                 };
 344                                                 rpmpd_opp_turbo: opp5 {
 345                                                         opp-level = <5>;
 346                                                 };
 347                                                 rpmpd_opp_super_turbo: opp6 {
 348                                                         opp-level = <6>;
 349                                                 };
 350                                         };
 351                                 };
 352                         };
 353                 };
 354         };
 355
 356         smp2p-hexagon {
 357                 compatible = "qcom,smp2p";
 358                 qcom,smem = <435>, <428>;
 359
 360                 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
 361
 362                 qcom,ipc = <&apcs 8 14>;
 363
 364                 qcom,local-pid = <0>;
 365                 qcom,remote-pid = <1>;
 366
 367                 hexagon_smp2p_out: master-kernel {
 368                         qcom,entry-name = "master-kernel";
 369
 370                         #qcom,smem-state-cells = <1>;
 371                 };
 372
 373                 hexagon_smp2p_in: slave-kernel {
 374                         qcom,entry-name = "slave-kernel";
 375
 376                         interrupt-controller;
 377                         #interrupt-cells = <2>;
 378                 };
 379         };
 380
 381         smp2p-wcnss {
 382                 compatible = "qcom,smp2p";
 383                 qcom,smem = <451>, <431>;
 384
 385                 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
 386
 387                 qcom,ipc = <&apcs 8 18>;
 388
 389                 qcom,local-pid = <0>;
 390                 qcom,remote-pid = <4>;
 391
 392                 wcnss_smp2p_out: master-kernel {
 393                         qcom,entry-name = "master-kernel";
 394
 395                         #qcom,smem-state-cells = <1>;
 396                 };
 397
 398                 wcnss_smp2p_in: slave-kernel {
 399                         qcom,entry-name = "slave-kernel";
 400
 401                         interrupt-controller;
 402                         #interrupt-cells = <2>;
 403                 };
 404         };
 405
 406         smsm {
 407                 compatible = "qcom,smsm";
 408
 409                 #address-cells = <1>;
 410                 #size-cells = <0>;
 411
 412                 qcom,ipc-1 = <&apcs 8 13>;
 413                 qcom,ipc-3 = <&apcs 8 19>;
 414
 415                 apps_smsm: apps@0 {
 416                         reg = <0>;
 417
 418                         #qcom,smem-state-cells = <1>;
 419                 };
 420
 421                 hexagon_smsm: hexagon@1 {
 422                         reg = <1>;
 423                         interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
 424
 425                         interrupt-controller;
 426                         #interrupt-cells = <2>;
 427                 };
 428
 429                 wcnss_smsm: wcnss@6 {
 430                         reg = <6>;
 431                         interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
 432
 433                         interrupt-controller;
 434                         #interrupt-cells = <2>;
 435                 };
 436         };
 437
 438         soc: soc@0 {
 439                 #address-cells = <1>;
 440                 #size-cells = <1>;
 441                 ranges = <0 0 0 0xffffffff>;
 442                 compatible = "simple-bus";
 443
 444                 rng@22000 {
 445                         compatible = "qcom,prng";
 446                         reg = <0x00022000 0x200>;
 447                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 448                         clock-names = "core";
 449                 };
 450
 451                 restart@4ab000 {
 452                         compatible = "qcom,pshold";
 453                         reg = <0x004ab000 0x4>;
 454                 };
 455
 456                 qfprom: qfprom@5c000 {
 457                         compatible = "qcom,msm8916-qfprom", "qcom,qfprom";
 458                         reg = <0x0005c000 0x1000>;
 459                         #address-cells = <1>;
 460                         #size-cells = <1>;
 461
 462                         tsens_base1: base1@d0 {
 463                                 reg = <0xd0 0x1>;
 464                                 bits = <0 7>;
 465                         };
 466
 467                         tsens_s0_p1: s0-p1@d0 {
 468                                 reg = <0xd0 0x2>;
 469                                 bits = <7 5>;
 470                         };
 471
 472                         tsens_s0_p2: s0-p2@d1 {
 473                                 reg = <0xd1 0x2>;
 474                                 bits = <4 5>;
 475                         };
 476
 477                         tsens_s1_p1: s1-p1@d2 {
 478                                 reg = <0xd2 0x1>;
 479                                 bits = <1 5>;
 480                         };
 481                         tsens_s1_p2: s1-p2@d2 {
 482                                 reg = <0xd2 0x2>;
 483                                 bits = <6 5>;
 484                         };
 485                         tsens_s2_p1: s2-p1@d3 {
 486                                 reg = <0xd3 0x1>;
 487                                 bits = <3 5>;
 488                         };
 489
 490                         tsens_s2_p2: s2-p2@d4 {
 491                                 reg = <0xd4 0x1>;
 492                                 bits = <0 5>;
 493                         };
 494
 495                         // no tsens with hw_id 3
 496
 497                         tsens_s4_p1: s4-p1@d4 {
 498                                 reg = <0xd4 0x2>;
 499                                 bits = <5 5>;
 500                         };
 501
 502                         tsens_s4_p2: s4-p2@d5 {
 503                                 reg = <0xd5 0x1>;
 504                                 bits = <2 5>;
 505                         };
 506
 507                         tsens_s5_p1: s5-p1@d5 {
 508                                 reg = <0xd5 0x2>;
 509                                 bits = <7 5>;
 510                         };
 511
 512                         tsens_s5_p2: s5-p2@d6 {
 513                                 reg = <0xd6 0x2>;
 514                                 bits = <4 5>;
 515                         };
 516
 517                         tsens_base2: base2@d7 {
 518                                 reg = <0xd7 0x1>;
 519                                 bits = <1 7>;
 520                         };
 521
 522                         tsens_mode: mode@ef {
 523                                 reg = <0xef 0x1>;
 524                                 bits = <5 3>;
 525                         };
 526                 };
 527
 528                 rpm_msg_ram: sram@60000 {
 529                         compatible = "qcom,rpm-msg-ram";
 530                         reg = <0x00060000 0x8000>;
 531                 };
 532
 533                 sram@290000 {
 534                         compatible = "qcom,msm8916-rpm-stats";
 535                         reg = <0x00290000 0x10000>;
 536                 };
 537
 538                 bimc: interconnect@400000 {
 539                         compatible = "qcom,msm8916-bimc";
 540                         reg = <0x00400000 0x62000>;
 541                         #interconnect-cells = <1>;
 542                 };
 543
 544                 tsens: thermal-sensor@4a9000 {
 545                         compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1";
 546                         reg = <0x004a9000 0x1000>, /* TM */
 547                               <0x004a8000 0x1000>; /* SROT */
 548
 549                         // no hw_id 3
 550                         nvmem-cells = <&tsens_mode>,
 551                                       <&tsens_base1>, <&tsens_base2>,
 552                                       <&tsens_s0_p1>, <&tsens_s0_p2>,
 553                                       <&tsens_s1_p1>, <&tsens_s1_p2>,
 554                                       <&tsens_s2_p1>, <&tsens_s2_p2>,
 555                                       <&tsens_s4_p1>, <&tsens_s4_p2>,
 556                                       <&tsens_s5_p1>, <&tsens_s5_p2>;
 557                         nvmem-cell-names = "mode",
 558                                            "base1", "base2",
 559                                            "s0_p1", "s0_p2",
 560                                            "s1_p1", "s1_p2",
 561                                            "s2_p1", "s2_p2",
 562                                            "s4_p1", "s4_p2",
 563                                            "s5_p1", "s5_p2";
 564                         #qcom,sensors = <5>;
 565                         interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 566                         interrupt-names = "uplow";
 567                         #thermal-sensor-cells = <1>;
 568                 };
 569
 570                 pcnoc: interconnect@500000 {
 571                         compatible = "qcom,msm8916-pcnoc";
 572                         reg = <0x00500000 0x11000>;
 573                         #interconnect-cells = <1>;
 574                 };
 575
 576                 snoc: interconnect@580000 {
 577                         compatible = "qcom,msm8916-snoc";
 578                         reg = <0x00580000 0x14000>;
 579                         #interconnect-cells = <1>;
 580                 };
 581
 582                 stm: stm@802000 {
 583                         compatible = "arm,coresight-stm", "arm,primecell";
 584                         reg = <0x00802000 0x1000>,
 585                               <0x09280000 0x180000>;
 586                         reg-names = "stm-base", "stm-stimulus-base";
 587
 588                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 589                         clock-names = "apb_pclk", "atclk";
 590
 591                         status = "disabled";
 592
 593                         out-ports {
 594                                 port {
 595                                         stm_out: endpoint {
 596                                                 remote-endpoint = <&funnel0_in7>;
 597                                         };
 598                                 };
 599                         };
 600                 };
 601
 602                 /* System CTIs */
 603                 /* CTI 0 - TMC connections */
 604                 cti0: cti@810000 {
 605                         compatible = "arm,coresight-cti", "arm,primecell";
 606                         reg = <0x00810000 0x1000>;
 607
 608                         clocks = <&rpmcc RPM_QDSS_CLK>;
 609                         clock-names = "apb_pclk";
 610
 611                         status = "disabled";
 612                 };
 613
 614                 /* CTI 1 - TPIU connections */
 615                 cti1: cti@811000 {
 616                         compatible = "arm,coresight-cti", "arm,primecell";
 617                         reg = <0x00811000 0x1000>;
 618
 619                         clocks = <&rpmcc RPM_QDSS_CLK>;
 620                         clock-names = "apb_pclk";
 621
 622                         status = "disabled";
 623                 };
 624
 625                 /* CTIs 2-11 - no information - not instantiated */
 626
 627                 tpiu: tpiu@820000 {
 628                         compatible = "arm,coresight-tpiu", "arm,primecell";
 629                         reg = <0x00820000 0x1000>;
 630
 631                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 632                         clock-names = "apb_pclk", "atclk";
 633
 634                         status = "disabled";
 635
 636                         in-ports {
 637                                 port {
 638                                         tpiu_in: endpoint {
 639                                                 remote-endpoint = <&replicator_out1>;
 640                                         };
 641                                 };
 642                         };
 643                 };
 644
 645                 funnel0: funnel@821000 {
 646                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 647                         reg = <0x00821000 0x1000>;
 648
 649                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 650                         clock-names = "apb_pclk", "atclk";
 651
 652                         status = "disabled";
 653
 654                         in-ports {
 655                                 #address-cells = <1>;
 656                                 #size-cells = <0>;
 657
 658                                 /*
 659                                  * Not described input ports:
 660                                  * 0 - connected to Resource and Power Manger CPU ETM
 661                                  * 1 - not-connected
 662                                  * 2 - connected to Modem CPU ETM
 663                                  * 3 - not-connected
 664                                  * 5 - not-connected
 665                                  * 6 - connected trought funnel to Wireless CPU ETM
 666                                  * 7 - connected to STM component
 667                                  */
 668
 669                                 port@4 {
 670                                         reg = <4>;
 671                                         funnel0_in4: endpoint {
 672                                                 remote-endpoint = <&funnel1_out>;
 673                                         };
 674                                 };
 675
 676                                 port@7 {
 677                                         reg = <7>;
 678                                         funnel0_in7: endpoint {
 679                                                 remote-endpoint = <&stm_out>;
 680                                         };
 681                                 };
 682                         };
 683
 684                         out-ports {
 685                                 port {
 686                                         funnel0_out: endpoint {
 687                                                 remote-endpoint = <&etf_in>;
 688                                         };
 689                                 };
 690                         };
 691                 };
 692
 693                 replicator: replicator@824000 {
 694                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
 695                         reg = <0x00824000 0x1000>;
 696
 697                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 698                         clock-names = "apb_pclk", "atclk";
 699
 700                         status = "disabled";
 701
 702                         out-ports {
 703                                 #address-cells = <1>;
 704                                 #size-cells = <0>;
 705
 706                                 port@0 {
 707                                         reg = <0>;
 708                                         replicator_out0: endpoint {
 709                                                 remote-endpoint = <&etr_in>;
 710                                         };
 711                                 };
 712                                 port@1 {
 713                                         reg = <1>;
 714                                         replicator_out1: endpoint {
 715                                                 remote-endpoint = <&tpiu_in>;
 716                                         };
 717                                 };
 718                         };
 719
 720                         in-ports {
 721                                 port {
 722                                         replicator_in: endpoint {
 723                                                 remote-endpoint = <&etf_out>;
 724                                         };
 725                                 };
 726                         };
 727                 };
 728
 729                 etf: etf@825000 {
 730                         compatible = "arm,coresight-tmc", "arm,primecell";
 731                         reg = <0x00825000 0x1000>;
 732
 733                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 734                         clock-names = "apb_pclk", "atclk";
 735
 736                         status = "disabled";
 737
 738                         in-ports {
 739                                 port {
 740                                         etf_in: endpoint {
 741                                                 remote-endpoint = <&funnel0_out>;
 742                                         };
 743                                 };
 744                         };
 745
 746                         out-ports {
 747                                 port {
 748                                         etf_out: endpoint {
 749                                                 remote-endpoint = <&replicator_in>;
 750                                         };
 751                                 };
 752                         };
 753                 };
 754
 755                 etr: etr@826000 {
 756                         compatible = "arm,coresight-tmc", "arm,primecell";
 757                         reg = <0x00826000 0x1000>;
 758
 759                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 760                         clock-names = "apb_pclk", "atclk";
 761
 762                         status = "disabled";
 763
 764                         in-ports {
 765                                 port {
 766                                         etr_in: endpoint {
 767                                                 remote-endpoint = <&replicator_out0>;
 768                                         };
 769                                 };
 770                         };
 771                 };
 772
 773                 funnel1: funnel@841000 {        /* APSS funnel only 4 inputs are used */
 774                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 775                         reg = <0x00841000 0x1000>;
 776
 777                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 778                         clock-names = "apb_pclk", "atclk";
 779
 780                         status = "disabled";
 781
 782                         in-ports {
 783                                 #address-cells = <1>;
 784                                 #size-cells = <0>;
 785
 786                                 port@0 {
 787                                         reg = <0>;
 788                                         funnel1_in0: endpoint {
 789                                                 remote-endpoint = <&etm0_out>;
 790                                         };
 791                                 };
 792                                 port@1 {
 793                                         reg = <1>;
 794                                         funnel1_in1: endpoint {
 795                                                 remote-endpoint = <&etm1_out>;
 796                                         };
 797                                 };
 798                                 port@2 {
 799                                         reg = <2>;
 800                                         funnel1_in2: endpoint {
 801                                                 remote-endpoint = <&etm2_out>;
 802                                         };
 803                                 };
 804                                 port@3 {
 805                                         reg = <3>;
 806                                         funnel1_in3: endpoint {
 807                                                 remote-endpoint = <&etm3_out>;
 808                                         };
 809                                 };
 810                         };
 811
 812                         out-ports {
 813                                 port {
 814                                         funnel1_out: endpoint {
 815                                                 remote-endpoint = <&funnel0_in4>;
 816                                         };
 817                                 };
 818                         };
 819                 };
 820
 821                 debug0: debug@850000 {
 822                         compatible = "arm,coresight-cpu-debug", "arm,primecell";
 823                         reg = <0x00850000 0x1000>;
 824                         clocks = <&rpmcc RPM_QDSS_CLK>;
 825                         clock-names = "apb_pclk";
 826                         cpu = <&CPU0>;
 827                         status = "disabled";
 828                 };
 829
 830                 debug1: debug@852000 {
 831                         compatible = "arm,coresight-cpu-debug", "arm,primecell";
 832                         reg = <0x00852000 0x1000>;
 833                         clocks = <&rpmcc RPM_QDSS_CLK>;
 834                         clock-names = "apb_pclk";
 835                         cpu = <&CPU1>;
 836                         status = "disabled";
 837                 };
 838
 839                 debug2: debug@854000 {
 840                         compatible = "arm,coresight-cpu-debug", "arm,primecell";
 841                         reg = <0x00854000 0x1000>;
 842                         clocks = <&rpmcc RPM_QDSS_CLK>;
 843                         clock-names = "apb_pclk";
 844                         cpu = <&CPU2>;
 845                         status = "disabled";
 846                 };
 847
 848                 debug3: debug@856000 {
 849                         compatible = "arm,coresight-cpu-debug", "arm,primecell";
 850                         reg = <0x00856000 0x1000>;
 851                         clocks = <&rpmcc RPM_QDSS_CLK>;
 852                         clock-names = "apb_pclk";
 853                         cpu = <&CPU3>;
 854                         status = "disabled";
 855                 };
 856
 857                 /* Core CTIs; CTIs 12-15 */
 858                 /* CTI - CPU-0 */
 859                 cti12: cti@858000 {
 860                         compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
 861                                      "arm,primecell";
 862                         reg = <0x00858000 0x1000>;
 863
 864                         clocks = <&rpmcc RPM_QDSS_CLK>;
 865                         clock-names = "apb_pclk";
 866
 867                         cpu = <&CPU0>;
 868                         arm,cs-dev-assoc = <&etm0>;
 869
 870                         status = "disabled";
 871                 };
 872
 873                 /* CTI - CPU-1 */
 874                 cti13: cti@859000 {
 875                         compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
 876                                      "arm,primecell";
 877                         reg = <0x00859000 0x1000>;
 878
 879                         clocks = <&rpmcc RPM_QDSS_CLK>;
 880                         clock-names = "apb_pclk";
 881
 882                         cpu = <&CPU1>;
 883                         arm,cs-dev-assoc = <&etm1>;
 884
 885                         status = "disabled";
 886                 };
 887
 888                 /* CTI - CPU-2 */
 889                 cti14: cti@85a000 {
 890                         compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
 891                                      "arm,primecell";
 892                         reg = <0x0085a000 0x1000>;
 893
 894                         clocks = <&rpmcc RPM_QDSS_CLK>;
 895                         clock-names = "apb_pclk";
 896
 897                         cpu = <&CPU2>;
 898                         arm,cs-dev-assoc = <&etm2>;
 899
 900                         status = "disabled";
 901                 };
 902
 903                 /* CTI - CPU-3 */
 904                 cti15: cti@85b000 {
 905                         compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
 906                                      "arm,primecell";
 907                         reg = <0x0085b000 0x1000>;
 908
 909                         clocks = <&rpmcc RPM_QDSS_CLK>;
 910                         clock-names = "apb_pclk";
 911
 912                         cpu = <&CPU3>;
 913                         arm,cs-dev-assoc = <&etm3>;
 914
 915                         status = "disabled";
 916                 };
 917
 918                 etm0: etm@85c000 {
 919                         compatible = "arm,coresight-etm4x", "arm,primecell";
 920                         reg = <0x0085c000 0x1000>;
 921
 922                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 923                         clock-names = "apb_pclk", "atclk";
 924                         arm,coresight-loses-context-with-cpu;
 925
 926                         cpu = <&CPU0>;
 927
 928                         status = "disabled";
 929
 930                         out-ports {
 931                                 port {
 932                                         etm0_out: endpoint {
 933                                                 remote-endpoint = <&funnel1_in0>;
 934                                         };
 935                                 };
 936                         };
 937                 };
 938
 939                 etm1: etm@85d000 {
 940                         compatible = "arm,coresight-etm4x", "arm,primecell";
 941                         reg = <0x0085d000 0x1000>;
 942
 943                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 944                         clock-names = "apb_pclk", "atclk";
 945                         arm,coresight-loses-context-with-cpu;
 946
 947                         cpu = <&CPU1>;
 948
 949                         status = "disabled";
 950
 951                         out-ports {
 952                                 port {
 953                                         etm1_out: endpoint {
 954                                                 remote-endpoint = <&funnel1_in1>;
 955                                         };
 956                                 };
 957                         };
 958                 };
 959
 960                 etm2: etm@85e000 {
 961                         compatible = "arm,coresight-etm4x", "arm,primecell";
 962                         reg = <0x0085e000 0x1000>;
 963
 964                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 965                         clock-names = "apb_pclk", "atclk";
 966                         arm,coresight-loses-context-with-cpu;
 967
 968                         cpu = <&CPU2>;
 969
 970                         status = "disabled";
 971
 972                         out-ports {
 973                                 port {
 974                                         etm2_out: endpoint {
 975                                                 remote-endpoint = <&funnel1_in2>;
 976                                         };
 977                                 };
 978                         };
 979                 };
 980
 981                 etm3: etm@85f000 {
 982                         compatible = "arm,coresight-etm4x", "arm,primecell";
 983                         reg = <0x0085f000 0x1000>;
 984
 985                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 986                         clock-names = "apb_pclk", "atclk";
 987                         arm,coresight-loses-context-with-cpu;
 988
 989                         cpu = <&CPU3>;
 990
 991                         status = "disabled";
 992
 993                         out-ports {
 994                                 port {
 995                                         etm3_out: endpoint {
 996                                                 remote-endpoint = <&funnel1_in3>;
 997                                         };
 998                                 };
 999                         };
1000                 };
1001
1002                 tlmm: pinctrl@1000000 {
1003                         compatible = "qcom,msm8916-pinctrl";
1004                         reg = <0x01000000 0x300000>;
1005                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1006                         gpio-controller;
1007                         gpio-ranges = <&tlmm 0 0 122>;
1008                         #gpio-cells = <2>;
1009                         interrupt-controller;
1010                         #interrupt-cells = <2>;
1011
1012                         blsp_i2c1_default: blsp-i2c1-default-state {
1013                                 pins = "gpio2", "gpio3";
1014                                 function = "blsp_i2c1";
1015                                 drive-strength = <2>;
1016                                 bias-disable;
1017                         };
1018
1019                         blsp_i2c1_sleep: blsp-i2c1-sleep-state {
1020                                 pins = "gpio2", "gpio3";
1021                                 function = "gpio";
1022                                 drive-strength = <2>;
1023                                 bias-disable;
1024                         };
1025
1026                         blsp_i2c2_default: blsp-i2c2-default-state {
1027                                 pins = "gpio6", "gpio7";
1028                                 function = "blsp_i2c2";
1029                                 drive-strength = <2>;
1030                                 bias-disable;
1031                         };
1032
1033                         blsp_i2c2_sleep: blsp-i2c2-sleep-state {
1034                                 pins = "gpio6", "gpio7";
1035                                 function = "gpio";
1036                                 drive-strength = <2>;
1037                                 bias-disable;
1038                         };
1039
1040                         blsp_i2c3_default: blsp-i2c3-default-state {
1041                                 pins = "gpio10", "gpio11";
1042                                 function = "blsp_i2c3";
1043                                 drive-strength = <2>;
1044                                 bias-disable;
1045                         };
1046
1047                         blsp_i2c3_sleep: blsp-i2c3-sleep-state {
1048                                 pins = "gpio10", "gpio11";
1049                                 function = "gpio";
1050                                 drive-strength = <2>;
1051                                 bias-disable;
1052                         };
1053
1054                         blsp_i2c4_default: blsp-i2c4-default-state {
1055                                 pins = "gpio14", "gpio15";
1056                                 function = "blsp_i2c4";
1057                                 drive-strength = <2>;
1058                                 bias-disable;
1059                         };
1060
1061                         blsp_i2c4_sleep: blsp-i2c4-sleep-state {
1062                                 pins = "gpio14", "gpio15";
1063                                 function = "gpio";
1064                                 drive-strength = <2>;
1065                                 bias-disable;
1066                         };
1067
1068                         blsp_i2c5_default: blsp-i2c5-default-state {
1069                                 pins = "gpio18", "gpio19";
1070                                 function = "blsp_i2c5";
1071                                 drive-strength = <2>;
1072                                 bias-disable;
1073                         };
1074
1075                         blsp_i2c5_sleep: blsp-i2c5-sleep-state {
1076                                 pins = "gpio18", "gpio19";
1077                                 function = "gpio";
1078                                 drive-strength = <2>;
1079                                 bias-disable;
1080                         };
1081
1082                         blsp_i2c6_default: blsp-i2c6-default-state {
1083                                 pins = "gpio22", "gpio23";
1084                                 function = "blsp_i2c6";
1085                                 drive-strength = <2>;
1086                                 bias-disable;
1087                         };
1088
1089                         blsp_i2c6_sleep: blsp-i2c6-sleep-state {
1090                                 pins = "gpio22", "gpio23";
1091                                 function = "gpio";
1092                                 drive-strength = <2>;
1093                                 bias-disable;
1094                         };
1095
1096                         blsp_spi1_default: blsp-spi1-default-state {
1097                                 spi-pins {
1098                                         pins = "gpio0", "gpio1", "gpio3";
1099                                         function = "blsp_spi1";
1100                                         drive-strength = <12>;
1101                                         bias-disable;
1102                                 };
1103                                 cs-pins {
1104                                         pins = "gpio2";
1105                                         function = "gpio";
1106                                         drive-strength = <16>;
1107                                         bias-disable;
1108                                         output-high;
1109                                 };
1110                         };
1111
1112                         blsp_spi1_sleep: blsp-spi1-sleep-state {
1113                                 pins = "gpio0", "gpio1", "gpio2", "gpio3";
1114                                 function = "gpio";
1115                                 drive-strength = <2>;
1116                                 bias-pull-down;
1117                         };
1118
1119                         blsp_spi2_default: blsp-spi2-default-state {
1120                                 spi-pins {
1121                                         pins = "gpio4", "gpio5", "gpio7";
1122                                         function = "blsp_spi2";
1123                                         drive-strength = <12>;
1124                                         bias-disable;
1125                                 };
1126                                 cs-pins {
1127                                         pins = "gpio6";
1128                                         function = "gpio";
1129                                         drive-strength = <16>;
1130                                         bias-disable;
1131                                         output-high;
1132                                 };
1133                         };
1134
1135                         blsp_spi2_sleep: blsp-spi2-sleep-state {
1136                                 pins = "gpio4", "gpio5", "gpio6", "gpio7";
1137                                 function = "gpio";
1138                                 drive-strength = <2>;
1139                                 bias-pull-down;
1140                         };
1141
1142                         blsp_spi3_default: blsp-spi3-default-state {
1143                                 spi-pins {
1144                                         pins = "gpio8", "gpio9", "gpio11";
1145                                         function = "blsp_spi3";
1146                                         drive-strength = <12>;
1147                                         bias-disable;
1148                                 };
1149                                 cs-pins {
1150                                         pins = "gpio10";
1151                                         function = "gpio";
1152                                         drive-strength = <16>;
1153                                         bias-disable;
1154                                         output-high;
1155                                 };
1156                         };
1157
1158                         blsp_spi3_sleep: blsp-spi3-sleep-state {
1159                                 pins = "gpio8", "gpio9", "gpio10", "gpio11";
1160                                 function = "gpio";
1161                                 drive-strength = <2>;
1162                                 bias-pull-down;
1163                         };
1164
1165                         blsp_spi4_default: blsp-spi4-default-state {
1166                                 spi-pins {
1167                                         pins = "gpio12", "gpio13", "gpio15";
1168                                         function = "blsp_spi4";
1169                                         drive-strength = <12>;
1170                                         bias-disable;
1171                                 };
1172                                 cs-pins {
1173                                         pins = "gpio14";
1174                                         function = "gpio";
1175                                         drive-strength = <16>;
1176                                         bias-disable;
1177                                         output-high;
1178                                 };
1179                         };
1180
1181                         blsp_spi4_sleep: blsp-spi4-sleep-state {
1182                                 pins = "gpio12", "gpio13", "gpio14", "gpio15";
1183                                 function = "gpio";
1184                                 drive-strength = <2>;
1185                                 bias-pull-down;
1186                         };
1187
1188                         blsp_spi5_default: blsp-spi5-default-state {
1189                                 spi-pins {
1190                                         pins = "gpio16", "gpio17", "gpio19";
1191                                         function = "blsp_spi5";
1192                                         drive-strength = <12>;
1193                                         bias-disable;
1194                                 };
1195                                 cs-pins {
1196                                         pins = "gpio18";
1197                                         function = "gpio";
1198                                         drive-strength = <16>;
1199                                         bias-disable;
1200                                         output-high;
1201                                 };
1202                         };
1203
1204                         blsp_spi5_sleep: blsp-spi5-sleep-state {
1205                                 pins = "gpio16", "gpio17", "gpio18", "gpio19";
1206                                 function = "gpio";
1207                                 drive-strength = <2>;
1208                                 bias-pull-down;
1209                         };
1210
1211                         blsp_spi6_default: blsp-spi6-default-state {
1212                                 spi-pins {
1213                                         pins = "gpio20", "gpio21", "gpio23";
1214                                         function = "blsp_spi6";
1215                                         drive-strength = <12>;
1216                                         bias-disable;
1217                                 };
1218                                 cs-pins {
1219                                         pins = "gpio22";
1220                                         function = "gpio";
1221                                         drive-strength = <16>;
1222                                         bias-disable;
1223                                         output-high;
1224                                 };
1225                         };
1226
1227                         blsp_spi6_sleep: blsp-spi6-sleep-state {
1228                                 pins = "gpio20", "gpio21", "gpio22", "gpio23";
1229                                 function = "gpio";
1230                                 drive-strength = <2>;
1231                                 bias-pull-down;
1232                         };
1233
1234                         blsp_uart1_default: blsp-uart1-default-state {
1235                                 /* TX, RX, CTS_N, RTS_N */
1236                                 pins = "gpio0", "gpio1", "gpio2", "gpio3";
1237                                 function = "blsp_uart1";
1238                                 drive-strength = <16>;
1239                                 bias-disable;
1240                         };
1241
1242                         blsp_uart1_sleep: blsp-uart1-sleep-state {
1243                                 pins = "gpio0", "gpio1", "gpio2", "gpio3";
1244                                 function = "gpio";
1245                                 drive-strength = <2>;
1246                                 bias-pull-down;
1247                         };
1248
1249                         blsp_uart2_default: blsp-uart2-default-state {
1250                                 pins = "gpio4", "gpio5";
1251                                 function = "blsp_uart2";
1252                                 drive-strength = <16>;
1253                                 bias-disable;
1254                         };
1255
1256                         blsp_uart2_sleep: blsp-uart2-sleep-state {
1257                                 pins = "gpio4", "gpio5";
1258                                 function = "gpio";
1259                                 drive-strength = <2>;
1260                                 bias-pull-down;
1261                         };
1262
1263                         camera_front_default: camera-front-default-state {
1264                                 pwdn-pins {
1265                                         pins = "gpio33";
1266                                         function = "gpio";
1267                                         drive-strength = <16>;
1268                                         bias-disable;
1269                                 };
1270                                 rst-pins {
1271                                         pins = "gpio28";
1272                                         function = "gpio";
1273                                         drive-strength = <16>;
1274                                         bias-disable;
1275                                 };
1276                                 mclk1-pins {
1277                                         pins = "gpio27";
1278                                         function = "cam_mclk1";
1279                                         drive-strength = <16>;
1280                                         bias-disable;
1281                                 };
1282                         };
1283
1284                         camera_rear_default: camera-rear-default-state {
1285                                 pwdn-pins {
1286                                         pins = "gpio34";
1287                                         function = "gpio";
1288                                         drive-strength = <16>;
1289                                         bias-disable;
1290                                 };
1291                                 rst-pins {
1292                                         pins = "gpio35";
1293                                         function = "gpio";
1294                                         drive-strength = <16>;
1295                                         bias-disable;
1296                                 };
1297                                 mclk0-pins {
1298                                         pins = "gpio26";
1299                                         function = "cam_mclk0";
1300                                         drive-strength = <16>;
1301                                         bias-disable;
1302                                 };
1303                         };
1304
1305                         cci0_default: cci0-default-state {
1306                                 pins = "gpio29", "gpio30";
1307                                 function = "cci_i2c";
1308                                 drive-strength = <16>;
1309                                 bias-disable;
1310                         };
1311
1312                         cdc_dmic_default: cdc-dmic-default-state {
1313                                 clk-pins {
1314                                         pins = "gpio0";
1315                                         function = "dmic0_clk";
1316                                         drive-strength = <8>;
1317                                 };
1318                                 data-pins {
1319                                         pins = "gpio1";
1320                                         function = "dmic0_data";
1321                                         drive-strength = <8>;
1322                                 };
1323                         };
1324
1325                         cdc_dmic_sleep: cdc-dmic-sleep-state {
1326                                 clk-pins {
1327                                         pins = "gpio0";
1328                                         function = "dmic0_clk";
1329                                         drive-strength = <2>;
1330                                         bias-disable;
1331                                 };
1332                                 data-pins {
1333                                         pins = "gpio1";
1334                                         function = "dmic0_data";
1335                                         drive-strength = <2>;
1336                                         bias-disable;
1337                                 };
1338                         };
1339
1340                         cdc_pdm_default: cdc-pdm-default-state {
1341                                 pins = "gpio63", "gpio64", "gpio65", "gpio66",
1342                                        "gpio67", "gpio68";
1343                                 function = "cdc_pdm0";
1344                                 drive-strength = <8>;
1345                                 bias-disable;
1346                         };
1347
1348                         cdc_pdm_sleep: cdc-pdm-sleep-state {
1349                                 pins = "gpio63", "gpio64", "gpio65", "gpio66",
1350                                        "gpio67", "gpio68";
1351                                 function = "cdc_pdm0";
1352                                 drive-strength = <2>;
1353                                 bias-pull-down;
1354                         };
1355
1356                         pri_mi2s_default: mi2s-pri-default-state {
1357                                 pins = "gpio113", "gpio114", "gpio115", "gpio116";
1358                                 function = "pri_mi2s";
1359                                 drive-strength = <8>;
1360                                 bias-disable;
1361                         };
1362
1363                         pri_mi2s_sleep: mi2s-pri-sleep-state {
1364                                 pins = "gpio113", "gpio114", "gpio115", "gpio116";
1365                                 function = "pri_mi2s";
1366                                 drive-strength = <2>;
1367                                 bias-disable;
1368                         };
1369
1370                         pri_mi2s_mclk_default: mi2s-pri-mclk-default-state {
1371                                 pins = "gpio116";
1372                                 function = "pri_mi2s";
1373                                 drive-strength = <8>;
1374                                 bias-disable;
1375                         };
1376
1377                         pri_mi2s_mclk_sleep: mi2s-pri-mclk-sleep-state {
1378                                 pins = "gpio116";
1379                                 function = "pri_mi2s";
1380                                 drive-strength = <2>;
1381                                 bias-disable;
1382                         };
1383
1384                         pri_mi2s_ws_default: mi2s-pri-ws-default-state {
1385                                 pins = "gpio110";
1386                                 function = "pri_mi2s_ws";
1387                                 drive-strength = <8>;
1388                                 bias-disable;
1389                         };
1390
1391                         pri_mi2s_ws_sleep: mi2s-pri-ws-sleep-state {
1392                                 pins = "gpio110";
1393                                 function = "pri_mi2s_ws";
1394                                 drive-strength = <2>;
1395                                 bias-disable;
1396                         };
1397
1398                         sec_mi2s_default: mi2s-sec-default-state {
1399                                 pins = "gpio112", "gpio117", "gpio118", "gpio119";
1400                                 function = "sec_mi2s";
1401                                 drive-strength = <8>;
1402                                 bias-disable;
1403                         };
1404
1405                         sec_mi2s_sleep: mi2s-sec-sleep-state {
1406                                 pins = "gpio112", "gpio117", "gpio118", "gpio119";
1407                                 function = "sec_mi2s";
1408                                 drive-strength = <2>;
1409                                 bias-disable;
1410                         };
1411
1412                         sdc1_default: sdc1-default-state {
1413                                 clk-pins {
1414                                         pins = "sdc1_clk";
1415                                         bias-disable;
1416                                         drive-strength = <16>;
1417                                 };
1418                                 cmd-pins {
1419                                         pins = "sdc1_cmd";
1420                                         bias-pull-up;
1421                                         drive-strength = <10>;
1422                                 };
1423                                 data-pins {
1424                                         pins = "sdc1_data";
1425                                         bias-pull-up;
1426                                         drive-strength = <10>;
1427                                 };
1428                         };
1429
1430                         sdc1_sleep: sdc1-sleep-state {
1431                                 clk-pins {
1432                                         pins = "sdc1_clk";
1433                                         bias-disable;
1434                                         drive-strength = <2>;
1435                                 };
1436                                 cmd-pins {
1437                                         pins = "sdc1_cmd";
1438                                         bias-pull-up;
1439                                         drive-strength = <2>;
1440                                 };
1441                                 data-pins {
1442                                         pins = "sdc1_data";
1443                                         bias-pull-up;
1444                                         drive-strength = <2>;
1445                                 };
1446                         };
1447
1448                         sdc2_default: sdc2-default-state {
1449                                 clk-pins {
1450                                         pins = "sdc2_clk";
1451                                         bias-disable;
1452                                         drive-strength = <16>;
1453                                 };
1454                                 cmd-pins {
1455                                         pins = "sdc2_cmd";
1456                                         bias-pull-up;
1457                                         drive-strength = <10>;
1458                                 };
1459                                 data-pins {
1460                                         pins = "sdc2_data";
1461                                         bias-pull-up;
1462                                         drive-strength = <10>;
1463                                 };
1464                         };
1465
1466                         sdc2_sleep: sdc2-sleep-state {
1467                                 clk-pins {
1468                                         pins = "sdc2_clk";
1469                                         bias-disable;
1470                                         drive-strength = <2>;
1471                                 };
1472                                 cmd-pins {
1473                                         pins = "sdc2_cmd";
1474                                         bias-pull-up;
1475                                         drive-strength = <2>;
1476                                 };
1477                                 data-pins {
1478                                         pins = "sdc2_data";
1479                                         bias-pull-up;
1480                                         drive-strength = <2>;
1481                                 };
1482                         };
1483
1484                         wcss_wlan_default: wcss-wlan-default-state {
1485                                 pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44";
1486                                 function = "wcss_wlan";
1487                                 drive-strength = <6>;
1488                                 bias-pull-up;
1489                         };
1490                 };
1491
1492                 gcc: clock-controller@1800000 {
1493                         compatible = "qcom,gcc-msm8916";
1494                         #clock-cells = <1>;
1495                         #reset-cells = <1>;
1496                         #power-domain-cells = <1>;
1497                         reg = <0x01800000 0x80000>;
1498                         clocks = <&xo_board>,
1499                                  <&sleep_clk>,
1500                                  <&mdss_dsi0_phy 1>,
1501                                  <&mdss_dsi0_phy 0>,
1502                                  <0>,
1503                                  <0>,
1504                                  <0>;
1505                         clock-names = "xo",
1506                                       "sleep_clk",
1507                                       "dsi0pll",
1508                                       "dsi0pllbyte",
1509                                       "ext_mclk",
1510                                       "ext_pri_i2s",
1511                                       "ext_sec_i2s";
1512                 };
1513
1514                 tcsr_mutex: hwlock@1905000 {
1515                         compatible = "qcom,tcsr-mutex";
1516                         reg = <0x01905000 0x20000>;
1517                         #hwlock-cells = <1>;
1518                 };
1519
1520                 tcsr: syscon@1937000 {
1521                         compatible = "qcom,tcsr-msm8916", "syscon";
1522                         reg = <0x01937000 0x30000>;
1523                 };
1524
1525                 mdss: display-subsystem@1a00000 {
1526                         status = "disabled";
1527                         compatible = "qcom,mdss";
1528                         reg = <0x01a00000 0x1000>,
1529                               <0x01ac8000 0x3000>;
1530                         reg-names = "mdss_phys", "vbif_phys";
1531
1532                         power-domains = <&gcc MDSS_GDSC>;
1533
1534                         clocks = <&gcc GCC_MDSS_AHB_CLK>,
1535                                  <&gcc GCC_MDSS_AXI_CLK>,
1536                                  <&gcc GCC_MDSS_VSYNC_CLK>;
1537                         clock-names = "iface",
1538                                       "bus",
1539                                       "vsync";
1540
1541                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1542
1543                         interrupt-controller;
1544                         #interrupt-cells = <1>;
1545
1546                         #address-cells = <1>;
1547                         #size-cells = <1>;
1548                         ranges;
1549
1550                         mdss_mdp: display-controller@1a01000 {
1551                                 compatible = "qcom,msm8916-mdp5", "qcom,mdp5";
1552                                 reg = <0x01a01000 0x89000>;
1553                                 reg-names = "mdp_phys";
1554
1555                                 interrupt-parent = <&mdss>;
1556                                 interrupts = <0>;
1557
1558                                 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1559                                          <&gcc GCC_MDSS_AXI_CLK>,
1560                                          <&gcc GCC_MDSS_MDP_CLK>,
1561                                          <&gcc GCC_MDSS_VSYNC_CLK>;
1562                                 clock-names = "iface",
1563                                               "bus",
1564                                               "core",
1565                                               "vsync";
1566
1567                                 iommus = <&apps_iommu 4>;
1568
1569                                 ports {
1570                                         #address-cells = <1>;
1571                                         #size-cells = <0>;
1572
1573                                         port@0 {
1574                                                 reg = <0>;
1575                                                 mdss_mdp_intf1_out: endpoint {
1576                                                         remote-endpoint = <&mdss_dsi0_in>;
1577                                                 };
1578                                         };
1579                                 };
1580                         };
1581
1582                         mdss_dsi0: dsi@1a98000 {
1583                                 compatible = "qcom,msm8916-dsi-ctrl",
1584                                              "qcom,mdss-dsi-ctrl";
1585                                 reg = <0x01a98000 0x25c>;
1586                                 reg-names = "dsi_ctrl";
1587
1588                                 interrupt-parent = <&mdss>;
1589                                 interrupts = <4>;
1590
1591                                 assigned-clocks = <&gcc BYTE0_CLK_SRC>,
1592                                                   <&gcc PCLK0_CLK_SRC>;
1593                                 assigned-clock-parents = <&mdss_dsi0_phy 0>,
1594                                                          <&mdss_dsi0_phy 1>;
1595
1596                                 clocks = <&gcc GCC_MDSS_MDP_CLK>,
1597                                          <&gcc GCC_MDSS_AHB_CLK>,
1598                                          <&gcc GCC_MDSS_AXI_CLK>,
1599                                          <&gcc GCC_MDSS_BYTE0_CLK>,
1600                                          <&gcc GCC_MDSS_PCLK0_CLK>,
1601                                          <&gcc GCC_MDSS_ESC0_CLK>;
1602                                 clock-names = "mdp_core",
1603                                               "iface",
1604                                               "bus",
1605                                               "byte",
1606                                               "pixel",
1607                                               "core";
1608                                 phys = <&mdss_dsi0_phy>;
1609
1610                                 #address-cells = <1>;
1611                                 #size-cells = <0>;
1612
1613                                 ports {
1614                                         #address-cells = <1>;
1615                                         #size-cells = <0>;
1616
1617                                         port@0 {
1618                                                 reg = <0>;
1619                                                 mdss_dsi0_in: endpoint {
1620                                                         remote-endpoint = <&mdss_mdp_intf1_out>;
1621                                                 };
1622                                         };
1623
1624                                         port@1 {
1625                                                 reg = <1>;
1626                                                 mdss_dsi0_out: endpoint {
1627                                                 };
1628                                         };
1629                                 };
1630                         };
1631
1632                         mdss_dsi0_phy: phy@1a98300 {
1633                                 compatible = "qcom,dsi-phy-28nm-lp";
1634                                 reg = <0x01a98300 0xd4>,
1635                                       <0x01a98500 0x280>,
1636                                       <0x01a98780 0x30>;
1637                                 reg-names = "dsi_pll",
1638                                             "dsi_phy",
1639                                             "dsi_phy_regulator";
1640
1641                                 #clock-cells = <1>;
1642                                 #phy-cells = <0>;
1643
1644                                 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1645                                          <&xo_board>;
1646                                 clock-names = "iface", "ref";
1647                         };
1648                 };
1649
1650                 camss: camss@1b0ac00 {
1651                         compatible = "qcom,msm8916-camss";
1652                         reg = <0x01b0ac00 0x200>,
1653                                 <0x01b00030 0x4>,
1654                                 <0x01b0b000 0x200>,
1655                                 <0x01b00038 0x4>,
1656                                 <0x01b08000 0x100>,
1657                                 <0x01b08400 0x100>,
1658                                 <0x01b0a000 0x500>,
1659                                 <0x01b00020 0x10>,
1660                                 <0x01b10000 0x1000>;
1661                         reg-names = "csiphy0",
1662                                 "csiphy0_clk_mux",
1663                                 "csiphy1",
1664                                 "csiphy1_clk_mux",
1665                                 "csid0",
1666                                 "csid1",
1667                                 "ispif",
1668                                 "csi_clk_mux",
1669                                 "vfe0";
1670                         interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
1671                                 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
1672                                 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
1673                                 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
1674                                 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
1675                                 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
1676                         interrupt-names = "csiphy0",
1677                                 "csiphy1",
1678                                 "csid0",
1679                                 "csid1",
1680                                 "ispif",
1681                                 "vfe0";
1682                         power-domains = <&gcc VFE_GDSC>;
1683                         clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
1684                                 <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
1685                                 <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
1686                                 <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
1687                                 <&gcc GCC_CAMSS_CSI0_AHB_CLK>,
1688                                 <&gcc GCC_CAMSS_CSI0_CLK>,
1689                                 <&gcc GCC_CAMSS_CSI0PHY_CLK>,
1690                                 <&gcc GCC_CAMSS_CSI0PIX_CLK>,
1691                                 <&gcc GCC_CAMSS_CSI0RDI_CLK>,
1692                                 <&gcc GCC_CAMSS_CSI1_AHB_CLK>,
1693                                 <&gcc GCC_CAMSS_CSI1_CLK>,
1694                                 <&gcc GCC_CAMSS_CSI1PHY_CLK>,
1695                                 <&gcc GCC_CAMSS_CSI1PIX_CLK>,
1696                                 <&gcc GCC_CAMSS_CSI1RDI_CLK>,
1697                                 <&gcc GCC_CAMSS_AHB_CLK>,
1698                                 <&gcc GCC_CAMSS_VFE0_CLK>,
1699                                 <&gcc GCC_CAMSS_CSI_VFE0_CLK>,
1700                                 <&gcc GCC_CAMSS_VFE_AHB_CLK>,
1701                                 <&gcc GCC_CAMSS_VFE_AXI_CLK>;
1702                         clock-names = "top_ahb",
1703                                 "ispif_ahb",
1704                                 "csiphy0_timer",
1705                                 "csiphy1_timer",
1706                                 "csi0_ahb",
1707                                 "csi0",
1708                                 "csi0_phy",
1709                                 "csi0_pix",
1710                                 "csi0_rdi",
1711                                 "csi1_ahb",
1712                                 "csi1",
1713                                 "csi1_phy",
1714                                 "csi1_pix",
1715                                 "csi1_rdi",
1716                                 "ahb",
1717                                 "vfe0",
1718                                 "csi_vfe0",
1719                                 "vfe_ahb",
1720                                 "vfe_axi";
1721                         iommus = <&apps_iommu 3>;
1722                         status = "disabled";
1723                         ports {
1724                                 #address-cells = <1>;
1725                                 #size-cells = <0>;
1726
1727                                 port@0 {
1728                                         reg = <0>;
1729                                 };
1730
1731                                 port@1 {
1732                                         reg = <1>;
1733                                 };
1734                         };
1735                 };
1736
1737                 cci: cci@1b0c000 {
1738                         compatible = "qcom,msm8916-cci", "qcom,msm8226-cci";
1739                         #address-cells = <1>;
1740                         #size-cells = <0>;
1741                         reg = <0x01b0c000 0x1000>;
1742                         interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
1743                         clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
1744                                 <&gcc GCC_CAMSS_CCI_AHB_CLK>,
1745                                 <&gcc GCC_CAMSS_CCI_CLK>,
1746                                 <&gcc GCC_CAMSS_AHB_CLK>;
1747                         clock-names = "camss_top_ahb", "cci_ahb",
1748                                           "cci", "camss_ahb";
1749                         assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>,
1750                                           <&gcc GCC_CAMSS_CCI_CLK>;
1751                         assigned-clock-rates = <80000000>, <19200000>;
1752                         pinctrl-names = "default";
1753                         pinctrl-0 = <&cci0_default>;
1754                         status = "disabled";
1755
1756                         cci_i2c0: i2c-bus@0 {
1757                                 reg = <0>;
1758                                 clock-frequency = <400000>;
1759                                 #address-cells = <1>;
1760                                 #size-cells = <0>;
1761                         };
1762                 };
1763
1764                 gpu: gpu@1c00000 {
1765                         compatible = "qcom,adreno-306.0", "qcom,adreno";
1766                         reg = <0x01c00000 0x20000>;
1767                         reg-names = "kgsl_3d0_reg_memory";
1768                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1769                         interrupt-names = "kgsl_3d0_irq";
1770                         clock-names =
1771                             "core",
1772                             "iface",
1773                             "mem",
1774                             "mem_iface",
1775                             "alt_mem_iface",
1776                             "gfx3d";
1777                         clocks =
1778                             <&gcc GCC_OXILI_GFX3D_CLK>,
1779                             <&gcc GCC_OXILI_AHB_CLK>,
1780                             <&gcc GCC_OXILI_GMEM_CLK>,
1781                             <&gcc GCC_BIMC_GFX_CLK>,
1782                             <&gcc GCC_BIMC_GPU_CLK>,
1783                             <&gcc GFX3D_CLK_SRC>;
1784                         power-domains = <&gcc OXILI_GDSC>;
1785                         operating-points-v2 = <&gpu_opp_table>;
1786                         iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
1787                         status = "disabled";
1788
1789                         gpu_opp_table: opp-table {
1790                                 compatible = "operating-points-v2";
1791
1792                                 opp-400000000 {
1793                                         opp-hz = /bits/ 64 <400000000>;
1794                                 };
1795                                 opp-19200000 {
1796                                         opp-hz = /bits/ 64 <19200000>;
1797                                 };
1798                         };
1799                 };
1800
1801                 venus: video-codec@1d00000 {
1802                         compatible = "qcom,msm8916-venus";
1803                         reg = <0x01d00000 0xff000>;
1804                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1805                         power-domains = <&gcc VENUS_GDSC>;
1806                         clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>,
1807                                  <&gcc GCC_VENUS0_AHB_CLK>,
1808                                  <&gcc GCC_VENUS0_AXI_CLK>;
1809                         clock-names = "core", "iface", "bus";
1810                         iommus = <&apps_iommu 5>;
1811                         memory-region = <&venus_mem>;
1812                         status = "disabled";
1813
1814                         video-decoder {
1815                                 compatible = "venus-decoder";
1816                         };
1817
1818                         video-encoder {
1819                                 compatible = "venus-encoder";
1820                         };
1821                 };
1822
1823                 apps_iommu: iommu@1ef0000 {
1824                         #address-cells = <1>;
1825                         #size-cells = <1>;
1826                         #iommu-cells = <1>;
1827                         compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
1828                         ranges = <0 0x01e20000 0x20000>;
1829                         reg = <0x01ef0000 0x3000>;
1830                         clocks = <&gcc GCC_SMMU_CFG_CLK>,
1831                                  <&gcc GCC_APSS_TCU_CLK>;
1832                         clock-names = "iface", "bus";
1833                         qcom,iommu-secure-id = <17>;
1834
1835                         /* VFE */
1836                         iommu-ctx@3000 {
1837                                 compatible = "qcom,msm-iommu-v1-sec";
1838                                 reg = <0x3000 0x1000>;
1839                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1840                         };
1841
1842                         /* MDP_0 */
1843                         iommu-ctx@4000 {
1844                                 compatible = "qcom,msm-iommu-v1-ns";
1845                                 reg = <0x4000 0x1000>;
1846                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1847                         };
1848
1849                         /* VENUS_NS */
1850                         iommu-ctx@5000 {
1851                                 compatible = "qcom,msm-iommu-v1-sec";
1852                                 reg = <0x5000 0x1000>;
1853                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1854                         };
1855                 };
1856
1857                 gpu_iommu: iommu@1f08000 {
1858                         #address-cells = <1>;
1859                         #size-cells = <1>;
1860                         #iommu-cells = <1>;
1861                         compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
1862                         ranges = <0 0x01f08000 0x10000>;
1863                         clocks = <&gcc GCC_SMMU_CFG_CLK>,
1864                                  <&gcc GCC_GFX_TCU_CLK>;
1865                         clock-names = "iface", "bus";
1866                         qcom,iommu-secure-id = <18>;
1867
1868                         /* GFX3D_USER */
1869                         iommu-ctx@1000 {
1870                                 compatible = "qcom,msm-iommu-v1-ns";
1871                                 reg = <0x1000 0x1000>;
1872                                 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
1873                         };
1874
1875                         /* GFX3D_PRIV */
1876                         iommu-ctx@2000 {
1877                                 compatible = "qcom,msm-iommu-v1-ns";
1878                                 reg = <0x2000 0x1000>;
1879                                 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
1880                         };
1881                 };
1882
1883                 spmi_bus: spmi@200f000 {
1884                         compatible = "qcom,spmi-pmic-arb";
1885                         reg = <0x0200f000 0x001000>,
1886                               <0x02400000 0x400000>,
1887                               <0x02c00000 0x400000>,
1888                               <0x03800000 0x200000>,
1889                               <0x0200a000 0x002100>;
1890                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1891                         interrupt-names = "periph_irq";
1892                         interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1893                         qcom,ee = <0>;
1894                         qcom,channel = <0>;
1895                         #address-cells = <2>;
1896                         #size-cells = <0>;
1897                         interrupt-controller;
1898                         #interrupt-cells = <4>;
1899                 };
1900
1901                 bam_dmux_dma: dma-controller@4044000 {
1902                         compatible = "qcom,bam-v1.7.0";
1903                         reg = <0x04044000 0x19000>;
1904                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1905                         #dma-cells = <1>;
1906                         qcom,ee = <0>;
1907
1908                         num-channels = <6>;
1909                         qcom,num-ees = <1>;
1910                         qcom,powered-remotely;
1911
1912                         status = "disabled";
1913                 };
1914
1915                 mpss: remoteproc@4080000 {
1916                         compatible = "qcom,msm8916-mss-pil";
1917                         reg = <0x04080000 0x100>,
1918                               <0x04020000 0x040>;
1919
1920                         reg-names = "qdsp6", "rmb";
1921
1922                         interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
1923                                               <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1924                                               <&hexagon_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1925                                               <&hexagon_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1926                                               <&hexagon_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1927                         interrupt-names = "wdog", "fatal", "ready",
1928                                           "handover", "stop-ack";
1929
1930                         power-domains = <&rpmpd MSM8916_VDDCX>,
1931                                         <&rpmpd MSM8916_VDDMX>;
1932                         power-domain-names = "cx", "mx";
1933
1934                         clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1935                                  <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
1936                                  <&gcc GCC_BOOT_ROM_AHB_CLK>,
1937                                  <&xo_board>;
1938                         clock-names = "iface", "bus", "mem", "xo";
1939
1940                         qcom,smem-states = <&hexagon_smp2p_out 0>;
1941                         qcom,smem-state-names = "stop";
1942
1943                         resets = <&scm 0>;
1944                         reset-names = "mss_restart";
1945
1946                         qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
1947
1948                         status = "disabled";
1949
1950                         mba {
1951                                 memory-region = <&mba_mem>;
1952                         };
1953
1954                         mpss {
1955                                 memory-region = <&mpss_mem>;
1956                         };
1957
1958                         bam_dmux: bam-dmux {
1959                                 compatible = "qcom,bam-dmux";
1960
1961                                 interrupt-parent = <&hexagon_smsm>;
1962                                 interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>;
1963                                 interrupt-names = "pc", "pc-ack";
1964
1965                                 qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>;
1966                                 qcom,smem-state-names = "pc", "pc-ack";
1967
1968                                 dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>;
1969                                 dma-names = "tx", "rx";
1970
1971                                 status = "disabled";
1972                         };
1973
1974                         smd-edge {
1975                                 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
1976
1977                                 qcom,smd-edge = <0>;
1978                                 qcom,ipc = <&apcs 8 12>;
1979                                 qcom,remote-pid = <1>;
1980
1981                                 label = "hexagon";
1982
1983                                 fastrpc {
1984                                         compatible = "qcom,fastrpc";
1985                                         qcom,smd-channels = "fastrpcsmd-apps-dsp";
1986                                         label = "adsp";
1987                                         qcom,non-secure-domain;
1988
1989                                         #address-cells = <1>;
1990                                         #size-cells = <0>;
1991
1992                                         cb@1 {
1993                                                 compatible = "qcom,fastrpc-compute-cb";
1994                                                 reg = <1>;
1995                                         };
1996                                 };
1997                         };
1998                 };
1999
2000                 sound: sound@7702000 {
2001                         status = "disabled";
2002                         compatible = "qcom,apq8016-sbc-sndcard";
2003                         reg = <0x07702000 0x4>, <0x07702004 0x4>;
2004                         reg-names = "mic-iomux", "spkr-iomux";
2005                 };
2006
2007                 lpass: audio-controller@7708000 {
2008                         status = "disabled";
2009                         compatible = "qcom,apq8016-lpass-cpu";
2010
2011                         /*
2012                          * Note: Unlike the name would suggest, the SEC_I2S_CLK
2013                          * is actually only used by Tertiary MI2S while
2014                          * Primary/Secondary MI2S both use the PRI_I2S_CLK.
2015                          */
2016                         clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
2017                                  <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
2018                                  <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
2019                                  <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
2020                                  <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>,
2021                                  <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
2022                                  <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>;
2023
2024                         clock-names = "ahbix-clk",
2025                                         "mi2s-bit-clk0",
2026                                         "mi2s-bit-clk1",
2027                                         "mi2s-bit-clk2",
2028                                         "mi2s-bit-clk3",
2029                                         "pcnoc-mport-clk",
2030                                         "pcnoc-sway-clk";
2031                         #sound-dai-cells = <1>;
2032
2033                         interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
2034                         interrupt-names = "lpass-irq-lpaif";
2035                         reg = <0x07708000 0x10000>;
2036                         reg-names = "lpass-lpaif";
2037
2038                         #address-cells = <1>;
2039                         #size-cells = <0>;
2040                 };
2041
2042                 lpass_codec: audio-codec@771c000 {
2043                         compatible = "qcom,msm8916-wcd-digital-codec";
2044                         reg = <0x0771c000 0x400>;
2045                         clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
2046                                  <&gcc GCC_CODEC_DIGCODEC_CLK>;
2047                         clock-names = "ahbix-clk", "mclk";
2048                         #sound-dai-cells = <1>;
2049                         status = "disabled";
2050                 };
2051
2052                 sdhc_1: mmc@7824900 {
2053                         compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
2054                         reg = <0x07824900 0x11c>, <0x07824000 0x800>;
2055                         reg-names = "hc", "core";
2056
2057                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
2058                                      <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
2059                         interrupt-names = "hc_irq", "pwr_irq";
2060                         clocks = <&gcc GCC_SDCC1_AHB_CLK>,
2061                                  <&gcc GCC_SDCC1_APPS_CLK>,
2062                                  <&xo_board>;
2063                         clock-names = "iface", "core", "xo";
2064                         pinctrl-0 = <&sdc1_default>;
2065                         pinctrl-1 = <&sdc1_sleep>;
2066                         pinctrl-names = "default", "sleep";
2067                         mmc-ddr-1_8v;
2068                         bus-width = <8>;
2069                         non-removable;
2070                         status = "disabled";
2071                 };
2072
2073                 sdhc_2: mmc@7864900 {
2074                         compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
2075                         reg = <0x07864900 0x11c>, <0x07864000 0x800>;
2076                         reg-names = "hc", "core";
2077
2078                         interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
2079                                      <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
2080                         interrupt-names = "hc_irq", "pwr_irq";
2081                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2082                                  <&gcc GCC_SDCC2_APPS_CLK>,
2083                                  <&xo_board>;
2084                         clock-names = "iface", "core", "xo";
2085                         pinctrl-0 = <&sdc2_default>;
2086                         pinctrl-1 = <&sdc2_sleep>;
2087                         pinctrl-names = "default", "sleep";
2088                         bus-width = <4>;
2089                         status = "disabled";
2090                 };
2091
2092                 blsp_dma: dma-controller@7884000 {
2093                         compatible = "qcom,bam-v1.7.0";
2094                         reg = <0x07884000 0x23000>;
2095                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
2096                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
2097                         clock-names = "bam_clk";
2098                         #dma-cells = <1>;
2099                         qcom,ee = <0>;
2100                 };
2101
2102                 blsp_uart1: serial@78af000 {
2103                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2104                         reg = <0x078af000 0x200>;
2105                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
2106                         clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
2107                         clock-names = "core", "iface";
2108                         dmas = <&blsp_dma 0>, <&blsp_dma 1>;
2109                         dma-names = "tx", "rx";
2110                         pinctrl-names = "default", "sleep";
2111                         pinctrl-0 = <&blsp_uart1_default>;
2112                         pinctrl-1 = <&blsp_uart1_sleep>;
2113                         status = "disabled";
2114                 };
2115
2116                 blsp_uart2: serial@78b0000 {
2117                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2118                         reg = <0x078b0000 0x200>;
2119                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2120                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
2121                         clock-names = "core", "iface";
2122                         dmas = <&blsp_dma 2>, <&blsp_dma 3>;
2123                         dma-names = "tx", "rx";
2124                         pinctrl-names = "default", "sleep";
2125                         pinctrl-0 = <&blsp_uart2_default>;
2126                         pinctrl-1 = <&blsp_uart2_sleep>;
2127                         status = "disabled";
2128                 };
2129
2130                 blsp_i2c1: i2c@78b5000 {
2131                         compatible = "qcom,i2c-qup-v2.2.1";
2132                         reg = <0x078b5000 0x500>;
2133                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
2134                         clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
2135                                  <&gcc GCC_BLSP1_AHB_CLK>;
2136                         clock-names = "core", "iface";
2137                         dmas = <&blsp_dma 4>, <&blsp_dma 5>;
2138                         dma-names = "tx", "rx";
2139                         pinctrl-names = "default", "sleep";
2140                         pinctrl-0 = <&blsp_i2c1_default>;
2141                         pinctrl-1 = <&blsp_i2c1_sleep>;
2142                         #address-cells = <1>;
2143                         #size-cells = <0>;
2144                         status = "disabled";
2145                 };
2146
2147                 blsp_spi1: spi@78b5000 {
2148                         compatible = "qcom,spi-qup-v2.2.1";
2149                         reg = <0x078b5000 0x500>;
2150                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
2151                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
2152                                  <&gcc GCC_BLSP1_AHB_CLK>;
2153                         clock-names = "core", "iface";
2154                         dmas = <&blsp_dma 4>, <&blsp_dma 5>;
2155                         dma-names = "tx", "rx";
2156                         pinctrl-names = "default", "sleep";
2157                         pinctrl-0 = <&blsp_spi1_default>;
2158                         pinctrl-1 = <&blsp_spi1_sleep>;
2159                         #address-cells = <1>;
2160                         #size-cells = <0>;
2161                         status = "disabled";
2162                 };
2163
2164                 blsp_i2c2: i2c@78b6000 {
2165                         compatible = "qcom,i2c-qup-v2.2.1";
2166                         reg = <0x078b6000 0x500>;
2167                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
2168                         clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
2169                                  <&gcc GCC_BLSP1_AHB_CLK>;
2170                         clock-names = "core", "iface";
2171                         dmas = <&blsp_dma 6>, <&blsp_dma 7>;
2172                         dma-names = "tx", "rx";
2173                         pinctrl-names = "default", "sleep";
2174                         pinctrl-0 = <&blsp_i2c2_default>;
2175                         pinctrl-1 = <&blsp_i2c2_sleep>;
2176                         #address-cells = <1>;
2177                         #size-cells = <0>;
2178                         status = "disabled";
2179                 };
2180
2181                 blsp_spi2: spi@78b6000 {
2182                         compatible = "qcom,spi-qup-v2.2.1";
2183                         reg = <0x078b6000 0x500>;
2184                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
2185                         clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
2186                                  <&gcc GCC_BLSP1_AHB_CLK>;
2187                         clock-names = "core", "iface";
2188                         dmas = <&blsp_dma 6>, <&blsp_dma 7>;
2189                         dma-names = "tx", "rx";
2190                         pinctrl-names = "default", "sleep";
2191                         pinctrl-0 = <&blsp_spi2_default>;
2192                         pinctrl-1 = <&blsp_spi2_sleep>;
2193                         #address-cells = <1>;
2194                         #size-cells = <0>;
2195                         status = "disabled";
2196                 };
2197
2198                 blsp_i2c3: i2c@78b7000 {
2199                         compatible = "qcom,i2c-qup-v2.2.1";
2200                         reg = <0x078b7000 0x500>;
2201                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
2202                         clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
2203                                  <&gcc GCC_BLSP1_AHB_CLK>;
2204                         clock-names = "core", "iface";
2205                         dmas = <&blsp_dma 8>, <&blsp_dma 9>;
2206                         dma-names = "tx", "rx";
2207                         pinctrl-names = "default", "sleep";
2208                         pinctrl-0 = <&blsp_i2c3_default>;
2209                         pinctrl-1 = <&blsp_i2c3_sleep>;
2210                         #address-cells = <1>;
2211                         #size-cells = <0>;
2212                         status = "disabled";
2213                 };
2214
2215                 blsp_spi3: spi@78b7000 {
2216                         compatible = "qcom,spi-qup-v2.2.1";
2217                         reg = <0x078b7000 0x500>;
2218                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
2219                         clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
2220                                  <&gcc GCC_BLSP1_AHB_CLK>;
2221                         clock-names = "core", "iface";
2222                         dmas = <&blsp_dma 8>, <&blsp_dma 9>;
2223                         dma-names = "tx", "rx";
2224                         pinctrl-names = "default", "sleep";
2225                         pinctrl-0 = <&blsp_spi3_default>;
2226                         pinctrl-1 = <&blsp_spi3_sleep>;
2227                         #address-cells = <1>;
2228                         #size-cells = <0>;
2229                         status = "disabled";
2230                 };
2231
2232                 blsp_i2c4: i2c@78b8000 {
2233                         compatible = "qcom,i2c-qup-v2.2.1";
2234                         reg = <0x078b8000 0x500>;
2235                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
2236                         clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
2237                                  <&gcc GCC_BLSP1_AHB_CLK>;
2238                         clock-names = "core", "iface";
2239                         dmas = <&blsp_dma 10>, <&blsp_dma 11>;
2240                         dma-names = "tx", "rx";
2241                         pinctrl-names = "default", "sleep";
2242                         pinctrl-0 = <&blsp_i2c4_default>;
2243                         pinctrl-1 = <&blsp_i2c4_sleep>;
2244                         #address-cells = <1>;
2245                         #size-cells = <0>;
2246                         status = "disabled";
2247                 };
2248
2249                 blsp_spi4: spi@78b8000 {
2250                         compatible = "qcom,spi-qup-v2.2.1";
2251                         reg = <0x078b8000 0x500>;
2252                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
2253                         clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
2254                                  <&gcc GCC_BLSP1_AHB_CLK>;
2255                         clock-names = "core", "iface";
2256                         dmas = <&blsp_dma 10>, <&blsp_dma 11>;
2257                         dma-names = "tx", "rx";
2258                         pinctrl-names = "default", "sleep";
2259                         pinctrl-0 = <&blsp_spi4_default>;
2260                         pinctrl-1 = <&blsp_spi4_sleep>;
2261                         #address-cells = <1>;
2262                         #size-cells = <0>;
2263                         status = "disabled";
2264                 };
2265
2266                 blsp_i2c5: i2c@78b9000 {
2267                         compatible = "qcom,i2c-qup-v2.2.1";
2268                         reg = <0x078b9000 0x500>;
2269                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
2270                         clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
2271                                  <&gcc GCC_BLSP1_AHB_CLK>;
2272                         clock-names = "core", "iface";
2273                         dmas = <&blsp_dma 12>, <&blsp_dma 13>;
2274                         dma-names = "tx", "rx";
2275                         pinctrl-names = "default", "sleep";
2276                         pinctrl-0 = <&blsp_i2c5_default>;
2277                         pinctrl-1 = <&blsp_i2c5_sleep>;
2278                         #address-cells = <1>;
2279                         #size-cells = <0>;
2280                         status = "disabled";
2281                 };
2282
2283                 blsp_spi5: spi@78b9000 {
2284                         compatible = "qcom,spi-qup-v2.2.1";
2285                         reg = <0x078b9000 0x500>;
2286                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
2287                         clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
2288                                  <&gcc GCC_BLSP1_AHB_CLK>;
2289                         clock-names = "core", "iface";
2290                         dmas = <&blsp_dma 12>, <&blsp_dma 13>;
2291                         dma-names = "tx", "rx";
2292                         pinctrl-names = "default", "sleep";
2293                         pinctrl-0 = <&blsp_spi5_default>;
2294                         pinctrl-1 = <&blsp_spi5_sleep>;
2295                         #address-cells = <1>;
2296                         #size-cells = <0>;
2297                         status = "disabled";
2298                 };
2299
2300                 blsp_i2c6: i2c@78ba000 {
2301                         compatible = "qcom,i2c-qup-v2.2.1";
2302                         reg = <0x078ba000 0x500>;
2303                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
2304                         clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
2305                                  <&gcc GCC_BLSP1_AHB_CLK>;
2306                         clock-names = "core", "iface";
2307                         dmas = <&blsp_dma 14>, <&blsp_dma 15>;
2308                         dma-names = "tx", "rx";
2309                         pinctrl-names = "default", "sleep";
2310                         pinctrl-0 = <&blsp_i2c6_default>;
2311                         pinctrl-1 = <&blsp_i2c6_sleep>;
2312                         #address-cells = <1>;
2313                         #size-cells = <0>;
2314                         status = "disabled";
2315                 };
2316
2317                 blsp_spi6: spi@78ba000 {
2318                         compatible = "qcom,spi-qup-v2.2.1";
2319                         reg = <0x078ba000 0x500>;
2320                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
2321                         clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
2322                                  <&gcc GCC_BLSP1_AHB_CLK>;
2323                         clock-names = "core", "iface";
2324                         dmas = <&blsp_dma 14>, <&blsp_dma 15>;
2325                         dma-names = "tx", "rx";
2326                         pinctrl-names = "default", "sleep";
2327                         pinctrl-0 = <&blsp_spi6_default>;
2328                         pinctrl-1 = <&blsp_spi6_sleep>;
2329                         #address-cells = <1>;
2330                         #size-cells = <0>;
2331                         status = "disabled";
2332                 };
2333
2334                 usb: usb@78d9000 {
2335                         compatible = "qcom,ci-hdrc";
2336                         reg = <0x078d9000 0x200>,
2337                               <0x078d9200 0x200>;
2338                         interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
2339                                      <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
2340                         clocks = <&gcc GCC_USB_HS_AHB_CLK>,
2341                                  <&gcc GCC_USB_HS_SYSTEM_CLK>;
2342                         clock-names = "iface", "core";
2343                         assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
2344                         assigned-clock-rates = <80000000>;
2345                         resets = <&gcc GCC_USB_HS_BCR>;
2346                         reset-names = "core";
2347                         phy_type = "ulpi";
2348                         dr_mode = "otg";
2349                         hnp-disable;
2350                         srp-disable;
2351                         adp-disable;
2352                         ahb-burst-config = <0>;
2353                         phy-names = "usb-phy";
2354                         phys = <&usb_hs_phy>;
2355                         status = "disabled";
2356                         #reset-cells = <1>;
2357
2358                         ulpi {
2359                                 usb_hs_phy: phy {
2360                                         compatible = "qcom,usb-hs-phy-msm8916",
2361                                                      "qcom,usb-hs-phy";
2362                                         #phy-cells = <0>;
2363                                         clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
2364                                         clock-names = "ref", "sleep";
2365                                         resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
2366                                         reset-names = "phy", "por";
2367                                         qcom,init-seq = /bits/ 8 <0x0 0x44>,
2368                                                                  <0x1 0x6b>,
2369                                                                  <0x2 0x24>,
2370                                                                  <0x3 0x13>;
2371                                 };
2372                         };
2373                 };
2374
2375                 wcnss: remoteproc@a204000 {
2376                         compatible = "qcom,pronto-v2-pil", "qcom,pronto";
2377                         reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>;
2378                         reg-names = "ccu", "dxe", "pmu";
2379
2380                         memory-region = <&wcnss_mem>;
2381
2382                         interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
2383                                               <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2384                                               <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2385                                               <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2386                                               <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2387                         interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
2388
2389                         power-domains = <&rpmpd MSM8916_VDDCX>,
2390                                         <&rpmpd MSM8916_VDDMX>;
2391                         power-domain-names = "cx", "mx";
2392
2393                         qcom,smem-states = <&wcnss_smp2p_out 0>;
2394                         qcom,smem-state-names = "stop";
2395
2396                         pinctrl-names = "default";
2397                         pinctrl-0 = <&wcss_wlan_default>;
2398
2399                         status = "disabled";
2400
2401                         wcnss_iris: iris {
2402                                 /* Separate chip, compatible is board-specific */
2403                                 clocks = <&rpmcc RPM_SMD_RF_CLK2>;
2404                                 clock-names = "xo";
2405                         };
2406
2407                         smd-edge {
2408                                 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
2409
2410                                 qcom,ipc = <&apcs 8 17>;
2411                                 qcom,smd-edge = <6>;
2412                                 qcom,remote-pid = <4>;
2413
2414                                 label = "pronto";
2415
2416                                 wcnss_ctrl: wcnss {
2417                                         compatible = "qcom,wcnss";
2418                                         qcom,smd-channels = "WCNSS_CTRL";
2419
2420                                         qcom,mmio = <&wcnss>;
2421
2422                                         wcnss_bt: bluetooth {
2423                                                 compatible = "qcom,wcnss-bt";
2424                                         };
2425
2426                                         wcnss_wifi: wifi {
2427                                                 compatible = "qcom,wcnss-wlan";
2428
2429                                                 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
2430                                                              <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
2431                                                 interrupt-names = "tx", "rx";
2432
2433                                                 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
2434                                                 qcom,smem-state-names = "tx-enable", "tx-rings-empty";
2435                                         };
2436                                 };
2437                         };
2438                 };
2439
2440                 intc: interrupt-controller@b000000 {
2441                         compatible = "qcom,msm-qgic2";
2442                         interrupt-controller;
2443                         #interrupt-cells = <3>;
2444                         reg = <0x0b000000 0x1000>, <0x0b002000 0x2000>,
2445                               <0x0b001000 0x1000>, <0x0b004000 0x2000>;
2446                         interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
2447                 };
2448
2449                 apcs: mailbox@b011000 {
2450                         compatible = "qcom,msm8916-apcs-kpss-global", "syscon";
2451                         reg = <0x0b011000 0x1000>;
2452                         #mbox-cells = <1>;
2453                         clocks = <&a53pll>, <&gcc GPLL0_VOTE>;
2454                         clock-names = "pll", "aux";
2455                         #clock-cells = <0>;
2456                 };
2457
2458                 a53pll: clock@b016000 {
2459                         compatible = "qcom,msm8916-a53pll";
2460                         reg = <0x0b016000 0x40>;
2461                         #clock-cells = <0>;
2462                         clocks = <&xo_board>;
2463                         clock-names = "xo";
2464                 };
2465
2466                 timer@b020000 {
2467                         #address-cells = <1>;
2468                         #size-cells = <1>;
2469                         ranges;
2470                         compatible = "arm,armv7-timer-mem";
2471                         reg = <0x0b020000 0x1000>;
2472                         clock-frequency = <19200000>;
2473
2474                         frame@b021000 {
2475                                 frame-number = <0>;
2476                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
2477                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
2478                                 reg = <0x0b021000 0x1000>,
2479                                       <0x0b022000 0x1000>;
2480                         };
2481
2482                         frame@b023000 {
2483                                 frame-number = <1>;
2484                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
2485                                 reg = <0x0b023000 0x1000>;
2486                                 status = "disabled";
2487                         };
2488
2489                         frame@b024000 {
2490                                 frame-number = <2>;
2491                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
2492                                 reg = <0x0b024000 0x1000>;
2493                                 status = "disabled";
2494                         };
2495
2496                         frame@b025000 {
2497                                 frame-number = <3>;
2498                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
2499                                 reg = <0x0b025000 0x1000>;
2500                                 status = "disabled";
2501                         };
2502
2503                         frame@b026000 {
2504                                 frame-number = <4>;
2505                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
2506                                 reg = <0x0b026000 0x1000>;
2507                                 status = "disabled";
2508                         };
2509
2510                         frame@b027000 {
2511                                 frame-number = <5>;
2512                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
2513                                 reg = <0x0b027000 0x1000>;
2514                                 status = "disabled";
2515                         };
2516
2517                         frame@b028000 {
2518                                 frame-number = <6>;
2519                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
2520                                 reg = <0x0b028000 0x1000>;
2521                                 status = "disabled";
2522                         };
2523                 };
2524
2525                 cpu0_acc: power-manager@b088000 {
2526                         compatible = "qcom,msm8916-acc";
2527                         reg = <0x0b088000 0x1000>;
2528                         status = "reserved"; /* Controlled by PSCI firmware */
2529                 };
2530
2531                 cpu0_saw: power-manager@b089000 {
2532                         compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
2533                         reg = <0x0b089000 0x1000>;
2534                         status = "reserved"; /* Controlled by PSCI firmware */
2535                 };
2536
2537                 cpu1_acc: power-manager@b098000 {
2538                         compatible = "qcom,msm8916-acc";
2539                         reg = <0x0b098000 0x1000>;
2540                         status = "reserved"; /* Controlled by PSCI firmware */
2541                 };
2542
2543                 cpu1_saw: power-manager@b099000 {
2544                         compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
2545                         reg = <0x0b099000 0x1000>;
2546                         status = "reserved"; /* Controlled by PSCI firmware */
2547                 };
2548
2549                 cpu2_acc: power-manager@b0a8000 {
2550                         compatible = "qcom,msm8916-acc";
2551                         reg = <0x0b0a8000 0x1000>;
2552                         status = "reserved"; /* Controlled by PSCI firmware */
2553                 };
2554
2555                 cpu2_saw: power-manager@b0a9000 {
2556                         compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
2557                         reg = <0x0b0a9000 0x1000>;
2558                         status = "reserved"; /* Controlled by PSCI firmware */
2559                 };
2560
2561                 cpu3_acc: power-manager@b0b8000 {
2562                         compatible = "qcom,msm8916-acc";
2563                         reg = <0x0b0b8000 0x1000>;
2564                         status = "reserved"; /* Controlled by PSCI firmware */
2565                 };
2566
2567                 cpu3_saw: power-manager@b0b9000 {
2568                         compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
2569                         reg = <0x0b0b9000 0x1000>;
2570                         status = "reserved"; /* Controlled by PSCI firmware */
2571                 };
2572         };
2573
2574         thermal-zones {
2575                 cpu0-1-thermal {
2576                         polling-delay-passive = <250>;
2577                         polling-delay = <1000>;
2578
2579                         thermal-sensors = <&tsens 5>;
2580
2581                         trips {
2582                                 cpu0_1_alert0: trip-point0 {
2583                                         temperature = <75000>;
2584                                         hysteresis = <2000>;
2585                                         type = "passive";
2586                                 };
2587                                 cpu0_1_crit: cpu-crit {
2588                                         temperature = <110000>;
2589                                         hysteresis = <2000>;
2590                                         type = "critical";
2591                                 };
2592                         };
2593
2594                         cooling-maps {
2595                                 map0 {
2596                                         trip = <&cpu0_1_alert0>;
2597                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2598                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2599                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2600                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2601                                 };
2602                         };
2603                 };
2604
2605                 cpu2-3-thermal {
2606                         polling-delay-passive = <250>;
2607                         polling-delay = <1000>;
2608
2609                         thermal-sensors = <&tsens 4>;
2610
2611                         trips {
2612                                 cpu2_3_alert0: trip-point0 {
2613                                         temperature = <75000>;
2614                                         hysteresis = <2000>;
2615                                         type = "passive";
2616                                 };
2617                                 cpu2_3_crit: cpu-crit {
2618                                         temperature = <110000>;
2619                                         hysteresis = <2000>;
2620                                         type = "critical";
2621                                 };
2622                         };
2623
2624                         cooling-maps {
2625                                 map0 {
2626                                         trip = <&cpu2_3_alert0>;
2627                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2628                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2629                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2630                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2631                                 };
2632                         };
2633                 };
2634
2635                 gpu-thermal {
2636                         polling-delay-passive = <250>;
2637                         polling-delay = <1000>;
2638
2639                         thermal-sensors = <&tsens 2>;
2640
2641                         trips {
2642                                 gpu_alert0: trip-point0 {
2643                                         temperature = <75000>;
2644                                         hysteresis = <2000>;
2645                                         type = "passive";
2646                                 };
2647                                 gpu_crit: gpu-crit {
2648                                         temperature = <95000>;
2649                                         hysteresis = <2000>;
2650                                         type = "critical";
2651                                 };
2652                         };
2653                 };
2654
2655                 camera-thermal {
2656                         polling-delay-passive = <250>;
2657                         polling-delay = <1000>;
2658
2659                         thermal-sensors = <&tsens 1>;
2660
2661                         trips {
2662                                 cam_alert0: trip-point0 {
2663                                         temperature = <75000>;
2664                                         hysteresis = <2000>;
2665                                         type = "hot";
2666                                 };
2667                         };
2668                 };
2669
2670                 modem-thermal {
2671                         polling-delay-passive = <250>;
2672                         polling-delay = <1000>;
2673
2674                         thermal-sensors = <&tsens 0>;
2675
2676                         trips {
2677                                 modem_alert0: trip-point0 {
2678                                         temperature = <85000>;
2679                                         hysteresis = <2000>;
2680                                         type = "hot";
2681                                 };
2682                         };
2683                 };
2684         };
2685
2686         timer {
2687                 compatible = "arm,armv8-timer";
2688                 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2689                              <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2690                              <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2691                              <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
2692         };
2693 };