arch/arm64/boot/dts/qcom/msm8916.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <dt-bindings/arm/coresight-cti-dt.h>
   7 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
   8 #include <dt-bindings/clock/qcom,rpmcc.h>
   9 #include <dt-bindings/interconnect/qcom,msm8916.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/power/qcom-rpmpd.h>
  12 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
  13 #include <dt-bindings/soc/qcom,apr.h>
  14 #include <dt-bindings/thermal/thermal.h>
  15
  16 / {
  17         interrupt-parent = <&intc>;
  18
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         chosen { };
  23
  24         memory@80000000 {
  25                 device_type = "memory";
  26                 /* We expect the bootloader to fill in the reg */
  27                 reg = <0 0x80000000 0 0>;
  28         };
  29
  30         reserved-memory {
  31                 #address-cells = <2>;
  32                 #size-cells = <2>;
  33                 ranges;
  34
  35                 tz-apps@86000000 {
  36                         reg = <0x0 0x86000000 0x0 0x300000>;
  37                         no-map;
  38                 };
  39
  40                 smem@86300000 {
  41                         compatible = "qcom,smem";
  42                         reg = <0x0 0x86300000 0x0 0x100000>;
  43                         no-map;
  44
  45                         hwlocks = <&tcsr_mutex 3>;
  46                         qcom,rpm-msg-ram = <&rpm_msg_ram>;
  47                 };
  48
  49                 hypervisor@86400000 {
  50                         reg = <0x0 0x86400000 0x0 0x100000>;
  51                         no-map;
  52                 };
  53
  54                 tz@86500000 {
  55                         reg = <0x0 0x86500000 0x0 0x180000>;
  56                         no-map;
  57                 };
  58
  59                 reserved@86680000 {
  60                         reg = <0x0 0x86680000 0x0 0x80000>;
  61                         no-map;
  62                 };
  63
  64                 rmtfs@86700000 {
  65                         compatible = "qcom,rmtfs-mem";
  66                         reg = <0x0 0x86700000 0x0 0xe0000>;
  67                         no-map;
  68
  69                         qcom,client-id = <1>;
  70                 };
  71
  72                 rfsa@867e0000 {
  73                         reg = <0x0 0x867e0000 0x0 0x20000>;
  74                         no-map;
  75                 };
  76
  77                 mpss_mem: mpss@86800000 {
  78                         /*
  79                          * The memory region for the mpss firmware is generally
  80                          * relocatable and could be allocated dynamically.
  81                          * However, many firmware versions tend to fail when
  82                          * loaded to some special addresses, so it is hard to
  83                          * define reliable alloc-ranges.
  84                          *
  85                          * alignment = <0x0 0x400000>;
  86                          * alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
  87                          */
  88                         reg = <0x0 0x86800000 0x0 0>; /* size is device-specific */
  89                         no-map;
  90                         status = "disabled";
  91                 };
  92
  93                 wcnss_mem: wcnss {
  94                         size = <0x0 0x600000>;
  95                         alignment = <0x0 0x100000>;
  96                         alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
  97                         no-map;
  98                         status = "disabled";
  99                 };
 100
 101                 venus_mem: venus {
 102                         size = <0x0 0x500000>;
 103                         alignment = <0x0 0x100000>;
 104                         alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
 105                         no-map;
 106                         status = "disabled";
 107                 };
 108
 109                 mba_mem: mba {
 110                         size = <0x0 0x100000>;
 111                         alignment = <0x0 0x100000>;
 112                         alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
 113                         no-map;
 114                         status = "disabled";
 115                 };
 116         };
 117
 118         clocks {
 119                 xo_board: xo-board {
 120                         compatible = "fixed-clock";
 121                         #clock-cells = <0>;
 122                         clock-frequency = <19200000>;
 123                 };
 124
 125                 sleep_clk: sleep-clk {
 126                         compatible = "fixed-clock";
 127                         #clock-cells = <0>;
 128                         clock-frequency = <32768>;
 129                 };
 130         };
 131
 132         cpus {
 133                 #address-cells = <1>;
 134                 #size-cells = <0>;
 135
 136                 CPU0: cpu@0 {
 137                         device_type = "cpu";
 138                         compatible = "arm,cortex-a53";
 139                         reg = <0x0>;
 140                         next-level-cache = <&L2_0>;
 141                         enable-method = "psci";
 142                         clocks = <&apcs>;
 143                         operating-points-v2 = <&cpu_opp_table>;
 144                         #cooling-cells = <2>;
 145                         power-domains = <&CPU_PD0>;
 146                         power-domain-names = "psci";
 147                         qcom,acc = <&cpu0_acc>;
 148                         qcom,saw = <&cpu0_saw>;
 149                 };
 150
 151                 CPU1: cpu@1 {
 152                         device_type = "cpu";
 153                         compatible = "arm,cortex-a53";
 154                         reg = <0x1>;
 155                         next-level-cache = <&L2_0>;
 156                         enable-method = "psci";
 157                         clocks = <&apcs>;
 158                         operating-points-v2 = <&cpu_opp_table>;
 159                         #cooling-cells = <2>;
 160                         power-domains = <&CPU_PD1>;
 161                         power-domain-names = "psci";
 162                         qcom,acc = <&cpu1_acc>;
 163                         qcom,saw = <&cpu1_saw>;
 164                 };
 165
 166                 CPU2: cpu@2 {
 167                         device_type = "cpu";
 168                         compatible = "arm,cortex-a53";
 169                         reg = <0x2>;
 170                         next-level-cache = <&L2_0>;
 171                         enable-method = "psci";
 172                         clocks = <&apcs>;
 173                         operating-points-v2 = <&cpu_opp_table>;
 174                         #cooling-cells = <2>;
 175                         power-domains = <&CPU_PD2>;
 176                         power-domain-names = "psci";
 177                         qcom,acc = <&cpu2_acc>;
 178                         qcom,saw = <&cpu2_saw>;
 179                 };
 180
 181                 CPU3: cpu@3 {
 182                         device_type = "cpu";
 183                         compatible = "arm,cortex-a53";
 184                         reg = <0x3>;
 185                         next-level-cache = <&L2_0>;
 186                         enable-method = "psci";
 187                         clocks = <&apcs>;
 188                         operating-points-v2 = <&cpu_opp_table>;
 189                         #cooling-cells = <2>;
 190                         power-domains = <&CPU_PD3>;
 191                         power-domain-names = "psci";
 192                         qcom,acc = <&cpu3_acc>;
 193                         qcom,saw = <&cpu3_saw>;
 194                 };
 195
 196                 L2_0: l2-cache {
 197                         compatible = "cache";
 198                         cache-level = <2>;
 199                         cache-unified;
 200                 };
 201
 202                 idle-states {
 203                         entry-method = "psci";
 204
 205                         CPU_SLEEP_0: cpu-sleep-0 {
 206                                 compatible = "arm,idle-state";
 207                                 idle-state-name = "standalone-power-collapse";
 208                                 arm,psci-suspend-param = <0x40000002>;
 209                                 entry-latency-us = <130>;
 210                                 exit-latency-us = <150>;
 211                                 min-residency-us = <2000>;
 212                                 local-timer-stop;
 213                         };
 214                 };
 215
 216                 domain-idle-states {
 217
 218                         CLUSTER_RET: cluster-retention {
 219                                 compatible = "domain-idle-state";
 220                                 arm,psci-suspend-param = <0x41000012>;
 221                                 entry-latency-us = <500>;
 222                                 exit-latency-us = <500>;
 223                                 min-residency-us = <2000>;
 224                         };
 225
 226                         CLUSTER_PWRDN: cluster-gdhs {
 227                                 compatible = "domain-idle-state";
 228                                 arm,psci-suspend-param = <0x41000032>;
 229                                 entry-latency-us = <2000>;
 230                                 exit-latency-us = <2000>;
 231                                 min-residency-us = <6000>;
 232                         };
 233                 };
 234         };
 235
 236         cpu_opp_table: opp-table-cpu {
 237                 compatible = "operating-points-v2";
 238                 opp-shared;
 239
 240                 opp-200000000 {
 241                         opp-hz = /bits/ 64 <200000000>;
 242                 };
 243                 opp-400000000 {
 244                         opp-hz = /bits/ 64 <400000000>;
 245                 };
 246                 opp-800000000 {
 247                         opp-hz = /bits/ 64 <800000000>;
 248                 };
 249                 opp-998400000 {
 250                         opp-hz = /bits/ 64 <998400000>;
 251                 };
 252         };
 253
 254         firmware {
 255                 scm: scm {
 256                         compatible = "qcom,scm-msm8916", "qcom,scm";
 257                         clocks = <&gcc GCC_CRYPTO_CLK>,
 258                                  <&gcc GCC_CRYPTO_AXI_CLK>,
 259                                  <&gcc GCC_CRYPTO_AHB_CLK>;
 260                         clock-names = "core", "bus", "iface";
 261                         #reset-cells = <1>;
 262
 263                         qcom,dload-mode = <&tcsr 0x6100>;
 264                 };
 265         };
 266
 267         pmu {
 268                 compatible = "arm,cortex-a53-pmu";
 269                 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 270         };
 271
 272         psci {
 273                 compatible = "arm,psci-1.0";
 274                 method = "smc";
 275
 276                 CPU_PD0: power-domain-cpu0 {
 277                         #power-domain-cells = <0>;
 278                         power-domains = <&CLUSTER_PD>;
 279                         domain-idle-states = <&CPU_SLEEP_0>;
 280                 };
 281
 282                 CPU_PD1: power-domain-cpu1 {
 283                         #power-domain-cells = <0>;
 284                         power-domains = <&CLUSTER_PD>;
 285                         domain-idle-states = <&CPU_SLEEP_0>;
 286                 };
 287
 288                 CPU_PD2: power-domain-cpu2 {
 289                         #power-domain-cells = <0>;
 290                         power-domains = <&CLUSTER_PD>;
 291                         domain-idle-states = <&CPU_SLEEP_0>;
 292                 };
 293
 294                 CPU_PD3: power-domain-cpu3 {
 295                         #power-domain-cells = <0>;
 296                         power-domains = <&CLUSTER_PD>;
 297                         domain-idle-states = <&CPU_SLEEP_0>;
 298                 };
 299
 300                 CLUSTER_PD: power-domain-cluster {
 301                         #power-domain-cells = <0>;
 302                         domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>;
 303                 };
 304         };
 305
 306         rpm: remoteproc {
 307                 compatible = "qcom,msm8916-rpm-proc", "qcom,rpm-proc";
 308
 309                 smd-edge {
 310                         interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
 311                         qcom,ipc = <&apcs 8 0>;
 312                         qcom,smd-edge = <15>;
 313
 314                         rpm_requests: rpm-requests {
 315                                 compatible = "qcom,rpm-msm8916";
 316                                 qcom,smd-channels = "rpm_requests";
 317
 318                                 rpmcc: clock-controller {
 319                                         compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc";
 320                                         #clock-cells = <1>;
 321                                         clocks = <&xo_board>;
 322                                         clock-names = "xo";
 323                                 };
 324
 325                                 rpmpd: power-controller {
 326                                         compatible = "qcom,msm8916-rpmpd";
 327                                         #power-domain-cells = <1>;
 328                                         operating-points-v2 = <&rpmpd_opp_table>;
 329
 330                                         rpmpd_opp_table: opp-table {
 331                                                 compatible = "operating-points-v2";
 332
 333                                                 rpmpd_opp_ret: opp1 {
 334                                                         opp-level = <1>;
 335                                                 };
 336                                                 rpmpd_opp_svs_krait: opp2 {
 337                                                         opp-level = <2>;
 338                                                 };
 339                                                 rpmpd_opp_svs_soc: opp3 {
 340                                                         opp-level = <3>;
 341                                                 };
 342                                                 rpmpd_opp_nom: opp4 {
 343                                                         opp-level = <4>;
 344                                                 };
 345                                                 rpmpd_opp_turbo: opp5 {
 346                                                         opp-level = <5>;
 347                                                 };
 348                                                 rpmpd_opp_super_turbo: opp6 {
 349                                                         opp-level = <6>;
 350                                                 };
 351                                         };
 352                                 };
 353                         };
 354                 };
 355         };
 356
 357         smp2p-hexagon {
 358                 compatible = "qcom,smp2p";
 359                 qcom,smem = <435>, <428>;
 360
 361                 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
 362
 363                 qcom,ipc = <&apcs 8 14>;
 364
 365                 qcom,local-pid = <0>;
 366                 qcom,remote-pid = <1>;
 367
 368                 hexagon_smp2p_out: master-kernel {
 369                         qcom,entry-name = "master-kernel";
 370
 371                         #qcom,smem-state-cells = <1>;
 372                 };
 373
 374                 hexagon_smp2p_in: slave-kernel {
 375                         qcom,entry-name = "slave-kernel";
 376
 377                         interrupt-controller;
 378                         #interrupt-cells = <2>;
 379                 };
 380         };
 381
 382         smp2p-wcnss {
 383                 compatible = "qcom,smp2p";
 384                 qcom,smem = <451>, <431>;
 385
 386                 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
 387
 388                 qcom,ipc = <&apcs 8 18>;
 389
 390                 qcom,local-pid = <0>;
 391                 qcom,remote-pid = <4>;
 392
 393                 wcnss_smp2p_out: master-kernel {
 394                         qcom,entry-name = "master-kernel";
 395
 396                         #qcom,smem-state-cells = <1>;
 397                 };
 398
 399                 wcnss_smp2p_in: slave-kernel {
 400                         qcom,entry-name = "slave-kernel";
 401
 402                         interrupt-controller;
 403                         #interrupt-cells = <2>;
 404                 };
 405         };
 406
 407         smsm {
 408                 compatible = "qcom,smsm";
 409
 410                 #address-cells = <1>;
 411                 #size-cells = <0>;
 412
 413                 qcom,ipc-1 = <&apcs 8 13>;
 414                 qcom,ipc-3 = <&apcs 8 19>;
 415
 416                 apps_smsm: apps@0 {
 417                         reg = <0>;
 418
 419                         #qcom,smem-state-cells = <1>;
 420                 };
 421
 422                 hexagon_smsm: hexagon@1 {
 423                         reg = <1>;
 424                         interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
 425
 426                         interrupt-controller;
 427                         #interrupt-cells = <2>;
 428                 };
 429
 430                 wcnss_smsm: wcnss@6 {
 431                         reg = <6>;
 432                         interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
 433
 434                         interrupt-controller;
 435                         #interrupt-cells = <2>;
 436                 };
 437         };
 438
 439         soc: soc@0 {
 440                 #address-cells = <1>;
 441                 #size-cells = <1>;
 442                 ranges = <0 0 0 0xffffffff>;
 443                 compatible = "simple-bus";
 444
 445                 rng@22000 {
 446                         compatible = "qcom,prng";
 447                         reg = <0x00022000 0x200>;
 448                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 449                         clock-names = "core";
 450                 };
 451
 452                 restart@4ab000 {
 453                         compatible = "qcom,pshold";
 454                         reg = <0x004ab000 0x4>;
 455                 };
 456
 457                 qfprom: qfprom@5c000 {
 458                         compatible = "qcom,msm8916-qfprom", "qcom,qfprom";
 459                         reg = <0x0005c000 0x1000>;
 460                         #address-cells = <1>;
 461                         #size-cells = <1>;
 462
 463                         tsens_base1: base1@d0 {
 464                                 reg = <0xd0 0x1>;
 465                                 bits = <0 7>;
 466                         };
 467
 468                         tsens_s0_p1: s0-p1@d0 {
 469                                 reg = <0xd0 0x2>;
 470                                 bits = <7 5>;
 471                         };
 472
 473                         tsens_s0_p2: s0-p2@d1 {
 474                                 reg = <0xd1 0x2>;
 475                                 bits = <4 5>;
 476                         };
 477
 478                         tsens_s1_p1: s1-p1@d2 {
 479                                 reg = <0xd2 0x1>;
 480                                 bits = <1 5>;
 481                         };
 482                         tsens_s1_p2: s1-p2@d2 {
 483                                 reg = <0xd2 0x2>;
 484                                 bits = <6 5>;
 485                         };
 486                         tsens_s2_p1: s2-p1@d3 {
 487                                 reg = <0xd3 0x1>;
 488                                 bits = <3 5>;
 489                         };
 490
 491                         tsens_s2_p2: s2-p2@d4 {
 492                                 reg = <0xd4 0x1>;
 493                                 bits = <0 5>;
 494                         };
 495
 496                         // no tsens with hw_id 3
 497
 498                         tsens_s4_p1: s4-p1@d4 {
 499                                 reg = <0xd4 0x2>;
 500                                 bits = <5 5>;
 501                         };
 502
 503                         tsens_s4_p2: s4-p2@d5 {
 504                                 reg = <0xd5 0x1>;
 505                                 bits = <2 5>;
 506                         };
 507
 508                         tsens_s5_p1: s5-p1@d5 {
 509                                 reg = <0xd5 0x2>;
 510                                 bits = <7 5>;
 511                         };
 512
 513                         tsens_s5_p2: s5-p2@d6 {
 514                                 reg = <0xd6 0x2>;
 515                                 bits = <4 5>;
 516                         };
 517
 518                         tsens_base2: base2@d7 {
 519                                 reg = <0xd7 0x1>;
 520                                 bits = <1 7>;
 521                         };
 522
 523                         tsens_mode: mode@ef {
 524                                 reg = <0xef 0x1>;
 525                                 bits = <5 3>;
 526                         };
 527                 };
 528
 529                 rpm_msg_ram: sram@60000 {
 530                         compatible = "qcom,rpm-msg-ram";
 531                         reg = <0x00060000 0x8000>;
 532                 };
 533
 534                 sram@290000 {
 535                         compatible = "qcom,msm8916-rpm-stats";
 536                         reg = <0x00290000 0x10000>;
 537                 };
 538
 539                 bimc: interconnect@400000 {
 540                         compatible = "qcom,msm8916-bimc";
 541                         reg = <0x00400000 0x62000>;
 542                         #interconnect-cells = <1>;
 543                         clock-names = "bus", "bus_a";
 544                         clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
 545                                  <&rpmcc RPM_SMD_BIMC_A_CLK>;
 546                 };
 547
 548                 tsens: thermal-sensor@4a9000 {
 549                         compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1";
 550                         reg = <0x004a9000 0x1000>, /* TM */
 551                               <0x004a8000 0x1000>; /* SROT */
 552
 553                         // no hw_id 3
 554                         nvmem-cells = <&tsens_mode>,
 555                                       <&tsens_base1>, <&tsens_base2>,
 556                                       <&tsens_s0_p1>, <&tsens_s0_p2>,
 557                                       <&tsens_s1_p1>, <&tsens_s1_p2>,
 558                                       <&tsens_s2_p1>, <&tsens_s2_p2>,
 559                                       <&tsens_s4_p1>, <&tsens_s4_p2>,
 560                                       <&tsens_s5_p1>, <&tsens_s5_p2>;
 561                         nvmem-cell-names = "mode",
 562                                            "base1", "base2",
 563                                            "s0_p1", "s0_p2",
 564                                            "s1_p1", "s1_p2",
 565                                            "s2_p1", "s2_p2",
 566                                            "s4_p1", "s4_p2",
 567                                            "s5_p1", "s5_p2";
 568                         #qcom,sensors = <5>;
 569                         interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 570                         interrupt-names = "uplow";
 571                         #thermal-sensor-cells = <1>;
 572                 };
 573
 574                 pcnoc: interconnect@500000 {
 575                         compatible = "qcom,msm8916-pcnoc";
 576                         reg = <0x00500000 0x11000>;
 577                         #interconnect-cells = <1>;
 578                         clock-names = "bus", "bus_a";
 579                         clocks = <&rpmcc RPM_SMD_PCNOC_CLK>,
 580                                  <&rpmcc RPM_SMD_PCNOC_A_CLK>;
 581                 };
 582
 583                 snoc: interconnect@580000 {
 584                         compatible = "qcom,msm8916-snoc";
 585                         reg = <0x00580000 0x14000>;
 586                         #interconnect-cells = <1>;
 587                         clock-names = "bus", "bus_a";
 588                         clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
 589                                  <&rpmcc RPM_SMD_SNOC_A_CLK>;
 590                 };
 591
 592                 stm: stm@802000 {
 593                         compatible = "arm,coresight-stm", "arm,primecell";
 594                         reg = <0x00802000 0x1000>,
 595                               <0x09280000 0x180000>;
 596                         reg-names = "stm-base", "stm-stimulus-base";
 597
 598                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 599                         clock-names = "apb_pclk", "atclk";
 600
 601                         status = "disabled";
 602
 603                         out-ports {
 604                                 port {
 605                                         stm_out: endpoint {
 606                                                 remote-endpoint = <&funnel0_in7>;
 607                                         };
 608                                 };
 609                         };
 610                 };
 611
 612                 /* System CTIs */
 613                 /* CTI 0 - TMC connections */
 614                 cti0: cti@810000 {
 615                         compatible = "arm,coresight-cti", "arm,primecell";
 616                         reg = <0x00810000 0x1000>;
 617
 618                         clocks = <&rpmcc RPM_QDSS_CLK>;
 619                         clock-names = "apb_pclk";
 620
 621                         status = "disabled";
 622                 };
 623
 624                 /* CTI 1 - TPIU connections */
 625                 cti1: cti@811000 {
 626                         compatible = "arm,coresight-cti", "arm,primecell";
 627                         reg = <0x00811000 0x1000>;
 628
 629                         clocks = <&rpmcc RPM_QDSS_CLK>;
 630                         clock-names = "apb_pclk";
 631
 632                         status = "disabled";
 633                 };
 634
 635                 /* CTIs 2-11 - no information - not instantiated */
 636
 637                 tpiu: tpiu@820000 {
 638                         compatible = "arm,coresight-tpiu", "arm,primecell";
 639                         reg = <0x00820000 0x1000>;
 640
 641                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 642                         clock-names = "apb_pclk", "atclk";
 643
 644                         status = "disabled";
 645
 646                         in-ports {
 647                                 port {
 648                                         tpiu_in: endpoint {
 649                                                 remote-endpoint = <&replicator_out1>;
 650                                         };
 651                                 };
 652                         };
 653                 };
 654
 655                 funnel0: funnel@821000 {
 656                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 657                         reg = <0x00821000 0x1000>;
 658
 659                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 660                         clock-names = "apb_pclk", "atclk";
 661
 662                         status = "disabled";
 663
 664                         in-ports {
 665                                 #address-cells = <1>;
 666                                 #size-cells = <0>;
 667
 668                                 /*
 669                                  * Not described input ports:
 670                                  * 0 - connected to Resource and Power Manger CPU ETM
 671                                  * 1 - not-connected
 672                                  * 2 - connected to Modem CPU ETM
 673                                  * 3 - not-connected
 674                                  * 5 - not-connected
 675                                  * 6 - connected trought funnel to Wireless CPU ETM
 676                                  * 7 - connected to STM component
 677                                  */
 678
 679                                 port@4 {
 680                                         reg = <4>;
 681                                         funnel0_in4: endpoint {
 682                                                 remote-endpoint = <&funnel1_out>;
 683                                         };
 684                                 };
 685
 686                                 port@7 {
 687                                         reg = <7>;
 688                                         funnel0_in7: endpoint {
 689                                                 remote-endpoint = <&stm_out>;
 690                                         };
 691                                 };
 692                         };
 693
 694                         out-ports {
 695                                 port {
 696                                         funnel0_out: endpoint {
 697                                                 remote-endpoint = <&etf_in>;
 698                                         };
 699                                 };
 700                         };
 701                 };
 702
 703                 replicator: replicator@824000 {
 704                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
 705                         reg = <0x00824000 0x1000>;
 706
 707                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 708                         clock-names = "apb_pclk", "atclk";
 709
 710                         status = "disabled";
 711
 712                         out-ports {
 713                                 #address-cells = <1>;
 714                                 #size-cells = <0>;
 715
 716                                 port@0 {
 717                                         reg = <0>;
 718                                         replicator_out0: endpoint {
 719                                                 remote-endpoint = <&etr_in>;
 720                                         };
 721                                 };
 722                                 port@1 {
 723                                         reg = <1>;
 724                                         replicator_out1: endpoint {
 725                                                 remote-endpoint = <&tpiu_in>;
 726                                         };
 727                                 };
 728                         };
 729
 730                         in-ports {
 731                                 port {
 732                                         replicator_in: endpoint {
 733                                                 remote-endpoint = <&etf_out>;
 734                                         };
 735                                 };
 736                         };
 737                 };
 738
 739                 etf: etf@825000 {
 740                         compatible = "arm,coresight-tmc", "arm,primecell";
 741                         reg = <0x00825000 0x1000>;
 742
 743                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 744                         clock-names = "apb_pclk", "atclk";
 745
 746                         status = "disabled";
 747
 748                         in-ports {
 749                                 port {
 750                                         etf_in: endpoint {
 751                                                 remote-endpoint = <&funnel0_out>;
 752                                         };
 753                                 };
 754                         };
 755
 756                         out-ports {
 757                                 port {
 758                                         etf_out: endpoint {
 759                                                 remote-endpoint = <&replicator_in>;
 760                                         };
 761                                 };
 762                         };
 763                 };
 764
 765                 etr: etr@826000 {
 766                         compatible = "arm,coresight-tmc", "arm,primecell";
 767                         reg = <0x00826000 0x1000>;
 768
 769                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 770                         clock-names = "apb_pclk", "atclk";
 771
 772                         status = "disabled";
 773
 774                         in-ports {
 775                                 port {
 776                                         etr_in: endpoint {
 777                                                 remote-endpoint = <&replicator_out0>;
 778                                         };
 779                                 };
 780                         };
 781                 };
 782
 783                 funnel1: funnel@841000 {        /* APSS funnel only 4 inputs are used */
 784                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 785                         reg = <0x00841000 0x1000>;
 786
 787                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 788                         clock-names = "apb_pclk", "atclk";
 789
 790                         status = "disabled";
 791
 792                         in-ports {
 793                                 #address-cells = <1>;
 794                                 #size-cells = <0>;
 795
 796                                 port@0 {
 797                                         reg = <0>;
 798                                         funnel1_in0: endpoint {
 799                                                 remote-endpoint = <&etm0_out>;
 800                                         };
 801                                 };
 802                                 port@1 {
 803                                         reg = <1>;
 804                                         funnel1_in1: endpoint {
 805                                                 remote-endpoint = <&etm1_out>;
 806                                         };
 807                                 };
 808                                 port@2 {
 809                                         reg = <2>;
 810                                         funnel1_in2: endpoint {
 811                                                 remote-endpoint = <&etm2_out>;
 812                                         };
 813                                 };
 814                                 port@3 {
 815                                         reg = <3>;
 816                                         funnel1_in3: endpoint {
 817                                                 remote-endpoint = <&etm3_out>;
 818                                         };
 819                                 };
 820                         };
 821
 822                         out-ports {
 823                                 port {
 824                                         funnel1_out: endpoint {
 825                                                 remote-endpoint = <&funnel0_in4>;
 826                                         };
 827                                 };
 828                         };
 829                 };
 830
 831                 debug0: debug@850000 {
 832                         compatible = "arm,coresight-cpu-debug", "arm,primecell";
 833                         reg = <0x00850000 0x1000>;
 834                         clocks = <&rpmcc RPM_QDSS_CLK>;
 835                         clock-names = "apb_pclk";
 836                         cpu = <&CPU0>;
 837                         status = "disabled";
 838                 };
 839
 840                 debug1: debug@852000 {
 841                         compatible = "arm,coresight-cpu-debug", "arm,primecell";
 842                         reg = <0x00852000 0x1000>;
 843                         clocks = <&rpmcc RPM_QDSS_CLK>;
 844                         clock-names = "apb_pclk";
 845                         cpu = <&CPU1>;
 846                         status = "disabled";
 847                 };
 848
 849                 debug2: debug@854000 {
 850                         compatible = "arm,coresight-cpu-debug", "arm,primecell";
 851                         reg = <0x00854000 0x1000>;
 852                         clocks = <&rpmcc RPM_QDSS_CLK>;
 853                         clock-names = "apb_pclk";
 854                         cpu = <&CPU2>;
 855                         status = "disabled";
 856                 };
 857
 858                 debug3: debug@856000 {
 859                         compatible = "arm,coresight-cpu-debug", "arm,primecell";
 860                         reg = <0x00856000 0x1000>;
 861                         clocks = <&rpmcc RPM_QDSS_CLK>;
 862                         clock-names = "apb_pclk";
 863                         cpu = <&CPU3>;
 864                         status = "disabled";
 865                 };
 866
 867                 /* Core CTIs; CTIs 12-15 */
 868                 /* CTI - CPU-0 */
 869                 cti12: cti@858000 {
 870                         compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
 871                                      "arm,primecell";
 872                         reg = <0x00858000 0x1000>;
 873
 874                         clocks = <&rpmcc RPM_QDSS_CLK>;
 875                         clock-names = "apb_pclk";
 876
 877                         cpu = <&CPU0>;
 878                         arm,cs-dev-assoc = <&etm0>;
 879
 880                         status = "disabled";
 881                 };
 882
 883                 /* CTI - CPU-1 */
 884                 cti13: cti@859000 {
 885                         compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
 886                                      "arm,primecell";
 887                         reg = <0x00859000 0x1000>;
 888
 889                         clocks = <&rpmcc RPM_QDSS_CLK>;
 890                         clock-names = "apb_pclk";
 891
 892                         cpu = <&CPU1>;
 893                         arm,cs-dev-assoc = <&etm1>;
 894
 895                         status = "disabled";
 896                 };
 897
 898                 /* CTI - CPU-2 */
 899                 cti14: cti@85a000 {
 900                         compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
 901                                      "arm,primecell";
 902                         reg = <0x0085a000 0x1000>;
 903
 904                         clocks = <&rpmcc RPM_QDSS_CLK>;
 905                         clock-names = "apb_pclk";
 906
 907                         cpu = <&CPU2>;
 908                         arm,cs-dev-assoc = <&etm2>;
 909
 910                         status = "disabled";
 911                 };
 912
 913                 /* CTI - CPU-3 */
 914                 cti15: cti@85b000 {
 915                         compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
 916                                      "arm,primecell";
 917                         reg = <0x0085b000 0x1000>;
 918
 919                         clocks = <&rpmcc RPM_QDSS_CLK>;
 920                         clock-names = "apb_pclk";
 921
 922                         cpu = <&CPU3>;
 923                         arm,cs-dev-assoc = <&etm3>;
 924
 925                         status = "disabled";
 926                 };
 927
 928                 etm0: etm@85c000 {
 929                         compatible = "arm,coresight-etm4x", "arm,primecell";
 930                         reg = <0x0085c000 0x1000>;
 931
 932                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 933                         clock-names = "apb_pclk", "atclk";
 934                         arm,coresight-loses-context-with-cpu;
 935
 936                         cpu = <&CPU0>;
 937
 938                         status = "disabled";
 939
 940                         out-ports {
 941                                 port {
 942                                         etm0_out: endpoint {
 943                                                 remote-endpoint = <&funnel1_in0>;
 944                                         };
 945                                 };
 946                         };
 947                 };
 948
 949                 etm1: etm@85d000 {
 950                         compatible = "arm,coresight-etm4x", "arm,primecell";
 951                         reg = <0x0085d000 0x1000>;
 952
 953                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 954                         clock-names = "apb_pclk", "atclk";
 955                         arm,coresight-loses-context-with-cpu;
 956
 957                         cpu = <&CPU1>;
 958
 959                         status = "disabled";
 960
 961                         out-ports {
 962                                 port {
 963                                         etm1_out: endpoint {
 964                                                 remote-endpoint = <&funnel1_in1>;
 965                                         };
 966                                 };
 967                         };
 968                 };
 969
 970                 etm2: etm@85e000 {
 971                         compatible = "arm,coresight-etm4x", "arm,primecell";
 972                         reg = <0x0085e000 0x1000>;
 973
 974                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 975                         clock-names = "apb_pclk", "atclk";
 976                         arm,coresight-loses-context-with-cpu;
 977
 978                         cpu = <&CPU2>;
 979
 980                         status = "disabled";
 981
 982                         out-ports {
 983                                 port {
 984                                         etm2_out: endpoint {
 985                                                 remote-endpoint = <&funnel1_in2>;
 986                                         };
 987                                 };
 988                         };
 989                 };
 990
 991                 etm3: etm@85f000 {
 992                         compatible = "arm,coresight-etm4x", "arm,primecell";
 993                         reg = <0x0085f000 0x1000>;
 994
 995                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 996                         clock-names = "apb_pclk", "atclk";
 997                         arm,coresight-loses-context-with-cpu;
 998
 999                         cpu = <&CPU3>;
1000
1001                         status = "disabled";
1002
1003                         out-ports {
1004                                 port {
1005                                         etm3_out: endpoint {
1006                                                 remote-endpoint = <&funnel1_in3>;
1007                                         };
1008                                 };
1009                         };
1010                 };
1011
1012                 tlmm: pinctrl@1000000 {
1013                         compatible = "qcom,msm8916-pinctrl";
1014                         reg = <0x01000000 0x300000>;
1015                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1016                         gpio-controller;
1017                         gpio-ranges = <&tlmm 0 0 122>;
1018                         #gpio-cells = <2>;
1019                         interrupt-controller;
1020                         #interrupt-cells = <2>;
1021
1022                         blsp_i2c1_default: blsp-i2c1-default-state {
1023                                 pins = "gpio2", "gpio3";
1024                                 function = "blsp_i2c1";
1025                                 drive-strength = <2>;
1026                                 bias-disable;
1027                         };
1028
1029                         blsp_i2c1_sleep: blsp-i2c1-sleep-state {
1030                                 pins = "gpio2", "gpio3";
1031                                 function = "gpio";
1032                                 drive-strength = <2>;
1033                                 bias-disable;
1034                         };
1035
1036                         blsp_i2c2_default: blsp-i2c2-default-state {
1037                                 pins = "gpio6", "gpio7";
1038                                 function = "blsp_i2c2";
1039                                 drive-strength = <2>;
1040                                 bias-disable;
1041                         };
1042
1043                         blsp_i2c2_sleep: blsp-i2c2-sleep-state {
1044                                 pins = "gpio6", "gpio7";
1045                                 function = "gpio";
1046                                 drive-strength = <2>;
1047                                 bias-disable;
1048                         };
1049
1050                         blsp_i2c3_default: blsp-i2c3-default-state {
1051                                 pins = "gpio10", "gpio11";
1052                                 function = "blsp_i2c3";
1053                                 drive-strength = <2>;
1054                                 bias-disable;
1055                         };
1056
1057                         blsp_i2c3_sleep: blsp-i2c3-sleep-state {
1058                                 pins = "gpio10", "gpio11";
1059                                 function = "gpio";
1060                                 drive-strength = <2>;
1061                                 bias-disable;
1062                         };
1063
1064                         blsp_i2c4_default: blsp-i2c4-default-state {
1065                                 pins = "gpio14", "gpio15";
1066                                 function = "blsp_i2c4";
1067                                 drive-strength = <2>;
1068                                 bias-disable;
1069                         };
1070
1071                         blsp_i2c4_sleep: blsp-i2c4-sleep-state {
1072                                 pins = "gpio14", "gpio15";
1073                                 function = "gpio";
1074                                 drive-strength = <2>;
1075                                 bias-disable;
1076                         };
1077
1078                         blsp_i2c5_default: blsp-i2c5-default-state {
1079                                 pins = "gpio18", "gpio19";
1080                                 function = "blsp_i2c5";
1081                                 drive-strength = <2>;
1082                                 bias-disable;
1083                         };
1084
1085                         blsp_i2c5_sleep: blsp-i2c5-sleep-state {
1086                                 pins = "gpio18", "gpio19";
1087                                 function = "gpio";
1088                                 drive-strength = <2>;
1089                                 bias-disable;
1090                         };
1091
1092                         blsp_i2c6_default: blsp-i2c6-default-state {
1093                                 pins = "gpio22", "gpio23";
1094                                 function = "blsp_i2c6";
1095                                 drive-strength = <2>;
1096                                 bias-disable;
1097                         };
1098
1099                         blsp_i2c6_sleep: blsp-i2c6-sleep-state {
1100                                 pins = "gpio22", "gpio23";
1101                                 function = "gpio";
1102                                 drive-strength = <2>;
1103                                 bias-disable;
1104                         };
1105
1106                         blsp_spi1_default: blsp-spi1-default-state {
1107                                 spi-pins {
1108                                         pins = "gpio0", "gpio1", "gpio3";
1109                                         function = "blsp_spi1";
1110                                         drive-strength = <12>;
1111                                         bias-disable;
1112                                 };
1113                                 cs-pins {
1114                                         pins = "gpio2";
1115                                         function = "gpio";
1116                                         drive-strength = <16>;
1117                                         bias-disable;
1118                                         output-high;
1119                                 };
1120                         };
1121
1122                         blsp_spi1_sleep: blsp-spi1-sleep-state {
1123                                 pins = "gpio0", "gpio1", "gpio2", "gpio3";
1124                                 function = "gpio";
1125                                 drive-strength = <2>;
1126                                 bias-pull-down;
1127                         };
1128
1129                         blsp_spi2_default: blsp-spi2-default-state {
1130                                 spi-pins {
1131                                         pins = "gpio4", "gpio5", "gpio7";
1132                                         function = "blsp_spi2";
1133                                         drive-strength = <12>;
1134                                         bias-disable;
1135                                 };
1136                                 cs-pins {
1137                                         pins = "gpio6";
1138                                         function = "gpio";
1139                                         drive-strength = <16>;
1140                                         bias-disable;
1141                                         output-high;
1142                                 };
1143                         };
1144
1145                         blsp_spi2_sleep: blsp-spi2-sleep-state {
1146                                 pins = "gpio4", "gpio5", "gpio6", "gpio7";
1147                                 function = "gpio";
1148                                 drive-strength = <2>;
1149                                 bias-pull-down;
1150                         };
1151
1152                         blsp_spi3_default: blsp-spi3-default-state {
1153                                 spi-pins {
1154                                         pins = "gpio8", "gpio9", "gpio11";
1155                                         function = "blsp_spi3";
1156                                         drive-strength = <12>;
1157                                         bias-disable;
1158                                 };
1159                                 cs-pins {
1160                                         pins = "gpio10";
1161                                         function = "gpio";
1162                                         drive-strength = <16>;
1163                                         bias-disable;
1164                                         output-high;
1165                                 };
1166                         };
1167
1168                         blsp_spi3_sleep: blsp-spi3-sleep-state {
1169                                 pins = "gpio8", "gpio9", "gpio10", "gpio11";
1170                                 function = "gpio";
1171                                 drive-strength = <2>;
1172                                 bias-pull-down;
1173                         };
1174
1175                         blsp_spi4_default: blsp-spi4-default-state {
1176                                 spi-pins {
1177                                         pins = "gpio12", "gpio13", "gpio15";
1178                                         function = "blsp_spi4";
1179                                         drive-strength = <12>;
1180                                         bias-disable;
1181                                 };
1182                                 cs-pins {
1183                                         pins = "gpio14";
1184                                         function = "gpio";
1185                                         drive-strength = <16>;
1186                                         bias-disable;
1187                                         output-high;
1188                                 };
1189                         };
1190
1191                         blsp_spi4_sleep: blsp-spi4-sleep-state {
1192                                 pins = "gpio12", "gpio13", "gpio14", "gpio15";
1193                                 function = "gpio";
1194                                 drive-strength = <2>;
1195                                 bias-pull-down;
1196                         };
1197
1198                         blsp_spi5_default: blsp-spi5-default-state {
1199                                 spi-pins {
1200                                         pins = "gpio16", "gpio17", "gpio19";
1201                                         function = "blsp_spi5";
1202                                         drive-strength = <12>;
1203                                         bias-disable;
1204                                 };
1205                                 cs-pins {
1206                                         pins = "gpio18";
1207                                         function = "gpio";
1208                                         drive-strength = <16>;
1209                                         bias-disable;
1210                                         output-high;
1211                                 };
1212                         };
1213
1214                         blsp_spi5_sleep: blsp-spi5-sleep-state {
1215                                 pins = "gpio16", "gpio17", "gpio18", "gpio19";
1216                                 function = "gpio";
1217                                 drive-strength = <2>;
1218                                 bias-pull-down;
1219                         };
1220
1221                         blsp_spi6_default: blsp-spi6-default-state {
1222                                 spi-pins {
1223                                         pins = "gpio20", "gpio21", "gpio23";
1224                                         function = "blsp_spi6";
1225                                         drive-strength = <12>;
1226                                         bias-disable;
1227                                 };
1228                                 cs-pins {
1229                                         pins = "gpio22";
1230                                         function = "gpio";
1231                                         drive-strength = <16>;
1232                                         bias-disable;
1233                                         output-high;
1234                                 };
1235                         };
1236
1237                         blsp_spi6_sleep: blsp-spi6-sleep-state {
1238                                 pins = "gpio20", "gpio21", "gpio22", "gpio23";
1239                                 function = "gpio";
1240                                 drive-strength = <2>;
1241                                 bias-pull-down;
1242                         };
1243
1244                         blsp_uart1_default: blsp-uart1-default-state {
1245                                 /* TX, RX, CTS_N, RTS_N */
1246                                 pins = "gpio0", "gpio1", "gpio2", "gpio3";
1247                                 function = "blsp_uart1";
1248                                 drive-strength = <16>;
1249                                 bias-disable;
1250                         };
1251
1252                         blsp_uart1_sleep: blsp-uart1-sleep-state {
1253                                 pins = "gpio0", "gpio1", "gpio2", "gpio3";
1254                                 function = "gpio";
1255                                 drive-strength = <2>;
1256                                 bias-pull-down;
1257                         };
1258
1259                         blsp_uart2_default: blsp-uart2-default-state {
1260                                 pins = "gpio4", "gpio5";
1261                                 function = "blsp_uart2";
1262                                 drive-strength = <16>;
1263                                 bias-disable;
1264                         };
1265
1266                         blsp_uart2_sleep: blsp-uart2-sleep-state {
1267                                 pins = "gpio4", "gpio5";
1268                                 function = "gpio";
1269                                 drive-strength = <2>;
1270                                 bias-pull-down;
1271                         };
1272
1273                         camera_front_default: camera-front-default-state {
1274                                 pwdn-pins {
1275                                         pins = "gpio33";
1276                                         function = "gpio";
1277                                         drive-strength = <16>;
1278                                         bias-disable;
1279                                 };
1280                                 rst-pins {
1281                                         pins = "gpio28";
1282                                         function = "gpio";
1283                                         drive-strength = <16>;
1284                                         bias-disable;
1285                                 };
1286                                 mclk1-pins {
1287                                         pins = "gpio27";
1288                                         function = "cam_mclk1";
1289                                         drive-strength = <16>;
1290                                         bias-disable;
1291                                 };
1292                         };
1293
1294                         camera_rear_default: camera-rear-default-state {
1295                                 pwdn-pins {
1296                                         pins = "gpio34";
1297                                         function = "gpio";
1298                                         drive-strength = <16>;
1299                                         bias-disable;
1300                                 };
1301                                 rst-pins {
1302                                         pins = "gpio35";
1303                                         function = "gpio";
1304                                         drive-strength = <16>;
1305                                         bias-disable;
1306                                 };
1307                                 mclk0-pins {
1308                                         pins = "gpio26";
1309                                         function = "cam_mclk0";
1310                                         drive-strength = <16>;
1311                                         bias-disable;
1312                                 };
1313                         };
1314
1315                         cci0_default: cci0-default-state {
1316                                 pins = "gpio29", "gpio30";
1317                                 function = "cci_i2c";
1318                                 drive-strength = <16>;
1319                                 bias-disable;
1320                         };
1321
1322                         cdc_dmic_default: cdc-dmic-default-state {
1323                                 clk-pins {
1324                                         pins = "gpio0";
1325                                         function = "dmic0_clk";
1326                                         drive-strength = <8>;
1327                                 };
1328                                 data-pins {
1329                                         pins = "gpio1";
1330                                         function = "dmic0_data";
1331                                         drive-strength = <8>;
1332                                 };
1333                         };
1334
1335                         cdc_dmic_sleep: cdc-dmic-sleep-state {
1336                                 clk-pins {
1337                                         pins = "gpio0";
1338                                         function = "dmic0_clk";
1339                                         drive-strength = <2>;
1340                                         bias-disable;
1341                                 };
1342                                 data-pins {
1343                                         pins = "gpio1";
1344                                         function = "dmic0_data";
1345                                         drive-strength = <2>;
1346                                         bias-disable;
1347                                 };
1348                         };
1349
1350                         cdc_pdm_default: cdc-pdm-default-state {
1351                                 pins = "gpio63", "gpio64", "gpio65", "gpio66",
1352                                        "gpio67", "gpio68";
1353                                 function = "cdc_pdm0";
1354                                 drive-strength = <8>;
1355                                 bias-disable;
1356                         };
1357
1358                         cdc_pdm_sleep: cdc-pdm-sleep-state {
1359                                 pins = "gpio63", "gpio64", "gpio65", "gpio66",
1360                                        "gpio67", "gpio68";
1361                                 function = "cdc_pdm0";
1362                                 drive-strength = <2>;
1363                                 bias-pull-down;
1364                         };
1365
1366                         pri_mi2s_default: mi2s-pri-default-state {
1367                                 pins = "gpio113", "gpio114", "gpio115", "gpio116";
1368                                 function = "pri_mi2s";
1369                                 drive-strength = <8>;
1370                                 bias-disable;
1371                         };
1372
1373                         pri_mi2s_sleep: mi2s-pri-sleep-state {
1374                                 pins = "gpio113", "gpio114", "gpio115", "gpio116";
1375                                 function = "pri_mi2s";
1376                                 drive-strength = <2>;
1377                                 bias-disable;
1378                         };
1379
1380                         pri_mi2s_mclk_default: mi2s-pri-mclk-default-state {
1381                                 pins = "gpio116";
1382                                 function = "pri_mi2s";
1383                                 drive-strength = <8>;
1384                                 bias-disable;
1385                         };
1386
1387                         pri_mi2s_mclk_sleep: mi2s-pri-mclk-sleep-state {
1388                                 pins = "gpio116";
1389                                 function = "pri_mi2s";
1390                                 drive-strength = <2>;
1391                                 bias-disable;
1392                         };
1393
1394                         pri_mi2s_ws_default: mi2s-pri-ws-default-state {
1395                                 pins = "gpio110";
1396                                 function = "pri_mi2s_ws";
1397                                 drive-strength = <8>;
1398                                 bias-disable;
1399                         };
1400
1401                         pri_mi2s_ws_sleep: mi2s-pri-ws-sleep-state {
1402                                 pins = "gpio110";
1403                                 function = "pri_mi2s_ws";
1404                                 drive-strength = <2>;
1405                                 bias-disable;
1406                         };
1407
1408                         sec_mi2s_default: mi2s-sec-default-state {
1409                                 pins = "gpio112", "gpio117", "gpio118", "gpio119";
1410                                 function = "sec_mi2s";
1411                                 drive-strength = <8>;
1412                                 bias-disable;
1413                         };
1414
1415                         sec_mi2s_sleep: mi2s-sec-sleep-state {
1416                                 pins = "gpio112", "gpio117", "gpio118", "gpio119";
1417                                 function = "sec_mi2s";
1418                                 drive-strength = <2>;
1419                                 bias-disable;
1420                         };
1421
1422                         sdc1_default: sdc1-default-state {
1423                                 clk-pins {
1424                                         pins = "sdc1_clk";
1425                                         bias-disable;
1426                                         drive-strength = <16>;
1427                                 };
1428                                 cmd-pins {
1429                                         pins = "sdc1_cmd";
1430                                         bias-pull-up;
1431                                         drive-strength = <10>;
1432                                 };
1433                                 data-pins {
1434                                         pins = "sdc1_data";
1435                                         bias-pull-up;
1436                                         drive-strength = <10>;
1437                                 };
1438                         };
1439
1440                         sdc1_sleep: sdc1-sleep-state {
1441                                 clk-pins {
1442                                         pins = "sdc1_clk";
1443                                         bias-disable;
1444                                         drive-strength = <2>;
1445                                 };
1446                                 cmd-pins {
1447                                         pins = "sdc1_cmd";
1448                                         bias-pull-up;
1449                                         drive-strength = <2>;
1450                                 };
1451                                 data-pins {
1452                                         pins = "sdc1_data";
1453                                         bias-pull-up;
1454                                         drive-strength = <2>;
1455                                 };
1456                         };
1457
1458                         sdc2_default: sdc2-default-state {
1459                                 clk-pins {
1460                                         pins = "sdc2_clk";
1461                                         bias-disable;
1462                                         drive-strength = <16>;
1463                                 };
1464                                 cmd-pins {
1465                                         pins = "sdc2_cmd";
1466                                         bias-pull-up;
1467                                         drive-strength = <10>;
1468                                 };
1469                                 data-pins {
1470                                         pins = "sdc2_data";
1471                                         bias-pull-up;
1472                                         drive-strength = <10>;
1473                                 };
1474                         };
1475
1476                         sdc2_sleep: sdc2-sleep-state {
1477                                 clk-pins {
1478                                         pins = "sdc2_clk";
1479                                         bias-disable;
1480                                         drive-strength = <2>;
1481                                 };
1482                                 cmd-pins {
1483                                         pins = "sdc2_cmd";
1484                                         bias-pull-up;
1485                                         drive-strength = <2>;
1486                                 };
1487                                 data-pins {
1488                                         pins = "sdc2_data";
1489                                         bias-pull-up;
1490                                         drive-strength = <2>;
1491                                 };
1492                         };
1493
1494                         wcss_wlan_default: wcss-wlan-default-state {
1495                                 pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44";
1496                                 function = "wcss_wlan";
1497                                 drive-strength = <6>;
1498                                 bias-pull-up;
1499                         };
1500                 };
1501
1502                 gcc: clock-controller@1800000 {
1503                         compatible = "qcom,gcc-msm8916";
1504                         #clock-cells = <1>;
1505                         #reset-cells = <1>;
1506                         #power-domain-cells = <1>;
1507                         reg = <0x01800000 0x80000>;
1508                         clocks = <&xo_board>,
1509                                  <&sleep_clk>,
1510                                  <&mdss_dsi0_phy 1>,
1511                                  <&mdss_dsi0_phy 0>,
1512                                  <0>,
1513                                  <0>,
1514                                  <0>;
1515                         clock-names = "xo",
1516                                       "sleep_clk",
1517                                       "dsi0pll",
1518                                       "dsi0pllbyte",
1519                                       "ext_mclk",
1520                                       "ext_pri_i2s",
1521                                       "ext_sec_i2s";
1522                 };
1523
1524                 tcsr_mutex: hwlock@1905000 {
1525                         compatible = "qcom,tcsr-mutex";
1526                         reg = <0x01905000 0x20000>;
1527                         #hwlock-cells = <1>;
1528                 };
1529
1530                 tcsr: syscon@1937000 {
1531                         compatible = "qcom,tcsr-msm8916", "syscon";
1532                         reg = <0x01937000 0x30000>;
1533                 };
1534
1535                 mdss: display-subsystem@1a00000 {
1536                         status = "disabled";
1537                         compatible = "qcom,mdss";
1538                         reg = <0x01a00000 0x1000>,
1539                               <0x01ac8000 0x3000>;
1540                         reg-names = "mdss_phys", "vbif_phys";
1541
1542                         power-domains = <&gcc MDSS_GDSC>;
1543
1544                         clocks = <&gcc GCC_MDSS_AHB_CLK>,
1545                                  <&gcc GCC_MDSS_AXI_CLK>,
1546                                  <&gcc GCC_MDSS_VSYNC_CLK>;
1547                         clock-names = "iface",
1548                                       "bus",
1549                                       "vsync";
1550
1551                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1552
1553                         interrupt-controller;
1554                         #interrupt-cells = <1>;
1555
1556                         #address-cells = <1>;
1557                         #size-cells = <1>;
1558                         ranges;
1559
1560                         mdss_mdp: display-controller@1a01000 {
1561                                 compatible = "qcom,msm8916-mdp5", "qcom,mdp5";
1562                                 reg = <0x01a01000 0x89000>;
1563                                 reg-names = "mdp_phys";
1564
1565                                 interrupt-parent = <&mdss>;
1566                                 interrupts = <0>;
1567
1568                                 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1569                                          <&gcc GCC_MDSS_AXI_CLK>,
1570                                          <&gcc GCC_MDSS_MDP_CLK>,
1571                                          <&gcc GCC_MDSS_VSYNC_CLK>;
1572                                 clock-names = "iface",
1573                                               "bus",
1574                                               "core",
1575                                               "vsync";
1576
1577                                 iommus = <&apps_iommu 4>;
1578
1579                                 ports {
1580                                         #address-cells = <1>;
1581                                         #size-cells = <0>;
1582
1583                                         port@0 {
1584                                                 reg = <0>;
1585                                                 mdss_mdp_intf1_out: endpoint {
1586                                                         remote-endpoint = <&mdss_dsi0_in>;
1587                                                 };
1588                                         };
1589                                 };
1590                         };
1591
1592                         mdss_dsi0: dsi@1a98000 {
1593                                 compatible = "qcom,msm8916-dsi-ctrl",
1594                                              "qcom,mdss-dsi-ctrl";
1595                                 reg = <0x01a98000 0x25c>;
1596                                 reg-names = "dsi_ctrl";
1597
1598                                 interrupt-parent = <&mdss>;
1599                                 interrupts = <4>;
1600
1601                                 assigned-clocks = <&gcc BYTE0_CLK_SRC>,
1602                                                   <&gcc PCLK0_CLK_SRC>;
1603                                 assigned-clock-parents = <&mdss_dsi0_phy 0>,
1604                                                          <&mdss_dsi0_phy 1>;
1605
1606                                 clocks = <&gcc GCC_MDSS_MDP_CLK>,
1607                                          <&gcc GCC_MDSS_AHB_CLK>,
1608                                          <&gcc GCC_MDSS_AXI_CLK>,
1609                                          <&gcc GCC_MDSS_BYTE0_CLK>,
1610                                          <&gcc GCC_MDSS_PCLK0_CLK>,
1611                                          <&gcc GCC_MDSS_ESC0_CLK>;
1612                                 clock-names = "mdp_core",
1613                                               "iface",
1614                                               "bus",
1615                                               "byte",
1616                                               "pixel",
1617                                               "core";
1618                                 phys = <&mdss_dsi0_phy>;
1619
1620                                 #address-cells = <1>;
1621                                 #size-cells = <0>;
1622
1623                                 ports {
1624                                         #address-cells = <1>;
1625                                         #size-cells = <0>;
1626
1627                                         port@0 {
1628                                                 reg = <0>;
1629                                                 mdss_dsi0_in: endpoint {
1630                                                         remote-endpoint = <&mdss_mdp_intf1_out>;
1631                                                 };
1632                                         };
1633
1634                                         port@1 {
1635                                                 reg = <1>;
1636                                                 mdss_dsi0_out: endpoint {
1637                                                 };
1638                                         };
1639                                 };
1640                         };
1641
1642                         mdss_dsi0_phy: phy@1a98300 {
1643                                 compatible = "qcom,dsi-phy-28nm-lp";
1644                                 reg = <0x01a98300 0xd4>,
1645                                       <0x01a98500 0x280>,
1646                                       <0x01a98780 0x30>;
1647                                 reg-names = "dsi_pll",
1648                                             "dsi_phy",
1649                                             "dsi_phy_regulator";
1650
1651                                 #clock-cells = <1>;
1652                                 #phy-cells = <0>;
1653
1654                                 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1655                                          <&xo_board>;
1656                                 clock-names = "iface", "ref";
1657                         };
1658                 };
1659
1660                 camss: camss@1b0ac00 {
1661                         compatible = "qcom,msm8916-camss";
1662                         reg = <0x01b0ac00 0x200>,
1663                                 <0x01b00030 0x4>,
1664                                 <0x01b0b000 0x200>,
1665                                 <0x01b00038 0x4>,
1666                                 <0x01b08000 0x100>,
1667                                 <0x01b08400 0x100>,
1668                                 <0x01b0a000 0x500>,
1669                                 <0x01b00020 0x10>,
1670                                 <0x01b10000 0x1000>;
1671                         reg-names = "csiphy0",
1672                                 "csiphy0_clk_mux",
1673                                 "csiphy1",
1674                                 "csiphy1_clk_mux",
1675                                 "csid0",
1676                                 "csid1",
1677                                 "ispif",
1678                                 "csi_clk_mux",
1679                                 "vfe0";
1680                         interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
1681                                 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
1682                                 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
1683                                 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
1684                                 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
1685                                 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
1686                         interrupt-names = "csiphy0",
1687                                 "csiphy1",
1688                                 "csid0",
1689                                 "csid1",
1690                                 "ispif",
1691                                 "vfe0";
1692                         power-domains = <&gcc VFE_GDSC>;
1693                         clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
1694                                 <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
1695                                 <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
1696                                 <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
1697                                 <&gcc GCC_CAMSS_CSI0_AHB_CLK>,
1698                                 <&gcc GCC_CAMSS_CSI0_CLK>,
1699                                 <&gcc GCC_CAMSS_CSI0PHY_CLK>,
1700                                 <&gcc GCC_CAMSS_CSI0PIX_CLK>,
1701                                 <&gcc GCC_CAMSS_CSI0RDI_CLK>,
1702                                 <&gcc GCC_CAMSS_CSI1_AHB_CLK>,
1703                                 <&gcc GCC_CAMSS_CSI1_CLK>,
1704                                 <&gcc GCC_CAMSS_CSI1PHY_CLK>,
1705                                 <&gcc GCC_CAMSS_CSI1PIX_CLK>,
1706                                 <&gcc GCC_CAMSS_CSI1RDI_CLK>,
1707                                 <&gcc GCC_CAMSS_AHB_CLK>,
1708                                 <&gcc GCC_CAMSS_VFE0_CLK>,
1709                                 <&gcc GCC_CAMSS_CSI_VFE0_CLK>,
1710                                 <&gcc GCC_CAMSS_VFE_AHB_CLK>,
1711                                 <&gcc GCC_CAMSS_VFE_AXI_CLK>;
1712                         clock-names = "top_ahb",
1713                                 "ispif_ahb",
1714                                 "csiphy0_timer",
1715                                 "csiphy1_timer",
1716                                 "csi0_ahb",
1717                                 "csi0",
1718                                 "csi0_phy",
1719                                 "csi0_pix",
1720                                 "csi0_rdi",
1721                                 "csi1_ahb",
1722                                 "csi1",
1723                                 "csi1_phy",
1724                                 "csi1_pix",
1725                                 "csi1_rdi",
1726                                 "ahb",
1727                                 "vfe0",
1728                                 "csi_vfe0",
1729                                 "vfe_ahb",
1730                                 "vfe_axi";
1731                         iommus = <&apps_iommu 3>;
1732                         status = "disabled";
1733                         ports {
1734                                 #address-cells = <1>;
1735                                 #size-cells = <0>;
1736
1737                                 port@0 {
1738                                         reg = <0>;
1739                                 };
1740
1741                                 port@1 {
1742                                         reg = <1>;
1743                                 };
1744                         };
1745                 };
1746
1747                 cci: cci@1b0c000 {
1748                         compatible = "qcom,msm8916-cci", "qcom,msm8226-cci";
1749                         #address-cells = <1>;
1750                         #size-cells = <0>;
1751                         reg = <0x01b0c000 0x1000>;
1752                         interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
1753                         clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
1754                                 <&gcc GCC_CAMSS_CCI_AHB_CLK>,
1755                                 <&gcc GCC_CAMSS_CCI_CLK>,
1756                                 <&gcc GCC_CAMSS_AHB_CLK>;
1757                         clock-names = "camss_top_ahb", "cci_ahb",
1758                                           "cci", "camss_ahb";
1759                         assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>,
1760                                           <&gcc GCC_CAMSS_CCI_CLK>;
1761                         assigned-clock-rates = <80000000>, <19200000>;
1762                         pinctrl-names = "default";
1763                         pinctrl-0 = <&cci0_default>;
1764                         status = "disabled";
1765
1766                         cci_i2c0: i2c-bus@0 {
1767                                 reg = <0>;
1768                                 clock-frequency = <400000>;
1769                                 #address-cells = <1>;
1770                                 #size-cells = <0>;
1771                         };
1772                 };
1773
1774                 gpu: gpu@1c00000 {
1775                         compatible = "qcom,adreno-306.0", "qcom,adreno";
1776                         reg = <0x01c00000 0x20000>;
1777                         reg-names = "kgsl_3d0_reg_memory";
1778                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1779                         interrupt-names = "kgsl_3d0_irq";
1780                         clock-names =
1781                             "core",
1782                             "iface",
1783                             "mem",
1784                             "mem_iface",
1785                             "alt_mem_iface",
1786                             "gfx3d";
1787                         clocks =
1788                             <&gcc GCC_OXILI_GFX3D_CLK>,
1789                             <&gcc GCC_OXILI_AHB_CLK>,
1790                             <&gcc GCC_OXILI_GMEM_CLK>,
1791                             <&gcc GCC_BIMC_GFX_CLK>,
1792                             <&gcc GCC_BIMC_GPU_CLK>,
1793                             <&gcc GFX3D_CLK_SRC>;
1794                         power-domains = <&gcc OXILI_GDSC>;
1795                         operating-points-v2 = <&gpu_opp_table>;
1796                         iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
1797                         status = "disabled";
1798
1799                         gpu_opp_table: opp-table {
1800                                 compatible = "operating-points-v2";
1801
1802                                 opp-400000000 {
1803                                         opp-hz = /bits/ 64 <400000000>;
1804                                 };
1805                                 opp-19200000 {
1806                                         opp-hz = /bits/ 64 <19200000>;
1807                                 };
1808                         };
1809                 };
1810
1811                 venus: video-codec@1d00000 {
1812                         compatible = "qcom,msm8916-venus";
1813                         reg = <0x01d00000 0xff000>;
1814                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1815                         power-domains = <&gcc VENUS_GDSC>;
1816                         clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>,
1817                                  <&gcc GCC_VENUS0_AHB_CLK>,
1818                                  <&gcc GCC_VENUS0_AXI_CLK>;
1819                         clock-names = "core", "iface", "bus";
1820                         iommus = <&apps_iommu 5>;
1821                         memory-region = <&venus_mem>;
1822                         status = "disabled";
1823
1824                         video-decoder {
1825                                 compatible = "venus-decoder";
1826                         };
1827
1828                         video-encoder {
1829                                 compatible = "venus-encoder";
1830                         };
1831                 };
1832
1833                 apps_iommu: iommu@1ef0000 {
1834                         #address-cells = <1>;
1835                         #size-cells = <1>;
1836                         #iommu-cells = <1>;
1837                         compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
1838                         ranges = <0 0x01e20000 0x20000>;
1839                         reg = <0x01ef0000 0x3000>;
1840                         clocks = <&gcc GCC_SMMU_CFG_CLK>,
1841                                  <&gcc GCC_APSS_TCU_CLK>;
1842                         clock-names = "iface", "bus";
1843                         qcom,iommu-secure-id = <17>;
1844
1845                         /* VFE */
1846                         iommu-ctx@3000 {
1847                                 compatible = "qcom,msm-iommu-v1-sec";
1848                                 reg = <0x3000 0x1000>;
1849                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1850                         };
1851
1852                         /* MDP_0 */
1853                         iommu-ctx@4000 {
1854                                 compatible = "qcom,msm-iommu-v1-ns";
1855                                 reg = <0x4000 0x1000>;
1856                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1857                         };
1858
1859                         /* VENUS_NS */
1860                         iommu-ctx@5000 {
1861                                 compatible = "qcom,msm-iommu-v1-sec";
1862                                 reg = <0x5000 0x1000>;
1863                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1864                         };
1865                 };
1866
1867                 gpu_iommu: iommu@1f08000 {
1868                         #address-cells = <1>;
1869                         #size-cells = <1>;
1870                         #iommu-cells = <1>;
1871                         compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
1872                         ranges = <0 0x01f08000 0x10000>;
1873                         clocks = <&gcc GCC_SMMU_CFG_CLK>,
1874                                  <&gcc GCC_GFX_TCU_CLK>;
1875                         clock-names = "iface", "bus";
1876                         qcom,iommu-secure-id = <18>;
1877
1878                         /* GFX3D_USER */
1879                         iommu-ctx@1000 {
1880                                 compatible = "qcom,msm-iommu-v1-ns";
1881                                 reg = <0x1000 0x1000>;
1882                                 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
1883                         };
1884
1885                         /* GFX3D_PRIV */
1886                         iommu-ctx@2000 {
1887                                 compatible = "qcom,msm-iommu-v1-ns";
1888                                 reg = <0x2000 0x1000>;
1889                                 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
1890                         };
1891                 };
1892
1893                 spmi_bus: spmi@200f000 {
1894                         compatible = "qcom,spmi-pmic-arb";
1895                         reg = <0x0200f000 0x001000>,
1896                               <0x02400000 0x400000>,
1897                               <0x02c00000 0x400000>,
1898                               <0x03800000 0x200000>,
1899                               <0x0200a000 0x002100>;
1900                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1901                         interrupt-names = "periph_irq";
1902                         interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1903                         qcom,ee = <0>;
1904                         qcom,channel = <0>;
1905                         #address-cells = <2>;
1906                         #size-cells = <0>;
1907                         interrupt-controller;
1908                         #interrupt-cells = <4>;
1909                 };
1910
1911                 bam_dmux_dma: dma-controller@4044000 {
1912                         compatible = "qcom,bam-v1.7.0";
1913                         reg = <0x04044000 0x19000>;
1914                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1915                         #dma-cells = <1>;
1916                         qcom,ee = <0>;
1917
1918                         num-channels = <6>;
1919                         qcom,num-ees = <1>;
1920                         qcom,powered-remotely;
1921
1922                         status = "disabled";
1923                 };
1924
1925                 mpss: remoteproc@4080000 {
1926                         compatible = "qcom,msm8916-mss-pil";
1927                         reg = <0x04080000 0x100>,
1928                               <0x04020000 0x040>;
1929
1930                         reg-names = "qdsp6", "rmb";
1931
1932                         interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
1933                                               <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1934                                               <&hexagon_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1935                                               <&hexagon_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1936                                               <&hexagon_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1937                         interrupt-names = "wdog", "fatal", "ready",
1938                                           "handover", "stop-ack";
1939
1940                         power-domains = <&rpmpd MSM8916_VDDCX>,
1941                                         <&rpmpd MSM8916_VDDMX>;
1942                         power-domain-names = "cx", "mx";
1943
1944                         clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1945                                  <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
1946                                  <&gcc GCC_BOOT_ROM_AHB_CLK>,
1947                                  <&xo_board>;
1948                         clock-names = "iface", "bus", "mem", "xo";
1949
1950                         qcom,smem-states = <&hexagon_smp2p_out 0>;
1951                         qcom,smem-state-names = "stop";
1952
1953                         resets = <&scm 0>;
1954                         reset-names = "mss_restart";
1955
1956                         qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
1957
1958                         status = "disabled";
1959
1960                         mba {
1961                                 memory-region = <&mba_mem>;
1962                         };
1963
1964                         mpss {
1965                                 memory-region = <&mpss_mem>;
1966                         };
1967
1968                         bam_dmux: bam-dmux {
1969                                 compatible = "qcom,bam-dmux";
1970
1971                                 interrupt-parent = <&hexagon_smsm>;
1972                                 interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>;
1973                                 interrupt-names = "pc", "pc-ack";
1974
1975                                 qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>;
1976                                 qcom,smem-state-names = "pc", "pc-ack";
1977
1978                                 dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>;
1979                                 dma-names = "tx", "rx";
1980
1981                                 status = "disabled";
1982                         };
1983
1984                         smd-edge {
1985                                 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
1986
1987                                 qcom,smd-edge = <0>;
1988                                 qcom,ipc = <&apcs 8 12>;
1989                                 qcom,remote-pid = <1>;
1990
1991                                 label = "hexagon";
1992
1993                                 apr: apr {
1994                                         compatible = "qcom,apr-v2";
1995                                         qcom,smd-channels = "apr_audio_svc";
1996                                         qcom,domain = <APR_DOMAIN_ADSP>;
1997                                         #address-cells = <1>;
1998                                         #size-cells = <0>;
1999                                         status = "disabled";
2000
2001                                         q6core: service@3 {
2002                                                 compatible = "qcom,q6core";
2003                                                 reg = <APR_SVC_ADSP_CORE>;
2004                                         };
2005
2006                                         q6afe: service@4 {
2007                                                 compatible = "qcom,q6afe";
2008                                                 reg = <APR_SVC_AFE>;
2009
2010                                                 q6afedai: dais {
2011                                                         compatible = "qcom,q6afe-dais";
2012                                                         #address-cells = <1>;
2013                                                         #size-cells = <0>;
2014                                                         #sound-dai-cells = <1>;
2015                                                 };
2016                                         };
2017
2018                                         q6asm: service@7 {
2019                                                 compatible = "qcom,q6asm";
2020                                                 reg = <APR_SVC_ASM>;
2021
2022                                                 q6asmdai: dais {
2023                                                         compatible = "qcom,q6asm-dais";
2024                                                         #address-cells = <1>;
2025                                                         #size-cells = <0>;
2026                                                         #sound-dai-cells = <1>;
2027                                                 };
2028                                         };
2029
2030                                         q6adm: service@8 {
2031                                                 compatible = "qcom,q6adm";
2032                                                 reg = <APR_SVC_ADM>;
2033
2034                                                 q6routing: routing {
2035                                                         compatible = "qcom,q6adm-routing";
2036                                                         #sound-dai-cells = <0>;
2037                                                 };
2038                                         };
2039                                 };
2040
2041                                 fastrpc {
2042                                         compatible = "qcom,fastrpc";
2043                                         qcom,smd-channels = "fastrpcsmd-apps-dsp";
2044                                         label = "adsp";
2045                                         qcom,non-secure-domain;
2046
2047                                         #address-cells = <1>;
2048                                         #size-cells = <0>;
2049
2050                                         cb@1 {
2051                                                 compatible = "qcom,fastrpc-compute-cb";
2052                                                 reg = <1>;
2053                                         };
2054                                 };
2055                         };
2056                 };
2057
2058                 sound: sound@7702000 {
2059                         status = "disabled";
2060                         compatible = "qcom,apq8016-sbc-sndcard";
2061                         reg = <0x07702000 0x4>, <0x07702004 0x4>;
2062                         reg-names = "mic-iomux", "spkr-iomux";
2063                 };
2064
2065                 lpass: audio-controller@7708000 {
2066                         status = "disabled";
2067                         compatible = "qcom,apq8016-lpass-cpu";
2068
2069                         /*
2070                          * Note: Unlike the name would suggest, the SEC_I2S_CLK
2071                          * is actually only used by Tertiary MI2S while
2072                          * Primary/Secondary MI2S both use the PRI_I2S_CLK.
2073                          */
2074                         clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
2075                                  <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
2076                                  <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
2077                                  <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
2078                                  <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>,
2079                                  <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
2080                                  <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>;
2081
2082                         clock-names = "ahbix-clk",
2083                                         "mi2s-bit-clk0",
2084                                         "mi2s-bit-clk1",
2085                                         "mi2s-bit-clk2",
2086                                         "mi2s-bit-clk3",
2087                                         "pcnoc-mport-clk",
2088                                         "pcnoc-sway-clk";
2089                         #sound-dai-cells = <1>;
2090
2091                         interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
2092                         interrupt-names = "lpass-irq-lpaif";
2093                         reg = <0x07708000 0x10000>;
2094                         reg-names = "lpass-lpaif";
2095
2096                         #address-cells = <1>;
2097                         #size-cells = <0>;
2098                 };
2099
2100                 lpass_codec: audio-codec@771c000 {
2101                         compatible = "qcom,msm8916-wcd-digital-codec";
2102                         reg = <0x0771c000 0x400>;
2103                         clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
2104                                  <&gcc GCC_CODEC_DIGCODEC_CLK>;
2105                         clock-names = "ahbix-clk", "mclk";
2106                         #sound-dai-cells = <1>;
2107                         status = "disabled";
2108                 };
2109
2110                 sdhc_1: mmc@7824900 {
2111                         compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
2112                         reg = <0x07824900 0x11c>, <0x07824000 0x800>;
2113                         reg-names = "hc", "core";
2114
2115                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
2116                                      <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
2117                         interrupt-names = "hc_irq", "pwr_irq";
2118                         clocks = <&gcc GCC_SDCC1_AHB_CLK>,
2119                                  <&gcc GCC_SDCC1_APPS_CLK>,
2120                                  <&xo_board>;
2121                         clock-names = "iface", "core", "xo";
2122                         pinctrl-0 = <&sdc1_default>;
2123                         pinctrl-1 = <&sdc1_sleep>;
2124                         pinctrl-names = "default", "sleep";
2125                         mmc-ddr-1_8v;
2126                         bus-width = <8>;
2127                         non-removable;
2128                         status = "disabled";
2129                 };
2130
2131                 sdhc_2: mmc@7864900 {
2132                         compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
2133                         reg = <0x07864900 0x11c>, <0x07864000 0x800>;
2134                         reg-names = "hc", "core";
2135
2136                         interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
2137                                      <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
2138                         interrupt-names = "hc_irq", "pwr_irq";
2139                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2140                                  <&gcc GCC_SDCC2_APPS_CLK>,
2141                                  <&xo_board>;
2142                         clock-names = "iface", "core", "xo";
2143                         pinctrl-0 = <&sdc2_default>;
2144                         pinctrl-1 = <&sdc2_sleep>;
2145                         pinctrl-names = "default", "sleep";
2146                         bus-width = <4>;
2147                         status = "disabled";
2148                 };
2149
2150                 blsp_dma: dma-controller@7884000 {
2151                         compatible = "qcom,bam-v1.7.0";
2152                         reg = <0x07884000 0x23000>;
2153                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
2154                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
2155                         clock-names = "bam_clk";
2156                         #dma-cells = <1>;
2157                         qcom,ee = <0>;
2158                         qcom,controlled-remotely;
2159                 };
2160
2161                 blsp_uart1: serial@78af000 {
2162                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2163                         reg = <0x078af000 0x200>;
2164                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
2165                         clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
2166                         clock-names = "core", "iface";
2167                         dmas = <&blsp_dma 0>, <&blsp_dma 1>;
2168                         dma-names = "tx", "rx";
2169                         pinctrl-names = "default", "sleep";
2170                         pinctrl-0 = <&blsp_uart1_default>;
2171                         pinctrl-1 = <&blsp_uart1_sleep>;
2172                         status = "disabled";
2173                 };
2174
2175                 blsp_uart2: serial@78b0000 {
2176                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2177                         reg = <0x078b0000 0x200>;
2178                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2179                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
2180                         clock-names = "core", "iface";
2181                         dmas = <&blsp_dma 2>, <&blsp_dma 3>;
2182                         dma-names = "tx", "rx";
2183                         pinctrl-names = "default", "sleep";
2184                         pinctrl-0 = <&blsp_uart2_default>;
2185                         pinctrl-1 = <&blsp_uart2_sleep>;
2186                         status = "disabled";
2187                 };
2188
2189                 blsp_i2c1: i2c@78b5000 {
2190                         compatible = "qcom,i2c-qup-v2.2.1";
2191                         reg = <0x078b5000 0x500>;
2192                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
2193                         clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
2194                                  <&gcc GCC_BLSP1_AHB_CLK>;
2195                         clock-names = "core", "iface";
2196                         dmas = <&blsp_dma 4>, <&blsp_dma 5>;
2197                         dma-names = "tx", "rx";
2198                         pinctrl-names = "default", "sleep";
2199                         pinctrl-0 = <&blsp_i2c1_default>;
2200                         pinctrl-1 = <&blsp_i2c1_sleep>;
2201                         #address-cells = <1>;
2202                         #size-cells = <0>;
2203                         status = "disabled";
2204                 };
2205
2206                 blsp_spi1: spi@78b5000 {
2207                         compatible = "qcom,spi-qup-v2.2.1";
2208                         reg = <0x078b5000 0x500>;
2209                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
2210                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
2211                                  <&gcc GCC_BLSP1_AHB_CLK>;
2212                         clock-names = "core", "iface";
2213                         dmas = <&blsp_dma 4>, <&blsp_dma 5>;
2214                         dma-names = "tx", "rx";
2215                         pinctrl-names = "default", "sleep";
2216                         pinctrl-0 = <&blsp_spi1_default>;
2217                         pinctrl-1 = <&blsp_spi1_sleep>;
2218                         #address-cells = <1>;
2219                         #size-cells = <0>;
2220                         status = "disabled";
2221                 };
2222
2223                 blsp_i2c2: i2c@78b6000 {
2224                         compatible = "qcom,i2c-qup-v2.2.1";
2225                         reg = <0x078b6000 0x500>;
2226                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
2227                         clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
2228                                  <&gcc GCC_BLSP1_AHB_CLK>;
2229                         clock-names = "core", "iface";
2230                         dmas = <&blsp_dma 6>, <&blsp_dma 7>;
2231                         dma-names = "tx", "rx";
2232                         pinctrl-names = "default", "sleep";
2233                         pinctrl-0 = <&blsp_i2c2_default>;
2234                         pinctrl-1 = <&blsp_i2c2_sleep>;
2235                         #address-cells = <1>;
2236                         #size-cells = <0>;
2237                         status = "disabled";
2238                 };
2239
2240                 blsp_spi2: spi@78b6000 {
2241                         compatible = "qcom,spi-qup-v2.2.1";
2242                         reg = <0x078b6000 0x500>;
2243                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
2244                         clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
2245                                  <&gcc GCC_BLSP1_AHB_CLK>;
2246                         clock-names = "core", "iface";
2247                         dmas = <&blsp_dma 6>, <&blsp_dma 7>;
2248                         dma-names = "tx", "rx";
2249                         pinctrl-names = "default", "sleep";
2250                         pinctrl-0 = <&blsp_spi2_default>;
2251                         pinctrl-1 = <&blsp_spi2_sleep>;
2252                         #address-cells = <1>;
2253                         #size-cells = <0>;
2254                         status = "disabled";
2255                 };
2256
2257                 blsp_i2c3: i2c@78b7000 {
2258                         compatible = "qcom,i2c-qup-v2.2.1";
2259                         reg = <0x078b7000 0x500>;
2260                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
2261                         clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
2262                                  <&gcc GCC_BLSP1_AHB_CLK>;
2263                         clock-names = "core", "iface";
2264                         dmas = <&blsp_dma 8>, <&blsp_dma 9>;
2265                         dma-names = "tx", "rx";
2266                         pinctrl-names = "default", "sleep";
2267                         pinctrl-0 = <&blsp_i2c3_default>;
2268                         pinctrl-1 = <&blsp_i2c3_sleep>;
2269                         #address-cells = <1>;
2270                         #size-cells = <0>;
2271                         status = "disabled";
2272                 };
2273
2274                 blsp_spi3: spi@78b7000 {
2275                         compatible = "qcom,spi-qup-v2.2.1";
2276                         reg = <0x078b7000 0x500>;
2277                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
2278                         clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
2279                                  <&gcc GCC_BLSP1_AHB_CLK>;
2280                         clock-names = "core", "iface";
2281                         dmas = <&blsp_dma 8>, <&blsp_dma 9>;
2282                         dma-names = "tx", "rx";
2283                         pinctrl-names = "default", "sleep";
2284                         pinctrl-0 = <&blsp_spi3_default>;
2285                         pinctrl-1 = <&blsp_spi3_sleep>;
2286                         #address-cells = <1>;
2287                         #size-cells = <0>;
2288                         status = "disabled";
2289                 };
2290
2291                 blsp_i2c4: i2c@78b8000 {
2292                         compatible = "qcom,i2c-qup-v2.2.1";
2293                         reg = <0x078b8000 0x500>;
2294                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
2295                         clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
2296                                  <&gcc GCC_BLSP1_AHB_CLK>;
2297                         clock-names = "core", "iface";
2298                         dmas = <&blsp_dma 10>, <&blsp_dma 11>;
2299                         dma-names = "tx", "rx";
2300                         pinctrl-names = "default", "sleep";
2301                         pinctrl-0 = <&blsp_i2c4_default>;
2302                         pinctrl-1 = <&blsp_i2c4_sleep>;
2303                         #address-cells = <1>;
2304                         #size-cells = <0>;
2305                         status = "disabled";
2306                 };
2307
2308                 blsp_spi4: spi@78b8000 {
2309                         compatible = "qcom,spi-qup-v2.2.1";
2310                         reg = <0x078b8000 0x500>;
2311                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
2312                         clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
2313                                  <&gcc GCC_BLSP1_AHB_CLK>;
2314                         clock-names = "core", "iface";
2315                         dmas = <&blsp_dma 10>, <&blsp_dma 11>;
2316                         dma-names = "tx", "rx";
2317                         pinctrl-names = "default", "sleep";
2318                         pinctrl-0 = <&blsp_spi4_default>;
2319                         pinctrl-1 = <&blsp_spi4_sleep>;
2320                         #address-cells = <1>;
2321                         #size-cells = <0>;
2322                         status = "disabled";
2323                 };
2324
2325                 blsp_i2c5: i2c@78b9000 {
2326                         compatible = "qcom,i2c-qup-v2.2.1";
2327                         reg = <0x078b9000 0x500>;
2328                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
2329                         clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
2330                                  <&gcc GCC_BLSP1_AHB_CLK>;
2331                         clock-names = "core", "iface";
2332                         dmas = <&blsp_dma 12>, <&blsp_dma 13>;
2333                         dma-names = "tx", "rx";
2334                         pinctrl-names = "default", "sleep";
2335                         pinctrl-0 = <&blsp_i2c5_default>;
2336                         pinctrl-1 = <&blsp_i2c5_sleep>;
2337                         #address-cells = <1>;
2338                         #size-cells = <0>;
2339                         status = "disabled";
2340                 };
2341
2342                 blsp_spi5: spi@78b9000 {
2343                         compatible = "qcom,spi-qup-v2.2.1";
2344                         reg = <0x078b9000 0x500>;
2345                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
2346                         clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
2347                                  <&gcc GCC_BLSP1_AHB_CLK>;
2348                         clock-names = "core", "iface";
2349                         dmas = <&blsp_dma 12>, <&blsp_dma 13>;
2350                         dma-names = "tx", "rx";
2351                         pinctrl-names = "default", "sleep";
2352                         pinctrl-0 = <&blsp_spi5_default>;
2353                         pinctrl-1 = <&blsp_spi5_sleep>;
2354                         #address-cells = <1>;
2355                         #size-cells = <0>;
2356                         status = "disabled";
2357                 };
2358
2359                 blsp_i2c6: i2c@78ba000 {
2360                         compatible = "qcom,i2c-qup-v2.2.1";
2361                         reg = <0x078ba000 0x500>;
2362                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
2363                         clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
2364                                  <&gcc GCC_BLSP1_AHB_CLK>;
2365                         clock-names = "core", "iface";
2366                         dmas = <&blsp_dma 14>, <&blsp_dma 15>;
2367                         dma-names = "tx", "rx";
2368                         pinctrl-names = "default", "sleep";
2369                         pinctrl-0 = <&blsp_i2c6_default>;
2370                         pinctrl-1 = <&blsp_i2c6_sleep>;
2371                         #address-cells = <1>;
2372                         #size-cells = <0>;
2373                         status = "disabled";
2374                 };
2375
2376                 blsp_spi6: spi@78ba000 {
2377                         compatible = "qcom,spi-qup-v2.2.1";
2378                         reg = <0x078ba000 0x500>;
2379                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
2380                         clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
2381                                  <&gcc GCC_BLSP1_AHB_CLK>;
2382                         clock-names = "core", "iface";
2383                         dmas = <&blsp_dma 14>, <&blsp_dma 15>;
2384                         dma-names = "tx", "rx";
2385                         pinctrl-names = "default", "sleep";
2386                         pinctrl-0 = <&blsp_spi6_default>;
2387                         pinctrl-1 = <&blsp_spi6_sleep>;
2388                         #address-cells = <1>;
2389                         #size-cells = <0>;
2390                         status = "disabled";
2391                 };
2392
2393                 usb: usb@78d9000 {
2394                         compatible = "qcom,ci-hdrc";
2395                         reg = <0x078d9000 0x200>,
2396                               <0x078d9200 0x200>;
2397                         interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
2398                                      <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
2399                         clocks = <&gcc GCC_USB_HS_AHB_CLK>,
2400                                  <&gcc GCC_USB_HS_SYSTEM_CLK>;
2401                         clock-names = "iface", "core";
2402                         assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
2403                         assigned-clock-rates = <80000000>;
2404                         resets = <&gcc GCC_USB_HS_BCR>;
2405                         reset-names = "core";
2406                         phy_type = "ulpi";
2407                         dr_mode = "otg";
2408                         hnp-disable;
2409                         srp-disable;
2410                         adp-disable;
2411                         ahb-burst-config = <0>;
2412                         phy-names = "usb-phy";
2413                         phys = <&usb_hs_phy>;
2414                         status = "disabled";
2415                         #reset-cells = <1>;
2416
2417                         ulpi {
2418                                 usb_hs_phy: phy {
2419                                         compatible = "qcom,usb-hs-phy-msm8916",
2420                                                      "qcom,usb-hs-phy";
2421                                         #phy-cells = <0>;
2422                                         clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
2423                                         clock-names = "ref", "sleep";
2424                                         resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
2425                                         reset-names = "phy", "por";
2426                                         qcom,init-seq = /bits/ 8 <0x0 0x44>,
2427                                                                  <0x1 0x6b>,
2428                                                                  <0x2 0x24>,
2429                                                                  <0x3 0x13>;
2430                                 };
2431                         };
2432                 };
2433
2434                 wcnss: remoteproc@a204000 {
2435                         compatible = "qcom,pronto-v2-pil", "qcom,pronto";
2436                         reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>;
2437                         reg-names = "ccu", "dxe", "pmu";
2438
2439                         memory-region = <&wcnss_mem>;
2440
2441                         interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
2442                                               <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2443                                               <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2444                                               <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2445                                               <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2446                         interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
2447
2448                         power-domains = <&rpmpd MSM8916_VDDCX>,
2449                                         <&rpmpd MSM8916_VDDMX>;
2450                         power-domain-names = "cx", "mx";
2451
2452                         qcom,smem-states = <&wcnss_smp2p_out 0>;
2453                         qcom,smem-state-names = "stop";
2454
2455                         pinctrl-names = "default";
2456                         pinctrl-0 = <&wcss_wlan_default>;
2457
2458                         status = "disabled";
2459
2460                         wcnss_iris: iris {
2461                                 /* Separate chip, compatible is board-specific */
2462                                 clocks = <&rpmcc RPM_SMD_RF_CLK2>;
2463                                 clock-names = "xo";
2464                         };
2465
2466                         smd-edge {
2467                                 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
2468
2469                                 qcom,ipc = <&apcs 8 17>;
2470                                 qcom,smd-edge = <6>;
2471                                 qcom,remote-pid = <4>;
2472
2473                                 label = "pronto";
2474
2475                                 wcnss_ctrl: wcnss {
2476                                         compatible = "qcom,wcnss";
2477                                         qcom,smd-channels = "WCNSS_CTRL";
2478
2479                                         qcom,mmio = <&wcnss>;
2480
2481                                         wcnss_bt: bluetooth {
2482                                                 compatible = "qcom,wcnss-bt";
2483                                         };
2484
2485                                         wcnss_wifi: wifi {
2486                                                 compatible = "qcom,wcnss-wlan";
2487
2488                                                 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
2489                                                              <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
2490                                                 interrupt-names = "tx", "rx";
2491
2492                                                 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
2493                                                 qcom,smem-state-names = "tx-enable", "tx-rings-empty";
2494                                         };
2495                                 };
2496                         };
2497                 };
2498
2499                 intc: interrupt-controller@b000000 {
2500                         compatible = "qcom,msm-qgic2";
2501                         interrupt-controller;
2502                         #interrupt-cells = <3>;
2503                         reg = <0x0b000000 0x1000>, <0x0b002000 0x2000>,
2504                               <0x0b001000 0x1000>, <0x0b004000 0x2000>;
2505                         interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
2506                 };
2507
2508                 apcs: mailbox@b011000 {
2509                         compatible = "qcom,msm8916-apcs-kpss-global", "syscon";
2510                         reg = <0x0b011000 0x1000>;
2511                         #mbox-cells = <1>;
2512                         clocks = <&a53pll>, <&gcc GPLL0_VOTE>;
2513                         clock-names = "pll", "aux";
2514                         #clock-cells = <0>;
2515                 };
2516
2517                 a53pll: clock@b016000 {
2518                         compatible = "qcom,msm8916-a53pll";
2519                         reg = <0x0b016000 0x40>;
2520                         #clock-cells = <0>;
2521                         clocks = <&xo_board>;
2522                         clock-names = "xo";
2523                 };
2524
2525                 timer@b020000 {
2526                         #address-cells = <1>;
2527                         #size-cells = <1>;
2528                         ranges;
2529                         compatible = "arm,armv7-timer-mem";
2530                         reg = <0x0b020000 0x1000>;
2531                         clock-frequency = <19200000>;
2532
2533                         frame@b021000 {
2534                                 frame-number = <0>;
2535                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
2536                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
2537                                 reg = <0x0b021000 0x1000>,
2538                                       <0x0b022000 0x1000>;
2539                         };
2540
2541                         frame@b023000 {
2542                                 frame-number = <1>;
2543                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
2544                                 reg = <0x0b023000 0x1000>;
2545                                 status = "disabled";
2546                         };
2547
2548                         frame@b024000 {
2549                                 frame-number = <2>;
2550                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
2551                                 reg = <0x0b024000 0x1000>;
2552                                 status = "disabled";
2553                         };
2554
2555                         frame@b025000 {
2556                                 frame-number = <3>;
2557                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
2558                                 reg = <0x0b025000 0x1000>;
2559                                 status = "disabled";
2560                         };
2561
2562                         frame@b026000 {
2563                                 frame-number = <4>;
2564                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
2565                                 reg = <0x0b026000 0x1000>;
2566                                 status = "disabled";
2567                         };
2568
2569                         frame@b027000 {
2570                                 frame-number = <5>;
2571                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
2572                                 reg = <0x0b027000 0x1000>;
2573                                 status = "disabled";
2574                         };
2575
2576                         frame@b028000 {
2577                                 frame-number = <6>;
2578                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
2579                                 reg = <0x0b028000 0x1000>;
2580                                 status = "disabled";
2581                         };
2582                 };
2583
2584                 cpu0_acc: power-manager@b088000 {
2585                         compatible = "qcom,msm8916-acc";
2586                         reg = <0x0b088000 0x1000>;
2587                         status = "reserved"; /* Controlled by PSCI firmware */
2588                 };
2589
2590                 cpu0_saw: power-manager@b089000 {
2591                         compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
2592                         reg = <0x0b089000 0x1000>;
2593                         status = "reserved"; /* Controlled by PSCI firmware */
2594                 };
2595
2596                 cpu1_acc: power-manager@b098000 {
2597                         compatible = "qcom,msm8916-acc";
2598                         reg = <0x0b098000 0x1000>;
2599                         status = "reserved"; /* Controlled by PSCI firmware */
2600                 };
2601
2602                 cpu1_saw: power-manager@b099000 {
2603                         compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
2604                         reg = <0x0b099000 0x1000>;
2605                         status = "reserved"; /* Controlled by PSCI firmware */
2606                 };
2607
2608                 cpu2_acc: power-manager@b0a8000 {
2609                         compatible = "qcom,msm8916-acc";
2610                         reg = <0x0b0a8000 0x1000>;
2611                         status = "reserved"; /* Controlled by PSCI firmware */
2612                 };
2613
2614                 cpu2_saw: power-manager@b0a9000 {
2615                         compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
2616                         reg = <0x0b0a9000 0x1000>;
2617                         status = "reserved"; /* Controlled by PSCI firmware */
2618                 };
2619
2620                 cpu3_acc: power-manager@b0b8000 {
2621                         compatible = "qcom,msm8916-acc";
2622                         reg = <0x0b0b8000 0x1000>;
2623                         status = "reserved"; /* Controlled by PSCI firmware */
2624                 };
2625
2626                 cpu3_saw: power-manager@b0b9000 {
2627                         compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
2628                         reg = <0x0b0b9000 0x1000>;
2629                         status = "reserved"; /* Controlled by PSCI firmware */
2630                 };
2631         };
2632
2633         thermal-zones {
2634                 cpu0-1-thermal {
2635                         polling-delay-passive = <250>;
2636                         polling-delay = <1000>;
2637
2638                         thermal-sensors = <&tsens 5>;
2639
2640                         trips {
2641                                 cpu0_1_alert0: trip-point0 {
2642                                         temperature = <75000>;
2643                                         hysteresis = <2000>;
2644                                         type = "passive";
2645                                 };
2646                                 cpu0_1_crit: cpu-crit {
2647                                         temperature = <110000>;
2648                                         hysteresis = <2000>;
2649                                         type = "critical";
2650                                 };
2651                         };
2652
2653                         cooling-maps {
2654                                 map0 {
2655                                         trip = <&cpu0_1_alert0>;
2656                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2657                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2658                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2659                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2660                                 };
2661                         };
2662                 };
2663
2664                 cpu2-3-thermal {
2665                         polling-delay-passive = <250>;
2666                         polling-delay = <1000>;
2667
2668                         thermal-sensors = <&tsens 4>;
2669
2670                         trips {
2671                                 cpu2_3_alert0: trip-point0 {
2672                                         temperature = <75000>;
2673                                         hysteresis = <2000>;
2674                                         type = "passive";
2675                                 };
2676                                 cpu2_3_crit: cpu-crit {
2677                                         temperature = <110000>;
2678                                         hysteresis = <2000>;
2679                                         type = "critical";
2680                                 };
2681                         };
2682
2683                         cooling-maps {
2684                                 map0 {
2685                                         trip = <&cpu2_3_alert0>;
2686                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2687                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2688                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2689                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2690                                 };
2691                         };
2692                 };
2693
2694                 gpu-thermal {
2695                         polling-delay-passive = <250>;
2696                         polling-delay = <1000>;
2697
2698                         thermal-sensors = <&tsens 2>;
2699
2700                         trips {
2701                                 gpu_alert0: trip-point0 {
2702                                         temperature = <75000>;
2703                                         hysteresis = <2000>;
2704                                         type = "passive";
2705                                 };
2706                                 gpu_crit: gpu-crit {
2707                                         temperature = <95000>;
2708                                         hysteresis = <2000>;
2709                                         type = "critical";
2710                                 };
2711                         };
2712                 };
2713
2714                 camera-thermal {
2715                         polling-delay-passive = <250>;
2716                         polling-delay = <1000>;
2717
2718                         thermal-sensors = <&tsens 1>;
2719
2720                         trips {
2721                                 cam_alert0: trip-point0 {
2722                                         temperature = <75000>;
2723                                         hysteresis = <2000>;
2724                                         type = "hot";
2725                                 };
2726                         };
2727                 };
2728
2729                 modem-thermal {
2730                         polling-delay-passive = <250>;
2731                         polling-delay = <1000>;
2732
2733                         thermal-sensors = <&tsens 0>;
2734
2735                         trips {
2736                                 modem_alert0: trip-point0 {
2737                                         temperature = <85000>;
2738                                         hysteresis = <2000>;
2739                                         type = "hot";
2740                                 };
2741                         };
2742                 };
2743         };
2744
2745         timer {
2746                 compatible = "arm,armv8-timer";
2747                 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2748                              <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2749                              <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2750                              <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
2751         };
2752 };