arch/arm64/boot/dts/nvidia/tegra194.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <dt-bindings/clock/tegra194-clock.h>
   3 #include <dt-bindings/gpio/tegra194-gpio.h>
   4 #include <dt-bindings/interrupt-controller/arm-gic.h>
   5 #include <dt-bindings/mailbox/tegra186-hsp.h>
   6 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
   7 #include <dt-bindings/power/tegra194-powergate.h>
   8 #include <dt-bindings/reset/tegra194-reset.h>
   9 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
  10 #include <dt-bindings/memory/tegra194-mc.h>
  11
  12 / {
  13         compatible = "nvidia,tegra194";
  14         interrupt-parent = <&gic>;
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         /* control backbone */
  19         bus@0 {
  20                 compatible = "simple-bus";
  21                 #address-cells = <1>;
  22                 #size-cells = <1>;
  23                 ranges = <0x0 0x0 0x0 0x40000000>;
  24
  25                 misc@100000 {
  26                         compatible = "nvidia,tegra194-misc";
  27                         reg = <0x00100000 0xf000>,
  28                               <0x0010f000 0x1000>;
  29                 };
  30
  31                 gpio: gpio@2200000 {
  32                         compatible = "nvidia,tegra194-gpio";
  33                         reg-names = "security", "gpio";
  34                         reg = <0x2200000 0x10000>,
  35                               <0x2210000 0x10000>;
  36                         interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
  37                                      <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
  38                                      <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
  39                                      <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
  40                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
  41                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
  42                         #interrupt-cells = <2>;
  43                         interrupt-controller;
  44                         #gpio-cells = <2>;
  45                         gpio-controller;
  46                 };
  47
  48                 ethernet@2490000 {
  49                         compatible = "nvidia,tegra194-eqos",
  50                                      "nvidia,tegra186-eqos",
  51                                      "snps,dwc-qos-ethernet-4.10";
  52                         reg = <0x02490000 0x10000>;
  53                         interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
  54                         clocks = <&bpmp TEGRA194_CLK_AXI_CBB>,
  55                                  <&bpmp TEGRA194_CLK_EQOS_AXI>,
  56                                  <&bpmp TEGRA194_CLK_EQOS_RX>,
  57                                  <&bpmp TEGRA194_CLK_EQOS_TX>,
  58                                  <&bpmp TEGRA194_CLK_EQOS_PTP_REF>;
  59                         clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
  60                         resets = <&bpmp TEGRA194_RESET_EQOS>;
  61                         reset-names = "eqos";
  62                         interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>,
  63                                         <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>;
  64                         interconnect-names = "dma-mem", "write";
  65                         status = "disabled";
  66
  67                         snps,write-requests = <1>;
  68                         snps,read-requests = <3>;
  69                         snps,burst-map = <0x7>;
  70                         snps,txpbl = <16>;
  71                         snps,rxpbl = <8>;
  72                 };
  73
  74                 aconnect@2900000 {
  75                         compatible = "nvidia,tegra194-aconnect",
  76                                      "nvidia,tegra210-aconnect";
  77                         clocks = <&bpmp TEGRA194_CLK_APE>,
  78                                  <&bpmp TEGRA194_CLK_APB2APE>;
  79                         clock-names = "ape", "apb2ape";
  80                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>;
  81                         #address-cells = <1>;
  82                         #size-cells = <1>;
  83                         ranges = <0x02900000 0x02900000 0x200000>;
  84                         status = "disabled";
  85
  86                         dma-controller@2930000 {
  87                                 compatible = "nvidia,tegra194-adma",
  88                                              "nvidia,tegra186-adma";
  89                                 reg = <0x02930000 0x20000>;
  90                                 interrupt-parent = <&agic>;
  91                                 interrupts =  <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
  92                                               <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
  93                                               <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
  94                                               <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
  95                                               <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
  96                                               <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
  97                                               <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
  98                                               <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
  99                                               <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 100                                               <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 101                                               <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
 102                                               <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 103                                               <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 104                                               <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 105                                               <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 106                                               <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 107                                               <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 108                                               <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 109                                               <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 110                                               <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 111                                               <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
 112                                               <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
 113                                               <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
 114                                               <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
 115                                               <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
 116                                               <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
 117                                               <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
 118                                               <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
 119                                               <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
 120                                               <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
 121                                               <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
 122                                               <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 123                                 #dma-cells = <1>;
 124                                 clocks = <&bpmp TEGRA194_CLK_AHUB>;
 125                                 clock-names = "d_audio";
 126                                 status = "disabled";
 127                         };
 128
 129                         agic: interrupt-controller@2a40000 {
 130                                 compatible = "nvidia,tegra194-agic",
 131                                              "nvidia,tegra210-agic";
 132                                 #interrupt-cells = <3>;
 133                                 interrupt-controller;
 134                                 reg = <0x02a41000 0x1000>,
 135                                       <0x02a42000 0x2000>;
 136                                 interrupts = <GIC_SPI 145
 137                                               (GIC_CPU_MASK_SIMPLE(4) |
 138                                                IRQ_TYPE_LEVEL_HIGH)>;
 139                                 clocks = <&bpmp TEGRA194_CLK_APE>;
 140                                 clock-names = "clk";
 141                                 status = "disabled";
 142                         };
 143                 };
 144
 145                 pinmux: pinmux@2430000 {
 146                         compatible = "nvidia,tegra194-pinmux";
 147                         reg = <0x2430000 0x17000>,
 148                               <0xc300000 0x4000>;
 149
 150                         status = "okay";
 151
 152                         pex_rst_c5_out_state: pex_rst_c5_out {
 153                                 pex_rst {
 154                                         nvidia,pins = "pex_l5_rst_n_pgg1";
 155                                         nvidia,schmitt = <TEGRA_PIN_DISABLE>;
 156                                         nvidia,lpdr = <TEGRA_PIN_ENABLE>;
 157                                         nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 158                                         nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
 159                                         nvidia,tristate = <TEGRA_PIN_DISABLE>;
 160                                         nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 161                                 };
 162                         };
 163
 164                         clkreq_c5_bi_dir_state: clkreq_c5_bi_dir {
 165                                 clkreq {
 166                                         nvidia,pins = "pex_l5_clkreq_n_pgg0";
 167                                         nvidia,schmitt = <TEGRA_PIN_DISABLE>;
 168                                         nvidia,lpdr = <TEGRA_PIN_ENABLE>;
 169                                         nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 170                                         nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
 171                                         nvidia,tristate = <TEGRA_PIN_DISABLE>;
 172                                         nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 173                                 };
 174                         };
 175                 };
 176
 177                 mc: memory-controller@2c00000 {
 178                         compatible = "nvidia,tegra194-mc";
 179                         reg = <0x02c00000 0x100000>,
 180                               <0x02b80000 0x040000>,
 181                               <0x01700000 0x100000>;
 182                         interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
 183                         #interconnect-cells = <1>;
 184                         status = "disabled";
 185
 186                         #address-cells = <2>;
 187                         #size-cells = <2>;
 188
 189                         ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>,
 190                                  <0x02b80000 0x0 0x02b80000 0x0 0x040000>,
 191                                  <0x02c00000 0x0 0x02c00000 0x0 0x100000>;
 192
 193                         /*
 194                          * Bit 39 of addresses passing through the memory
 195                          * controller selects the XBAR format used when memory
 196                          * is accessed. This is used to transparently access
 197                          * memory in the XBAR format used by the discrete GPU
 198                          * (bit 39 set) or Tegra (bit 39 clear).
 199                          *
 200                          * As a consequence, the operating system must ensure
 201                          * that bit 39 is never used implicitly, for example
 202                          * via an I/O virtual address mapping of an IOMMU. If
 203                          * devices require access to the XBAR switch, their
 204                          * drivers must set this bit explicitly.
 205                          *
 206                          * Limit the DMA range for memory clients to [38:0].
 207                          */
 208                         dma-ranges = <0x0 0x0 0x0 0x80 0x0>;
 209
 210                         emc: external-memory-controller@2c60000 {
 211                                 compatible = "nvidia,tegra194-emc";
 212                                 reg = <0x0 0x02c60000 0x0 0x90000>,
 213                                       <0x0 0x01780000 0x0 0x80000>;
 214                                 clocks = <&bpmp TEGRA194_CLK_EMC>;
 215                                 clock-names = "emc";
 216
 217                                 #interconnect-cells = <0>;
 218
 219                                 nvidia,bpmp = <&bpmp>;
 220                         };
 221                 };
 222
 223                 uarta: serial@3100000 {
 224                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
 225                         reg = <0x03100000 0x40>;
 226                         reg-shift = <2>;
 227                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 228                         clocks = <&bpmp TEGRA194_CLK_UARTA>;
 229                         clock-names = "serial";
 230                         resets = <&bpmp TEGRA194_RESET_UARTA>;
 231                         reset-names = "serial";
 232                         status = "disabled";
 233                 };
 234
 235                 uartb: serial@3110000 {
 236                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
 237                         reg = <0x03110000 0x40>;
 238                         reg-shift = <2>;
 239                         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 240                         clocks = <&bpmp TEGRA194_CLK_UARTB>;
 241                         clock-names = "serial";
 242                         resets = <&bpmp TEGRA194_RESET_UARTB>;
 243                         reset-names = "serial";
 244                         status = "disabled";
 245                 };
 246
 247                 uartd: serial@3130000 {
 248                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
 249                         reg = <0x03130000 0x40>;
 250                         reg-shift = <2>;
 251                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 252                         clocks = <&bpmp TEGRA194_CLK_UARTD>;
 253                         clock-names = "serial";
 254                         resets = <&bpmp TEGRA194_RESET_UARTD>;
 255                         reset-names = "serial";
 256                         status = "disabled";
 257                 };
 258
 259                 uarte: serial@3140000 {
 260                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
 261                         reg = <0x03140000 0x40>;
 262                         reg-shift = <2>;
 263                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 264                         clocks = <&bpmp TEGRA194_CLK_UARTE>;
 265                         clock-names = "serial";
 266                         resets = <&bpmp TEGRA194_RESET_UARTE>;
 267                         reset-names = "serial";
 268                         status = "disabled";
 269                 };
 270
 271                 uartf: serial@3150000 {
 272                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
 273                         reg = <0x03150000 0x40>;
 274                         reg-shift = <2>;
 275                         interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 276                         clocks = <&bpmp TEGRA194_CLK_UARTF>;
 277                         clock-names = "serial";
 278                         resets = <&bpmp TEGRA194_RESET_UARTF>;
 279                         reset-names = "serial";
 280                         status = "disabled";
 281                 };
 282
 283                 gen1_i2c: i2c@3160000 {
 284                         compatible = "nvidia,tegra194-i2c";
 285                         reg = <0x03160000 0x10000>;
 286                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 287                         #address-cells = <1>;
 288                         #size-cells = <0>;
 289                         clocks = <&bpmp TEGRA194_CLK_I2C1>;
 290                         clock-names = "div-clk";
 291                         resets = <&bpmp TEGRA194_RESET_I2C1>;
 292                         reset-names = "i2c";
 293                         status = "disabled";
 294                 };
 295
 296                 uarth: serial@3170000 {
 297                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
 298                         reg = <0x03170000 0x40>;
 299                         reg-shift = <2>;
 300                         interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
 301                         clocks = <&bpmp TEGRA194_CLK_UARTH>;
 302                         clock-names = "serial";
 303                         resets = <&bpmp TEGRA194_RESET_UARTH>;
 304                         reset-names = "serial";
 305                         status = "disabled";
 306                 };
 307
 308                 cam_i2c: i2c@3180000 {
 309                         compatible = "nvidia,tegra194-i2c";
 310                         reg = <0x03180000 0x10000>;
 311                         interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 312                         #address-cells = <1>;
 313                         #size-cells = <0>;
 314                         clocks = <&bpmp TEGRA194_CLK_I2C3>;
 315                         clock-names = "div-clk";
 316                         resets = <&bpmp TEGRA194_RESET_I2C3>;
 317                         reset-names = "i2c";
 318                         status = "disabled";
 319                 };
 320
 321                 /* shares pads with dpaux1 */
 322                 dp_aux_ch1_i2c: i2c@3190000 {
 323                         compatible = "nvidia,tegra194-i2c";
 324                         reg = <0x03190000 0x10000>;
 325                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 326                         #address-cells = <1>;
 327                         #size-cells = <0>;
 328                         clocks = <&bpmp TEGRA194_CLK_I2C4>;
 329                         clock-names = "div-clk";
 330                         resets = <&bpmp TEGRA194_RESET_I2C4>;
 331                         reset-names = "i2c";
 332                         status = "disabled";
 333                 };
 334
 335                 /* shares pads with dpaux0 */
 336                 dp_aux_ch0_i2c: i2c@31b0000 {
 337                         compatible = "nvidia,tegra194-i2c";
 338                         reg = <0x031b0000 0x10000>;
 339                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 340                         #address-cells = <1>;
 341                         #size-cells = <0>;
 342                         clocks = <&bpmp TEGRA194_CLK_I2C6>;
 343                         clock-names = "div-clk";
 344                         resets = <&bpmp TEGRA194_RESET_I2C6>;
 345                         reset-names = "i2c";
 346                         status = "disabled";
 347                 };
 348
 349                 gen7_i2c: i2c@31c0000 {
 350                         compatible = "nvidia,tegra194-i2c";
 351                         reg = <0x031c0000 0x10000>;
 352                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 353                         #address-cells = <1>;
 354                         #size-cells = <0>;
 355                         clocks = <&bpmp TEGRA194_CLK_I2C7>;
 356                         clock-names = "div-clk";
 357                         resets = <&bpmp TEGRA194_RESET_I2C7>;
 358                         reset-names = "i2c";
 359                         status = "disabled";
 360                 };
 361
 362                 gen9_i2c: i2c@31e0000 {
 363                         compatible = "nvidia,tegra194-i2c";
 364                         reg = <0x031e0000 0x10000>;
 365                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 366                         #address-cells = <1>;
 367                         #size-cells = <0>;
 368                         clocks = <&bpmp TEGRA194_CLK_I2C9>;
 369                         clock-names = "div-clk";
 370                         resets = <&bpmp TEGRA194_RESET_I2C9>;
 371                         reset-names = "i2c";
 372                         status = "disabled";
 373                 };
 374
 375                 pwm1: pwm@3280000 {
 376                         compatible = "nvidia,tegra194-pwm",
 377                                      "nvidia,tegra186-pwm";
 378                         reg = <0x3280000 0x10000>;
 379                         clocks = <&bpmp TEGRA194_CLK_PWM1>;
 380                         clock-names = "pwm";
 381                         resets = <&bpmp TEGRA194_RESET_PWM1>;
 382                         reset-names = "pwm";
 383                         status = "disabled";
 384                         #pwm-cells = <2>;
 385                 };
 386
 387                 pwm2: pwm@3290000 {
 388                         compatible = "nvidia,tegra194-pwm",
 389                                      "nvidia,tegra186-pwm";
 390                         reg = <0x3290000 0x10000>;
 391                         clocks = <&bpmp TEGRA194_CLK_PWM2>;
 392                         clock-names = "pwm";
 393                         resets = <&bpmp TEGRA194_RESET_PWM2>;
 394                         reset-names = "pwm";
 395                         status = "disabled";
 396                         #pwm-cells = <2>;
 397                 };
 398
 399                 pwm3: pwm@32a0000 {
 400                         compatible = "nvidia,tegra194-pwm",
 401                                      "nvidia,tegra186-pwm";
 402                         reg = <0x32a0000 0x10000>;
 403                         clocks = <&bpmp TEGRA194_CLK_PWM3>;
 404                         clock-names = "pwm";
 405                         resets = <&bpmp TEGRA194_RESET_PWM3>;
 406                         reset-names = "pwm";
 407                         status = "disabled";
 408                         #pwm-cells = <2>;
 409                 };
 410
 411                 pwm5: pwm@32c0000 {
 412                         compatible = "nvidia,tegra194-pwm",
 413                                      "nvidia,tegra186-pwm";
 414                         reg = <0x32c0000 0x10000>;
 415                         clocks = <&bpmp TEGRA194_CLK_PWM5>;
 416                         clock-names = "pwm";
 417                         resets = <&bpmp TEGRA194_RESET_PWM5>;
 418                         reset-names = "pwm";
 419                         status = "disabled";
 420                         #pwm-cells = <2>;
 421                 };
 422
 423                 pwm6: pwm@32d0000 {
 424                         compatible = "nvidia,tegra194-pwm",
 425                                      "nvidia,tegra186-pwm";
 426                         reg = <0x32d0000 0x10000>;
 427                         clocks = <&bpmp TEGRA194_CLK_PWM6>;
 428                         clock-names = "pwm";
 429                         resets = <&bpmp TEGRA194_RESET_PWM6>;
 430                         reset-names = "pwm";
 431                         status = "disabled";
 432                         #pwm-cells = <2>;
 433                 };
 434
 435                 pwm7: pwm@32e0000 {
 436                         compatible = "nvidia,tegra194-pwm",
 437                                      "nvidia,tegra186-pwm";
 438                         reg = <0x32e0000 0x10000>;
 439                         clocks = <&bpmp TEGRA194_CLK_PWM7>;
 440                         clock-names = "pwm";
 441                         resets = <&bpmp TEGRA194_RESET_PWM7>;
 442                         reset-names = "pwm";
 443                         status = "disabled";
 444                         #pwm-cells = <2>;
 445                 };
 446
 447                 pwm8: pwm@32f0000 {
 448                         compatible = "nvidia,tegra194-pwm",
 449                                      "nvidia,tegra186-pwm";
 450                         reg = <0x32f0000 0x10000>;
 451                         clocks = <&bpmp TEGRA194_CLK_PWM8>;
 452                         clock-names = "pwm";
 453                         resets = <&bpmp TEGRA194_RESET_PWM8>;
 454                         reset-names = "pwm";
 455                         status = "disabled";
 456                         #pwm-cells = <2>;
 457                 };
 458
 459                 sdmmc1: mmc@3400000 {
 460                         compatible = "nvidia,tegra194-sdhci";
 461                         reg = <0x03400000 0x10000>;
 462                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 463                         clocks = <&bpmp TEGRA194_CLK_SDMMC1>,
 464                                  <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
 465                         clock-names = "sdhci", "tmclk";
 466                         resets = <&bpmp TEGRA194_RESET_SDMMC1>;
 467                         reset-names = "sdhci";
 468                         interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>,
 469                                         <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>;
 470                         interconnect-names = "dma-mem", "write";
 471                         nvidia,pad-autocal-pull-up-offset-3v3-timeout =
 472                                                                         <0x07>;
 473                         nvidia,pad-autocal-pull-down-offset-3v3-timeout =
 474                                                                         <0x07>;
 475                         nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
 476                         nvidia,pad-autocal-pull-down-offset-1v8-timeout =
 477                                                                         <0x07>;
 478                         nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
 479                         nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
 480                         nvidia,default-tap = <0x9>;
 481                         nvidia,default-trim = <0x5>;
 482                         status = "disabled";
 483                 };
 484
 485                 sdmmc3: mmc@3440000 {
 486                         compatible = "nvidia,tegra194-sdhci";
 487                         reg = <0x03440000 0x10000>;
 488                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 489                         clocks = <&bpmp TEGRA194_CLK_SDMMC3>,
 490                                  <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
 491                         clock-names = "sdhci", "tmclk";
 492                         resets = <&bpmp TEGRA194_RESET_SDMMC3>;
 493                         reset-names = "sdhci";
 494                         interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>,
 495                                         <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>;
 496                         interconnect-names = "dma-mem", "write";
 497                         nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
 498                         nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
 499                         nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
 500                         nvidia,pad-autocal-pull-down-offset-3v3-timeout =
 501                                                                         <0x07>;
 502                         nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
 503                         nvidia,pad-autocal-pull-down-offset-1v8-timeout =
 504                                                                         <0x07>;
 505                         nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
 506                         nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
 507                         nvidia,default-tap = <0x9>;
 508                         nvidia,default-trim = <0x5>;
 509                         status = "disabled";
 510                 };
 511
 512                 sdmmc4: mmc@3460000 {
 513                         compatible = "nvidia,tegra194-sdhci";
 514                         reg = <0x03460000 0x10000>;
 515                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 516                         clocks = <&bpmp TEGRA194_CLK_SDMMC4>,
 517                                  <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
 518                         clock-names = "sdhci", "tmclk";
 519                         assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>,
 520                                           <&bpmp TEGRA194_CLK_PLLC4>;
 521                         assigned-clock-parents =
 522                                           <&bpmp TEGRA194_CLK_PLLC4>;
 523                         resets = <&bpmp TEGRA194_RESET_SDMMC4>;
 524                         reset-names = "sdhci";
 525                         interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>,
 526                                         <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>;
 527                         interconnect-names = "dma-mem", "write";
 528                         nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
 529                         nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
 530                         nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
 531                         nvidia,pad-autocal-pull-down-offset-1v8-timeout =
 532                                                                         <0x0a>;
 533                         nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
 534                         nvidia,pad-autocal-pull-down-offset-3v3-timeout =
 535                                                                         <0x0a>;
 536                         nvidia,default-tap = <0x8>;
 537                         nvidia,default-trim = <0x14>;
 538                         nvidia,dqs-trim = <40>;
 539                         supports-cqe;
 540                         status = "disabled";
 541                 };
 542
 543                 hda@3510000 {
 544                         compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda";
 545                         reg = <0x3510000 0x10000>;
 546                         interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
 547                         clocks = <&bpmp TEGRA194_CLK_HDA>,
 548                                  <&bpmp TEGRA194_CLK_HDA2CODEC_2X>,
 549                                  <&bpmp TEGRA194_CLK_HDA2HDMICODEC>;
 550                         clock-names = "hda", "hda2codec_2x", "hda2hdmi";
 551                         resets = <&bpmp TEGRA194_RESET_HDA>,
 552                                  <&bpmp TEGRA194_RESET_HDA2CODEC_2X>,
 553                                  <&bpmp TEGRA194_RESET_HDA2HDMICODEC>;
 554                         reset-names = "hda", "hda2codec_2x", "hda2hdmi";
 555                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
 556                         interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>,
 557                                         <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>;
 558                         interconnect-names = "dma-mem", "write";
 559                         status = "disabled";
 560                 };
 561
 562                 xusb_padctl: padctl@3520000 {
 563                         compatible = "nvidia,tegra194-xusb-padctl";
 564                         reg = <0x03520000 0x1000>,
 565                               <0x03540000 0x1000>;
 566                         reg-names = "padctl", "ao";
 567
 568                         resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>;
 569                         reset-names = "padctl";
 570
 571                         status = "disabled";
 572
 573                         pads {
 574                                 usb2 {
 575                                         clocks = <&bpmp TEGRA194_CLK_USB2_TRK>;
 576                                         clock-names = "trk";
 577
 578                                         lanes {
 579                                                 usb2-0 {
 580                                                         nvidia,function = "xusb";
 581                                                         status = "disabled";
 582                                                         #phy-cells = <0>;
 583                                                 };
 584
 585                                                 usb2-1 {
 586                                                         nvidia,function = "xusb";
 587                                                         status = "disabled";
 588                                                         #phy-cells = <0>;
 589                                                 };
 590
 591                                                 usb2-2 {
 592                                                         nvidia,function = "xusb";
 593                                                         status = "disabled";
 594                                                         #phy-cells = <0>;
 595                                                 };
 596
 597                                                 usb2-3 {
 598                                                         nvidia,function = "xusb";
 599                                                         status = "disabled";
 600                                                         #phy-cells = <0>;
 601                                                 };
 602                                         };
 603                                 };
 604
 605                                 usb3 {
 606                                         lanes {
 607                                                 usb3-0 {
 608                                                         nvidia,function = "xusb";
 609                                                         status = "disabled";
 610                                                         #phy-cells = <0>;
 611                                                 };
 612
 613                                                 usb3-1 {
 614                                                         nvidia,function = "xusb";
 615                                                         status = "disabled";
 616                                                         #phy-cells = <0>;
 617                                                 };
 618
 619                                                 usb3-2 {
 620                                                         nvidia,function = "xusb";
 621                                                         status = "disabled";
 622                                                         #phy-cells = <0>;
 623                                                 };
 624
 625                                                 usb3-3 {
 626                                                         nvidia,function = "xusb";
 627                                                         status = "disabled";
 628                                                         #phy-cells = <0>;
 629                                                 };
 630                                         };
 631                                 };
 632                         };
 633
 634                         ports {
 635                                 usb2-0 {
 636                                         status = "disabled";
 637                                 };
 638
 639                                 usb2-1 {
 640                                         status = "disabled";
 641                                 };
 642
 643                                 usb2-2 {
 644                                         status = "disabled";
 645                                 };
 646
 647                                 usb2-3 {
 648                                         status = "disabled";
 649                                 };
 650
 651                                 usb3-0 {
 652                                         status = "disabled";
 653                                 };
 654
 655                                 usb3-1 {
 656                                         status = "disabled";
 657                                 };
 658
 659                                 usb3-2 {
 660                                         status = "disabled";
 661                                 };
 662
 663                                 usb3-3 {
 664                                         status = "disabled";
 665                                 };
 666                         };
 667                 };
 668
 669                 usb@3550000 {
 670                         compatible = "nvidia,tegra194-xudc";
 671                         reg = <0x03550000 0x8000>,
 672                               <0x03558000 0x1000>;
 673                         reg-names = "base", "fpci";
 674                         interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
 675                         clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>,
 676                                  <&bpmp TEGRA194_CLK_XUSB_CORE_SS>,
 677                                  <&bpmp TEGRA194_CLK_XUSB_SS>,
 678                                  <&bpmp TEGRA194_CLK_XUSB_FS>;
 679                         clock-names = "dev", "ss", "ss_src", "fs_src";
 680                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>,
 681                                         <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>;
 682                         power-domain-names = "dev", "ss";
 683                         nvidia,xusb-padctl = <&xusb_padctl>;
 684                         status = "disabled";
 685                 };
 686
 687                 usb@3610000 {
 688                         compatible = "nvidia,tegra194-xusb";
 689                         reg = <0x03610000 0x40000>,
 690                               <0x03600000 0x10000>;
 691                         reg-names = "hcd", "fpci";
 692
 693                         interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
 694                                      <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
 695
 696                         clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>,
 697                                  <&bpmp TEGRA194_CLK_XUSB_FALCON>,
 698                                  <&bpmp TEGRA194_CLK_XUSB_CORE_SS>,
 699                                  <&bpmp TEGRA194_CLK_XUSB_SS>,
 700                                  <&bpmp TEGRA194_CLK_CLK_M>,
 701                                  <&bpmp TEGRA194_CLK_XUSB_FS>,
 702                                  <&bpmp TEGRA194_CLK_UTMIPLL>,
 703                                  <&bpmp TEGRA194_CLK_CLK_M>,
 704                                  <&bpmp TEGRA194_CLK_PLLE>;
 705                         clock-names = "xusb_host", "xusb_falcon_src",
 706                                       "xusb_ss", "xusb_ss_src", "xusb_hs_src",
 707                                       "xusb_fs_src", "pll_u_480m", "clk_m",
 708                                       "pll_e";
 709
 710                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>,
 711                                         <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>;
 712                         power-domain-names = "xusb_host", "xusb_ss";
 713
 714                         nvidia,xusb-padctl = <&xusb_padctl>;
 715                         status = "disabled";
 716                 };
 717
 718                 fuse@3820000 {
 719                         compatible = "nvidia,tegra194-efuse";
 720                         reg = <0x03820000 0x10000>;
 721                         clocks = <&bpmp TEGRA194_CLK_FUSE>;
 722                         clock-names = "fuse";
 723                 };
 724
 725                 gic: interrupt-controller@3881000 {
 726                         compatible = "arm,gic-400";
 727                         #interrupt-cells = <3>;
 728                         interrupt-controller;
 729                         reg = <0x03881000 0x1000>,
 730                               <0x03882000 0x2000>,
 731                               <0x03884000 0x2000>,
 732                               <0x03886000 0x2000>;
 733                         interrupts = <GIC_PPI 9
 734                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 735                         interrupt-parent = <&gic>;
 736                 };
 737
 738                 cec@3960000 {
 739                         compatible = "nvidia,tegra194-cec";
 740                         reg = <0x03960000 0x10000>;
 741                         interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
 742                         clocks = <&bpmp TEGRA194_CLK_CEC>;
 743                         clock-names = "cec";
 744                         status = "disabled";
 745                 };
 746
 747                 hsp_top0: hsp@3c00000 {
 748                         compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp";
 749                         reg = <0x03c00000 0xa0000>;
 750                         interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
 751                                      <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 752                                      <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 753                                      <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 754                                      <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 755                                      <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
 756                                      <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
 757                                      <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
 758                                      <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 759                         interrupt-names = "doorbell", "shared0", "shared1", "shared2",
 760                                           "shared3", "shared4", "shared5", "shared6",
 761                                           "shared7";
 762                         #mbox-cells = <2>;
 763                 };
 764
 765                 p2u_hsio_0: phy@3e10000 {
 766                         compatible = "nvidia,tegra194-p2u";
 767                         reg = <0x03e10000 0x10000>;
 768                         reg-names = "ctl";
 769
 770                         #phy-cells = <0>;
 771                 };
 772
 773                 p2u_hsio_1: phy@3e20000 {
 774                         compatible = "nvidia,tegra194-p2u";
 775                         reg = <0x03e20000 0x10000>;
 776                         reg-names = "ctl";
 777
 778                         #phy-cells = <0>;
 779                 };
 780
 781                 p2u_hsio_2: phy@3e30000 {
 782                         compatible = "nvidia,tegra194-p2u";
 783                         reg = <0x03e30000 0x10000>;
 784                         reg-names = "ctl";
 785
 786                         #phy-cells = <0>;
 787                 };
 788
 789                 p2u_hsio_3: phy@3e40000 {
 790                         compatible = "nvidia,tegra194-p2u";
 791                         reg = <0x03e40000 0x10000>;
 792                         reg-names = "ctl";
 793
 794                         #phy-cells = <0>;
 795                 };
 796
 797                 p2u_hsio_4: phy@3e50000 {
 798                         compatible = "nvidia,tegra194-p2u";
 799                         reg = <0x03e50000 0x10000>;
 800                         reg-names = "ctl";
 801
 802                         #phy-cells = <0>;
 803                 };
 804
 805                 p2u_hsio_5: phy@3e60000 {
 806                         compatible = "nvidia,tegra194-p2u";
 807                         reg = <0x03e60000 0x10000>;
 808                         reg-names = "ctl";
 809
 810                         #phy-cells = <0>;
 811                 };
 812
 813                 p2u_hsio_6: phy@3e70000 {
 814                         compatible = "nvidia,tegra194-p2u";
 815                         reg = <0x03e70000 0x10000>;
 816                         reg-names = "ctl";
 817
 818                         #phy-cells = <0>;
 819                 };
 820
 821                 p2u_hsio_7: phy@3e80000 {
 822                         compatible = "nvidia,tegra194-p2u";
 823                         reg = <0x03e80000 0x10000>;
 824                         reg-names = "ctl";
 825
 826                         #phy-cells = <0>;
 827                 };
 828
 829                 p2u_hsio_8: phy@3e90000 {
 830                         compatible = "nvidia,tegra194-p2u";
 831                         reg = <0x03e90000 0x10000>;
 832                         reg-names = "ctl";
 833
 834                         #phy-cells = <0>;
 835                 };
 836
 837                 p2u_hsio_9: phy@3ea0000 {
 838                         compatible = "nvidia,tegra194-p2u";
 839                         reg = <0x03ea0000 0x10000>;
 840                         reg-names = "ctl";
 841
 842                         #phy-cells = <0>;
 843                 };
 844
 845                 p2u_nvhs_0: phy@3eb0000 {
 846                         compatible = "nvidia,tegra194-p2u";
 847                         reg = <0x03eb0000 0x10000>;
 848                         reg-names = "ctl";
 849
 850                         #phy-cells = <0>;
 851                 };
 852
 853                 p2u_nvhs_1: phy@3ec0000 {
 854                         compatible = "nvidia,tegra194-p2u";
 855                         reg = <0x03ec0000 0x10000>;
 856                         reg-names = "ctl";
 857
 858                         #phy-cells = <0>;
 859                 };
 860
 861                 p2u_nvhs_2: phy@3ed0000 {
 862                         compatible = "nvidia,tegra194-p2u";
 863                         reg = <0x03ed0000 0x10000>;
 864                         reg-names = "ctl";
 865
 866                         #phy-cells = <0>;
 867                 };
 868
 869                 p2u_nvhs_3: phy@3ee0000 {
 870                         compatible = "nvidia,tegra194-p2u";
 871                         reg = <0x03ee0000 0x10000>;
 872                         reg-names = "ctl";
 873
 874                         #phy-cells = <0>;
 875                 };
 876
 877                 p2u_nvhs_4: phy@3ef0000 {
 878                         compatible = "nvidia,tegra194-p2u";
 879                         reg = <0x03ef0000 0x10000>;
 880                         reg-names = "ctl";
 881
 882                         #phy-cells = <0>;
 883                 };
 884
 885                 p2u_nvhs_5: phy@3f00000 {
 886                         compatible = "nvidia,tegra194-p2u";
 887                         reg = <0x03f00000 0x10000>;
 888                         reg-names = "ctl";
 889
 890                         #phy-cells = <0>;
 891                 };
 892
 893                 p2u_nvhs_6: phy@3f10000 {
 894                         compatible = "nvidia,tegra194-p2u";
 895                         reg = <0x03f10000 0x10000>;
 896                         reg-names = "ctl";
 897
 898                         #phy-cells = <0>;
 899                 };
 900
 901                 p2u_nvhs_7: phy@3f20000 {
 902                         compatible = "nvidia,tegra194-p2u";
 903                         reg = <0x03f20000 0x10000>;
 904                         reg-names = "ctl";
 905
 906                         #phy-cells = <0>;
 907                 };
 908
 909                 p2u_hsio_10: phy@3f30000 {
 910                         compatible = "nvidia,tegra194-p2u";
 911                         reg = <0x03f30000 0x10000>;
 912                         reg-names = "ctl";
 913
 914                         #phy-cells = <0>;
 915                 };
 916
 917                 p2u_hsio_11: phy@3f40000 {
 918                         compatible = "nvidia,tegra194-p2u";
 919                         reg = <0x03f40000 0x10000>;
 920                         reg-names = "ctl";
 921
 922                         #phy-cells = <0>;
 923                 };
 924
 925                 hsp_aon: hsp@c150000 {
 926                         compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp";
 927                         reg = <0x0c150000 0xa0000>;
 928                         interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 929                                      <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 930                                      <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 931                                      <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
 932                         /*
 933                          * Shared interrupt 0 is routed only to AON/SPE, so
 934                          * we only have 4 shared interrupts for the CCPLEX.
 935                          */
 936                         interrupt-names = "shared1", "shared2", "shared3", "shared4";
 937                         #mbox-cells = <2>;
 938                 };
 939
 940                 gen2_i2c: i2c@c240000 {
 941                         compatible = "nvidia,tegra194-i2c";
 942                         reg = <0x0c240000 0x10000>;
 943                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 944                         #address-cells = <1>;
 945                         #size-cells = <0>;
 946                         clocks = <&bpmp TEGRA194_CLK_I2C2>;
 947                         clock-names = "div-clk";
 948                         resets = <&bpmp TEGRA194_RESET_I2C2>;
 949                         reset-names = "i2c";
 950                         status = "disabled";
 951                 };
 952
 953                 gen8_i2c: i2c@c250000 {
 954                         compatible = "nvidia,tegra194-i2c";
 955                         reg = <0x0c250000 0x10000>;
 956                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 957                         #address-cells = <1>;
 958                         #size-cells = <0>;
 959                         clocks = <&bpmp TEGRA194_CLK_I2C8>;
 960                         clock-names = "div-clk";
 961                         resets = <&bpmp TEGRA194_RESET_I2C8>;
 962                         reset-names = "i2c";
 963                         status = "disabled";
 964                 };
 965
 966                 uartc: serial@c280000 {
 967                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
 968                         reg = <0x0c280000 0x40>;
 969                         reg-shift = <2>;
 970                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 971                         clocks = <&bpmp TEGRA194_CLK_UARTC>;
 972                         clock-names = "serial";
 973                         resets = <&bpmp TEGRA194_RESET_UARTC>;
 974                         reset-names = "serial";
 975                         status = "disabled";
 976                 };
 977
 978                 uartg: serial@c290000 {
 979                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
 980                         reg = <0x0c290000 0x40>;
 981                         reg-shift = <2>;
 982                         interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 983                         clocks = <&bpmp TEGRA194_CLK_UARTG>;
 984                         clock-names = "serial";
 985                         resets = <&bpmp TEGRA194_RESET_UARTG>;
 986                         reset-names = "serial";
 987                         status = "disabled";
 988                 };
 989
 990                 rtc: rtc@c2a0000 {
 991                         compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc";
 992                         reg = <0x0c2a0000 0x10000>;
 993                         interrupt-parent = <&pmc>;
 994                         interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
 995                         clocks = <&bpmp TEGRA194_CLK_CLK_32K>;
 996                         clock-names = "rtc";
 997                         status = "disabled";
 998                 };
 999
1000                 gpio_aon: gpio@c2f0000 {
1001                         compatible = "nvidia,tegra194-gpio-aon";
1002                         reg-names = "security", "gpio";
1003                         reg = <0xc2f0000 0x1000>,
1004                               <0xc2f1000 0x1000>;
1005                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
1006                         gpio-controller;
1007                         #gpio-cells = <2>;
1008                         interrupt-controller;
1009                         #interrupt-cells = <2>;
1010                 };
1011
1012                 pwm4: pwm@c340000 {
1013                         compatible = "nvidia,tegra194-pwm",
1014                                      "nvidia,tegra186-pwm";
1015                         reg = <0xc340000 0x10000>;
1016                         clocks = <&bpmp TEGRA194_CLK_PWM4>;
1017                         clock-names = "pwm";
1018                         resets = <&bpmp TEGRA194_RESET_PWM4>;
1019                         reset-names = "pwm";
1020                         status = "disabled";
1021                         #pwm-cells = <2>;
1022                 };
1023
1024                 pmc: pmc@c360000 {
1025                         compatible = "nvidia,tegra194-pmc";
1026                         reg = <0x0c360000 0x10000>,
1027                               <0x0c370000 0x10000>,
1028                               <0x0c380000 0x10000>,
1029                               <0x0c390000 0x10000>,
1030                               <0x0c3a0000 0x10000>;
1031                         reg-names = "pmc", "wake", "aotag", "scratch", "misc";
1032
1033                         #interrupt-cells = <2>;
1034                         interrupt-controller;
1035                 };
1036
1037                 host1x@13e00000 {
1038                         compatible = "nvidia,tegra194-host1x";
1039                         reg = <0x13e00000 0x10000>,
1040                               <0x13e10000 0x10000>;
1041                         reg-names = "hypervisor", "vm";
1042                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
1043                                      <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
1044                         interrupt-names = "syncpt", "host1x";
1045                         clocks = <&bpmp TEGRA194_CLK_HOST1X>;
1046                         clock-names = "host1x";
1047                         resets = <&bpmp TEGRA194_RESET_HOST1X>;
1048                         reset-names = "host1x";
1049
1050                         #address-cells = <1>;
1051                         #size-cells = <1>;
1052
1053                         ranges = <0x15000000 0x15000000 0x01000000>;
1054                         interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>;
1055                         interconnect-names = "dma-mem";
1056
1057                         display-hub@15200000 {
1058                                 compatible = "nvidia,tegra194-display";
1059                                 reg = <0x15200000 0x00040000>;
1060                                 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>,
1061                                          <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>,
1062                                          <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>,
1063                                          <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>,
1064                                          <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>,
1065                                          <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>,
1066                                          <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>;
1067                                 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
1068                                               "wgrp3", "wgrp4", "wgrp5";
1069                                 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>,
1070                                          <&bpmp TEGRA194_CLK_NVDISPLAYHUB>;
1071                                 clock-names = "disp", "hub";
1072                                 status = "disabled";
1073
1074                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1075
1076                                 #address-cells = <1>;
1077                                 #size-cells = <1>;
1078
1079                                 ranges = <0x15200000 0x15200000 0x40000>;
1080
1081                                 display@15200000 {
1082                                         compatible = "nvidia,tegra194-dc";
1083                                         reg = <0x15200000 0x10000>;
1084                                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1085                                         clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>;
1086                                         clock-names = "dc";
1087                                         resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>;
1088                                         reset-names = "dc";
1089
1090                                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1091                                         interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
1092                                                         <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1093                                         interconnect-names = "dma-mem", "read-1";
1094
1095                                         nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
1096                                         nvidia,head = <0>;
1097                                 };
1098
1099                                 display@15210000 {
1100                                         compatible = "nvidia,tegra194-dc";
1101                                         reg = <0x15210000 0x10000>;
1102                                         interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
1103                                         clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>;
1104                                         clock-names = "dc";
1105                                         resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>;
1106                                         reset-names = "dc";
1107
1108                                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>;
1109                                         interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
1110                                                         <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1111                                         interconnect-names = "dma-mem", "read-1";
1112
1113                                         nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
1114                                         nvidia,head = <1>;
1115                                 };
1116
1117                                 display@15220000 {
1118                                         compatible = "nvidia,tegra194-dc";
1119                                         reg = <0x15220000 0x10000>;
1120                                         interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
1121                                         clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>;
1122                                         clock-names = "dc";
1123                                         resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>;
1124                                         reset-names = "dc";
1125
1126                                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
1127                                         interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
1128                                                         <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1129                                         interconnect-names = "dma-mem", "read-1";
1130
1131                                         nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
1132                                         nvidia,head = <2>;
1133                                 };
1134
1135                                 display@15230000 {
1136                                         compatible = "nvidia,tegra194-dc";
1137                                         reg = <0x15230000 0x10000>;
1138                                         interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
1139                                         clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>;
1140                                         clock-names = "dc";
1141                                         resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>;
1142                                         reset-names = "dc";
1143
1144                                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
1145                                         interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
1146                                                         <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
1147                                         interconnect-names = "dma-mem", "read-1";
1148
1149                                         nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
1150                                         nvidia,head = <3>;
1151                                 };
1152                         };
1153
1154                         vic@15340000 {
1155                                 compatible = "nvidia,tegra194-vic";
1156                                 reg = <0x15340000 0x00040000>;
1157                                 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
1158                                 clocks = <&bpmp TEGRA194_CLK_VIC>;
1159                                 clock-names = "vic";
1160                                 resets = <&bpmp TEGRA194_RESET_VIC>;
1161                                 reset-names = "vic";
1162
1163                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>;
1164                                 interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>,
1165                                                 <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>;
1166                                 interconnect-names = "dma-mem", "write";
1167                         };
1168
1169                         dpaux0: dpaux@155c0000 {
1170                                 compatible = "nvidia,tegra194-dpaux";
1171                                 reg = <0x155c0000 0x10000>;
1172                                 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1173                                 clocks = <&bpmp TEGRA194_CLK_DPAUX>,
1174                                          <&bpmp TEGRA194_CLK_PLLDP>;
1175                                 clock-names = "dpaux", "parent";
1176                                 resets = <&bpmp TEGRA194_RESET_DPAUX>;
1177                                 reset-names = "dpaux";
1178                                 status = "disabled";
1179
1180                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1181
1182                                 state_dpaux0_aux: pinmux-aux {
1183                                         groups = "dpaux-io";
1184                                         function = "aux";
1185                                 };
1186
1187                                 state_dpaux0_i2c: pinmux-i2c {
1188                                         groups = "dpaux-io";
1189                                         function = "i2c";
1190                                 };
1191
1192                                 state_dpaux0_off: pinmux-off {
1193                                         groups = "dpaux-io";
1194                                         function = "off";
1195                                 };
1196
1197                                 i2c-bus {
1198                                         #address-cells = <1>;
1199                                         #size-cells = <0>;
1200                                 };
1201                         };
1202
1203                         dpaux1: dpaux@155d0000 {
1204                                 compatible = "nvidia,tegra194-dpaux";
1205                                 reg = <0x155d0000 0x10000>;
1206                                 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
1207                                 clocks = <&bpmp TEGRA194_CLK_DPAUX1>,
1208                                          <&bpmp TEGRA194_CLK_PLLDP>;
1209                                 clock-names = "dpaux", "parent";
1210                                 resets = <&bpmp TEGRA194_RESET_DPAUX1>;
1211                                 reset-names = "dpaux";
1212                                 status = "disabled";
1213
1214                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1215
1216                                 state_dpaux1_aux: pinmux-aux {
1217                                         groups = "dpaux-io";
1218                                         function = "aux";
1219                                 };
1220
1221                                 state_dpaux1_i2c: pinmux-i2c {
1222                                         groups = "dpaux-io";
1223                                         function = "i2c";
1224                                 };
1225
1226                                 state_dpaux1_off: pinmux-off {
1227                                         groups = "dpaux-io";
1228                                         function = "off";
1229                                 };
1230
1231                                 i2c-bus {
1232                                         #address-cells = <1>;
1233                                         #size-cells = <0>;
1234                                 };
1235                         };
1236
1237                         dpaux2: dpaux@155e0000 {
1238                                 compatible = "nvidia,tegra194-dpaux";
1239                                 reg = <0x155e0000 0x10000>;
1240                                 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
1241                                 clocks = <&bpmp TEGRA194_CLK_DPAUX2>,
1242                                          <&bpmp TEGRA194_CLK_PLLDP>;
1243                                 clock-names = "dpaux", "parent";
1244                                 resets = <&bpmp TEGRA194_RESET_DPAUX2>;
1245                                 reset-names = "dpaux";
1246                                 status = "disabled";
1247
1248                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1249
1250                                 state_dpaux2_aux: pinmux-aux {
1251                                         groups = "dpaux-io";
1252                                         function = "aux";
1253                                 };
1254
1255                                 state_dpaux2_i2c: pinmux-i2c {
1256                                         groups = "dpaux-io";
1257                                         function = "i2c";
1258                                 };
1259
1260                                 state_dpaux2_off: pinmux-off {
1261                                         groups = "dpaux-io";
1262                                         function = "off";
1263                                 };
1264
1265                                 i2c-bus {
1266                                         #address-cells = <1>;
1267                                         #size-cells = <0>;
1268                                 };
1269                         };
1270
1271                         dpaux3: dpaux@155f0000 {
1272                                 compatible = "nvidia,tegra194-dpaux";
1273                                 reg = <0x155f0000 0x10000>;
1274                                 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
1275                                 clocks = <&bpmp TEGRA194_CLK_DPAUX3>,
1276                                          <&bpmp TEGRA194_CLK_PLLDP>;
1277                                 clock-names = "dpaux", "parent";
1278                                 resets = <&bpmp TEGRA194_RESET_DPAUX3>;
1279                                 reset-names = "dpaux";
1280                                 status = "disabled";
1281
1282                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1283
1284                                 state_dpaux3_aux: pinmux-aux {
1285                                         groups = "dpaux-io";
1286                                         function = "aux";
1287                                 };
1288
1289                                 state_dpaux3_i2c: pinmux-i2c {
1290                                         groups = "dpaux-io";
1291                                         function = "i2c";
1292                                 };
1293
1294                                 state_dpaux3_off: pinmux-off {
1295                                         groups = "dpaux-io";
1296                                         function = "off";
1297                                 };
1298
1299                                 i2c-bus {
1300                                         #address-cells = <1>;
1301                                         #size-cells = <0>;
1302                                 };
1303                         };
1304
1305                         sor0: sor@15b00000 {
1306                                 compatible = "nvidia,tegra194-sor";
1307                                 reg = <0x15b00000 0x40000>;
1308                                 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1309                                 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>,
1310                                          <&bpmp TEGRA194_CLK_SOR0_OUT>,
1311                                          <&bpmp TEGRA194_CLK_PLLD>,
1312                                          <&bpmp TEGRA194_CLK_PLLDP>,
1313                                          <&bpmp TEGRA194_CLK_SOR_SAFE>,
1314                                          <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>;
1315                                 clock-names = "sor", "out", "parent", "dp", "safe",
1316                                               "pad";
1317                                 resets = <&bpmp TEGRA194_RESET_SOR0>;
1318                                 reset-names = "sor";
1319                                 pinctrl-0 = <&state_dpaux0_aux>;
1320                                 pinctrl-1 = <&state_dpaux0_i2c>;
1321                                 pinctrl-2 = <&state_dpaux0_off>;
1322                                 pinctrl-names = "aux", "i2c", "off";
1323                                 status = "disabled";
1324
1325                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1326                                 nvidia,interface = <0>;
1327                         };
1328
1329                         sor1: sor@15b40000 {
1330                                 compatible = "nvidia,tegra194-sor";
1331                                 reg = <0x15b40000 0x40000>;
1332                                 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1333                                 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>,
1334                                          <&bpmp TEGRA194_CLK_SOR1_OUT>,
1335                                          <&bpmp TEGRA194_CLK_PLLD2>,
1336                                          <&bpmp TEGRA194_CLK_PLLDP>,
1337                                          <&bpmp TEGRA194_CLK_SOR_SAFE>,
1338                                          <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>;
1339                                 clock-names = "sor", "out", "parent", "dp", "safe",
1340                                               "pad";
1341                                 resets = <&bpmp TEGRA194_RESET_SOR1>;
1342                                 reset-names = "sor";
1343                                 pinctrl-0 = <&state_dpaux1_aux>;
1344                                 pinctrl-1 = <&state_dpaux1_i2c>;
1345                                 pinctrl-2 = <&state_dpaux1_off>;
1346                                 pinctrl-names = "aux", "i2c", "off";
1347                                 status = "disabled";
1348
1349                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1350                                 nvidia,interface = <1>;
1351                         };
1352
1353                         sor2: sor@15b80000 {
1354                                 compatible = "nvidia,tegra194-sor";
1355                                 reg = <0x15b80000 0x40000>;
1356                                 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
1357                                 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>,
1358                                          <&bpmp TEGRA194_CLK_SOR2_OUT>,
1359                                          <&bpmp TEGRA194_CLK_PLLD3>,
1360                                          <&bpmp TEGRA194_CLK_PLLDP>,
1361                                          <&bpmp TEGRA194_CLK_SOR_SAFE>,
1362                                          <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>;
1363                                 clock-names = "sor", "out", "parent", "dp", "safe",
1364                                               "pad";
1365                                 resets = <&bpmp TEGRA194_RESET_SOR2>;
1366                                 reset-names = "sor";
1367                                 pinctrl-0 = <&state_dpaux2_aux>;
1368                                 pinctrl-1 = <&state_dpaux2_i2c>;
1369                                 pinctrl-2 = <&state_dpaux2_off>;
1370                                 pinctrl-names = "aux", "i2c", "off";
1371                                 status = "disabled";
1372
1373                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1374                                 nvidia,interface = <2>;
1375                         };
1376
1377                         sor3: sor@15bc0000 {
1378                                 compatible = "nvidia,tegra194-sor";
1379                                 reg = <0x15bc0000 0x40000>;
1380                                 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
1381                                 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>,
1382                                          <&bpmp TEGRA194_CLK_SOR3_OUT>,
1383                                          <&bpmp TEGRA194_CLK_PLLD4>,
1384                                          <&bpmp TEGRA194_CLK_PLLDP>,
1385                                          <&bpmp TEGRA194_CLK_SOR_SAFE>,
1386                                          <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>;
1387                                 clock-names = "sor", "out", "parent", "dp", "safe",
1388                                               "pad";
1389                                 resets = <&bpmp TEGRA194_RESET_SOR3>;
1390                                 reset-names = "sor";
1391                                 pinctrl-0 = <&state_dpaux3_aux>;
1392                                 pinctrl-1 = <&state_dpaux3_i2c>;
1393                                 pinctrl-2 = <&state_dpaux3_off>;
1394                                 pinctrl-names = "aux", "i2c", "off";
1395                                 status = "disabled";
1396
1397                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1398                                 nvidia,interface = <3>;
1399                         };
1400                 };
1401
1402                 gpu@17000000 {
1403                         compatible = "nvidia,gv11b";
1404                         reg = <0x17000000 0x10000000>,
1405                               <0x18000000 0x10000000>;
1406                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
1407                                      <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1408                         interrupt-names = "stall", "nonstall";
1409                         clocks = <&bpmp TEGRA194_CLK_GPCCLK>,
1410                                  <&bpmp TEGRA194_CLK_GPU_PWR>,
1411                                  <&bpmp TEGRA194_CLK_FUSE>;
1412                         clock-names = "gpu", "pwr", "fuse";
1413                         resets = <&bpmp TEGRA194_RESET_GPU>;
1414                         reset-names = "gpu";
1415                         dma-coherent;
1416
1417                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>;
1418                         interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>,
1419                                         <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>,
1420                                         <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>,
1421                                         <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>,
1422                                         <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>,
1423                                         <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>,
1424                                         <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>,
1425                                         <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>,
1426                                         <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>,
1427                                         <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>,
1428                                         <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>,
1429                                         <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>;
1430                         interconnect-names = "dma-mem", "read-0-hp", "write-0",
1431                                              "read-1", "read-1-hp", "write-1",
1432                                              "read-2", "read-2-hp", "write-2",
1433                                              "read-3", "read-3-hp", "write-3";
1434                 };
1435         };
1436
1437         pcie@14100000 {
1438                 compatible = "nvidia,tegra194-pcie";
1439                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
1440                 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K)      */
1441                       <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */
1442                       <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
1443                       <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K)       */
1444                 reg-names = "appl", "config", "atu_dma", "dbi";
1445
1446                 status = "disabled";
1447
1448                 #address-cells = <3>;
1449                 #size-cells = <2>;
1450                 device_type = "pci";
1451                 num-lanes = <1>;
1452                 num-viewport = <8>;
1453                 linux,pci-domain = <1>;
1454
1455                 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>;
1456                 clock-names = "core";
1457
1458                 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>,
1459                          <&bpmp TEGRA194_RESET_PEX0_CORE_1>;
1460                 reset-names = "apb", "core";
1461
1462                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
1463                              <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
1464                 interrupt-names = "intr", "msi";
1465
1466                 #interrupt-cells = <1>;
1467                 interrupt-map-mask = <0 0 0 0>;
1468                 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1469
1470                 nvidia,bpmp = <&bpmp 1>;
1471
1472                 nvidia,aspm-cmrt-us = <60>;
1473                 nvidia,aspm-pwr-on-t-us = <20>;
1474                 nvidia,aspm-l0s-entrance-latency-us = <3>;
1475
1476                 bus-range = <0x0 0xff>;
1477
1478                 ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */
1479                          <0x02000000 0x0  0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */
1480                          <0x01000000 0x0  0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
1481
1482                 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>,
1483                                 <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>;
1484                 interconnect-names = "read", "write";
1485         };
1486
1487         pcie@14120000 {
1488                 compatible = "nvidia,tegra194-pcie";
1489                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
1490                 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K)      */
1491                       <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */
1492                       <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
1493                       <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K)       */
1494                 reg-names = "appl", "config", "atu_dma", "dbi";
1495
1496                 status = "disabled";
1497
1498                 #address-cells = <3>;
1499                 #size-cells = <2>;
1500                 device_type = "pci";
1501                 num-lanes = <1>;
1502                 num-viewport = <8>;
1503                 linux,pci-domain = <2>;
1504
1505                 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>;
1506                 clock-names = "core";
1507
1508                 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>,
1509                          <&bpmp TEGRA194_RESET_PEX0_CORE_2>;
1510                 reset-names = "apb", "core";
1511
1512                 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
1513                              <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
1514                 interrupt-names = "intr", "msi";
1515
1516                 #interrupt-cells = <1>;
1517                 interrupt-map-mask = <0 0 0 0>;
1518                 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1519
1520                 nvidia,bpmp = <&bpmp 2>;
1521
1522                 nvidia,aspm-cmrt-us = <60>;
1523                 nvidia,aspm-pwr-on-t-us = <20>;
1524                 nvidia,aspm-l0s-entrance-latency-us = <3>;
1525
1526                 bus-range = <0x0 0xff>;
1527
1528                 ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */
1529                          <0x02000000 0x0  0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */
1530                          <0x01000000 0x0  0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
1531
1532                 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>,
1533                                 <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>;
1534                 interconnect-names = "read", "write";
1535         };
1536
1537         pcie@14140000 {
1538                 compatible = "nvidia,tegra194-pcie";
1539                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
1540                 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K)      */
1541                       <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */
1542                       <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
1543                       <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K)       */
1544                 reg-names = "appl", "config", "atu_dma", "dbi";
1545
1546                 status = "disabled";
1547
1548                 #address-cells = <3>;
1549                 #size-cells = <2>;
1550                 device_type = "pci";
1551                 num-lanes = <1>;
1552                 num-viewport = <8>;
1553                 linux,pci-domain = <3>;
1554
1555                 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>;
1556                 clock-names = "core";
1557
1558                 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>,
1559                          <&bpmp TEGRA194_RESET_PEX0_CORE_3>;
1560                 reset-names = "apb", "core";
1561
1562                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
1563                              <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
1564                 interrupt-names = "intr", "msi";
1565
1566                 #interrupt-cells = <1>;
1567                 interrupt-map-mask = <0 0 0 0>;
1568                 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1569
1570                 nvidia,bpmp = <&bpmp 3>;
1571
1572                 nvidia,aspm-cmrt-us = <60>;
1573                 nvidia,aspm-pwr-on-t-us = <20>;
1574                 nvidia,aspm-l0s-entrance-latency-us = <3>;
1575
1576                 bus-range = <0x0 0xff>;
1577
1578                 ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */
1579                          <0x02000000 0x0  0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */
1580                          <0x01000000 0x0  0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
1581
1582                 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>,
1583                                 <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>;
1584                 interconnect-names = "read", "write";
1585         };
1586
1587         pcie@14160000 {
1588                 compatible = "nvidia,tegra194-pcie";
1589                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
1590                 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K)      */
1591                       <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */
1592                       <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
1593                       <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K)       */
1594                 reg-names = "appl", "config", "atu_dma", "dbi";
1595
1596                 status = "disabled";
1597
1598                 #address-cells = <3>;
1599                 #size-cells = <2>;
1600                 device_type = "pci";
1601                 num-lanes = <4>;
1602                 num-viewport = <8>;
1603                 linux,pci-domain = <4>;
1604
1605                 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>;
1606                 clock-names = "core";
1607
1608                 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>,
1609                          <&bpmp TEGRA194_RESET_PEX0_CORE_4>;
1610                 reset-names = "apb", "core";
1611
1612                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
1613                              <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
1614                 interrupt-names = "intr", "msi";
1615
1616                 #interrupt-cells = <1>;
1617                 interrupt-map-mask = <0 0 0 0>;
1618                 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1619
1620                 nvidia,bpmp = <&bpmp 4>;
1621
1622                 nvidia,aspm-cmrt-us = <60>;
1623                 nvidia,aspm-pwr-on-t-us = <20>;
1624                 nvidia,aspm-l0s-entrance-latency-us = <3>;
1625
1626                 bus-range = <0x0 0xff>;
1627
1628                 ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */
1629                          <0x02000000 0x0  0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */
1630                          <0x01000000 0x0  0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
1631
1632                 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>,
1633                                 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>;
1634                 interconnect-names = "read", "write";
1635         };
1636
1637         pcie@14180000 {
1638                 compatible = "nvidia,tegra194-pcie";
1639                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
1640                 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K)      */
1641                       <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
1642                       <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
1643                       <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K)       */
1644                 reg-names = "appl", "config", "atu_dma", "dbi";
1645
1646                 status = "disabled";
1647
1648                 #address-cells = <3>;
1649                 #size-cells = <2>;
1650                 device_type = "pci";
1651                 num-lanes = <8>;
1652                 num-viewport = <8>;
1653                 linux,pci-domain = <0>;
1654
1655                 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
1656                 clock-names = "core";
1657
1658                 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
1659                          <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
1660                 reset-names = "apb", "core";
1661
1662                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
1663                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
1664                 interrupt-names = "intr", "msi";
1665
1666                 #interrupt-cells = <1>;
1667                 interrupt-map-mask = <0 0 0 0>;
1668                 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1669
1670                 nvidia,bpmp = <&bpmp 0>;
1671
1672                 nvidia,aspm-cmrt-us = <60>;
1673                 nvidia,aspm-pwr-on-t-us = <20>;
1674                 nvidia,aspm-l0s-entrance-latency-us = <3>;
1675
1676                 bus-range = <0x0 0xff>;
1677
1678                 ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */
1679                          <0x02000000 0x0  0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */
1680                          <0x01000000 0x0  0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
1681
1682                 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>,
1683                                 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>;
1684                 interconnect-names = "read", "write";
1685         };
1686
1687         pcie@141a0000 {
1688                 compatible = "nvidia,tegra194-pcie";
1689                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
1690                 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K)      */
1691                       <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */
1692                       <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
1693                       <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K)       */
1694                 reg-names = "appl", "config", "atu_dma", "dbi";
1695
1696                 status = "disabled";
1697
1698                 #address-cells = <3>;
1699                 #size-cells = <2>;
1700                 device_type = "pci";
1701                 num-lanes = <8>;
1702                 num-viewport = <8>;
1703                 linux,pci-domain = <5>;
1704
1705                 pinctrl-names = "default";
1706                 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
1707
1708                 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>,
1709                          <&bpmp TEGRA194_CLK_PEX1_CORE_5M>;
1710                 clock-names = "core", "core_m";
1711
1712                 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
1713                          <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
1714                 reset-names = "apb", "core";
1715
1716                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
1717                              <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
1718                 interrupt-names = "intr", "msi";
1719
1720                 nvidia,bpmp = <&bpmp 5>;
1721
1722                 #interrupt-cells = <1>;
1723                 interrupt-map-mask = <0 0 0 0>;
1724                 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1725
1726                 nvidia,aspm-cmrt-us = <60>;
1727                 nvidia,aspm-pwr-on-t-us = <20>;
1728                 nvidia,aspm-l0s-entrance-latency-us = <3>;
1729
1730                 bus-range = <0x0 0xff>;
1731
1732                 ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */
1733                          <0x02000000 0x0  0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */
1734                          <0x01000000 0x0  0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */
1735
1736                 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>,
1737                                 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>;
1738                 interconnect-names = "read", "write";
1739         };
1740
1741         pcie_ep@14160000 {
1742                 compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
1743                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
1744                 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K)      */
1745                       <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
1746                       <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K)       */
1747                       <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G)        */
1748                 reg-names = "appl", "atu_dma", "dbi", "addr_space";
1749
1750                 status = "disabled";
1751
1752                 num-lanes = <4>;
1753                 num-ib-windows = <2>;
1754                 num-ob-windows = <8>;
1755
1756                 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>;
1757                 clock-names = "core";
1758
1759                 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>,
1760                          <&bpmp TEGRA194_RESET_PEX0_CORE_4>;
1761                 reset-names = "apb", "core";
1762
1763                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;  /* controller interrupt */
1764                 interrupt-names = "intr";
1765
1766                 nvidia,bpmp = <&bpmp 4>;
1767
1768                 nvidia,aspm-cmrt-us = <60>;
1769                 nvidia,aspm-pwr-on-t-us = <20>;
1770                 nvidia,aspm-l0s-entrance-latency-us = <3>;
1771         };
1772
1773         pcie_ep@14180000 {
1774                 compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
1775                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
1776                 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K)      */
1777                       <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
1778                       <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K)       */
1779                       <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G)        */
1780                 reg-names = "appl", "atu_dma", "dbi", "addr_space";
1781
1782                 status = "disabled";
1783
1784                 num-lanes = <8>;
1785                 num-ib-windows = <2>;
1786                 num-ob-windows = <8>;
1787
1788                 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
1789                 clock-names = "core";
1790
1791                 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
1792                          <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
1793                 reset-names = "apb", "core";
1794
1795                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;  /* controller interrupt */
1796                 interrupt-names = "intr";
1797
1798                 nvidia,bpmp = <&bpmp 0>;
1799
1800                 nvidia,aspm-cmrt-us = <60>;
1801                 nvidia,aspm-pwr-on-t-us = <20>;
1802                 nvidia,aspm-l0s-entrance-latency-us = <3>;
1803         };
1804
1805         pcie_ep@141a0000 {
1806                 compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
1807                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
1808                 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K)      */
1809                       <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
1810                       <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K)       */
1811                       <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G)        */
1812                 reg-names = "appl", "atu_dma", "dbi", "addr_space";
1813
1814                 status = "disabled";
1815
1816                 num-lanes = <8>;
1817                 num-ib-windows = <2>;
1818                 num-ob-windows = <8>;
1819
1820                 pinctrl-names = "default";
1821                 pinctrl-0 = <&clkreq_c5_bi_dir_state>;
1822
1823                 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>;
1824                 clock-names = "core";
1825
1826                 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
1827                          <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
1828                 reset-names = "apb", "core";
1829
1830                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;  /* controller interrupt */
1831                 interrupt-names = "intr";
1832
1833                 nvidia,bpmp = <&bpmp 5>;
1834
1835                 nvidia,aspm-cmrt-us = <60>;
1836                 nvidia,aspm-pwr-on-t-us = <20>;
1837                 nvidia,aspm-l0s-entrance-latency-us = <3>;
1838         };
1839
1840         sram@40000000 {
1841                 compatible = "nvidia,tegra194-sysram", "mmio-sram";
1842                 reg = <0x0 0x40000000 0x0 0x50000>;
1843                 #address-cells = <1>;
1844                 #size-cells = <1>;
1845                 ranges = <0x0 0x0 0x40000000 0x50000>;
1846
1847                 cpu_bpmp_tx: sram@4e000 {
1848                         reg = <0x4e000 0x1000>;
1849                         label = "cpu-bpmp-tx";
1850                         pool;
1851                 };
1852
1853                 cpu_bpmp_rx: sram@4f000 {
1854                         reg = <0x4f000 0x1000>;
1855                         label = "cpu-bpmp-rx";
1856                         pool;
1857                 };
1858         };
1859
1860         bpmp: bpmp {
1861                 compatible = "nvidia,tegra186-bpmp";
1862                 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
1863                                     TEGRA_HSP_DB_MASTER_BPMP>;
1864                 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
1865                 #clock-cells = <1>;
1866                 #reset-cells = <1>;
1867                 #power-domain-cells = <1>;
1868                 interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>,
1869                                 <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>,
1870                                 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>,
1871                                 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>;
1872                 interconnect-names = "read", "write", "dma-mem", "dma-write";
1873
1874                 bpmp_i2c: i2c {
1875                         compatible = "nvidia,tegra186-bpmp-i2c";
1876                         nvidia,bpmp-bus-id = <5>;
1877                         #address-cells = <1>;
1878                         #size-cells = <0>;
1879                 };
1880
1881                 bpmp_thermal: thermal {
1882                         compatible = "nvidia,tegra186-bpmp-thermal";
1883                         #thermal-sensor-cells = <1>;
1884                 };
1885         };
1886
1887         cpus {
1888                 compatible = "nvidia,tegra194-ccplex";
1889                 nvidia,bpmp = <&bpmp>;
1890                 #address-cells = <1>;
1891                 #size-cells = <0>;
1892
1893                 cpu0_0: cpu@0 {
1894                         compatible = "nvidia,tegra194-carmel";
1895                         device_type = "cpu";
1896                         reg = <0x000>;
1897                         enable-method = "psci";
1898                         i-cache-size = <131072>;
1899                         i-cache-line-size = <64>;
1900                         i-cache-sets = <512>;
1901                         d-cache-size = <65536>;
1902                         d-cache-line-size = <64>;
1903                         d-cache-sets = <256>;
1904                         next-level-cache = <&l2c_0>;
1905                 };
1906
1907                 cpu0_1: cpu@1 {
1908                         compatible = "nvidia,tegra194-carmel";
1909                         device_type = "cpu";
1910                         reg = <0x001>;
1911                         enable-method = "psci";
1912                         i-cache-size = <131072>;
1913                         i-cache-line-size = <64>;
1914                         i-cache-sets = <512>;
1915                         d-cache-size = <65536>;
1916                         d-cache-line-size = <64>;
1917                         d-cache-sets = <256>;
1918                         next-level-cache = <&l2c_0>;
1919                 };
1920
1921                 cpu1_0: cpu@100 {
1922                         compatible = "nvidia,tegra194-carmel";
1923                         device_type = "cpu";
1924                         reg = <0x100>;
1925                         enable-method = "psci";
1926                         i-cache-size = <131072>;
1927                         i-cache-line-size = <64>;
1928                         i-cache-sets = <512>;
1929                         d-cache-size = <65536>;
1930                         d-cache-line-size = <64>;
1931                         d-cache-sets = <256>;
1932                         next-level-cache = <&l2c_1>;
1933                 };
1934
1935                 cpu1_1: cpu@101 {
1936                         compatible = "nvidia,tegra194-carmel";
1937                         device_type = "cpu";
1938                         reg = <0x101>;
1939                         enable-method = "psci";
1940                         i-cache-size = <131072>;
1941                         i-cache-line-size = <64>;
1942                         i-cache-sets = <512>;
1943                         d-cache-size = <65536>;
1944                         d-cache-line-size = <64>;
1945                         d-cache-sets = <256>;
1946                         next-level-cache = <&l2c_1>;
1947                 };
1948
1949                 cpu2_0: cpu@200 {
1950                         compatible = "nvidia,tegra194-carmel";
1951                         device_type = "cpu";
1952                         reg = <0x200>;
1953                         enable-method = "psci";
1954                         i-cache-size = <131072>;
1955                         i-cache-line-size = <64>;
1956                         i-cache-sets = <512>;
1957                         d-cache-size = <65536>;
1958                         d-cache-line-size = <64>;
1959                         d-cache-sets = <256>;
1960                         next-level-cache = <&l2c_2>;
1961                 };
1962
1963                 cpu2_1: cpu@201 {
1964                         compatible = "nvidia,tegra194-carmel";
1965                         device_type = "cpu";
1966                         reg = <0x201>;
1967                         enable-method = "psci";
1968                         i-cache-size = <131072>;
1969                         i-cache-line-size = <64>;
1970                         i-cache-sets = <512>;
1971                         d-cache-size = <65536>;
1972                         d-cache-line-size = <64>;
1973                         d-cache-sets = <256>;
1974                         next-level-cache = <&l2c_2>;
1975                 };
1976
1977                 cpu3_0: cpu@300 {
1978                         compatible = "nvidia,tegra194-carmel";
1979                         device_type = "cpu";
1980                         reg = <0x300>;
1981                         enable-method = "psci";
1982                         i-cache-size = <131072>;
1983                         i-cache-line-size = <64>;
1984                         i-cache-sets = <512>;
1985                         d-cache-size = <65536>;
1986                         d-cache-line-size = <64>;
1987                         d-cache-sets = <256>;
1988                         next-level-cache = <&l2c_3>;
1989                 };
1990
1991                 cpu3_1: cpu@301 {
1992                         compatible = "nvidia,tegra194-carmel";
1993                         device_type = "cpu";
1994                         reg = <0x301>;
1995                         enable-method = "psci";
1996                         i-cache-size = <131072>;
1997                         i-cache-line-size = <64>;
1998                         i-cache-sets = <512>;
1999                         d-cache-size = <65536>;
2000                         d-cache-line-size = <64>;
2001                         d-cache-sets = <256>;
2002                         next-level-cache = <&l2c_3>;
2003                 };
2004
2005                 cpu-map {
2006                         cluster0 {
2007                                 core0 {
2008                                         cpu = <&cpu0_0>;
2009                                 };
2010
2011                                 core1 {
2012                                         cpu = <&cpu0_1>;
2013                                 };
2014                         };
2015
2016                         cluster1 {
2017                                 core0 {
2018                                         cpu = <&cpu1_0>;
2019                                 };
2020
2021                                 core1 {
2022                                         cpu = <&cpu1_1>;
2023                                 };
2024                         };
2025
2026                         cluster2 {
2027                                 core0 {
2028                                         cpu = <&cpu2_0>;
2029                                 };
2030
2031                                 core1 {
2032                                         cpu = <&cpu2_1>;
2033                                 };
2034                         };
2035
2036                         cluster3 {
2037                                 core0 {
2038                                         cpu = <&cpu3_0>;
2039                                 };
2040
2041                                 core1 {
2042                                         cpu = <&cpu3_1>;
2043                                 };
2044                         };
2045                 };
2046
2047                 l2c_0: l2-cache0 {
2048                         cache-size = <2097152>;
2049                         cache-line-size = <64>;
2050                         cache-sets = <2048>;
2051                         next-level-cache = <&l3c>;
2052                 };
2053
2054                 l2c_1: l2-cache1 {
2055                         cache-size = <2097152>;
2056                         cache-line-size = <64>;
2057                         cache-sets = <2048>;
2058                         next-level-cache = <&l3c>;
2059                 };
2060
2061                 l2c_2: l2-cache2 {
2062                         cache-size = <2097152>;
2063                         cache-line-size = <64>;
2064                         cache-sets = <2048>;
2065                         next-level-cache = <&l3c>;
2066                 };
2067
2068                 l2c_3: l2-cache3 {
2069                         cache-size = <2097152>;
2070                         cache-line-size = <64>;
2071                         cache-sets = <2048>;
2072                         next-level-cache = <&l3c>;
2073                 };
2074
2075                 l3c: l3-cache {
2076                         cache-size = <4194304>;
2077                         cache-line-size = <64>;
2078                         cache-sets = <4096>;
2079                 };
2080         };
2081
2082         psci {
2083                 compatible = "arm,psci-1.0";
2084                 status = "okay";
2085                 method = "smc";
2086         };
2087
2088         tcu: tcu {
2089                 compatible = "nvidia,tegra194-tcu";
2090                 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>,
2091                          <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>;
2092                 mbox-names = "rx", "tx";
2093         };
2094
2095         thermal-zones {
2096                 cpu {
2097                         thermal-sensors = <&{/bpmp/thermal}
2098                                            TEGRA194_BPMP_THERMAL_ZONE_CPU>;
2099                         status = "disabled";
2100                 };
2101
2102                 gpu {
2103                         thermal-sensors = <&{/bpmp/thermal}
2104                                            TEGRA194_BPMP_THERMAL_ZONE_GPU>;
2105                         status = "disabled";
2106                 };
2107
2108                 aux {
2109                         thermal-sensors = <&{/bpmp/thermal}
2110                                            TEGRA194_BPMP_THERMAL_ZONE_AUX>;
2111                         status = "disabled";
2112                 };
2113
2114                 pllx {
2115                         thermal-sensors = <&{/bpmp/thermal}
2116                                            TEGRA194_BPMP_THERMAL_ZONE_PLLX>;
2117                         status = "disabled";
2118                 };
2119
2120                 ao {
2121                         thermal-sensors = <&{/bpmp/thermal}
2122                                            TEGRA194_BPMP_THERMAL_ZONE_AO>;
2123                         status = "disabled";
2124                 };
2125
2126                 tj {
2127                         thermal-sensors = <&{/bpmp/thermal}
2128                                            TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>;
2129                         status = "disabled";
2130                 };
2131         };
2132
2133         timer {
2134                 compatible = "arm,armv8-timer";
2135                 interrupts = <GIC_PPI 13
2136                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2137                              <GIC_PPI 14
2138                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2139                              <GIC_PPI 11
2140                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2141                              <GIC_PPI 10
2142                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
2143                 interrupt-parent = <&gic>;
2144                 always-on;
2145         };
2146 };