arch/arm64/boot/dts/mediatek/mt6797.dtsi

   1 /*
   2  * Copyright (c) 2017 MediaTek Inc.
   3  * Author: Mars.C <mars.cheng@mediatek.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <dt-bindings/clock/mt6797-clk.h>
  15 #include <dt-bindings/interrupt-controller/irq.h>
  16 #include <dt-bindings/interrupt-controller/arm-gic.h>
  17
  18 / {
  19         compatible = "mediatek,mt6797";
  20         interrupt-parent = <&sysirq>;
  21         #address-cells = <2>;
  22         #size-cells = <2>;
  23
  24         psci {
  25                 compatible = "arm,psci-0.2";
  26                 method = "smc";
  27         };
  28
  29         cpus {
  30                 #address-cells = <1>;
  31                 #size-cells = <0>;
  32
  33                 cpu0: cpu@0 {
  34                         device_type = "cpu";
  35                         compatible = "arm,cortex-a53";
  36                         enable-method = "psci";
  37                         reg = <0x000>;
  38                 };
  39
  40                 cpu1: cpu@1 {
  41                         device_type = "cpu";
  42                         compatible = "arm,cortex-a53";
  43                         enable-method = "psci";
  44                         reg = <0x001>;
  45                 };
  46
  47                 cpu2: cpu@2 {
  48                         device_type = "cpu";
  49                         compatible = "arm,cortex-a53";
  50                         enable-method = "psci";
  51                         reg = <0x002>;
  52                 };
  53
  54                 cpu3: cpu@3 {
  55                         device_type = "cpu";
  56                         compatible = "arm,cortex-a53";
  57                         enable-method = "psci";
  58                         reg = <0x003>;
  59                 };
  60
  61                 cpu4: cpu@100 {
  62                         device_type = "cpu";
  63                         compatible = "arm,cortex-a53";
  64                         enable-method = "psci";
  65                         reg = <0x100>;
  66                 };
  67
  68                 cpu5: cpu@101 {
  69                         device_type = "cpu";
  70                         compatible = "arm,cortex-a53";
  71                         enable-method = "psci";
  72                         reg = <0x101>;
  73                 };
  74
  75                 cpu6: cpu@102 {
  76                         device_type = "cpu";
  77                         compatible = "arm,cortex-a53";
  78                         enable-method = "psci";
  79                         reg = <0x102>;
  80                 };
  81
  82                 cpu7: cpu@103 {
  83                         device_type = "cpu";
  84                         compatible = "arm,cortex-a53";
  85                         enable-method = "psci";
  86                         reg = <0x103>;
  87                 };
  88
  89                 cpu8: cpu@200 {
  90                         device_type = "cpu";
  91                         compatible = "arm,cortex-a72";
  92                         enable-method = "psci";
  93                         reg = <0x200>;
  94                 };
  95
  96                 cpu9: cpu@201 {
  97                         device_type = "cpu";
  98                         compatible = "arm,cortex-a72";
  99                         enable-method = "psci";
 100                         reg = <0x201>;
 101                 };
 102         };
 103
 104         clk26m: oscillator@0 {
 105                 compatible = "fixed-clock";
 106                 #clock-cells = <0>;
 107                 clock-frequency = <26000000>;
 108                 clock-output-names = "clk26m";
 109         };
 110
 111         timer {
 112                 compatible = "arm,armv8-timer";
 113                 interrupt-parent = <&gic>;
 114                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 115                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 116                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 117                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 118         };
 119
 120         topckgen: topckgen@10000000 {
 121                 compatible = "mediatek,mt6797-topckgen";
 122                 reg = <0 0x10000000 0 0x1000>;
 123                 #clock-cells = <1>;
 124         };
 125
 126         infrasys: infracfg_ao@10001000 {
 127                 compatible = "mediatek,mt6797-infracfg", "syscon";
 128                 reg = <0 0x10001000 0 0x1000>;
 129                 #clock-cells = <1>;
 130         };
 131
 132         scpsys: scpsys@10006000 {
 133                 compatible = "mediatek,mt6797-scpsys";
 134                 #power-domain-cells = <1>;
 135                 reg = <0 0x10006000 0 0x1000>;
 136                 clocks = <&topckgen CLK_TOP_MUX_MFG>,
 137                          <&topckgen CLK_TOP_MUX_MM>,
 138                          <&topckgen CLK_TOP_MUX_VDEC>;
 139                 clock-names = "mfg", "mm", "vdec";
 140                 infracfg = <&infrasys>;
 141         };
 142
 143         watchdog: watchdog@10007000 {
 144                 compatible = "mediatek,mt6797-wdt", "mediatek,mt6589-wdt";
 145                 reg = <0 0x10007000 0 0x100>;
 146         };
 147
 148         apmixedsys: apmixed@1000c000 {
 149                 compatible = "mediatek,mt6797-apmixedsys";
 150                 reg = <0 0x1000c000 0 0x1000>;
 151                 #clock-cells = <1>;
 152         };
 153
 154         sysirq: intpol-controller@10200620 {
 155                 compatible = "mediatek,mt6797-sysirq",
 156                              "mediatek,mt6577-sysirq";
 157                 interrupt-controller;
 158                 #interrupt-cells = <3>;
 159                 interrupt-parent = <&gic>;
 160                 reg = <0 0x10220620 0 0x20>,
 161                       <0 0x10220690 0 0x10>;
 162         };
 163
 164         uart0: serial@11002000 {
 165                 compatible = "mediatek,mt6797-uart",
 166                              "mediatek,mt6577-uart";
 167                 reg = <0 0x11002000 0 0x400>;
 168                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
 169                 clocks = <&infrasys CLK_INFRA_UART0>,
 170                          <&infrasys CLK_INFRA_AP_DMA>;
 171                 clock-names = "baud", "bus";
 172                 status = "disabled";
 173         };
 174
 175         uart1: serial@11003000 {
 176                 compatible = "mediatek,mt6797-uart",
 177                              "mediatek,mt6577-uart";
 178                 reg = <0 0x11003000 0 0x400>;
 179                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
 180                 clocks = <&infrasys CLK_INFRA_UART1>,
 181                          <&infrasys CLK_INFRA_AP_DMA>;
 182                 clock-names = "baud", "bus";
 183                 status = "disabled";
 184         };
 185
 186         uart2: serial@11004000 {
 187                 compatible = "mediatek,mt6797-uart",
 188                              "mediatek,mt6577-uart";
 189                 reg = <0 0x11004000 0 0x400>;
 190                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
 191                 clocks = <&infrasys CLK_INFRA_UART2>,
 192                          <&infrasys CLK_INFRA_AP_DMA>;
 193                 clock-names = "baud", "bus";
 194                 status = "disabled";
 195         };
 196
 197         uart3: serial@11005000 {
 198                 compatible = "mediatek,mt6797-uart",
 199                              "mediatek,mt6577-uart";
 200                 reg = <0 0x11005000 0 0x400>;
 201                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
 202                 clocks = <&infrasys CLK_INFRA_UART3>,
 203                          <&infrasys CLK_INFRA_AP_DMA>;
 204                 clock-names = "baud", "bus";
 205                 status = "disabled";
 206         };
 207
 208         mmsys: mmsys_config@14000000 {
 209                 compatible = "mediatek,mt6797-mmsys", "syscon";
 210                 reg = <0 0x14000000 0 0x1000>;
 211                 #clock-cells = <1>;
 212         };
 213
 214         imgsys: imgsys_config@15000000  {
 215                 compatible = "mediatek,mt6797-imgsys", "syscon";
 216                 reg = <0 0x15000000 0 0x1000>;
 217                 #clock-cells = <1>;
 218         };
 219
 220         vdecsys: vdec_gcon@16000000 {
 221                 compatible = "mediatek,mt6797-vdecsys", "syscon";
 222                 reg = <0 0x16000000 0 0x10000>;
 223                 #clock-cells = <1>;
 224         };
 225
 226         vencsys: venc_gcon@17000000 {
 227                 compatible = "mediatek,mt6797-vencsys", "syscon";
 228                 reg = <0 0x17000000 0 0x1000>;
 229                 #clock-cells = <1>;
 230         };
 231
 232         gic: interrupt-controller@19000000 {
 233                 compatible = "arm,gic-v3";
 234                 #interrupt-cells = <3>;
 235                 interrupt-parent = <&gic>;
 236                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 237                 interrupt-controller;
 238                 reg = <0 0x19000000 0 0x10000>,    /* GICD */
 239                       <0 0x19200000 0 0x200000>,   /* GICR */
 240                       <0 0x10240000 0 0x2000>;     /* GICC */
 241         };
 242 };