arch/arm64/boot/dts/freescale/imx93.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2022 NXP
   4  */
   5
   6 #include <dt-bindings/clock/imx93-clock.h>
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/input/input.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/power/fsl,imx93-power.h>
  11 #include <dt-bindings/thermal/thermal.h>
  12
  13 #include "imx93-pinfunc.h"
  14
  15 / {
  16         interrupt-parent = <&gic>;
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         aliases {
  21                 gpio0 = &gpio1;
  22                 gpio1 = &gpio2;
  23                 gpio2 = &gpio3;
  24                 gpio3 = &gpio4;
  25                 i2c0 = &lpi2c1;
  26                 i2c1 = &lpi2c2;
  27                 i2c2 = &lpi2c3;
  28                 i2c3 = &lpi2c4;
  29                 i2c4 = &lpi2c5;
  30                 i2c5 = &lpi2c6;
  31                 i2c6 = &lpi2c7;
  32                 i2c7 = &lpi2c8;
  33                 mmc0 = &usdhc1;
  34                 mmc1 = &usdhc2;
  35                 mmc2 = &usdhc3;
  36                 serial0 = &lpuart1;
  37                 serial1 = &lpuart2;
  38                 serial2 = &lpuart3;
  39                 serial3 = &lpuart4;
  40                 serial4 = &lpuart5;
  41                 serial5 = &lpuart6;
  42                 serial6 = &lpuart7;
  43                 serial7 = &lpuart8;
  44         };
  45
  46         cpus {
  47                 #address-cells = <1>;
  48                 #size-cells = <0>;
  49
  50                 idle-states {
  51                         entry-method = "psci";
  52
  53                         cpu_pd_wait: cpu-pd-wait {
  54                                 compatible = "arm,idle-state";
  55                                 arm,psci-suspend-param = <0x0010033>;
  56                                 local-timer-stop;
  57                                 entry-latency-us = <10000>;
  58                                 exit-latency-us = <7000>;
  59                                 min-residency-us = <27000>;
  60                                 wakeup-latency-us = <15000>;
  61                         };
  62                 };
  63
  64                 A55_0: cpu@0 {
  65                         device_type = "cpu";
  66                         compatible = "arm,cortex-a55";
  67                         reg = <0x0>;
  68                         enable-method = "psci";
  69                         #cooling-cells = <2>;
  70                         cpu-idle-states = <&cpu_pd_wait>;
  71                 };
  72
  73                 A55_1: cpu@100 {
  74                         device_type = "cpu";
  75                         compatible = "arm,cortex-a55";
  76                         reg = <0x100>;
  77                         enable-method = "psci";
  78                         #cooling-cells = <2>;
  79                         cpu-idle-states = <&cpu_pd_wait>;
  80                 };
  81
  82         };
  83
  84         osc_32k: clock-osc-32k {
  85                 compatible = "fixed-clock";
  86                 #clock-cells = <0>;
  87                 clock-frequency = <32768>;
  88                 clock-output-names = "osc_32k";
  89         };
  90
  91         osc_24m: clock-osc-24m {
  92                 compatible = "fixed-clock";
  93                 #clock-cells = <0>;
  94                 clock-frequency = <24000000>;
  95                 clock-output-names = "osc_24m";
  96         };
  97
  98         clk_ext1: clock-ext1 {
  99                 compatible = "fixed-clock";
 100                 #clock-cells = <0>;
 101                 clock-frequency = <133000000>;
 102                 clock-output-names = "clk_ext1";
 103         };
 104
 105         pmu {
 106                 compatible = "arm,cortex-a55-pmu";
 107                 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 108         };
 109
 110         psci {
 111                 compatible = "arm,psci-1.0";
 112                 method = "smc";
 113         };
 114
 115         timer {
 116                 compatible = "arm,armv8-timer";
 117                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
 118                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
 119                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
 120                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
 121                 clock-frequency = <24000000>;
 122                 arm,no-tick-in-suspend;
 123                 interrupt-parent = <&gic>;
 124         };
 125
 126         gic: interrupt-controller@48000000 {
 127                 compatible = "arm,gic-v3";
 128                 reg = <0 0x48000000 0 0x10000>,
 129                       <0 0x48040000 0 0xc0000>;
 130                 #interrupt-cells = <3>;
 131                 interrupt-controller;
 132                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 133                 interrupt-parent = <&gic>;
 134         };
 135
 136         thermal-zones {
 137                 cpu-thermal {
 138                         polling-delay-passive = <250>;
 139                         polling-delay = <2000>;
 140
 141                         thermal-sensors = <&tmu 0>;
 142
 143                         trips {
 144                                 cpu_alert: cpu-alert {
 145                                         temperature = <80000>;
 146                                         hysteresis = <2000>;
 147                                         type = "passive";
 148                                 };
 149
 150                                 cpu_crit: cpu-crit {
 151                                         temperature = <90000>;
 152                                         hysteresis = <2000>;
 153                                         type = "critical";
 154                                 };
 155                         };
 156
 157                         cooling-maps {
 158                                 map0 {
 159                                         trip = <&cpu_alert>;
 160                                         cooling-device =
 161                                                 <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 162                                                 <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 163                                 };
 164                         };
 165                 };
 166         };
 167
 168         cm33: remoteproc-cm33 {
 169                 compatible = "fsl,imx93-cm33";
 170                 clocks = <&clk IMX93_CLK_CM33_GATE>;
 171                 status = "disabled";
 172         };
 173
 174         mqs1: mqs1 {
 175                 compatible = "fsl,imx93-mqs";
 176                 gpr = <&aonmix_ns_gpr>;
 177                 status = "disabled";
 178         };
 179
 180         mqs2: mqs2 {
 181                 compatible = "fsl,imx93-mqs";
 182                 gpr = <&wakeupmix_gpr>;
 183                 status = "disabled";
 184         };
 185
 186         soc@0 {
 187                 compatible = "simple-bus";
 188                 #address-cells = <1>;
 189                 #size-cells = <1>;
 190                 ranges = <0x0 0x0 0x0 0x80000000>,
 191                          <0x28000000 0x0 0x28000000 0x10000000>;
 192
 193                 aips1: bus@44000000 {
 194                         compatible = "fsl,aips-bus", "simple-bus";
 195                         reg = <0x44000000 0x800000>;
 196                         #address-cells = <1>;
 197                         #size-cells = <1>;
 198                         ranges;
 199
 200                         edma1: dma-controller@44000000 {
 201                                 compatible = "fsl,imx93-edma3";
 202                                 reg = <0x44000000 0x200000>;
 203                                 #dma-cells = <3>;
 204                                 dma-channels = <31>;
 205                                 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,  //  0: Reserved
 206                                              <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,  //  1: CANFD1
 207                                              <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,  //  2: Reserved
 208                                              <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,  //  3: GPIO1 CH0
 209                                              <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,  //  4: GPIO1 CH1
 210                                              <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, //  5: I3C1 TO Bus
 211                                              <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, //  6: I3C1 From Bus
 212                                              <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, //  7: LPI2C1 M TX
 213                                              <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, //  8: LPI2C1 S TX
 214                                              <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, //  9: LPI2C2 M RX
 215                                              <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, // 10: LPI2C2 S RX
 216                                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, // 11: LPSPI1 TX
 217                                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, // 12: LPSPI1 RX
 218                                              <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, // 13: LPSPI2 TX
 219                                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, // 14: LPSPI2 RX
 220                                              <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, // 15: LPTMR1
 221                                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, // 16: LPUART1 TX
 222                                              <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, // 17: LPUART1 RX
 223                                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, // 18: LPUART2 TX
 224                                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, // 19: LPUART2 RX
 225                                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, // 20: S400
 226                                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, // 21: SAI TX
 227                                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, // 22: SAI RX
 228                                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, // 23: TPM1 CH0/CH2
 229                                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, // 24: TPM1 CH1/CH3
 230                                              <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, // 25: TPM1 Overflow
 231                                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, // 26: TMP2 CH0/CH2
 232                                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, // 27: TMP2 CH1/CH3
 233                                              <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, // 28: TMP2 Overflow
 234                                              <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, // 29: PDM
 235                                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; // 30: ADC1
 236                                 clocks = <&clk IMX93_CLK_EDMA1_GATE>;
 237                                 clock-names = "dma";
 238                         };
 239
 240                         aonmix_ns_gpr: syscon@44210000 {
 241                                 compatible = "fsl,imx93-aonmix-ns-syscfg", "syscon";
 242                                 reg = <0x44210000 0x1000>;
 243                         };
 244
 245                         mu1: mailbox@44230000 {
 246                                 compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu";
 247                                 reg = <0x44230000 0x10000>;
 248                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 249                                 clocks = <&clk IMX93_CLK_MU1_B_GATE>;
 250                                 #mbox-cells = <2>;
 251                                 status = "disabled";
 252                         };
 253
 254                         system_counter: timer@44290000 {
 255                                 compatible = "nxp,sysctr-timer";
 256                                 reg = <0x44290000 0x30000>;
 257                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 258                                 clocks = <&osc_24m>;
 259                                 clock-names = "per";
 260                                 nxp,no-divider;
 261                         };
 262
 263                         wdog1: watchdog@442d0000 {
 264                                 compatible = "fsl,imx93-wdt";
 265                                 reg = <0x442d0000 0x10000>;
 266                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 267                                 clocks = <&clk IMX93_CLK_WDOG1_GATE>;
 268                                 timeout-sec = <40>;
 269                                 status = "disabled";
 270                         };
 271
 272                         wdog2: watchdog@442e0000 {
 273                                 compatible = "fsl,imx93-wdt";
 274                                 reg = <0x442e0000 0x10000>;
 275                                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 276                                 clocks = <&clk IMX93_CLK_WDOG2_GATE>;
 277                                 timeout-sec = <40>;
 278                                 status = "disabled";
 279                         };
 280
 281                         tpm1: pwm@44310000 {
 282                                 compatible = "fsl,imx7ulp-pwm";
 283                                 reg = <0x44310000 0x1000>;
 284                                 clocks = <&clk IMX93_CLK_TPM1_GATE>;
 285                                 #pwm-cells = <3>;
 286                                 status = "disabled";
 287                         };
 288
 289                         tpm2: pwm@44320000 {
 290                                 compatible = "fsl,imx7ulp-pwm";
 291                                 reg = <0x44320000 0x10000>;
 292                                 clocks = <&clk IMX93_CLK_TPM2_GATE>;
 293                                 #pwm-cells = <3>;
 294                                 status = "disabled";
 295                         };
 296
 297                         i3c1: i3c@44330000 {
 298                                 compatible = "silvaco,i3c-master-v1";
 299                                 reg = <0x44330000 0x10000>;
 300                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 301                                 #address-cells = <3>;
 302                                 #size-cells = <0>;
 303                                 clocks = <&clk IMX93_CLK_BUS_AON>,
 304                                          <&clk IMX93_CLK_I3C1_GATE>,
 305                                          <&clk IMX93_CLK_I3C1_SLOW>;
 306                                 clock-names = "pclk", "fast_clk", "slow_clk";
 307                                 status = "disabled";
 308                         };
 309
 310                         lpi2c1: i2c@44340000 {
 311                                 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
 312                                 reg = <0x44340000 0x10000>;
 313                                 #address-cells = <1>;
 314                                 #size-cells = <0>;
 315                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 316                                 clocks = <&clk IMX93_CLK_LPI2C1_GATE>,
 317                                          <&clk IMX93_CLK_BUS_AON>;
 318                                 clock-names = "per", "ipg";
 319                                 status = "disabled";
 320                         };
 321
 322                         lpi2c2: i2c@44350000 {
 323                                 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
 324                                 reg = <0x44350000 0x10000>;
 325                                 #address-cells = <1>;
 326                                 #size-cells = <0>;
 327                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 328                                 clocks = <&clk IMX93_CLK_LPI2C2_GATE>,
 329                                          <&clk IMX93_CLK_BUS_AON>;
 330                                 clock-names = "per", "ipg";
 331                                 status = "disabled";
 332                         };
 333
 334                         lpspi1: spi@44360000 {
 335                                 #address-cells = <1>;
 336                                 #size-cells = <0>;
 337                                 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
 338                                 reg = <0x44360000 0x10000>;
 339                                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 340                                 clocks = <&clk IMX93_CLK_LPSPI1_GATE>,
 341                                          <&clk IMX93_CLK_BUS_AON>;
 342                                 clock-names = "per", "ipg";
 343                                 status = "disabled";
 344                         };
 345
 346                         lpspi2: spi@44370000 {
 347                                 #address-cells = <1>;
 348                                 #size-cells = <0>;
 349                                 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
 350                                 reg = <0x44370000 0x10000>;
 351                                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 352                                 clocks = <&clk IMX93_CLK_LPSPI2_GATE>,
 353                                          <&clk IMX93_CLK_BUS_AON>;
 354                                 clock-names = "per", "ipg";
 355                                 status = "disabled";
 356                         };
 357
 358                         lpuart1: serial@44380000 {
 359                                 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
 360                                 reg = <0x44380000 0x1000>;
 361                                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 362                                 clocks = <&clk IMX93_CLK_LPUART1_GATE>;
 363                                 clock-names = "ipg";
 364                                 dmas = <&edma1 17 0 1>, <&edma1 16 0 0>;
 365                                 dma-names = "rx", "tx";
 366                                 status = "disabled";
 367                         };
 368
 369                         lpuart2: serial@44390000 {
 370                                 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
 371                                 reg = <0x44390000 0x1000>;
 372                                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 373                                 clocks = <&clk IMX93_CLK_LPUART2_GATE>;
 374                                 clock-names = "ipg";
 375                                 dmas = <&edma1 19 0 1>, <&edma1 18 0 0>;
 376                                 dma-names = "rx", "tx";
 377                                 status = "disabled";
 378                         };
 379
 380                         flexcan1: can@443a0000 {
 381                                 compatible = "fsl,imx93-flexcan";
 382                                 reg = <0x443a0000 0x10000>;
 383                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 384                                 clocks = <&clk IMX93_CLK_BUS_AON>,
 385                                          <&clk IMX93_CLK_CAN1_GATE>;
 386                                 clock-names = "ipg", "per";
 387                                 assigned-clocks = <&clk IMX93_CLK_CAN1>;
 388                                 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
 389                                 assigned-clock-rates = <40000000>;
 390                                 fsl,clk-source = /bits/ 8 <0>;
 391                                 fsl,stop-mode = <&aonmix_ns_gpr 0x14 0>;
 392                                 status = "disabled";
 393                         };
 394
 395                         sai1: sai@443b0000 {
 396                                 compatible = "fsl,imx93-sai";
 397                                 reg = <0x443b0000 0x10000>;
 398                                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 399                                 clocks = <&clk IMX93_CLK_SAI1_IPG>, <&clk IMX93_CLK_DUMMY>,
 400                                          <&clk IMX93_CLK_SAI1_GATE>, <&clk IMX93_CLK_DUMMY>,
 401                                          <&clk IMX93_CLK_DUMMY>;
 402                                 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
 403                                 dmas = <&edma1 22 0 1>, <&edma1 21 0 0>;
 404                                 dma-names = "rx", "tx";
 405                                 status = "disabled";
 406                         };
 407
 408                         iomuxc: pinctrl@443c0000 {
 409                                 compatible = "fsl,imx93-iomuxc";
 410                                 reg = <0x443c0000 0x10000>;
 411                                 status = "okay";
 412                         };
 413
 414                         bbnsm: bbnsm@44440000 {
 415                                 compatible = "nxp,imx93-bbnsm", "syscon", "simple-mfd";
 416                                 reg = <0x44440000 0x10000>;
 417
 418                                 bbnsm_rtc: rtc {
 419                                         compatible = "nxp,imx93-bbnsm-rtc";
 420                                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 421                                 };
 422
 423                                 bbnsm_pwrkey: pwrkey {
 424                                         compatible = "nxp,imx93-bbnsm-pwrkey";
 425                                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 426                                         linux,code = <KEY_POWER>;
 427                                 };
 428                         };
 429
 430                         clk: clock-controller@44450000 {
 431                                 compatible = "fsl,imx93-ccm";
 432                                 reg = <0x44450000 0x10000>;
 433                                 #clock-cells = <1>;
 434                                 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>;
 435                                 clock-names = "osc_32k", "osc_24m", "clk_ext1";
 436                                 assigned-clocks = <&clk IMX93_CLK_AUDIO_PLL>;
 437                                 assigned-clock-rates = <393216000>;
 438                                 status = "okay";
 439                         };
 440
 441                         src: system-controller@44460000 {
 442                                 compatible = "fsl,imx93-src", "syscon";
 443                                 reg = <0x44460000 0x10000>;
 444                                 #address-cells = <1>;
 445                                 #size-cells = <1>;
 446                                 ranges;
 447
 448                                 mlmix: power-domain@44461800 {
 449                                         compatible = "fsl,imx93-src-slice";
 450                                         reg = <0x44461800 0x400>, <0x44464800 0x400>;
 451                                         #power-domain-cells = <0>;
 452                                         clocks = <&clk IMX93_CLK_ML_APB>,
 453                                                  <&clk IMX93_CLK_ML>;
 454                                 };
 455
 456                                 mediamix: power-domain@44462400 {
 457                                         compatible = "fsl,imx93-src-slice";
 458                                         reg = <0x44462400 0x400>, <0x44465800 0x400>;
 459                                         #power-domain-cells = <0>;
 460                                         clocks = <&clk IMX93_CLK_NIC_MEDIA_GATE>,
 461                                                  <&clk IMX93_CLK_MEDIA_APB>;
 462                                 };
 463                         };
 464
 465                         clock-controller@44480000 {
 466                                 compatible = "fsl,imx93-anatop";
 467                                 reg = <0x44480000 0x2000>;
 468                                 #clock-cells = <1>;
 469                         };
 470
 471                         tmu: tmu@44482000 {
 472                                 compatible = "fsl,qoriq-tmu";
 473                                 reg = <0x44482000 0x1000>;
 474                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 475                                 clocks = <&clk IMX93_CLK_TMC_GATE>;
 476                                 little-endian;
 477                                 fsl,tmu-range = <0x800000da 0x800000e9
 478                                                  0x80000102 0x8000012a
 479                                                  0x80000166 0x800001a7
 480                                                  0x800001b6>;
 481                                 fsl,tmu-calibration = <0x00000000 0x0000000e
 482                                                        0x00000001 0x00000029
 483                                                        0x00000002 0x00000056
 484                                                        0x00000003 0x000000a2
 485                                                        0x00000004 0x00000116
 486                                                        0x00000005 0x00000195
 487                                                        0x00000006 0x000001b2>;
 488                                 #thermal-sensor-cells = <1>;
 489                         };
 490
 491                         micfil: micfil@44520000 {
 492                                 compatible = "fsl,imx93-micfil";
 493                                 reg = <0x44520000 0x10000>;
 494                                 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
 495                                              <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
 496                                              <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
 497                                              <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
 498                                 clocks = <&clk IMX93_CLK_PDM_IPG>,
 499                                          <&clk IMX93_CLK_PDM_GATE>,
 500                                          <&clk IMX93_CLK_AUDIO_PLL>;
 501                                 clock-names = "ipg_clk", "ipg_clk_app", "pll8k";
 502                                 dmas = <&edma1 29 0 5>;
 503                                 dma-names = "rx";
 504                                 status = "disabled";
 505                         };
 506
 507                         adc1: adc@44530000 {
 508                                 compatible = "nxp,imx93-adc";
 509                                 reg = <0x44530000 0x10000>;
 510                                 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
 511                                              <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
 512                                              <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
 513                                              <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
 514                                 clocks = <&clk IMX93_CLK_ADC1_GATE>;
 515                                 clock-names = "ipg";
 516                                 #io-channel-cells = <1>;
 517                                 status = "disabled";
 518                         };
 519                 };
 520
 521                 aips2: bus@42000000 {
 522                         compatible = "fsl,aips-bus", "simple-bus";
 523                         reg = <0x42000000 0x800000>;
 524                         #address-cells = <1>;
 525                         #size-cells = <1>;
 526                         ranges;
 527
 528                         edma2: dma-controller@42000000 {
 529                                 compatible = "fsl,imx93-edma4";
 530                                 reg = <0x42000000 0x210000>;
 531                                 #dma-cells = <3>;
 532                                 dma-channels = <64>;
 533                                 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
 534                                              <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
 535                                              <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
 536                                              <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
 537                                              <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
 538                                              <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
 539                                              <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
 540                                              <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
 541                                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
 542                                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
 543                                              <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 544                                              <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 545                                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 546                                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 547                                              <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 548                                              <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 549                                              <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
 550                                              <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
 551                                              <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 552                                              <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 553                                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 554                                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 555                                              <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
 556                                              <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
 557                                              <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
 558                                              <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
 559                                              <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 560                                              <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 561                                              <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 562                                              <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 563                                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
 564                                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
 565                                              <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
 566                                              <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
 567                                              <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
 568                                              <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
 569                                              <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 570                                              <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 571                                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 572                                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 573                                              <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 574                                              <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 575                                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
 576                                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
 577                                              <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
 578                                              <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
 579                                              <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
 580                                              <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
 581                                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
 582                                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
 583                                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
 584                                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
 585                                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
 586                                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
 587                                              <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
 588                                              <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
 589                                              <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
 590                                              <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
 591                                              <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
 592                                              <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
 593                                              <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
 594                                              <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
 595                                              <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
 596                                              <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
 597                                 clocks = <&clk IMX93_CLK_EDMA2_GATE>;
 598                                 clock-names = "dma";
 599                         };
 600
 601                         wakeupmix_gpr: syscon@42420000 {
 602                                 compatible = "fsl,imx93-wakeupmix-syscfg", "syscon";
 603                                 reg = <0x42420000 0x1000>;
 604                         };
 605
 606                         mu2: mailbox@42440000 {
 607                                 compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu";
 608                                 reg = <0x42440000 0x10000>;
 609                                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 610                                 clocks = <&clk IMX93_CLK_MU2_B_GATE>;
 611                                 #mbox-cells = <2>;
 612                                 status = "disabled";
 613                         };
 614
 615                         wdog3: watchdog@42490000 {
 616                                 compatible = "fsl,imx93-wdt";
 617                                 reg = <0x42490000 0x10000>;
 618                                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 619                                 clocks = <&clk IMX93_CLK_WDOG3_GATE>;
 620                                 timeout-sec = <40>;
 621                                 status = "disabled";
 622                         };
 623
 624                         wdog4: watchdog@424a0000 {
 625                                 compatible = "fsl,imx93-wdt";
 626                                 reg = <0x424a0000 0x10000>;
 627                                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 628                                 clocks = <&clk IMX93_CLK_WDOG4_GATE>;
 629                                 timeout-sec = <40>;
 630                                 status = "disabled";
 631                         };
 632
 633                         wdog5: watchdog@424b0000 {
 634                                 compatible = "fsl,imx93-wdt";
 635                                 reg = <0x424b0000 0x10000>;
 636                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 637                                 clocks = <&clk IMX93_CLK_WDOG5_GATE>;
 638                                 timeout-sec = <40>;
 639                                 status = "disabled";
 640                         };
 641
 642                         tpm3: pwm@424e0000 {
 643                                 compatible = "fsl,imx7ulp-pwm";
 644                                 reg = <0x424e0000 0x1000>;
 645                                 clocks = <&clk IMX93_CLK_TPM3_GATE>;
 646                                 #pwm-cells = <3>;
 647                                 status = "disabled";
 648                         };
 649
 650                         tpm4: pwm@424f0000 {
 651                                 compatible = "fsl,imx7ulp-pwm";
 652                                 reg = <0x424f0000 0x10000>;
 653                                 clocks = <&clk IMX93_CLK_TPM4_GATE>;
 654                                 #pwm-cells = <3>;
 655                                 status = "disabled";
 656                         };
 657
 658                         tpm5: pwm@42500000 {
 659                                 compatible = "fsl,imx7ulp-pwm";
 660                                 reg = <0x42500000 0x10000>;
 661                                 clocks = <&clk IMX93_CLK_TPM5_GATE>;
 662                                 #pwm-cells = <3>;
 663                                 status = "disabled";
 664                         };
 665
 666                         tpm6: pwm@42510000 {
 667                                 compatible = "fsl,imx7ulp-pwm";
 668                                 reg = <0x42510000 0x10000>;
 669                                 clocks = <&clk IMX93_CLK_TPM6_GATE>;
 670                                 #pwm-cells = <3>;
 671                                 status = "disabled";
 672                         };
 673
 674                         i3c2: i3c@42520000 {
 675                                 compatible = "silvaco,i3c-master-v1";
 676                                 reg = <0x42520000 0x10000>;
 677                                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 678                                 #address-cells = <3>;
 679                                 #size-cells = <0>;
 680                                 clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
 681                                          <&clk IMX93_CLK_I3C2_GATE>,
 682                                          <&clk IMX93_CLK_I3C2_SLOW>;
 683                                 clock-names = "pclk", "fast_clk", "slow_clk";
 684                                 status = "disabled";
 685                         };
 686
 687                         lpi2c3: i2c@42530000 {
 688                                 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
 689                                 reg = <0x42530000 0x10000>;
 690                                 #address-cells = <1>;
 691                                 #size-cells = <0>;
 692                                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 693                                 clocks = <&clk IMX93_CLK_LPI2C3_GATE>,
 694                                          <&clk IMX93_CLK_BUS_WAKEUP>;
 695                                 clock-names = "per", "ipg";
 696                                 status = "disabled";
 697                         };
 698
 699                         lpi2c4: i2c@42540000 {
 700                                 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
 701                                 reg = <0x42540000 0x10000>;
 702                                 #address-cells = <1>;
 703                                 #size-cells = <0>;
 704                                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 705                                 clocks = <&clk IMX93_CLK_LPI2C4_GATE>,
 706                                          <&clk IMX93_CLK_BUS_WAKEUP>;
 707                                 clock-names = "per", "ipg";
 708                                 status = "disabled";
 709                         };
 710
 711                         lpspi3: spi@42550000 {
 712                                 #address-cells = <1>;
 713                                 #size-cells = <0>;
 714                                 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
 715                                 reg = <0x42550000 0x10000>;
 716                                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 717                                 clocks = <&clk IMX93_CLK_LPSPI3_GATE>,
 718                                          <&clk IMX93_CLK_BUS_WAKEUP>;
 719                                 clock-names = "per", "ipg";
 720                                 status = "disabled";
 721                         };
 722
 723                         lpspi4: spi@42560000 {
 724                                 #address-cells = <1>;
 725                                 #size-cells = <0>;
 726                                 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
 727                                 reg = <0x42560000 0x10000>;
 728                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 729                                 clocks = <&clk IMX93_CLK_LPSPI4_GATE>,
 730                                          <&clk IMX93_CLK_BUS_WAKEUP>;
 731                                 clock-names = "per", "ipg";
 732                                 status = "disabled";
 733                         };
 734
 735                         lpuart3: serial@42570000 {
 736                                 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
 737                                 reg = <0x42570000 0x1000>;
 738                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 739                                 clocks = <&clk IMX93_CLK_LPUART3_GATE>;
 740                                 clock-names = "ipg";
 741                                 dmas = <&edma2 18 0 1>, <&edma2 17 0 0>;
 742                                 dma-names = "rx", "tx";
 743                                 status = "disabled";
 744                         };
 745
 746                         lpuart4: serial@42580000 {
 747                                 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
 748                                 reg = <0x42580000 0x1000>;
 749                                 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 750                                 clocks = <&clk IMX93_CLK_LPUART4_GATE>;
 751                                 clock-names = "ipg";
 752                                 dmas = <&edma2 20 0 1>, <&edma2 19 0 0>;
 753                                 dma-names = "rx", "tx";
 754                                 status = "disabled";
 755                         };
 756
 757                         lpuart5: serial@42590000 {
 758                                 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
 759                                 reg = <0x42590000 0x1000>;
 760                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 761                                 clocks = <&clk IMX93_CLK_LPUART5_GATE>;
 762                                 clock-names = "ipg";
 763                                 dmas = <&edma2 22 0 1>, <&edma2 21 0 0>;
 764                                 dma-names = "rx", "tx";
 765                                 status = "disabled";
 766                         };
 767
 768                         lpuart6: serial@425a0000 {
 769                                 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
 770                                 reg = <0x425a0000 0x1000>;
 771                                 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 772                                 clocks = <&clk IMX93_CLK_LPUART6_GATE>;
 773                                 clock-names = "ipg";
 774                                 dmas = <&edma2 24 0 1>, <&edma2 23 0 0>;
 775                                 dma-names = "rx", "tx";
 776                                 status = "disabled";
 777                         };
 778
 779                         flexcan2: can@425b0000 {
 780                                 compatible = "fsl,imx93-flexcan";
 781                                 reg = <0x425b0000 0x10000>;
 782                                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 783                                 clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
 784                                          <&clk IMX93_CLK_CAN2_GATE>;
 785                                 clock-names = "ipg", "per";
 786                                 assigned-clocks = <&clk IMX93_CLK_CAN2>;
 787                                 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
 788                                 assigned-clock-rates = <40000000>;
 789                                 fsl,clk-source = /bits/ 8 <0>;
 790                                 fsl,stop-mode = <&wakeupmix_gpr 0x0c 2>;
 791                                 status = "disabled";
 792                         };
 793
 794                         flexspi1: spi@425e0000 {
 795                                 compatible = "nxp,imx8mm-fspi";
 796                                 reg = <0x425e0000 0x10000>, <0x28000000 0x10000000>;
 797                                 reg-names = "fspi_base", "fspi_mmap";
 798                                 #address-cells = <1>;
 799                                 #size-cells = <0>;
 800                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 801                                 clocks = <&clk IMX93_CLK_FLEXSPI1_GATE>,
 802                                          <&clk IMX93_CLK_FLEXSPI1_GATE>;
 803                                 clock-names = "fspi_en", "fspi";
 804                                 assigned-clocks = <&clk IMX93_CLK_FLEXSPI1>;
 805                                 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>;
 806                                 status = "disabled";
 807                         };
 808
 809                         sai2: sai@42650000 {
 810                                 compatible = "fsl,imx93-sai";
 811                                 reg = <0x42650000 0x10000>;
 812                                 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
 813                                 clocks = <&clk IMX93_CLK_SAI2_IPG>, <&clk IMX93_CLK_DUMMY>,
 814                                          <&clk IMX93_CLK_SAI2_GATE>, <&clk IMX93_CLK_DUMMY>,
 815                                          <&clk IMX93_CLK_DUMMY>;
 816                                 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
 817                                 dmas = <&edma2 59 0 1>, <&edma2 58 0 0>;
 818                                 dma-names = "rx", "tx";
 819                                 status = "disabled";
 820                         };
 821
 822                         sai3: sai@42660000 {
 823                                 compatible = "fsl,imx93-sai";
 824                                 reg = <0x42660000 0x10000>;
 825                                 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
 826                                 clocks = <&clk IMX93_CLK_SAI3_IPG>, <&clk IMX93_CLK_DUMMY>,
 827                                          <&clk IMX93_CLK_SAI3_GATE>, <&clk IMX93_CLK_DUMMY>,
 828                                          <&clk IMX93_CLK_DUMMY>;
 829                                 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
 830                                 dmas = <&edma2 61 0 1>, <&edma2 60 0 0>;
 831                                 dma-names = "rx", "tx";
 832                                 status = "disabled";
 833                         };
 834
 835                         xcvr: xcvr@42680000 {
 836                                 compatible = "fsl,imx93-xcvr";
 837                                 reg = <0x42680000 0x800>,
 838                                       <0x42680800 0x400>,
 839                                       <0x42680c00 0x080>,
 840                                       <0x42680e00 0x080>;
 841                                 reg-names = "ram", "regs", "rxfifo", "txfifo";
 842                                 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
 843                                              <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
 844                                 clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
 845                                          <&clk IMX93_CLK_SPDIF_GATE>,
 846                                          <&clk IMX93_CLK_DUMMY>,
 847                                          <&clk IMX93_CLK_AUD_XCVR_GATE>;
 848                                 clock-names = "ipg", "phy", "spba", "pll_ipg";
 849                                 dmas = <&edma2 65 0 1>, <&edma2 66 0 0>;
 850                                 dma-names = "rx", "tx";
 851                                 status = "disabled";
 852                         };
 853
 854                         lpuart7: serial@42690000 {
 855                                 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
 856                                 reg = <0x42690000 0x1000>;
 857                                 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>;
 858                                 clocks = <&clk IMX93_CLK_LPUART7_GATE>;
 859                                 clock-names = "ipg";
 860                                 dmas = <&edma2 88 0 1>, <&edma2 87 0 0>;
 861                                 dma-names = "rx", "tx";
 862                                 status = "disabled";
 863                         };
 864
 865                         lpuart8: serial@426a0000 {
 866                                 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
 867                                 reg = <0x426a0000 0x1000>;
 868                                 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
 869                                 clocks = <&clk IMX93_CLK_LPUART8_GATE>;
 870                                 clock-names = "ipg";
 871                                 dmas = <&edma2 90 0 1>, <&edma2 89 0 0>;
 872                                 dma-names = "rx", "tx";
 873                                 status = "disabled";
 874                         };
 875
 876                         lpi2c5: i2c@426b0000 {
 877                                 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
 878                                 reg = <0x426b0000 0x10000>;
 879                                 #address-cells = <1>;
 880                                 #size-cells = <0>;
 881                                 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
 882                                 clocks = <&clk IMX93_CLK_LPI2C5_GATE>,
 883                                          <&clk IMX93_CLK_BUS_WAKEUP>;
 884                                 clock-names = "per", "ipg";
 885                                 status = "disabled";
 886                         };
 887
 888                         lpi2c6: i2c@426c0000 {
 889                                 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
 890                                 reg = <0x426c0000 0x10000>;
 891                                 #address-cells = <1>;
 892                                 #size-cells = <0>;
 893                                 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
 894                                 clocks = <&clk IMX93_CLK_LPI2C6_GATE>,
 895                                          <&clk IMX93_CLK_BUS_WAKEUP>;
 896                                 clock-names = "per", "ipg";
 897                                 status = "disabled";
 898                         };
 899
 900                         lpi2c7: i2c@426d0000 {
 901                                 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
 902                                 reg = <0x426d0000 0x10000>;
 903                                 #address-cells = <1>;
 904                                 #size-cells = <0>;
 905                                 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
 906                                 clocks = <&clk IMX93_CLK_LPI2C7_GATE>,
 907                                          <&clk IMX93_CLK_BUS_WAKEUP>;
 908                                 clock-names = "per", "ipg";
 909                                 status = "disabled";
 910                         };
 911
 912                         lpi2c8: i2c@426e0000 {
 913                                 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
 914                                 reg = <0x426e0000 0x10000>;
 915                                 #address-cells = <1>;
 916                                 #size-cells = <0>;
 917                                 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
 918                                 clocks = <&clk IMX93_CLK_LPI2C8_GATE>,
 919                                          <&clk IMX93_CLK_BUS_WAKEUP>;
 920                                 clock-names = "per", "ipg";
 921                                 status = "disabled";
 922                         };
 923
 924                         lpspi5: spi@426f0000 {
 925                                 #address-cells = <1>;
 926                                 #size-cells = <0>;
 927                                 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
 928                                 reg = <0x426f0000 0x10000>;
 929                                 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
 930                                 clocks = <&clk IMX93_CLK_LPSPI5_GATE>,
 931                                          <&clk IMX93_CLK_BUS_WAKEUP>;
 932                                 clock-names = "per", "ipg";
 933                                 status = "disabled";
 934                         };
 935
 936                         lpspi6: spi@42700000 {
 937                                 #address-cells = <1>;
 938                                 #size-cells = <0>;
 939                                 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
 940                                 reg = <0x42700000 0x10000>;
 941                                 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
 942                                 clocks = <&clk IMX93_CLK_LPSPI6_GATE>,
 943                                          <&clk IMX93_CLK_BUS_WAKEUP>;
 944                                 clock-names = "per", "ipg";
 945                                 status = "disabled";
 946                         };
 947
 948                         lpspi7: spi@42710000 {
 949                                 #address-cells = <1>;
 950                                 #size-cells = <0>;
 951                                 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
 952                                 reg = <0x42710000 0x10000>;
 953                                 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
 954                                 clocks = <&clk IMX93_CLK_LPSPI7_GATE>,
 955                                          <&clk IMX93_CLK_BUS_WAKEUP>;
 956                                 clock-names = "per", "ipg";
 957                                 status = "disabled";
 958                         };
 959
 960                         lpspi8: spi@42720000 {
 961                                 #address-cells = <1>;
 962                                 #size-cells = <0>;
 963                                 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
 964                                 reg = <0x42720000 0x10000>;
 965                                 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
 966                                 clocks = <&clk IMX93_CLK_LPSPI8_GATE>,
 967                                          <&clk IMX93_CLK_BUS_WAKEUP>;
 968                                 clock-names = "per", "ipg";
 969                                 status = "disabled";
 970                         };
 971
 972                 };
 973
 974                 aips3: bus@42800000 {
 975                         compatible = "fsl,aips-bus", "simple-bus";
 976                         reg = <0x42800000 0x800000>;
 977                         #address-cells = <1>;
 978                         #size-cells = <1>;
 979                         ranges;
 980
 981                         usdhc1: mmc@42850000 {
 982                                 compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";
 983                                 reg = <0x42850000 0x10000>;
 984                                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 985                                 clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
 986                                          <&clk IMX93_CLK_WAKEUP_AXI>,
 987                                          <&clk IMX93_CLK_USDHC1_GATE>;
 988                                 clock-names = "ipg", "ahb", "per";
 989                                 bus-width = <8>;
 990                                 fsl,tuning-start-tap = <1>;
 991                                 fsl,tuning-step = <2>;
 992                                 status = "disabled";
 993                         };
 994
 995                         usdhc2: mmc@42860000 {
 996                                 compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";
 997                                 reg = <0x42860000 0x10000>;
 998                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 999                                 clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
1000                                          <&clk IMX93_CLK_WAKEUP_AXI>,
1001                                          <&clk IMX93_CLK_USDHC2_GATE>;
1002                                 clock-names = "ipg", "ahb", "per";
1003                                 bus-width = <4>;
1004                                 fsl,tuning-start-tap = <1>;
1005                                 fsl,tuning-step = <2>;
1006                                 status = "disabled";
1007                         };
1008
1009                         fec: ethernet@42890000 {
1010                                 compatible = "fsl,imx93-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
1011                                 reg = <0x42890000 0x10000>;
1012                                 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
1013                                              <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
1014                                              <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
1015                                              <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
1016                                 clocks = <&clk IMX93_CLK_ENET1_GATE>,
1017                                          <&clk IMX93_CLK_ENET1_GATE>,
1018                                          <&clk IMX93_CLK_ENET_TIMER1>,
1019                                          <&clk IMX93_CLK_ENET_REF>,
1020                                          <&clk IMX93_CLK_ENET_REF_PHY>;
1021                                 clock-names = "ipg", "ahb", "ptp",
1022                                               "enet_clk_ref", "enet_out";
1023                                 assigned-clocks = <&clk IMX93_CLK_ENET_TIMER1>,
1024                                                   <&clk IMX93_CLK_ENET_REF>,
1025                                                   <&clk IMX93_CLK_ENET_REF_PHY>;
1026                                 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
1027                                                          <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>,
1028                                                          <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
1029                                 assigned-clock-rates = <100000000>, <250000000>, <50000000>;
1030                                 fsl,num-tx-queues = <3>;
1031                                 fsl,num-rx-queues = <3>;
1032                                 fsl,stop-mode = <&wakeupmix_gpr 0x0c 1>;
1033                                 status = "disabled";
1034                         };
1035
1036                         eqos: ethernet@428a0000 {
1037                                 compatible = "nxp,imx93-dwmac-eqos", "snps,dwmac-5.10a";
1038                                 reg = <0x428a0000 0x10000>;
1039                                 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
1040                                              <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
1041                                 interrupt-names = "macirq", "eth_wake_irq";
1042                                 clocks = <&clk IMX93_CLK_ENET_QOS_GATE>,
1043                                          <&clk IMX93_CLK_ENET_QOS_GATE>,
1044                                          <&clk IMX93_CLK_ENET_TIMER2>,
1045                                          <&clk IMX93_CLK_ENET>,
1046                                          <&clk IMX93_CLK_ENET_QOS_GATE>;
1047                                 clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem";
1048                                 assigned-clocks = <&clk IMX93_CLK_ENET_TIMER2>,
1049                                                   <&clk IMX93_CLK_ENET>;
1050                                 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
1051                                                          <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>;
1052                                 assigned-clock-rates = <100000000>, <250000000>;
1053                                 intf_mode = <&wakeupmix_gpr 0x28>;
1054                                 snps,clk-csr = <0>;
1055                                 status = "disabled";
1056                         };
1057
1058                         usdhc3: mmc@428b0000 {
1059                                 compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";
1060                                 reg = <0x428b0000 0x10000>;
1061                                 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
1062                                 clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
1063                                          <&clk IMX93_CLK_WAKEUP_AXI>,
1064                                          <&clk IMX93_CLK_USDHC3_GATE>;
1065                                 clock-names = "ipg", "ahb", "per";
1066                                 bus-width = <4>;
1067                                 fsl,tuning-start-tap = <1>;
1068                                 fsl,tuning-step = <2>;
1069                                 status = "disabled";
1070                         };
1071                 };
1072
1073                 gpio2: gpio@43810000 {
1074                         compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio";
1075                         reg = <0x43810000 0x1000>;
1076                         gpio-controller;
1077                         #gpio-cells = <2>;
1078                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
1079                                      <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
1080                         interrupt-controller;
1081                         #interrupt-cells = <2>;
1082                         clocks = <&clk IMX93_CLK_GPIO2_GATE>,
1083                                  <&clk IMX93_CLK_GPIO2_GATE>;
1084                         clock-names = "gpio", "port";
1085                         gpio-ranges = <&iomuxc 0 4 30>;
1086                 };
1087
1088                 gpio3: gpio@43820000 {
1089                         compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio";
1090                         reg = <0x43820000 0x1000>;
1091                         gpio-controller;
1092                         #gpio-cells = <2>;
1093                         interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
1094                                      <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1095                         interrupt-controller;
1096                         #interrupt-cells = <2>;
1097                         clocks = <&clk IMX93_CLK_GPIO3_GATE>,
1098                                  <&clk IMX93_CLK_GPIO3_GATE>;
1099                         clock-names = "gpio", "port";
1100                         gpio-ranges = <&iomuxc 0 84 8>, <&iomuxc 8 66 18>,
1101                                       <&iomuxc 26 34 2>, <&iomuxc 28 0 4>;
1102                 };
1103
1104                 gpio4: gpio@43830000 {
1105                         compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio";
1106                         reg = <0x43830000 0x1000>;
1107                         gpio-controller;
1108                         #gpio-cells = <2>;
1109                         interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
1110                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1111                         interrupt-controller;
1112                         #interrupt-cells = <2>;
1113                         clocks = <&clk IMX93_CLK_GPIO4_GATE>,
1114                                  <&clk IMX93_CLK_GPIO4_GATE>;
1115                         clock-names = "gpio", "port";
1116                         gpio-ranges = <&iomuxc 0 38 28>, <&iomuxc 28 36 2>;
1117                 };
1118
1119                 gpio1: gpio@47400000 {
1120                         compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio";
1121                         reg = <0x47400000 0x1000>;
1122                         gpio-controller;
1123                         #gpio-cells = <2>;
1124                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
1125                                      <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1126                         interrupt-controller;
1127                         #interrupt-cells = <2>;
1128                         clocks = <&clk IMX93_CLK_GPIO1_GATE>,
1129                                  <&clk IMX93_CLK_GPIO1_GATE>;
1130                         clock-names = "gpio", "port";
1131                         gpio-ranges = <&iomuxc 0 92 16>;
1132                 };
1133
1134                 ocotp: efuse@47510000 {
1135                         compatible = "fsl,imx93-ocotp", "syscon";
1136                         reg = <0x47510000 0x10000>;
1137                         #address-cells = <1>;
1138                         #size-cells = <1>;
1139                 };
1140
1141                 s4muap: mailbox@47520000 {
1142                         compatible = "fsl,imx93-mu-s4";
1143                         reg = <0x47520000 0x10000>;
1144                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
1145                                      <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1146                         interrupt-names = "tx", "rx";
1147                         #mbox-cells = <2>;
1148                 };
1149
1150                 media_blk_ctrl: system-controller@4ac10000 {
1151                         compatible = "fsl,imx93-media-blk-ctrl", "syscon";
1152                         reg = <0x4ac10000 0x10000>;
1153                         power-domains = <&mediamix>;
1154                         clocks = <&clk IMX93_CLK_MEDIA_APB>,
1155                                  <&clk IMX93_CLK_MEDIA_AXI>,
1156                                  <&clk IMX93_CLK_NIC_MEDIA_GATE>,
1157                                  <&clk IMX93_CLK_MEDIA_DISP_PIX>,
1158                                  <&clk IMX93_CLK_CAM_PIX>,
1159                                  <&clk IMX93_CLK_PXP_GATE>,
1160                                  <&clk IMX93_CLK_LCDIF_GATE>,
1161                                  <&clk IMX93_CLK_ISI_GATE>,
1162                                  <&clk IMX93_CLK_MIPI_CSI_GATE>,
1163                                  <&clk IMX93_CLK_MIPI_DSI_GATE>;
1164                         clock-names = "apb", "axi", "nic", "disp", "cam",
1165                                       "pxp", "lcdif", "isi", "csi", "dsi";
1166                         #power-domain-cells = <1>;
1167                         status = "disabled";
1168                 };
1169
1170                 ddr-pmu@4e300dc0 {
1171                         compatible = "fsl,imx93-ddr-pmu";
1172                         reg = <0x4e300dc0 0x200>;
1173                         interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1174                 };
1175         };
1176 };