1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
7 #include <dt-bindings/clock/imx8mq-clock.h>
8 #include <dt-bindings/power/imx8mq-power.h>
9 #include <dt-bindings/reset/imx8mq-reset.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include "dt-bindings/input/input.h"
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include "imx8mq-pinfunc.h"
17 interrupt-parent = <&gpc>;
42 compatible = "fixed-clock";
44 clock-frequency = <32768>;
45 clock-output-names = "ckil";
48 osc_25m: clock-osc-25m {
49 compatible = "fixed-clock";
51 clock-frequency = <25000000>;
52 clock-output-names = "osc_25m";
55 osc_27m: clock-osc-27m {
56 compatible = "fixed-clock";
58 clock-frequency = <27000000>;
59 clock-output-names = "osc_27m";
62 clk_ext1: clock-ext1 {
63 compatible = "fixed-clock";
65 clock-frequency = <133000000>;
66 clock-output-names = "clk_ext1";
69 clk_ext2: clock-ext2 {
70 compatible = "fixed-clock";
72 clock-frequency = <133000000>;
73 clock-output-names = "clk_ext2";
76 clk_ext3: clock-ext3 {
77 compatible = "fixed-clock";
79 clock-frequency = <133000000>;
80 clock-output-names = "clk_ext3";
83 clk_ext4: clock-ext4 {
84 compatible = "fixed-clock";
86 clock-frequency= <133000000>;
87 clock-output-names = "clk_ext4";
96 compatible = "arm,cortex-a53";
98 clock-latency = <61036>; /* two CLK32 periods */
99 clocks = <&clk IMX8MQ_CLK_ARM>;
100 enable-method = "psci";
101 next-level-cache = <&A53_L2>;
102 operating-points-v2 = <&a53_opp_table>;
103 #cooling-cells = <2>;
104 nvmem-cells = <&cpu_speed_grade>;
105 nvmem-cell-names = "speed_grade";
110 compatible = "arm,cortex-a53";
112 clock-latency = <61036>; /* two CLK32 periods */
113 clocks = <&clk IMX8MQ_CLK_ARM>;
114 enable-method = "psci";
115 next-level-cache = <&A53_L2>;
116 operating-points-v2 = <&a53_opp_table>;
117 #cooling-cells = <2>;
122 compatible = "arm,cortex-a53";
124 clock-latency = <61036>; /* two CLK32 periods */
125 clocks = <&clk IMX8MQ_CLK_ARM>;
126 enable-method = "psci";
127 next-level-cache = <&A53_L2>;
128 operating-points-v2 = <&a53_opp_table>;
129 #cooling-cells = <2>;
134 compatible = "arm,cortex-a53";
136 clock-latency = <61036>; /* two CLK32 periods */
137 clocks = <&clk IMX8MQ_CLK_ARM>;
138 enable-method = "psci";
139 next-level-cache = <&A53_L2>;
140 operating-points-v2 = <&a53_opp_table>;
141 #cooling-cells = <2>;
145 compatible = "cache";
149 a53_opp_table: opp-table {
150 compatible = "operating-points-v2";
154 opp-hz = /bits/ 64 <800000000>;
155 opp-microvolt = <900000>;
156 /* Industrial only */
157 opp-supported-hw = <0xf>, <0x4>;
158 clock-latency-ns = <150000>;
163 opp-hz = /bits/ 64 <1000000000>;
164 opp-microvolt = <900000>;
166 opp-supported-hw = <0xe>, <0x3>;
167 clock-latency-ns = <150000>;
172 opp-hz = /bits/ 64 <1300000000>;
173 opp-microvolt = <1000000>;
174 opp-supported-hw = <0xc>, <0x4>;
175 clock-latency-ns = <150000>;
180 opp-hz = /bits/ 64 <1500000000>;
181 opp-microvolt = <1000000>;
182 opp-supported-hw = <0x8>, <0x3>;
183 clock-latency-ns = <150000>;
189 compatible = "arm,cortex-a53-pmu";
190 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
191 interrupt-parent = <&gic>;
192 interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
196 compatible = "arm,psci-1.0";
202 polling-delay-passive = <250>;
203 polling-delay = <2000>;
204 thermal-sensors = <&tmu 0>;
207 cpu_alert: cpu-alert {
208 temperature = <80000>;
214 temperature = <90000>;
224 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
225 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
226 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
227 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
233 polling-delay-passive = <250>;
234 polling-delay = <2000>;
235 thermal-sensors = <&tmu 1>;
238 gpu_alert: gpu-alert {
239 temperature = <80000>;
245 temperature = <90000>;
255 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
261 polling-delay-passive = <250>;
262 polling-delay = <2000>;
263 thermal-sensors = <&tmu 2>;
267 temperature = <90000>;
276 compatible = "arm,armv8-timer";
277 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
278 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
279 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
280 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
281 interrupt-parent = <&gic>;
282 arm,no-tick-in-suspend;
286 compatible = "simple-bus";
287 #address-cells = <1>;
289 ranges = <0x0 0x0 0x0 0x3e000000>;
290 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
292 bus@30000000 { /* AIPS1 */
293 compatible = "fsl,imx8mq-aips-bus", "simple-bus";
294 #address-cells = <1>;
296 ranges = <0x30000000 0x30000000 0x400000>;
298 gpio1: gpio@30200000 {
299 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
300 reg = <0x30200000 0x10000>;
301 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
302 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
303 clocks = <&clk IMX8MQ_CLK_GPIO1_ROOT>;
306 interrupt-controller;
307 #interrupt-cells = <2>;
308 gpio-ranges = <&iomuxc 0 10 30>;
311 gpio2: gpio@30210000 {
312 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
313 reg = <0x30210000 0x10000>;
314 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
315 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
316 clocks = <&clk IMX8MQ_CLK_GPIO2_ROOT>;
319 interrupt-controller;
320 #interrupt-cells = <2>;
321 gpio-ranges = <&iomuxc 0 40 21>;
324 gpio3: gpio@30220000 {
325 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
326 reg = <0x30220000 0x10000>;
327 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
328 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
329 clocks = <&clk IMX8MQ_CLK_GPIO3_ROOT>;
332 interrupt-controller;
333 #interrupt-cells = <2>;
334 gpio-ranges = <&iomuxc 0 61 26>;
337 gpio4: gpio@30230000 {
338 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
339 reg = <0x30230000 0x10000>;
340 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
341 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
342 clocks = <&clk IMX8MQ_CLK_GPIO4_ROOT>;
345 interrupt-controller;
346 #interrupt-cells = <2>;
347 gpio-ranges = <&iomuxc 0 87 32>;
350 gpio5: gpio@30240000 {
351 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
352 reg = <0x30240000 0x10000>;
353 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
354 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
355 clocks = <&clk IMX8MQ_CLK_GPIO5_ROOT>;
358 interrupt-controller;
359 #interrupt-cells = <2>;
360 gpio-ranges = <&iomuxc 0 119 30>;
364 compatible = "fsl,imx8mq-tmu";
365 reg = <0x30260000 0x10000>;
366 interrupt = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
367 clocks = <&clk IMX8MQ_CLK_TMU_ROOT>;
369 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
370 fsl,tmu-calibration = <0x00000000 0x00000023
371 0x00000001 0x00000029
372 0x00000002 0x0000002f
373 0x00000003 0x00000035
374 0x00000004 0x0000003d
375 0x00000005 0x00000043
376 0x00000006 0x0000004b
377 0x00000007 0x00000051
378 0x00000008 0x00000057
379 0x00000009 0x0000005f
380 0x0000000a 0x00000067
381 0x0000000b 0x0000006f
383 0x00010000 0x0000001b
384 0x00010001 0x00000023
385 0x00010002 0x0000002b
386 0x00010003 0x00000033
387 0x00010004 0x0000003b
388 0x00010005 0x00000043
389 0x00010006 0x0000004b
390 0x00010007 0x00000055
391 0x00010008 0x0000005d
392 0x00010009 0x00000067
393 0x0001000a 0x00000070
395 0x00020000 0x00000017
396 0x00020001 0x00000023
397 0x00020002 0x0000002d
398 0x00020003 0x00000037
399 0x00020004 0x00000041
400 0x00020005 0x0000004b
401 0x00020006 0x00000057
402 0x00020007 0x00000063
403 0x00020008 0x0000006f
405 0x00030000 0x00000015
406 0x00030001 0x00000021
407 0x00030002 0x0000002d
408 0x00030003 0x00000039
409 0x00030004 0x00000045
410 0x00030005 0x00000053
411 0x00030006 0x0000005f
412 0x00030007 0x00000071>;
413 #thermal-sensor-cells = <1>;
416 wdog1: watchdog@30280000 {
417 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
418 reg = <0x30280000 0x10000>;
419 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
420 clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>;
424 wdog2: watchdog@30290000 {
425 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
426 reg = <0x30290000 0x10000>;
427 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
428 clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>;
432 wdog3: watchdog@302a0000 {
433 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
434 reg = <0x302a0000 0x10000>;
435 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
436 clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>;
440 sdma2: sdma@302c0000 {
441 compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
442 reg = <0x302c0000 0x10000>;
443 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
444 clocks = <&clk IMX8MQ_CLK_SDMA2_ROOT>,
445 <&clk IMX8MQ_CLK_SDMA2_ROOT>;
446 clock-names = "ipg", "ahb";
448 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
451 iomuxc: iomuxc@30330000 {
452 compatible = "fsl,imx8mq-iomuxc";
453 reg = <0x30330000 0x10000>;
456 iomuxc_gpr: syscon@30340000 {
457 compatible = "fsl,imx8mq-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr",
458 "syscon", "simple-mfd";
459 reg = <0x30340000 0x10000>;
461 mux: mux-controller {
462 compatible = "mmio-mux";
463 #mux-control-cells = <1>;
464 mux-reg-masks = <0x34 0x00000004>; /* MIPI_MUX_SEL */
468 ocotp: ocotp-ctrl@30350000 {
469 compatible = "fsl,imx8mq-ocotp", "syscon";
470 reg = <0x30350000 0x10000>;
471 clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>;
472 #address-cells = <1>;
475 cpu_speed_grade: speed-grade@10 {
480 anatop: syscon@30360000 {
481 compatible = "fsl,imx8mq-anatop", "syscon";
482 reg = <0x30360000 0x10000>;
483 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
486 snvs: snvs@30370000 {
487 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
488 reg = <0x30370000 0x10000>;
490 snvs_rtc: snvs-rtc-lp{
491 compatible = "fsl,sec-v4.0-mon-rtc-lp";
494 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
495 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
496 clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>;
497 clock-names = "snvs-rtc";
500 snvs_pwrkey: snvs-powerkey {
501 compatible = "fsl,sec-v4.0-pwrkey";
503 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
504 linux,keycode = <KEY_POWER>;
510 clk: clock-controller@30380000 {
511 compatible = "fsl,imx8mq-ccm";
512 reg = <0x30380000 0x10000>;
513 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
514 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
516 clocks = <&ckil>, <&osc_25m>, <&osc_27m>,
517 <&clk_ext1>, <&clk_ext2>,
518 <&clk_ext3>, <&clk_ext4>;
519 clock-names = "ckil", "osc_25m", "osc_27m",
520 "clk_ext1", "clk_ext2",
521 "clk_ext3", "clk_ext4";
524 src: reset-controller@30390000 {
525 compatible = "fsl,imx8mq-src", "syscon";
526 reg = <0x30390000 0x10000>;
531 compatible = "fsl,imx8mq-gpc";
532 reg = <0x303a0000 0x10000>;
533 interrupt-parent = <&gic>;
534 interrupt-controller;
535 #interrupt-cells = <3>;
538 #address-cells = <1>;
541 pgc_mipi: power-domain@0 {
542 #power-domain-cells = <0>;
543 reg = <IMX8M_POWER_DOMAIN_MIPI>;
547 * As per comment in ATF source code:
549 * PCIE1 and PCIE2 share the
550 * same reset signal, if we
551 * power down PCIE2, PCIE1
552 * will be held in reset too.
554 * So instead of creating two
555 * separate power domains for
556 * PCIE1 and PCIE2 we create a
557 * link between both and use
558 * it as a shared PCIE power
561 pgc_pcie: power-domain@1 {
562 #power-domain-cells = <0>;
563 reg = <IMX8M_POWER_DOMAIN_PCIE1>;
564 power-domains = <&pgc_pcie2>;
567 pgc_otg1: power-domain@2 {
568 #power-domain-cells = <0>;
569 reg = <IMX8M_POWER_DOMAIN_USB_OTG1>;
572 pgc_otg2: power-domain@3 {
573 #power-domain-cells = <0>;
574 reg = <IMX8M_POWER_DOMAIN_USB_OTG2>;
577 pgc_ddr1: power-domain@4 {
578 #power-domain-cells = <0>;
579 reg = <IMX8M_POWER_DOMAIN_DDR1>;
582 pgc_gpu: power-domain@5 {
583 #power-domain-cells = <0>;
584 reg = <IMX8M_POWER_DOMAIN_GPU>;
585 clocks = <&clk IMX8MQ_CLK_GPU_ROOT>,
586 <&clk IMX8MQ_CLK_GPU_SHADER_DIV>,
587 <&clk IMX8MQ_CLK_GPU_AXI>,
588 <&clk IMX8MQ_CLK_GPU_AHB>;
591 pgc_vpu: power-domain@6 {
592 #power-domain-cells = <0>;
593 reg = <IMX8M_POWER_DOMAIN_VPU>;
596 pgc_disp: power-domain@7 {
597 #power-domain-cells = <0>;
598 reg = <IMX8M_POWER_DOMAIN_DISP>;
601 pgc_mipi_csi1: power-domain@8 {
602 #power-domain-cells = <0>;
603 reg = <IMX8M_POWER_DOMAIN_MIPI_CSI1>;
606 pgc_mipi_csi2: power-domain@9 {
607 #power-domain-cells = <0>;
608 reg = <IMX8M_POWER_DOMAIN_MIPI_CSI2>;
611 pgc_pcie2: power-domain@a {
612 #power-domain-cells = <0>;
613 reg = <IMX8M_POWER_DOMAIN_PCIE2>;
619 bus@30400000 { /* AIPS2 */
620 compatible = "fsl,imx8mq-aips-bus", "simple-bus";
621 #address-cells = <1>;
623 ranges = <0x30400000 0x30400000 0x400000>;
626 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
627 reg = <0x30660000 0x10000>;
628 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
629 clocks = <&clk IMX8MQ_CLK_PWM1_ROOT>,
630 <&clk IMX8MQ_CLK_PWM1_ROOT>;
631 clock-names = "ipg", "per";
637 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
638 reg = <0x30670000 0x10000>;
639 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
640 clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>,
641 <&clk IMX8MQ_CLK_PWM2_ROOT>;
642 clock-names = "ipg", "per";
648 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
649 reg = <0x30680000 0x10000>;
650 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
651 clocks = <&clk IMX8MQ_CLK_PWM3_ROOT>,
652 <&clk IMX8MQ_CLK_PWM3_ROOT>;
653 clock-names = "ipg", "per";
659 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
660 reg = <0x30690000 0x10000>;
661 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
662 clocks = <&clk IMX8MQ_CLK_PWM4_ROOT>,
663 <&clk IMX8MQ_CLK_PWM4_ROOT>;
664 clock-names = "ipg", "per";
669 system_counter: timer@306a0000 {
670 compatible = "nxp,sysctr-timer";
671 reg = <0x306a0000 0x20000>;
672 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
678 bus@30800000 { /* AIPS3 */
679 compatible = "fsl,imx8mq-aips-bus", "simple-bus";
680 #address-cells = <1>;
682 ranges = <0x30800000 0x30800000 0x400000>,
683 <0x08000000 0x08000000 0x10000000>;
685 ecspi1: spi@30820000 {
686 #address-cells = <1>;
688 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
689 reg = <0x30820000 0x10000>;
690 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
691 clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>,
692 <&clk IMX8MQ_CLK_ECSPI1_ROOT>;
693 clock-names = "ipg", "per";
697 ecspi2: spi@30830000 {
698 #address-cells = <1>;
700 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
701 reg = <0x30830000 0x10000>;
702 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
703 clocks = <&clk IMX8MQ_CLK_ECSPI2_ROOT>,
704 <&clk IMX8MQ_CLK_ECSPI2_ROOT>;
705 clock-names = "ipg", "per";
709 ecspi3: spi@30840000 {
710 #address-cells = <1>;
712 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
713 reg = <0x30840000 0x10000>;
714 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
715 clocks = <&clk IMX8MQ_CLK_ECSPI3_ROOT>,
716 <&clk IMX8MQ_CLK_ECSPI3_ROOT>;
717 clock-names = "ipg", "per";
721 uart1: serial@30860000 {
722 compatible = "fsl,imx8mq-uart",
724 reg = <0x30860000 0x10000>;
725 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
726 clocks = <&clk IMX8MQ_CLK_UART1_ROOT>,
727 <&clk IMX8MQ_CLK_UART1_ROOT>;
728 clock-names = "ipg", "per";
732 uart3: serial@30880000 {
733 compatible = "fsl,imx8mq-uart",
735 reg = <0x30880000 0x10000>;
736 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
737 clocks = <&clk IMX8MQ_CLK_UART3_ROOT>,
738 <&clk IMX8MQ_CLK_UART3_ROOT>;
739 clock-names = "ipg", "per";
743 uart2: serial@30890000 {
744 compatible = "fsl,imx8mq-uart",
746 reg = <0x30890000 0x10000>;
747 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
748 clocks = <&clk IMX8MQ_CLK_UART2_ROOT>,
749 <&clk IMX8MQ_CLK_UART2_ROOT>;
750 clock-names = "ipg", "per";
755 #sound-dai-cells = <0>;
756 compatible = "fsl,imx8mq-sai";
757 reg = <0x308b0000 0x10000>;
758 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
759 clocks = <&clk IMX8MQ_CLK_SAI2_IPG>,
760 <&clk IMX8MQ_CLK_SAI2_ROOT>,
761 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
762 clock-names = "bus", "mclk1", "mclk2", "mclk3";
763 dmas = <&sdma1 10 24 0>, <&sdma1 11 24 0>;
764 dma-names = "rx", "tx";
768 crypto: crypto@30900000 {
769 compatible = "fsl,sec-v4.0";
770 #address-cells = <1>;
772 reg = <0x30900000 0x40000>;
773 ranges = <0 0x30900000 0x40000>;
774 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
775 clocks = <&clk IMX8MQ_CLK_AHB>,
776 <&clk IMX8MQ_CLK_IPG_ROOT>;
777 clock-names = "aclk", "ipg";
780 compatible = "fsl,sec-v4.0-job-ring";
781 reg = <0x1000 0x1000>;
782 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
786 compatible = "fsl,sec-v4.0-job-ring";
787 reg = <0x2000 0x1000>;
788 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
792 compatible = "fsl,sec-v4.0-job-ring";
793 reg = <0x3000 0x1000>;
794 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
798 dphy: dphy@30a00300 {
799 compatible = "fsl,imx8mq-mipi-dphy";
800 reg = <0x30a00300 0x100>;
801 clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
802 clock-names = "phy_ref";
803 assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
804 assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>;
805 assigned-clock-rates = <24000000>;
807 power-domains = <&pgc_mipi>;
812 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
813 reg = <0x30a20000 0x10000>;
814 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
815 clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>;
816 #address-cells = <1>;
822 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
823 reg = <0x30a30000 0x10000>;
824 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
825 clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>;
826 #address-cells = <1>;
832 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
833 reg = <0x30a40000 0x10000>;
834 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
835 clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>;
836 #address-cells = <1>;
842 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
843 reg = <0x30a50000 0x10000>;
844 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
845 clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>;
846 #address-cells = <1>;
851 uart4: serial@30a60000 {
852 compatible = "fsl,imx8mq-uart",
854 reg = <0x30a60000 0x10000>;
855 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
856 clocks = <&clk IMX8MQ_CLK_UART4_ROOT>,
857 <&clk IMX8MQ_CLK_UART4_ROOT>;
858 clock-names = "ipg", "per";
862 usdhc1: mmc@30b40000 {
863 compatible = "fsl,imx8mq-usdhc",
865 reg = <0x30b40000 0x10000>;
866 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
867 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>,
868 <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
869 <&clk IMX8MQ_CLK_USDHC1_ROOT>;
870 clock-names = "ipg", "ahb", "per";
871 fsl,tuning-start-tap = <20>;
872 fsl,tuning-step = <2>;
877 usdhc2: mmc@30b50000 {
878 compatible = "fsl,imx8mq-usdhc",
880 reg = <0x30b50000 0x10000>;
881 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
882 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>,
883 <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
884 <&clk IMX8MQ_CLK_USDHC2_ROOT>;
885 clock-names = "ipg", "ahb", "per";
886 fsl,tuning-start-tap = <20>;
887 fsl,tuning-step = <2>;
892 qspi0: spi@30bb0000 {
893 #address-cells = <1>;
895 compatible = "fsl,imx8mq-qspi", "fsl,imx7d-qspi";
896 reg = <0x30bb0000 0x10000>,
897 <0x08000000 0x10000000>;
898 reg-names = "QuadSPI", "QuadSPI-memory";
899 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
900 clocks = <&clk IMX8MQ_CLK_QSPI_ROOT>,
901 <&clk IMX8MQ_CLK_QSPI_ROOT>;
902 clock-names = "qspi_en", "qspi";
906 sdma1: sdma@30bd0000 {
907 compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
908 reg = <0x30bd0000 0x10000>;
909 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
910 clocks = <&clk IMX8MQ_CLK_SDMA1_ROOT>,
911 <&clk IMX8MQ_CLK_AHB>;
912 clock-names = "ipg", "ahb";
914 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
917 fec1: ethernet@30be0000 {
918 compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec";
919 reg = <0x30be0000 0x10000>;
920 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
921 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
922 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
923 clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>,
924 <&clk IMX8MQ_CLK_ENET1_ROOT>,
925 <&clk IMX8MQ_CLK_ENET_TIMER>,
926 <&clk IMX8MQ_CLK_ENET_REF>,
927 <&clk IMX8MQ_CLK_ENET_PHY_REF>;
928 clock-names = "ipg", "ahb", "ptp",
929 "enet_clk_ref", "enet_out";
930 fsl,num-tx-queues = <3>;
931 fsl,num-rx-queues = <3>;
936 bus@32c00000 { /* AIPS4 */
937 compatible = "fsl,imx8mq-aips-bus", "simple-bus";
938 #address-cells = <1>;
940 ranges = <0x32c00000 0x32c00000 0x400000>;
942 irqsteer: interrupt-controller@32e2d000 {
943 compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer";
944 reg = <0x32e2d000 0x1000>;
945 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
946 clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>;
950 interrupt-controller;
951 #interrupt-cells = <1>;
956 compatible = "vivante,gc";
957 reg = <0x38000000 0x40000>;
958 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
959 clocks = <&clk IMX8MQ_CLK_GPU_ROOT>,
960 <&clk IMX8MQ_CLK_GPU_SHADER_DIV>,
961 <&clk IMX8MQ_CLK_GPU_AXI>,
962 <&clk IMX8MQ_CLK_GPU_AHB>;
963 clock-names = "core", "shader", "bus", "reg";
964 #cooling-cells = <2>;
965 assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>,
966 <&clk IMX8MQ_CLK_GPU_SHADER_SRC>,
967 <&clk IMX8MQ_CLK_GPU_AXI>,
968 <&clk IMX8MQ_CLK_GPU_AHB>,
969 <&clk IMX8MQ_GPU_PLL_BYPASS>;
970 assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>,
971 <&clk IMX8MQ_GPU_PLL_OUT>,
972 <&clk IMX8MQ_GPU_PLL_OUT>,
973 <&clk IMX8MQ_GPU_PLL_OUT>,
974 <&clk IMX8MQ_GPU_PLL>;
975 assigned-clock-rates = <800000000>, <800000000>,
976 <800000000>, <800000000>, <0>;
977 power-domains = <&pgc_gpu>;
980 usb_dwc3_0: usb@38100000 {
981 compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
982 reg = <0x38100000 0x10000>;
983 clocks = <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>,
984 <&clk IMX8MQ_CLK_USB_CORE_REF>,
985 <&clk IMX8MQ_CLK_32K>;
986 clock-names = "bus_early", "ref", "suspend";
987 assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
988 <&clk IMX8MQ_CLK_USB_CORE_REF>;
989 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
990 <&clk IMX8MQ_SYS1_PLL_100M>;
991 assigned-clock-rates = <500000000>, <100000000>;
992 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
993 phys = <&usb3_phy0>, <&usb3_phy0>;
994 phy-names = "usb2-phy", "usb3-phy";
995 power-domains = <&pgc_otg1>;
996 usb3-resume-missing-cas;
1000 usb3_phy0: usb-phy@381f0040 {
1001 compatible = "fsl,imx8mq-usb-phy";
1002 reg = <0x381f0040 0x40>;
1003 clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>;
1004 clock-names = "phy";
1005 assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
1006 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
1007 assigned-clock-rates = <100000000>;
1009 status = "disabled";
1012 usb_dwc3_1: usb@38200000 {
1013 compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
1014 reg = <0x38200000 0x10000>;
1015 clocks = <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>,
1016 <&clk IMX8MQ_CLK_USB_CORE_REF>,
1017 <&clk IMX8MQ_CLK_32K>;
1018 clock-names = "bus_early", "ref", "suspend";
1019 assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
1020 <&clk IMX8MQ_CLK_USB_CORE_REF>;
1021 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
1022 <&clk IMX8MQ_SYS1_PLL_100M>;
1023 assigned-clock-rates = <500000000>, <100000000>;
1024 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1025 phys = <&usb3_phy1>, <&usb3_phy1>;
1026 phy-names = "usb2-phy", "usb3-phy";
1027 power-domains = <&pgc_otg2>;
1028 usb3-resume-missing-cas;
1029 status = "disabled";
1032 usb3_phy1: usb-phy@382f0040 {
1033 compatible = "fsl,imx8mq-usb-phy";
1034 reg = <0x382f0040 0x40>;
1035 clocks = <&clk IMX8MQ_CLK_USB2_PHY_ROOT>;
1036 clock-names = "phy";
1037 assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
1038 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
1039 assigned-clock-rates = <100000000>;
1041 status = "disabled";
1044 pcie0: pcie@33800000 {
1045 compatible = "fsl,imx8mq-pcie";
1046 reg = <0x33800000 0x400000>,
1047 <0x1ff00000 0x80000>;
1048 reg-names = "dbi", "config";
1049 #address-cells = <3>;
1051 device_type = "pci";
1052 bus-range = <0x00 0xff>;
1053 ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
1054 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
1057 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1058 interrupt-names = "msi";
1059 #interrupt-cells = <1>;
1060 interrupt-map-mask = <0 0 0 0x7>;
1061 interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1062 <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1063 <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1064 <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1065 fsl,max-link-speed = <2>;
1066 power-domains = <&pgc_pcie>;
1067 resets = <&src IMX8MQ_RESET_PCIEPHY>,
1068 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
1069 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
1070 reset-names = "pciephy", "apps", "turnoff";
1071 status = "disabled";
1074 pcie1: pcie@33c00000 {
1075 compatible = "fsl,imx8mq-pcie";
1076 reg = <0x33c00000 0x400000>,
1077 <0x27f00000 0x80000>;
1078 reg-names = "dbi", "config";
1079 #address-cells = <3>;
1081 device_type = "pci";
1082 ranges = <0x81000000 0 0x00000000 0x27f80000 0 0x00010000 /* downstream I/O 64KB */
1083 0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */
1086 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1087 interrupt-names = "msi";
1088 #interrupt-cells = <1>;
1089 interrupt-map-mask = <0 0 0 0x7>;
1090 interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
1091 <0 0 0 2 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
1092 <0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
1093 <0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1094 fsl,max-link-speed = <2>;
1095 power-domains = <&pgc_pcie>;
1096 resets = <&src IMX8MQ_RESET_PCIEPHY2>,
1097 <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>,
1098 <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>;
1099 reset-names = "pciephy", "apps", "turnoff";
1100 status = "disabled";
1103 gic: interrupt-controller@38800000 {
1104 compatible = "arm,gic-v3";
1105 reg = <0x38800000 0x10000>, /* GIC Dist */
1106 <0x38880000 0xc0000>, /* GICR */
1107 <0x31000000 0x2000>, /* GICC */
1108 <0x31010000 0x2000>, /* GICV */
1109 <0x31020000 0x2000>; /* GICH */
1110 #interrupt-cells = <3>;
1111 interrupt-controller;
1112 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1113 interrupt-parent = <&gic>;
1117 compatible = "fsl,imx8mq-ddr-pmu", "fsl,imx8m-ddr-pmu";
1118 reg = <0x3d800000 0x400000>;
1119 interrupt-parent = <&gic>;
1120 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;