arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2019 NXP
   4  * Copyright 2019-2020 Variscite Ltd.
   5  * Copyright (C) 2020 Krzysztof Kozlowski <krzk@kernel.org>
   6  */
   7
   8 #include "imx8mn.dtsi"
   9
  10 / {
  11         model = "Variscite VAR-SOM-MX8MN module";
  12         compatible = "variscite,var-som-mx8mn", "fsl,imx8mn";
  13
  14         chosen {
  15                 stdout-path = &uart4;
  16         };
  17
  18         memory@40000000 {
  19                 device_type = "memory";
  20                 reg = <0x0 0x40000000 0 0x40000000>;
  21         };
  22
  23         reg_eth_phy: regulator-eth-phy {
  24                 compatible = "regulator-fixed";
  25                 pinctrl-names = "default";
  26                 pinctrl-0 = <&pinctrl_reg_eth_phy>;
  27                 regulator-name = "eth_phy_pwr";
  28                 regulator-min-microvolt = <3300000>;
  29                 regulator-max-microvolt = <3300000>;
  30                 gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>;
  31                 enable-active-high;
  32         };
  33 };
  34
  35 &A53_0 {
  36         cpu-supply = <&buck2_reg>;
  37 };
  38
  39 &A53_1 {
  40         cpu-supply = <&buck2_reg>;
  41 };
  42
  43 &A53_2 {
  44         cpu-supply = <&buck2_reg>;
  45 };
  46
  47 &A53_3 {
  48         cpu-supply = <&buck2_reg>;
  49 };
  50
  51 &ecspi1 {
  52         pinctrl-names = "default";
  53         pinctrl-0 = <&pinctrl_ecspi1>;
  54         cs-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>,
  55                    <&gpio1  0 GPIO_ACTIVE_LOW>;
  56         /delete-property/ dmas;
  57         /delete-property/ dma-names;
  58         status = "okay";
  59
  60         /* Resistive touch controller */
  61         touchscreen@0 {
  62                 reg = <0>;
  63                 compatible = "ti,ads7846";
  64                 pinctrl-names = "default";
  65                 pinctrl-0 = <&pinctrl_restouch>;
  66                 interrupt-parent = <&gpio1>;
  67                 interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
  68
  69                 spi-max-frequency = <1500000>;
  70                 pendown-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
  71
  72                 ti,x-min = /bits/ 16 <125>;
  73                 touchscreen-size-x = /bits/ 16 <4008>;
  74                 ti,y-min = /bits/ 16 <282>;
  75                 touchscreen-size-y = /bits/ 16 <3864>;
  76                 ti,x-plate-ohms = /bits/ 16 <180>;
  77                 touchscreen-max-pressure = /bits/ 16 <255>;
  78                 touchscreen-average-samples = /bits/ 16 <10>;
  79                 ti,debounce-tol = /bits/ 16 <3>;
  80                 ti,debounce-rep = /bits/ 16 <1>;
  81                 ti,settle-delay-usec = /bits/ 16 <150>;
  82                 ti,keep-vref-on;
  83                 wakeup-source;
  84         };
  85 };
  86
  87 &fec1 {
  88         pinctrl-names = "default", "sleep";
  89         pinctrl-0 = <&pinctrl_fec1>;
  90         pinctrl-1 = <&pinctrl_fec1_sleep>;
  91         phy-mode = "rgmii";
  92         phy-handle = <&ethphy>;
  93         phy-supply = <&reg_eth_phy>;
  94         fsl,magic-packet;
  95         status = "okay";
  96
  97         mdio {
  98                 #address-cells = <1>;
  99                 #size-cells = <0>;
 100
 101                 ethphy: ethernet-phy@4 {
 102                         compatible = "ethernet-phy-ieee802.3-c22";
 103                         reg = <4>;
 104                         reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
 105                         reset-assert-us = <10000>;
 106                 };
 107         };
 108 };
 109
 110 &i2c1 {
 111         clock-frequency = <400000>;
 112         pinctrl-names = "default";
 113         pinctrl-0 = <&pinctrl_i2c1>;
 114         status = "okay";
 115
 116         pmic@4b {
 117                 compatible = "rohm,bd71847";
 118                 reg = <0x4b>;
 119                 pinctrl-0 = <&pinctrl_pmic>;
 120                 interrupt-parent = <&gpio2>;
 121                 /*
 122                  * The interrupt is not correct. It should be level low,
 123                  * however with internal pull up this causes IRQ storm.
 124                  */
 125                 interrupts = <8 IRQ_TYPE_EDGE_RISING>;
 126                 rohm,reset-snvs-powered;
 127
 128                 regulators {
 129                         buck1_reg: BUCK1 {
 130                                 regulator-name = "buck1";
 131                                 regulator-min-microvolt = <700000>;
 132                                 regulator-max-microvolt = <1300000>;
 133                                 regulator-boot-on;
 134                                 regulator-always-on;
 135                                 regulator-ramp-delay = <1250>;
 136                         };
 137
 138                         buck2_reg: BUCK2 {
 139                                 regulator-name = "buck2";
 140                                 regulator-min-microvolt = <700000>;
 141                                 regulator-max-microvolt = <1300000>;
 142                                 regulator-boot-on;
 143                                 regulator-always-on;
 144                                 regulator-ramp-delay = <1250>;
 145                                 rohm,dvs-run-voltage = <1000000>;
 146                                 rohm,dvs-idle-voltage = <900000>;
 147                         };
 148
 149                         buck3_reg: BUCK3 {
 150                                 regulator-name = "buck3";
 151                                 regulator-min-microvolt = <700000>;
 152                                 regulator-max-microvolt = <1350000>;
 153                                 regulator-boot-on;
 154                                 regulator-always-on;
 155                         };
 156
 157                         buck4_reg: BUCK4 {
 158                                 regulator-name = "buck4";
 159                                 regulator-min-microvolt = <2600000>;
 160                                 regulator-max-microvolt = <3300000>;
 161                                 regulator-boot-on;
 162                                 regulator-always-on;
 163                         };
 164
 165                         buck5_reg: BUCK5 {
 166                                 regulator-name = "buck5";
 167                                 regulator-min-microvolt = <1605000>;
 168                                 regulator-max-microvolt = <1995000>;
 169                                 regulator-boot-on;
 170                                 regulator-always-on;
 171                         };
 172
 173                         buck6_reg: BUCK6 {
 174                                 regulator-name = "buck6";
 175                                 regulator-min-microvolt = <800000>;
 176                                 regulator-max-microvolt = <1400000>;
 177                                 regulator-boot-on;
 178                                 regulator-always-on;
 179                         };
 180
 181                         ldo1_reg: LDO1 {
 182                                 regulator-name = "ldo1";
 183                                 regulator-min-microvolt = <1600000>;
 184                                 regulator-max-microvolt = <1900000>;
 185                                 regulator-boot-on;
 186                                 regulator-always-on;
 187                         };
 188
 189                         ldo2_reg: LDO2 {
 190                                 regulator-name = "ldo2";
 191                                 regulator-min-microvolt = <800000>;
 192                                 regulator-max-microvolt = <900000>;
 193                                 regulator-boot-on;
 194                                 regulator-always-on;
 195                         };
 196
 197                         ldo3_reg: LDO3 {
 198                                 regulator-name = "ldo3";
 199                                 regulator-min-microvolt = <1800000>;
 200                                 regulator-max-microvolt = <3300000>;
 201                                 regulator-boot-on;
 202                                 regulator-always-on;
 203                         };
 204
 205                         ldo4_reg: LDO4 {
 206                                 regulator-name = "ldo4";
 207                                 regulator-min-microvolt = <900000>;
 208                                 regulator-max-microvolt = <1800000>;
 209                                 regulator-always-on;
 210                         };
 211
 212                         ldo5_reg: LDO5 {
 213                                 regulator-compatible = "ldo5";
 214                                 regulator-min-microvolt = <1800000>;
 215                                 regulator-max-microvolt = <1800000>;
 216                                 regulator-always-on;
 217                         };
 218
 219                         ldo6_reg: LDO6 {
 220                                 regulator-name = "ldo6";
 221                                 regulator-min-microvolt = <900000>;
 222                                 regulator-max-microvolt = <1800000>;
 223                                 regulator-boot-on;
 224                                 regulator-always-on;
 225                         };
 226                 };
 227         };
 228 };
 229
 230 &i2c3 {
 231         clock-frequency = <400000>;
 232         pinctrl-names = "default";
 233         pinctrl-0 = <&pinctrl_i2c3>;
 234         status = "okay";
 235
 236         /* TODO: configure audio, as of now just put a placeholder */
 237         wm8904: codec@1a {
 238                 compatible = "wlf,wm8904";
 239                 reg = <0x1a>;
 240                 status = "disabled";
 241         };
 242 };
 243
 244 &snvs_pwrkey {
 245         status = "okay";
 246 };
 247
 248 /* Bluetooth */
 249 &uart2 {
 250         pinctrl-names = "default";
 251         pinctrl-0 = <&pinctrl_uart2>;
 252         assigned-clocks = <&clk IMX8MN_CLK_UART2>;
 253         assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
 254         uart-has-rtscts;
 255         status = "okay";
 256 };
 257
 258 /* Console */
 259 &uart4 {
 260         pinctrl-names = "default";
 261         pinctrl-0 = <&pinctrl_uart4>;
 262         status = "okay";
 263 };
 264
 265 &usbotg1 {
 266         dr_mode = "otg";
 267         usb-role-switch;
 268         status = "okay";
 269 };
 270
 271 /* WIFI */
 272 &usdhc1 {
 273         #address-cells = <1>;
 274         #size-cells = <0>;
 275         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 276         pinctrl-0 = <&pinctrl_usdhc1>;
 277         pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
 278         pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
 279         bus-width = <4>;
 280         non-removable;
 281         keep-power-in-suspend;
 282         status = "okay";
 283
 284         brcmf: bcrmf@1 {
 285                 reg = <1>;
 286                 compatible = "brcm,bcm4329-fmac";
 287         };
 288 };
 289
 290 /* SD */
 291 &usdhc2 {
 292         assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
 293         assigned-clock-rates = <200000000>;
 294         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 295         pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
 296         pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
 297         pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
 298         cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
 299         bus-width = <4>;
 300         vmmc-supply = <&reg_usdhc2_vmmc>;
 301         status = "okay";
 302 };
 303
 304 /* eMMC */
 305 &usdhc3 {
 306         assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
 307         assigned-clock-rates = <400000000>;
 308         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 309         pinctrl-0 = <&pinctrl_usdhc3>;
 310         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 311         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 312         bus-width = <8>;
 313         non-removable;
 314         status = "okay";
 315 };
 316
 317 &wdog1 {
 318         pinctrl-names = "default";
 319         pinctrl-0 = <&pinctrl_wdog>;
 320         fsl,ext-reset-output;
 321         status = "okay";
 322 };
 323
 324 &iomuxc {
 325         pinctrl_ecspi1: ecspi1grp {
 326                 fsl,pins = <
 327                         MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK            0x13
 328                         MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI            0x13
 329                         MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO            0x13
 330                         MX8MN_IOMUXC_GPIO1_IO14_GPIO1_IO14              0x13
 331                         MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0               0x13
 332                 >;
 333         };
 334
 335         pinctrl_fec1: fec1grp {
 336                 fsl,pins = <
 337                         MX8MN_IOMUXC_ENET_MDC_ENET1_MDC                 0x3
 338                         MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO               0x3
 339                         MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3           0x1f
 340                         MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2           0x1f
 341                         MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1           0x1f
 342                         MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0           0x1f
 343                         MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3           0x91
 344                         MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2           0x91
 345                         MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1           0x91
 346                         MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0           0x91
 347                         MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC           0x1f
 348                         MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC           0x91
 349                         MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL     0x91
 350                         MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL     0x1f
 351                         MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9               0x19
 352                 >;
 353         };
 354
 355         pinctrl_fec1_sleep: fec1sleepgrp {
 356                 fsl,pins = <
 357                         MX8MN_IOMUXC_ENET_MDC_GPIO1_IO16                0x120
 358                         MX8MN_IOMUXC_ENET_MDIO_GPIO1_IO17               0x120
 359                         MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18                0x120
 360                         MX8MN_IOMUXC_ENET_TD2_GPIO1_IO19                0x120
 361                         MX8MN_IOMUXC_ENET_TD1_GPIO1_IO20                0x120
 362                         MX8MN_IOMUXC_ENET_TD0_GPIO1_IO21                0x120
 363                         MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29                0x120
 364                         MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28                0x120
 365                         MX8MN_IOMUXC_ENET_RD1_GPIO1_IO27                0x120
 366                         MX8MN_IOMUXC_ENET_RD0_GPIO1_IO26                0x120
 367                         MX8MN_IOMUXC_ENET_TXC_GPIO1_IO23                0x120
 368                         MX8MN_IOMUXC_ENET_RXC_GPIO1_IO25                0x120
 369                         MX8MN_IOMUXC_ENET_RX_CTL_GPIO1_IO24             0x120
 370                         MX8MN_IOMUXC_ENET_TX_CTL_GPIO1_IO22             0x120
 371                         MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9               0x120
 372                 >;
 373         };
 374
 375         pinctrl_i2c1: i2c1grp {
 376                 fsl,pins = <
 377                         MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL          0x400001c3
 378                         MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA          0x400001c3
 379                 >;
 380         };
 381
 382         pinctrl_i2c3: i2c3grp {
 383                 fsl,pins = <
 384                         MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL          0x400001c3
 385                         MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA          0x400001c3
 386                 >;
 387         };
 388
 389         pinctrl_pmic: pmicirqgrp {
 390                 fsl,pins = <
 391                         MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8        0x101
 392                 >;
 393         };
 394
 395         pinctrl_reg_eth_phy: regethphygrp {
 396                 fsl,pins = <
 397                         MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9        0x41
 398                 >;
 399         };
 400
 401         pinctrl_restouch: restouchgrp {
 402                 fsl,pins = <
 403                         MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3       0x1c0
 404                 >;
 405         };
 406
 407         pinctrl_uart2: uart2grp {
 408                 fsl,pins = <
 409                         MX8MN_IOMUXC_SAI3_TXFS_UART2_DCE_RX     0x140
 410                         MX8MN_IOMUXC_SAI3_TXC_UART2_DCE_TX      0x140
 411                         MX8MN_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B   0x140
 412                         MX8MN_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B   0x140
 413                 >;
 414         };
 415
 416         pinctrl_uart4: uart4grp {
 417                 fsl,pins = <
 418                         MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX     0x140
 419                         MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX     0x140
 420                 >;
 421         };
 422
 423         pinctrl_usdhc1: usdhc1grp {
 424                 fsl,pins = <
 425                         MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK         0x190
 426                         MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD         0x1d0
 427                         MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0     0x1d0
 428                         MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1     0x1d0
 429                         MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2     0x1d0
 430                         MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3     0x1d0
 431                 >;
 432         };
 433
 434         pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
 435                 fsl,pins = <
 436                         MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK         0x194
 437                         MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD         0x1d4
 438                         MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0     0x1d4
 439                         MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1     0x1d4
 440                         MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2     0x1d4
 441                         MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3     0x1d4
 442                 >;
 443         };
 444
 445         pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
 446                 fsl,pins = <
 447                         MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK         0x196
 448                         MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD         0x1d6
 449                         MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0     0x1d6
 450                         MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1     0x1d6
 451                         MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2     0x1d6
 452                         MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3     0x1d6
 453                 >;
 454         };
 455
 456         pinctrl_usdhc2_gpio: usdhc2gpiogrp {
 457                 fsl,pins = <
 458                         MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10      0x41
 459                 >;
 460         };
 461
 462         pinctrl_usdhc2: usdhc2grp {
 463                 fsl,pins = <
 464                         MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK         0x190
 465                         MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d0
 466                         MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d0
 467                         MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d0
 468                         MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d0
 469                         MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d0
 470                         MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
 471                 >;
 472         };
 473
 474         pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
 475                 fsl,pins = <
 476                         MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK         0x194
 477                         MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d4
 478                         MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d4
 479                         MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d4
 480                         MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d4
 481                         MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d4
 482                         MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
 483                 >;
 484         };
 485
 486         pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
 487                 fsl,pins = <
 488                         MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK         0x196
 489                         MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d6
 490                         MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d6
 491                         MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d6
 492                         MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d6
 493                         MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d6
 494                         MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
 495                 >;
 496         };
 497
 498         pinctrl_usdhc3: usdhc3grp {
 499                 fsl,pins = <
 500                         MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK       0x190
 501                         MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD       0x1d0
 502                         MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0   0x1d0
 503                         MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1   0x1d0
 504                         MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2   0x1d0
 505                         MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3   0x1d0
 506                         MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4     0x1d0
 507                         MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5    0x1d0
 508                         MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6    0x1d0
 509                         MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7      0x1d0
 510                         MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE   0x190
 511                 >;
 512         };
 513
 514         pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
 515                 fsl,pins = <
 516                         MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK       0x194
 517                         MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD       0x1d4
 518                         MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0   0x1d4
 519                         MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1   0x1d4
 520                         MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2   0x1d4
 521                         MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3   0x1d4
 522                         MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4     0x1d4
 523                         MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5    0x1d4
 524                         MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6    0x1d4
 525                         MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7      0x1d4
 526                         MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE   0x194
 527                 >;
 528         };
 529
 530         pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
 531                 fsl,pins = <
 532                         MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK       0x196
 533                         MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD       0x1d6
 534                         MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0   0x1d6
 535                         MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1   0x1d6
 536                         MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2   0x1d6
 537                         MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3   0x1d6
 538                         MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4     0x1d6
 539                         MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5    0x1d6
 540                         MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6    0x1d6
 541                         MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7      0x1d6
 542                         MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE   0x196
 543                 >;
 544         };
 545
 546         pinctrl_wdog: wdoggrp {
 547                 fsl,pins = <
 548                         MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B    0xc6
 549                 >;
 550         };
 551 };