arch/arm64/boot/dts/exynos/google/gs101.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * GS101 SoC
   4  *
   5  * Copyright 2019-2023 Google LLC
   6  * Copyright 2023 Linaro Ltd - <peter.griffin@linaro.org>
   7  */
   8
   9 #include <dt-bindings/clock/google,gs101.h>
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12 #include <dt-bindings/soc/samsung,exynos-usi.h>
  13
  14 / {
  15         compatible = "google,gs101";
  16         #address-cells = <2>;
  17         #size-cells = <1>;
  18
  19         interrupt-parent = <&gic>;
  20
  21         aliases {
  22                 pinctrl0 = &pinctrl_gpio_alive;
  23                 pinctrl1 = &pinctrl_far_alive;
  24                 pinctrl2 = &pinctrl_gsacore;
  25                 pinctrl3 = &pinctrl_gsactrl;
  26                 pinctrl4 = &pinctrl_peric0;
  27                 pinctrl5 = &pinctrl_peric1;
  28                 pinctrl6 = &pinctrl_hsi1;
  29                 pinctrl7 = &pinctrl_hsi2;
  30         };
  31
  32         cpus {
  33                 #address-cells = <1>;
  34                 #size-cells = <0>;
  35
  36                 cpu-map {
  37                         cluster0 {
  38                                 core0 {
  39                                         cpu = <&cpu0>;
  40                                 };
  41                                 core1 {
  42                                         cpu = <&cpu1>;
  43                                 };
  44                                 core2 {
  45                                         cpu = <&cpu2>;
  46                                 };
  47                                 core3 {
  48                                         cpu = <&cpu3>;
  49                                 };
  50                         };
  51
  52                         cluster1 {
  53                                 core0 {
  54                                         cpu = <&cpu4>;
  55                                 };
  56                                 core1 {
  57                                         cpu = <&cpu5>;
  58                                 };
  59                         };
  60
  61                         cluster2 {
  62                                 core0 {
  63                                         cpu = <&cpu6>;
  64                                 };
  65                                 core1 {
  66                                         cpu = <&cpu7>;
  67                                 };
  68                         };
  69                 };
  70
  71                 cpu0: cpu@0 {
  72                         device_type = "cpu";
  73                         compatible = "arm,cortex-a55";
  74                         reg = <0x0000>;
  75                         enable-method = "psci";
  76                         cpu-idle-states =  <&ANANKE_CPU_SLEEP>;
  77                         capacity-dmips-mhz = <250>;
  78                         dynamic-power-coefficient = <70>;
  79                 };
  80
  81                 cpu1: cpu@100 {
  82                         device_type = "cpu";
  83                         compatible = "arm,cortex-a55";
  84                         reg = <0x0100>;
  85                         enable-method = "psci";
  86                         cpu-idle-states =  <&ANANKE_CPU_SLEEP>;
  87                         capacity-dmips-mhz = <250>;
  88                         dynamic-power-coefficient = <70>;
  89                 };
  90
  91                 cpu2: cpu@200 {
  92                         device_type = "cpu";
  93                         compatible = "arm,cortex-a55";
  94                         reg = <0x0200>;
  95                         enable-method = "psci";
  96                         cpu-idle-states =  <&ANANKE_CPU_SLEEP>;
  97                         capacity-dmips-mhz = <250>;
  98                         dynamic-power-coefficient = <70>;
  99                 };
 100
 101                 cpu3: cpu@300 {
 102                         device_type = "cpu";
 103                         compatible = "arm,cortex-a55";
 104                         reg = <0x0300>;
 105                         enable-method = "psci";
 106                         cpu-idle-states =  <&ANANKE_CPU_SLEEP>;
 107                         capacity-dmips-mhz = <250>;
 108                         dynamic-power-coefficient = <70>;
 109                 };
 110
 111                 cpu4: cpu@400 {
 112                         device_type = "cpu";
 113                         compatible = "arm,cortex-a76";
 114                         reg = <0x0400>;
 115                         enable-method = "psci";
 116                         cpu-idle-states =  <&ENYO_CPU_SLEEP>;
 117                         capacity-dmips-mhz = <620>;
 118                         dynamic-power-coefficient = <284>;
 119                 };
 120
 121                 cpu5: cpu@500 {
 122                         device_type = "cpu";
 123                         compatible = "arm,cortex-a76";
 124                         reg = <0x0500>;
 125                         enable-method = "psci";
 126                         cpu-idle-states =  <&ENYO_CPU_SLEEP>;
 127                         capacity-dmips-mhz = <620>;
 128                         dynamic-power-coefficient = <284>;
 129                 };
 130
 131                 cpu6: cpu@600 {
 132                         device_type = "cpu";
 133                         compatible = "arm,cortex-x1";
 134                         reg = <0x0600>;
 135                         enable-method = "psci";
 136                         cpu-idle-states =  <&HERA_CPU_SLEEP>;
 137                         capacity-dmips-mhz = <1024>;
 138                         dynamic-power-coefficient = <650>;
 139                 };
 140
 141                 cpu7: cpu@700 {
 142                         device_type = "cpu";
 143                         compatible = "arm,cortex-x1";
 144                         reg = <0x0700>;
 145                         enable-method = "psci";
 146                         cpu-idle-states =  <&HERA_CPU_SLEEP>;
 147                         capacity-dmips-mhz = <1024>;
 148                         dynamic-power-coefficient = <650>;
 149                 };
 150
 151                 idle-states {
 152                         entry-method = "psci";
 153
 154                         ANANKE_CPU_SLEEP: cpu-ananke-sleep {
 155                                 idle-state-name = "c2";
 156                                 compatible = "arm,idle-state";
 157                                 arm,psci-suspend-param = <0x0010000>;
 158                                 entry-latency-us = <70>;
 159                                 exit-latency-us = <160>;
 160                                 min-residency-us = <2000>;
 161                         };
 162
 163                         ENYO_CPU_SLEEP: cpu-enyo-sleep {
 164                                 idle-state-name = "c2";
 165                                 compatible = "arm,idle-state";
 166                                 arm,psci-suspend-param = <0x0010000>;
 167                                 entry-latency-us = <150>;
 168                                 exit-latency-us = <190>;
 169                                 min-residency-us = <2500>;
 170                         };
 171
 172                         HERA_CPU_SLEEP: cpu-hera-sleep {
 173                                 idle-state-name = "c2";
 174                                 compatible = "arm,idle-state";
 175                                 arm,psci-suspend-param = <0x0010000>;
 176                                 entry-latency-us = <235>;
 177                                 exit-latency-us = <220>;
 178                                 min-residency-us = <3500>;
 179                         };
 180                 };
 181         };
 182
 183         /* TODO replace with CCF clock */
 184         dummy_clk: clock-3 {
 185                 compatible = "fixed-clock";
 186                 #clock-cells = <0>;
 187                 clock-frequency = <12345>;
 188                 clock-output-names = "pclk";
 189         };
 190
 191         /* ect node is required to be present by bootloader */
 192         ect {
 193         };
 194
 195         ext_24_5m: clock-1 {
 196                 compatible = "fixed-clock";
 197                 #clock-cells = <0>;
 198                 clock-output-names = "oscclk";
 199         };
 200
 201         ext_200m: clock-2 {
 202                 compatible = "fixed-clock";
 203                 #clock-cells = <0>;
 204                 clock-output-names = "ext-200m";
 205         };
 206
 207         pmu-0 {
 208                 compatible = "arm,cortex-a55-pmu";
 209                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
 210         };
 211
 212         pmu-1 {
 213                 compatible = "arm,cortex-a76-pmu";
 214                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>;
 215         };
 216
 217         pmu-2 {
 218                 compatible = "arm,cortex-x1-pmu";
 219                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster2>;
 220         };
 221
 222         pmu-3 {
 223                 compatible = "arm,dsu-pmu";
 224                 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>;
 225                 cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
 226                        <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
 227         };
 228
 229         psci {
 230                 compatible = "arm,psci-1.0";
 231                 method = "smc";
 232         };
 233
 234         reserved_memory: reserved-memory {
 235                 #address-cells = <2>;
 236                 #size-cells = <1>;
 237                 ranges;
 238
 239                 gsa_reserved_protected: gsa@90200000 {
 240                         reg = <0x0 0x90200000 0x400000>;
 241                         no-map;
 242                 };
 243
 244                 tpu_fw_reserved: tpu-fw@93000000 {
 245                         reg = <0x0 0x93000000 0x1000000>;
 246                         no-map;
 247                 };
 248
 249                 aoc_reserve: aoc@94000000 {
 250                         reg = <0x0 0x94000000 0x03000000>;
 251                         no-map;
 252                 };
 253
 254                 abl_reserved: abl@f8800000 {
 255                         reg = <0x0 0xf8800000 0x02000000>;
 256                         no-map;
 257                 };
 258
 259                 dss_log_reserved: dss-log-reserved@fd3f0000 {
 260                         reg = <0x0 0xfd3f0000 0x0000e000>;
 261                         no-map;
 262                 };
 263
 264                 debug_kinfo_reserved: debug-kinfo-reserved@fd3fe000 {
 265                         reg = <0x0 0xfd3fe000 0x00001000>;
 266                         no-map;
 267                 };
 268
 269                 bldr_log_reserved: bldr-log-reserved@fd800000 {
 270                         reg = <0x0 0xfd800000 0x00100000>;
 271                         no-map;
 272                 };
 273
 274                 bldr_log_hist_reserved: bldr-log-hist-reserved@fd900000 {
 275                         reg = <0x0 0xfd900000 0x00002000>;
 276                         no-map;
 277                 };
 278         };
 279
 280         soc: soc@0 {
 281                 compatible = "simple-bus";
 282                 #address-cells = <1>;
 283                 #size-cells = <1>;
 284                 ranges = <0x0 0x0 0x0 0x40000000>;
 285
 286                 cmu_misc: clock-controller@10010000 {
 287                         compatible = "google,gs101-cmu-misc";
 288                         reg = <0x10010000 0x8000>;
 289                         #clock-cells = <1>;
 290                         clocks = <&cmu_top CLK_DOUT_CMU_MISC_BUS>,
 291                                  <&cmu_top CLK_DOUT_CMU_MISC_SSS>;
 292                         clock-names = "bus", "sss";
 293                 };
 294
 295                 watchdog_cl0: watchdog@10060000 {
 296                         compatible = "google,gs101-wdt";
 297                         reg = <0x10060000 0x100>;
 298                         interrupts = <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH 0>;
 299                         clocks = <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER0_PCLK>,
 300                                  <&ext_24_5m>;
 301                         clock-names = "watchdog", "watchdog_src";
 302                         samsung,syscon-phandle = <&pmu_system_controller>;
 303                         samsung,cluster-index = <0>;
 304                         status = "disabled";
 305                 };
 306
 307                 watchdog_cl1: watchdog@10070000 {
 308                         compatible = "google,gs101-wdt";
 309                         reg = <0x10070000 0x100>;
 310                         interrupts = <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH 0>;
 311                         clocks = <&cmu_misc CLK_GOUT_MISC_WDT_CLUSTER1_PCLK>,
 312                                  <&ext_24_5m>;
 313                         clock-names = "watchdog", "watchdog_src";
 314                         samsung,syscon-phandle = <&pmu_system_controller>;
 315                         samsung,cluster-index = <1>;
 316                         status = "disabled";
 317                 };
 318
 319                 gic: interrupt-controller@10400000 {
 320                         compatible = "arm,gic-v3";
 321                         #interrupt-cells = <4>;
 322                         interrupt-controller;
 323                         reg = <0x10400000 0x10000>, /* GICD */
 324                               <0x10440000 0x100000>;/* GICR * 8 */
 325                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 326
 327                         ppi-partitions {
 328                                 ppi_cluster0: interrupt-partition-0 {
 329                                         affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
 330                                 };
 331
 332                                 ppi_cluster1: interrupt-partition-1 {
 333                                         affinity = <&cpu4 &cpu5>;
 334                                 };
 335
 336                                 ppi_cluster2: interrupt-partition-2 {
 337                                         affinity = <&cpu6 &cpu7>;
 338                                 };
 339                         };
 340                 };
 341
 342                 sysreg_peric0: syscon@10820000 {
 343                         compatible = "google,gs101-peric0-sysreg", "syscon";
 344                         reg = <0x10820000 0x10000>;
 345                 };
 346
 347                 pinctrl_peric0: pinctrl@10840000 {
 348                         compatible = "google,gs101-pinctrl";
 349                         reg = <0x10840000 0x00001000>;
 350                         interrupts = <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH 0>;
 351                 };
 352
 353                 usi_uart: usi@10a000c0 {
 354                         compatible = "google,gs101-usi",
 355                                      "samsung,exynos850-usi";
 356                         reg = <0x10a000c0 0x20>;
 357                         ranges;
 358                         #address-cells = <1>;
 359                         #size-cells = <1>;
 360                         clocks = <&dummy_clk>, <&dummy_clk>;
 361                         clock-names = "pclk", "ipclk";
 362                         samsung,sysreg = <&sysreg_peric0 0x1020>;
 363                         samsung,mode = <USI_V2_UART>;
 364                         status = "disabled";
 365
 366                         serial_0: serial@10a00000 {
 367                                 compatible = "google,gs101-uart";
 368                                 reg = <0x10a00000 0xc0>;
 369                                 reg-io-width = <4>;
 370                                 interrupts = <GIC_SPI 634
 371                                               IRQ_TYPE_LEVEL_HIGH 0>;
 372                                 clocks = <&dummy_clk 0>, <&dummy_clk 0>;
 373                                 clock-names = "uart", "clk_uart_baud0";
 374                                 samsung,uart-fifosize = <256>;
 375                                 status = "disabled";
 376                         };
 377                 };
 378
 379                 sysreg_peric1: syscon@10c20000 {
 380                         compatible = "google,gs101-peric1-sysreg", "syscon";
 381                         reg = <0x10c20000 0x10000>;
 382                 };
 383
 384                 pinctrl_peric1: pinctrl@10c40000 {
 385                         compatible = "google,gs101-pinctrl";
 386                         reg = <0x10c40000 0x00001000>;
 387                         interrupts = <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0>;
 388                 };
 389
 390                 pinctrl_hsi1: pinctrl@11840000 {
 391                         compatible = "google,gs101-pinctrl";
 392                         reg = <0x11840000 0x00001000>;
 393                         interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH 0>;
 394                 };
 395
 396                 pinctrl_hsi2: pinctrl@14440000 {
 397                         compatible = "google,gs101-pinctrl";
 398                         reg = <0x14440000 0x00001000>;
 399                         interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>;
 400                 };
 401
 402                 cmu_apm: clock-controller@17400000 {
 403                         compatible = "google,gs101-cmu-apm";
 404                         reg = <0x17400000 0x8000>;
 405                         #clock-cells = <1>;
 406
 407                         clocks = <&ext_24_5m>;
 408                         clock-names = "oscclk";
 409                 };
 410
 411                 sysreg_apm: syscon@174204e0 {
 412                         compatible = "google,gs101-apm-sysreg", "syscon";
 413                         reg = <0x174204e0 0x1000>;
 414                 };
 415
 416                 pmu_system_controller: system-controller@17460000 {
 417                         compatible = "google,gs101-pmu", "syscon";
 418                         reg = <0x17460000 0x10000>;
 419                 };
 420
 421                 pinctrl_gpio_alive: pinctrl@174d0000 {
 422                         compatible = "google,gs101-pinctrl";
 423                         reg = <0x174d0000 0x00001000>;
 424
 425                         wakeup-interrupt-controller {
 426                                 compatible = "google,gs101-wakeup-eint",
 427                                              "samsung,exynos850-wakeup-eint",
 428                                              "samsung,exynos7-wakeup-eint";
 429                         };
 430                 };
 431
 432                 pinctrl_far_alive: pinctrl@174e0000 {
 433                         compatible = "google,gs101-pinctrl";
 434                         reg = <0x174e0000 0x00001000>;
 435
 436                         wakeup-interrupt-controller {
 437                                 compatible = "google,gs101-wakeup-eint",
 438                                              "samsung,exynos850-wakeup-eint",
 439                                              "samsung,exynos7-wakeup-eint";
 440                         };
 441                 };
 442
 443                 pinctrl_gsactrl: pinctrl@17940000 {
 444                         compatible = "google,gs101-pinctrl";
 445                         reg = <0x17940000 0x00001000>;
 446                 };
 447
 448                 pinctrl_gsacore: pinctrl@17a80000 {
 449                         compatible = "google,gs101-pinctrl";
 450                         reg = <0x17a80000 0x00001000>;
 451                 };
 452
 453                 cmu_top: clock-controller@1e080000 {
 454                         compatible = "google,gs101-cmu-top";
 455                         reg = <0x1e080000 0x8000>;
 456                         #clock-cells = <1>;
 457
 458                         clocks = <&ext_24_5m>;
 459                         clock-names = "oscclk";
 460                 };
 461         };
 462
 463         timer {
 464                 compatible = "arm,armv8-timer";
 465                 interrupts =
 466                    <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>,
 467                    <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>,
 468                    <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>,
 469                    <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>;
 470         };
 471 };
 472
 473 #include "gs101-pinctrl.dtsi"