arch/arm64/boot/dts/arm/juno-base.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include "juno-clocks.dtsi"
   3 #include "juno-motherboard.dtsi"
   4
   5 / {
   6         /*
   7          *  Devices shared by all Juno boards
   8          */
   9
  10         memtimer: timer@2a810000 {
  11                 compatible = "arm,armv7-timer-mem";
  12                 reg = <0x0 0x2a810000 0x0 0x10000>;
  13                 clock-frequency = <50000000>;
  14                 #address-cells = <1>;
  15                 #size-cells = <1>;
  16                 ranges = <0 0x0 0x2a820000 0x20000>;
  17                 status = "disabled";
  18                 frame@2a830000 {
  19                         frame-number = <1>;
  20                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
  21                         reg = <0x10000 0x10000>;
  22                 };
  23         };
  24
  25         mailbox: mhu@2b1f0000 {
  26                 compatible = "arm,mhu", "arm,primecell";
  27                 reg = <0x0 0x2b1f0000 0x0 0x1000>;
  28                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
  29                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
  30                 #mbox-cells = <1>;
  31                 clocks = <&soc_refclk100mhz>;
  32                 clock-names = "apb_pclk";
  33         };
  34
  35         smmu_gpu: iommu@2b400000 {
  36                 compatible = "arm,mmu-400", "arm,smmu-v1";
  37                 reg = <0x0 0x2b400000 0x0 0x10000>;
  38                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
  39                              <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
  40                 #iommu-cells = <1>;
  41                 #global-interrupts = <1>;
  42                 power-domains = <&scpi_devpd 1>;
  43                 dma-coherent;
  44                 status = "disabled";
  45         };
  46
  47         smmu_pcie: iommu@2b500000 {
  48                 compatible = "arm,mmu-401", "arm,smmu-v1";
  49                 reg = <0x0 0x2b500000 0x0 0x10000>;
  50                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
  51                              <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
  52                 #iommu-cells = <1>;
  53                 #global-interrupts = <1>;
  54                 dma-coherent;
  55                 status = "disabled";
  56         };
  57
  58         smmu_etr: iommu@2b600000 {
  59                 compatible = "arm,mmu-401", "arm,smmu-v1";
  60                 reg = <0x0 0x2b600000 0x0 0x10000>;
  61                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
  62                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
  63                 #iommu-cells = <1>;
  64                 #global-interrupts = <1>;
  65                 dma-coherent;
  66                 power-domains = <&scpi_devpd 0>;
  67         };
  68
  69         gic: interrupt-controller@2c010000 {
  70                 compatible = "arm,gic-400", "arm,cortex-a15-gic";
  71                 reg = <0x0 0x2c010000 0 0x1000>,
  72                       <0x0 0x2c02f000 0 0x2000>,
  73                       <0x0 0x2c04f000 0 0x2000>,
  74                       <0x0 0x2c06f000 0 0x2000>;
  75                 #address-cells = <1>;
  76                 #interrupt-cells = <3>;
  77                 #size-cells = <1>;
  78                 interrupt-controller;
  79                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
  80                 ranges = <0 0 0x2c1c0000 0x40000>;
  81
  82                 v2m_0: v2m@0 {
  83                         compatible = "arm,gic-v2m-frame";
  84                         msi-controller;
  85                         reg = <0 0x10000>;
  86                 };
  87
  88                 v2m@10000 {
  89                         compatible = "arm,gic-v2m-frame";
  90                         msi-controller;
  91                         reg = <0x10000 0x10000>;
  92                 };
  93
  94                 v2m@20000 {
  95                         compatible = "arm,gic-v2m-frame";
  96                         msi-controller;
  97                         reg = <0x20000 0x10000>;
  98                 };
  99
 100                 v2m@30000 {
 101                         compatible = "arm,gic-v2m-frame";
 102                         msi-controller;
 103                         reg = <0x30000 0x10000>;
 104                 };
 105         };
 106
 107         timer {
 108                 compatible = "arm,armv8-timer";
 109                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
 110                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
 111                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
 112                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
 113         };
 114
 115         /*
 116          * Juno TRMs specify the size for these coresight components as 64K.
 117          * The actual size is just 4K though 64K is reserved. Access to the
 118          * unmapped reserved region results in a DECERR response.
 119          */
 120         etf_sys0: etf@20010000 { /* etf0 */
 121                 compatible = "arm,coresight-tmc", "arm,primecell";
 122                 reg = <0 0x20010000 0 0x1000>;
 123
 124                 clocks = <&soc_smc50mhz>;
 125                 clock-names = "apb_pclk";
 126                 power-domains = <&scpi_devpd 0>;
 127
 128                 in-ports {
 129                         port {
 130                                 etf0_in_port: endpoint {
 131                                         remote-endpoint = <&main_funnel_out_port>;
 132                                 };
 133                         };
 134                 };
 135
 136                 out-ports {
 137                         port {
 138                                 etf0_out_port: endpoint {
 139                                 };
 140                         };
 141                 };
 142         };
 143
 144         tpiu_sys: tpiu@20030000 {
 145                 compatible = "arm,coresight-tpiu", "arm,primecell";
 146                 reg = <0 0x20030000 0 0x1000>;
 147
 148                 clocks = <&soc_smc50mhz>;
 149                 clock-names = "apb_pclk";
 150                 power-domains = <&scpi_devpd 0>;
 151                 in-ports {
 152                         port {
 153                                 tpiu_in_port: endpoint {
 154                                         remote-endpoint = <&replicator_out_port0>;
 155                                 };
 156                         };
 157                 };
 158         };
 159
 160         /* main funnel on Juno r0, cssys0 funnel on Juno r1/r2 as per TRM*/
 161         main_funnel: funnel@20040000 {
 162                 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 163                 reg = <0 0x20040000 0 0x1000>;
 164
 165                 clocks = <&soc_smc50mhz>;
 166                 clock-names = "apb_pclk";
 167                 power-domains = <&scpi_devpd 0>;
 168
 169                 out-ports {
 170                         port {
 171                                 main_funnel_out_port: endpoint {
 172                                         remote-endpoint = <&etf0_in_port>;
 173                                 };
 174                         };
 175                 };
 176
 177                 main_funnel_in_ports: in-ports {
 178                         #address-cells = <1>;
 179                         #size-cells = <0>;
 180
 181                         port@0 {
 182                                 reg = <0>;
 183                                 main_funnel_in_port0: endpoint {
 184                                         remote-endpoint = <&cluster0_funnel_out_port>;
 185                                 };
 186                         };
 187
 188                         port@1 {
 189                                 reg = <1>;
 190                                 main_funnel_in_port1: endpoint {
 191                                         remote-endpoint = <&cluster1_funnel_out_port>;
 192                                 };
 193                         };
 194                 };
 195         };
 196
 197         etr_sys: etr@20070000 {
 198                 compatible = "arm,coresight-tmc", "arm,primecell";
 199                 reg = <0 0x20070000 0 0x1000>;
 200                 iommus = <&smmu_etr 0>;
 201
 202                 clocks = <&soc_smc50mhz>;
 203                 clock-names = "apb_pclk";
 204                 power-domains = <&scpi_devpd 0>;
 205                 arm,scatter-gather;
 206                 in-ports {
 207                         port {
 208                                 etr_in_port: endpoint {
 209                                         remote-endpoint = <&replicator_out_port1>;
 210                                 };
 211                         };
 212                 };
 213         };
 214
 215         stm_sys: stm@20100000 {
 216                 compatible = "arm,coresight-stm", "arm,primecell";
 217                 reg = <0 0x20100000 0 0x1000>,
 218                       <0 0x28000000 0 0x1000000>;
 219                 reg-names = "stm-base", "stm-stimulus-base";
 220
 221                 clocks = <&soc_smc50mhz>;
 222                 clock-names = "apb_pclk";
 223                 power-domains = <&scpi_devpd 0>;
 224                 out-ports {
 225                         port {
 226                                 stm_out_port: endpoint {
 227                                 };
 228                         };
 229                 };
 230         };
 231
 232         replicator@20120000 {
 233                 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
 234                 reg = <0 0x20120000 0 0x1000>;
 235
 236                 clocks = <&soc_smc50mhz>;
 237                 clock-names = "apb_pclk";
 238                 power-domains = <&scpi_devpd 0>;
 239
 240                 out-ports {
 241                         #address-cells = <1>;
 242                         #size-cells = <0>;
 243
 244                         /* replicator output ports */
 245                         port@0 {
 246                                 reg = <0>;
 247                                 replicator_out_port0: endpoint {
 248                                         remote-endpoint = <&tpiu_in_port>;
 249                                 };
 250                         };
 251
 252                         port@1 {
 253                                 reg = <1>;
 254                                 replicator_out_port1: endpoint {
 255                                         remote-endpoint = <&etr_in_port>;
 256                                 };
 257                         };
 258                 };
 259                 in-ports {
 260                         port {
 261                                 replicator_in_port0: endpoint {
 262                                 };
 263                         };
 264                 };
 265         };
 266
 267         cpu_debug0: cpu-debug@22010000 {
 268                 compatible = "arm,coresight-cpu-debug", "arm,primecell";
 269                 reg = <0x0 0x22010000 0x0 0x1000>;
 270
 271                 clocks = <&soc_smc50mhz>;
 272                 clock-names = "apb_pclk";
 273                 power-domains = <&scpi_devpd 0>;
 274         };
 275
 276         etm0: etm@22040000 {
 277                 compatible = "arm,coresight-etm4x", "arm,primecell";
 278                 reg = <0 0x22040000 0 0x1000>;
 279
 280                 clocks = <&soc_smc50mhz>;
 281                 clock-names = "apb_pclk";
 282                 power-domains = <&scpi_devpd 0>;
 283                 out-ports {
 284                         port {
 285                                 cluster0_etm0_out_port: endpoint {
 286                                         remote-endpoint = <&cluster0_funnel_in_port0>;
 287                                 };
 288                         };
 289                 };
 290         };
 291
 292         cti0: cti@22020000 {
 293                 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
 294                              "arm,primecell";
 295                 reg = <0 0x22020000 0 0x1000>;
 296
 297                 clocks = <&soc_smc50mhz>;
 298                 clock-names = "apb_pclk";
 299                 power-domains = <&scpi_devpd 0>;
 300
 301                 arm,cs-dev-assoc = <&etm0>;
 302         };
 303
 304         funnel@220c0000 { /* cluster0 funnel */
 305                 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 306                 reg = <0 0x220c0000 0 0x1000>;
 307
 308                 clocks = <&soc_smc50mhz>;
 309                 clock-names = "apb_pclk";
 310                 power-domains = <&scpi_devpd 0>;
 311                 out-ports {
 312                         port {
 313                                 cluster0_funnel_out_port: endpoint {
 314                                         remote-endpoint = <&main_funnel_in_port0>;
 315                                 };
 316                         };
 317                 };
 318
 319                 in-ports {
 320                         #address-cells = <1>;
 321                         #size-cells = <0>;
 322
 323                         port@0 {
 324                                 reg = <0>;
 325                                 cluster0_funnel_in_port0: endpoint {
 326                                         remote-endpoint = <&cluster0_etm0_out_port>;
 327                                 };
 328                         };
 329
 330                         port@1 {
 331                                 reg = <1>;
 332                                 cluster0_funnel_in_port1: endpoint {
 333                                         remote-endpoint = <&cluster0_etm1_out_port>;
 334                                 };
 335                         };
 336                 };
 337         };
 338
 339         cpu_debug1: cpu-debug@22110000 {
 340                 compatible = "arm,coresight-cpu-debug", "arm,primecell";
 341                 reg = <0x0 0x22110000 0x0 0x1000>;
 342
 343                 clocks = <&soc_smc50mhz>;
 344                 clock-names = "apb_pclk";
 345                 power-domains = <&scpi_devpd 0>;
 346         };
 347
 348         etm1: etm@22140000 {
 349                 compatible = "arm,coresight-etm4x", "arm,primecell";
 350                 reg = <0 0x22140000 0 0x1000>;
 351
 352                 clocks = <&soc_smc50mhz>;
 353                 clock-names = "apb_pclk";
 354                 power-domains = <&scpi_devpd 0>;
 355                 out-ports {
 356                         port {
 357                                 cluster0_etm1_out_port: endpoint {
 358                                         remote-endpoint = <&cluster0_funnel_in_port1>;
 359                                 };
 360                         };
 361                 };
 362         };
 363
 364         cti1: cti@22120000 {
 365                 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
 366                              "arm,primecell";
 367                 reg = <0 0x22120000 0 0x1000>;
 368
 369                 clocks = <&soc_smc50mhz>;
 370                 clock-names = "apb_pclk";
 371                 power-domains = <&scpi_devpd 0>;
 372
 373                 arm,cs-dev-assoc = <&etm1>;
 374         };
 375
 376         cpu_debug2: cpu-debug@23010000 {
 377                 compatible = "arm,coresight-cpu-debug", "arm,primecell";
 378                 reg = <0x0 0x23010000 0x0 0x1000>;
 379
 380                 clocks = <&soc_smc50mhz>;
 381                 clock-names = "apb_pclk";
 382                 power-domains = <&scpi_devpd 0>;
 383         };
 384
 385         etm2: etm@23040000 {
 386                 compatible = "arm,coresight-etm4x", "arm,primecell";
 387                 reg = <0 0x23040000 0 0x1000>;
 388
 389                 clocks = <&soc_smc50mhz>;
 390                 clock-names = "apb_pclk";
 391                 power-domains = <&scpi_devpd 0>;
 392                 out-ports {
 393                         port {
 394                                 cluster1_etm0_out_port: endpoint {
 395                                         remote-endpoint = <&cluster1_funnel_in_port0>;
 396                                 };
 397                         };
 398                 };
 399         };
 400
 401         cti2: cti@23020000 {
 402                 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
 403                              "arm,primecell";
 404                 reg = <0 0x23020000 0 0x1000>;
 405
 406                 clocks = <&soc_smc50mhz>;
 407                 clock-names = "apb_pclk";
 408                 power-domains = <&scpi_devpd 0>;
 409
 410                 arm,cs-dev-assoc = <&etm2>;
 411         };
 412
 413         funnel@230c0000 { /* cluster1 funnel */
 414                 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 415                 reg = <0 0x230c0000 0 0x1000>;
 416
 417                 clocks = <&soc_smc50mhz>;
 418                 clock-names = "apb_pclk";
 419                 power-domains = <&scpi_devpd 0>;
 420                 out-ports {
 421                         port {
 422                                 cluster1_funnel_out_port: endpoint {
 423                                         remote-endpoint = <&main_funnel_in_port1>;
 424                                 };
 425                         };
 426                 };
 427
 428                 in-ports {
 429                         #address-cells = <1>;
 430                         #size-cells = <0>;
 431
 432                         port@0 {
 433                                 reg = <0>;
 434                                 cluster1_funnel_in_port0: endpoint {
 435                                         remote-endpoint = <&cluster1_etm0_out_port>;
 436                                 };
 437                         };
 438
 439                         port@1 {
 440                                 reg = <1>;
 441                                 cluster1_funnel_in_port1: endpoint {
 442                                         remote-endpoint = <&cluster1_etm1_out_port>;
 443                                 };
 444                         };
 445                         port@2 {
 446                                 reg = <2>;
 447                                 cluster1_funnel_in_port2: endpoint {
 448                                         remote-endpoint = <&cluster1_etm2_out_port>;
 449                                 };
 450                         };
 451                         port@3 {
 452                                 reg = <3>;
 453                                 cluster1_funnel_in_port3: endpoint {
 454                                         remote-endpoint = <&cluster1_etm3_out_port>;
 455                                 };
 456                         };
 457                 };
 458         };
 459
 460         cpu_debug3: cpu-debug@23110000 {
 461                 compatible = "arm,coresight-cpu-debug", "arm,primecell";
 462                 reg = <0x0 0x23110000 0x0 0x1000>;
 463
 464                 clocks = <&soc_smc50mhz>;
 465                 clock-names = "apb_pclk";
 466                 power-domains = <&scpi_devpd 0>;
 467         };
 468
 469         etm3: etm@23140000 {
 470                 compatible = "arm,coresight-etm4x", "arm,primecell";
 471                 reg = <0 0x23140000 0 0x1000>;
 472
 473                 clocks = <&soc_smc50mhz>;
 474                 clock-names = "apb_pclk";
 475                 power-domains = <&scpi_devpd 0>;
 476                 out-ports {
 477                         port {
 478                                 cluster1_etm1_out_port: endpoint {
 479                                         remote-endpoint = <&cluster1_funnel_in_port1>;
 480                                 };
 481                         };
 482                 };
 483         };
 484
 485         cti3: cti@23120000 {
 486                 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
 487                              "arm,primecell";
 488                 reg = <0 0x23120000 0 0x1000>;
 489
 490                 clocks = <&soc_smc50mhz>;
 491                 clock-names = "apb_pclk";
 492                 power-domains = <&scpi_devpd 0>;
 493
 494                 arm,cs-dev-assoc = <&etm3>;
 495         };
 496
 497         cpu_debug4: cpu-debug@23210000 {
 498                 compatible = "arm,coresight-cpu-debug", "arm,primecell";
 499                 reg = <0x0 0x23210000 0x0 0x1000>;
 500
 501                 clocks = <&soc_smc50mhz>;
 502                 clock-names = "apb_pclk";
 503                 power-domains = <&scpi_devpd 0>;
 504         };
 505
 506         etm4: etm@23240000 {
 507                 compatible = "arm,coresight-etm4x", "arm,primecell";
 508                 reg = <0 0x23240000 0 0x1000>;
 509
 510                 clocks = <&soc_smc50mhz>;
 511                 clock-names = "apb_pclk";
 512                 power-domains = <&scpi_devpd 0>;
 513                 out-ports {
 514                         port {
 515                                 cluster1_etm2_out_port: endpoint {
 516                                         remote-endpoint = <&cluster1_funnel_in_port2>;
 517                                 };
 518                         };
 519                 };
 520         };
 521
 522         cti4: cti@23220000 {
 523                 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
 524                              "arm,primecell";
 525                 reg = <0 0x23220000 0 0x1000>;
 526
 527                 clocks = <&soc_smc50mhz>;
 528                 clock-names = "apb_pclk";
 529                 power-domains = <&scpi_devpd 0>;
 530
 531                 arm,cs-dev-assoc = <&etm4>;
 532         };
 533
 534         cpu_debug5: cpu-debug@23310000 {
 535                 compatible = "arm,coresight-cpu-debug", "arm,primecell";
 536                 reg = <0x0 0x23310000 0x0 0x1000>;
 537
 538                 clocks = <&soc_smc50mhz>;
 539                 clock-names = "apb_pclk";
 540                 power-domains = <&scpi_devpd 0>;
 541         };
 542
 543         etm5: etm@23340000 {
 544                 compatible = "arm,coresight-etm4x", "arm,primecell";
 545                 reg = <0 0x23340000 0 0x1000>;
 546
 547                 clocks = <&soc_smc50mhz>;
 548                 clock-names = "apb_pclk";
 549                 power-domains = <&scpi_devpd 0>;
 550                 out-ports {
 551                         port {
 552                                 cluster1_etm3_out_port: endpoint {
 553                                         remote-endpoint = <&cluster1_funnel_in_port3>;
 554                                 };
 555                         };
 556                 };
 557         };
 558
 559         cti5: cti@23320000 {
 560                 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
 561                              "arm,primecell";
 562                 reg = <0 0x23320000 0 0x1000>;
 563
 564                 clocks = <&soc_smc50mhz>;
 565                 clock-names = "apb_pclk";
 566                 power-domains = <&scpi_devpd 0>;
 567
 568                 arm,cs-dev-assoc = <&etm5>;
 569         };
 570
 571         cti_sys0: cti@20020000 { /* sys_cti_0 */
 572                 compatible = "arm,coresight-cti", "arm,primecell";
 573                 reg = <0 0x20020000 0 0x1000>;
 574
 575                 clocks = <&soc_smc50mhz>;
 576                 clock-names = "apb_pclk";
 577                 power-domains = <&scpi_devpd 0>;
 578
 579                 #address-cells = <1>;
 580                 #size-cells = <0>;
 581
 582                 trig-conns@0 {
 583                         reg = <0>;
 584                         arm,trig-in-sigs=<2 3>;
 585                         arm,trig-in-types=<SNK_FULL SNK_ACQCOMP>;
 586                         arm,trig-out-sigs=<0 1>;
 587                         arm,trig-out-types=<SNK_FLUSHIN SNK_TRIGIN>;
 588                         arm,cs-dev-assoc = <&etr_sys>;
 589                 };
 590
 591                 trig-conns@1 {
 592                         reg = <1>;
 593                         arm,trig-in-sigs=<0 1>;
 594                         arm,trig-in-types=<SNK_FULL SNK_ACQCOMP>;
 595                         arm,trig-out-sigs=<7 6>;
 596                         arm,trig-out-types=<SNK_FLUSHIN SNK_TRIGIN>;
 597                         arm,cs-dev-assoc = <&etf_sys0>;
 598                 };
 599
 600                 trig-conns@2 {
 601                         reg = <2>;
 602                         arm,trig-in-sigs=<4 5 6 7>;
 603                         arm,trig-in-types=<STM_TOUT_SPTE STM_TOUT_SW
 604                                            STM_TOUT_HETE STM_ASYNCOUT>;
 605                         arm,trig-out-sigs=<4 5>;
 606                         arm,trig-out-types=<STM_HWEVENT STM_HWEVENT>;
 607                         arm,cs-dev-assoc = <&stm_sys>;
 608                 };
 609
 610                 trig-conns@3 {
 611                         reg = <3>;
 612                         arm,trig-out-sigs=<2 3>;
 613                         arm,trig-out-types=<SNK_FLUSHIN SNK_TRIGIN>;
 614                         arm,cs-dev-assoc = <&tpiu_sys>;
 615                 };
 616         };
 617
 618         cti_sys1: cti@20110000 { /* sys_cti_1 */
 619                 compatible = "arm,coresight-cti", "arm,primecell";
 620                 reg = <0 0x20110000 0 0x1000>;
 621
 622                 clocks = <&soc_smc50mhz>;
 623                 clock-names = "apb_pclk";
 624                 power-domains = <&scpi_devpd 0>;
 625
 626                 #address-cells = <1>;
 627                 #size-cells = <0>;
 628
 629                 trig-conns@0 {
 630                         reg = <0>;
 631                         arm,trig-in-sigs=<0>;
 632                         arm,trig-in-types=<GEN_INTREQ>;
 633                         arm,trig-out-sigs=<0>;
 634                         arm,trig-out-types=<GEN_HALTREQ>;
 635                         arm,trig-conn-name = "sys_profiler";
 636                 };
 637
 638                 trig-conns@1 {
 639                         reg = <1>;
 640                         arm,trig-out-sigs=<2 3>;
 641                         arm,trig-out-types=<GEN_HALTREQ GEN_RESTARTREQ>;
 642                         arm,trig-conn-name = "watchdog";
 643                 };
 644
 645                 trig-conns@2 {
 646                         reg = <2>;
 647                         arm,trig-out-sigs=<1 6>;
 648                         arm,trig-out-types=<GEN_HALTREQ GEN_RESTARTREQ>;
 649                         arm,trig-conn-name = "g_counter";
 650                 };
 651         };
 652
 653         gpu: gpu@2d000000 {
 654                 compatible = "arm,juno-mali", "arm,mali-t624";
 655                 reg = <0 0x2d000000 0 0x10000>;
 656                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 657                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 658                              <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 659                 interrupt-names = "job", "mmu", "gpu";
 660                 clocks = <&scpi_dvfs 2>;
 661                 power-domains = <&scpi_devpd 1>;
 662                 dma-coherent;
 663                 /* The SMMU is only really of interest to bare-metal hypervisors */
 664                 /* iommus = <&smmu_gpu 0>; */
 665                 status = "disabled";
 666         };
 667
 668         sram: sram@2e000000 {
 669                 compatible = "arm,juno-sram-ns", "mmio-sram";
 670                 reg = <0x0 0x2e000000 0x0 0x8000>;
 671
 672                 #address-cells = <1>;
 673                 #size-cells = <1>;
 674                 ranges = <0 0x0 0x2e000000 0x8000>;
 675
 676                 cpu_scp_lpri: scp-sram@0 {
 677                         compatible = "arm,juno-scp-shmem";
 678                         reg = <0x0 0x200>;
 679                 };
 680
 681                 cpu_scp_hpri: scp-sram@200 {
 682                         compatible = "arm,juno-scp-shmem";
 683                         reg = <0x200 0x200>;
 684                 };
 685         };
 686
 687         pcie_ctlr: pcie@40000000 {
 688                 compatible = "arm,juno-r1-pcie", "plda,xpressrich3-axi", "pci-host-ecam-generic";
 689                 device_type = "pci";
 690                 reg = <0 0x40000000 0 0x10000000>;      /* ECAM config space */
 691                 bus-range = <0 255>;
 692                 linux,pci-domain = <0>;
 693                 #address-cells = <3>;
 694                 #size-cells = <2>;
 695                 dma-coherent;
 696                 ranges = <0x01000000 0x00 0x00000000 0x00 0x5f800000 0x0 0x00800000>,
 697                          <0x02000000 0x00 0x50000000 0x00 0x50000000 0x0 0x08000000>,
 698                          <0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>;
 699                 /* Standard AXI Translation entries as programmed by EDK2 */
 700                 dma-ranges = <0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x80000000>,
 701                              <0x43000000 0x8 0x00000000 0x8 0x00000000 0x2 0x00000000>;
 702                 #interrupt-cells = <1>;
 703                 interrupt-map-mask = <0 0 0 7>;
 704                 interrupt-map = <0 0 0 1 &gic 0 GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
 705                                 <0 0 0 2 &gic 0 GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 706                                 <0 0 0 3 &gic 0 GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 707                                 <0 0 0 4 &gic 0 GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
 708                 msi-parent = <&v2m_0>;
 709                 status = "disabled";
 710                 iommu-map-mask = <0x0>; /* RC has no means to output PCI RID */
 711                 iommu-map = <0x0 &smmu_pcie 0x0 0x1>;
 712         };
 713
 714         scpi {
 715                 compatible = "arm,scpi";
 716                 mboxes = <&mailbox 1>;
 717                 shmem = <&cpu_scp_hpri>;
 718
 719                 clocks {
 720                         compatible = "arm,scpi-clocks";
 721
 722                         scpi_dvfs: clocks-0 {
 723                                 compatible = "arm,scpi-dvfs-clocks";
 724                                 #clock-cells = <1>;
 725                                 clock-indices = <0>, <1>, <2>;
 726                                 clock-output-names = "atlclk", "aplclk","gpuclk";
 727                         };
 728                         scpi_clk: clocks-1 {
 729                                 compatible = "arm,scpi-variable-clocks";
 730                                 #clock-cells = <1>;
 731                                 clock-indices = <3>;
 732                                 clock-output-names = "pxlclk";
 733                         };
 734                 };
 735
 736                 scpi_devpd: power-controller {
 737                         compatible = "arm,scpi-power-domains";
 738                         num-domains = <2>;
 739                         #power-domain-cells = <1>;
 740                 };
 741
 742                 scpi_sensors0: sensors {
 743                         compatible = "arm,scpi-sensors";
 744                         #thermal-sensor-cells = <1>;
 745                 };
 746         };
 747
 748         thermal-zones {
 749                 pmic {
 750                         polling-delay = <1000>;
 751                         polling-delay-passive = <100>;
 752                         thermal-sensors = <&scpi_sensors0 0>;
 753                 };
 754
 755                 soc {
 756                         polling-delay = <1000>;
 757                         polling-delay-passive = <100>;
 758                         thermal-sensors = <&scpi_sensors0 3>;
 759                 };
 760
 761                 big_cluster_thermal_zone: big-cluster {
 762                         polling-delay = <1000>;
 763                         polling-delay-passive = <100>;
 764                         thermal-sensors = <&scpi_sensors0 21>;
 765                         status = "disabled";
 766                 };
 767
 768                 little_cluster_thermal_zone: little-cluster {
 769                         polling-delay = <1000>;
 770                         polling-delay-passive = <100>;
 771                         thermal-sensors = <&scpi_sensors0 22>;
 772                         status = "disabled";
 773                 };
 774
 775                 gpu0_thermal_zone: gpu0 {
 776                         polling-delay = <1000>;
 777                         polling-delay-passive = <100>;
 778                         thermal-sensors = <&scpi_sensors0 23>;
 779                         status = "disabled";
 780                 };
 781
 782                 gpu1_thermal_zone: gpu1 {
 783                         polling-delay = <1000>;
 784                         polling-delay-passive = <100>;
 785                         thermal-sensors = <&scpi_sensors0 24>;
 786                         status = "disabled";
 787                 };
 788         };
 789
 790         smmu_dma: iommu@7fb00000 {
 791                 compatible = "arm,mmu-401", "arm,smmu-v1";
 792                 reg = <0x0 0x7fb00000 0x0 0x10000>;
 793                 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
 794                              <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 795                 #iommu-cells = <1>;
 796                 #global-interrupts = <1>;
 797                 dma-coherent;
 798         };
 799
 800         smmu_hdlcd1: iommu@7fb10000 {
 801                 compatible = "arm,mmu-401", "arm,smmu-v1";
 802                 reg = <0x0 0x7fb10000 0x0 0x10000>;
 803                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
 804                              <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 805                 #iommu-cells = <1>;
 806                 #global-interrupts = <1>;
 807         };
 808
 809         smmu_hdlcd0: iommu@7fb20000 {
 810                 compatible = "arm,mmu-401", "arm,smmu-v1";
 811                 reg = <0x0 0x7fb20000 0x0 0x10000>;
 812                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
 813                              <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 814                 #iommu-cells = <1>;
 815                 #global-interrupts = <1>;
 816         };
 817
 818         smmu_usb: iommu@7fb30000 {
 819                 compatible = "arm,mmu-401", "arm,smmu-v1";
 820                 reg = <0x0 0x7fb30000 0x0 0x10000>;
 821                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 822                              <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 823                 #iommu-cells = <1>;
 824                 #global-interrupts = <1>;
 825                 dma-coherent;
 826         };
 827
 828         dma-controller@7ff00000 {
 829                 compatible = "arm,pl330", "arm,primecell";
 830                 reg = <0x0 0x7ff00000 0 0x1000>;
 831                 #dma-cells = <1>;
 832                 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
 833                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 834                              <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
 835                              <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
 836                              <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
 837                              <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 838                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 839                              <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 840                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 841                 iommus = <&smmu_dma 0>,
 842                          <&smmu_dma 1>,
 843                          <&smmu_dma 2>,
 844                          <&smmu_dma 3>,
 845                          <&smmu_dma 4>,
 846                          <&smmu_dma 5>,
 847                          <&smmu_dma 6>,
 848                          <&smmu_dma 7>,
 849                          <&smmu_dma 8>;
 850                 clocks = <&soc_faxiclk>;
 851                 clock-names = "apb_pclk";
 852         };
 853
 854         hdlcd@7ff50000 {
 855                 compatible = "arm,hdlcd";
 856                 reg = <0 0x7ff50000 0 0x1000>;
 857                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 858                 iommus = <&smmu_hdlcd1 0>;
 859                 clocks = <&scpi_clk 3>;
 860                 clock-names = "pxlclk";
 861
 862                 port {
 863                         hdlcd1_output: endpoint {
 864                                 remote-endpoint = <&tda998x_1_input>;
 865                         };
 866                 };
 867         };
 868
 869         hdlcd@7ff60000 {
 870                 compatible = "arm,hdlcd";
 871                 reg = <0 0x7ff60000 0 0x1000>;
 872                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 873                 iommus = <&smmu_hdlcd0 0>;
 874                 clocks = <&scpi_clk 3>;
 875                 clock-names = "pxlclk";
 876
 877                 port {
 878                         hdlcd0_output: endpoint {
 879                                 remote-endpoint = <&tda998x_0_input>;
 880                         };
 881                 };
 882         };
 883
 884         soc_uart0: serial@7ff80000 {
 885                 compatible = "arm,pl011", "arm,primecell";
 886                 reg = <0x0 0x7ff80000 0x0 0x1000>;
 887                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 888                 clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
 889                 clock-names = "uartclk", "apb_pclk";
 890         };
 891
 892         i2c@7ffa0000 {
 893                 compatible = "snps,designware-i2c";
 894                 reg = <0x0 0x7ffa0000 0x0 0x1000>;
 895                 #address-cells = <1>;
 896                 #size-cells = <0>;
 897                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 898                 clock-frequency = <400000>;
 899                 i2c-sda-hold-time-ns = <500>;
 900                 clocks = <&soc_smc50mhz>;
 901
 902                 hdmi-transmitter@70 {
 903                         compatible = "nxp,tda998x";
 904                         reg = <0x70>;
 905                         port {
 906                                 tda998x_0_input: endpoint {
 907                                         remote-endpoint = <&hdlcd0_output>;
 908                                 };
 909                         };
 910                 };
 911
 912                 hdmi-transmitter@71 {
 913                         compatible = "nxp,tda998x";
 914                         reg = <0x71>;
 915                         port {
 916                                 tda998x_1_input: endpoint {
 917                                         remote-endpoint = <&hdlcd1_output>;
 918                                 };
 919                         };
 920                 };
 921         };
 922
 923         usb@7ffb0000 {
 924                 compatible = "generic-ohci";
 925                 reg = <0x0 0x7ffb0000 0x0 0x10000>;
 926                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 927                 iommus = <&smmu_usb 0>;
 928                 clocks = <&soc_usb48mhz>;
 929         };
 930
 931         usb@7ffc0000 {
 932                 compatible = "generic-ehci";
 933                 reg = <0x0 0x7ffc0000 0x0 0x10000>;
 934                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 935                 iommus = <&smmu_usb 0>;
 936                 clocks = <&soc_usb48mhz>;
 937         };
 938
 939         memory-controller@7ffd0000 {
 940                 compatible = "arm,pl354", "arm,primecell";
 941                 reg = <0 0x7ffd0000 0 0x1000>;
 942                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
 943                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 944                 clocks = <&soc_smc50mhz>;
 945                 clock-names = "apb_pclk";
 946         };
 947
 948         memory@80000000 {
 949                 device_type = "memory";
 950                 /* last 16MB of the first memory area is reserved for secure world use by firmware */
 951                 reg = <0x00000000 0x80000000 0x0 0x7f000000>,
 952                       <0x00000008 0x80000000 0x1 0x80000000>;
 953         };
 954
 955         bus@8000000 {
 956                 #interrupt-cells = <1>;
 957                 interrupt-map-mask = <0 0 15>;
 958                 interrupt-map = <0 0  0 &gic 0 GIC_SPI  68 IRQ_TYPE_LEVEL_HIGH>,
 959                                 <0 0  1 &gic 0 GIC_SPI  69 IRQ_TYPE_LEVEL_HIGH>,
 960                                 <0 0  2 &gic 0 GIC_SPI  70 IRQ_TYPE_LEVEL_HIGH>,
 961                                 <0 0  3 &gic 0 GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
 962                                 <0 0  4 &gic 0 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
 963                                 <0 0  5 &gic 0 GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
 964                                 <0 0  6 &gic 0 GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
 965                                 <0 0  7 &gic 0 GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
 966                                 <0 0  8 &gic 0 GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
 967                                 <0 0  9 &gic 0 GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
 968                                 <0 0 10 &gic 0 GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
 969                                 <0 0 11 &gic 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
 970                                 <0 0 12 &gic 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
 971         };
 972
 973         site2: tlx-bus@60000000 {
 974                 compatible = "simple-bus";
 975                 #address-cells = <1>;
 976                 #size-cells = <1>;
 977                 ranges = <0 0 0x60000000 0x10000000>;
 978                 #interrupt-cells = <1>;
 979                 interrupt-map-mask = <0 0>;
 980                 interrupt-map = <0 0 &gic 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
 981         };
 982 };