1 # SPDX-License-Identifier: GPL-2.0-only
4 select ACPI_CCA_REQUIRED if ACPI
5 select ACPI_GENERIC_GSI if ACPI
6 select ACPI_GTDT if ACPI
7 select ACPI_IORT if ACPI
8 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
9 select ACPI_MCFG if (ACPI && PCI)
10 select ACPI_SPCR_TABLE if ACPI
11 select ACPI_PPTT if ACPI
12 select ARCH_HAS_DEBUG_WX
13 select ARCH_BINFMT_ELF_STATE
14 select ARCH_HAS_DEBUG_VIRTUAL
15 select ARCH_HAS_DEBUG_VM_PGTABLE
16 select ARCH_HAS_DEVMEM_IS_ALLOWED
17 select ARCH_HAS_DMA_PREP_COHERENT
18 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
19 select ARCH_HAS_FAST_MULTIPLIER
20 select ARCH_HAS_FORTIFY_SOURCE
21 select ARCH_HAS_GCOV_PROFILE_ALL
22 select ARCH_HAS_GIGANTIC_PAGE
24 select ARCH_HAS_KEEPINITRD
25 select ARCH_HAS_MEMBARRIER_SYNC_CORE
26 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
27 select ARCH_HAS_PTE_DEVMAP
28 select ARCH_HAS_PTE_SPECIAL
29 select ARCH_HAS_SETUP_DMA_OPS
30 select ARCH_HAS_SET_DIRECT_MAP
31 select ARCH_HAS_SET_MEMORY
33 select ARCH_HAS_STRICT_KERNEL_RWX
34 select ARCH_HAS_STRICT_MODULE_RWX
35 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
36 select ARCH_HAS_SYNC_DMA_FOR_CPU
37 select ARCH_HAS_SYSCALL_WRAPPER
38 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
39 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
40 select ARCH_HAVE_ELF_PROT
41 select ARCH_HAVE_NMI_SAFE_CMPXCHG
42 select ARCH_INLINE_READ_LOCK if !PREEMPTION
43 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
44 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
45 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION
46 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION
47 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION
48 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION
49 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION
50 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION
51 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION
52 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION
53 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION
54 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION
55 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION
56 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION
57 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION
58 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION
59 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION
60 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION
61 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION
62 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION
63 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION
64 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION
65 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION
66 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION
67 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION
68 select ARCH_KEEP_MEMBLOCK
69 select ARCH_USE_CMPXCHG_LOCKREF
70 select ARCH_USE_GNU_PROPERTY
71 select ARCH_USE_QUEUED_RWLOCKS
72 select ARCH_USE_QUEUED_SPINLOCKS
73 select ARCH_USE_SYM_ANNOTATIONS
74 select ARCH_SUPPORTS_MEMORY_FAILURE
75 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK
76 select ARCH_SUPPORTS_ATOMIC_RMW
77 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 && (GCC_VERSION >= 50000 || CC_IS_CLANG)
78 select ARCH_SUPPORTS_NUMA_BALANCING
79 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
80 select ARCH_WANT_DEFAULT_BPF_JIT
81 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
82 select ARCH_WANT_FRAME_POINTERS
83 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
84 select ARCH_HAS_UBSAN_SANITIZE_ALL
88 select AUDIT_ARCH_COMPAT_GENERIC
89 select ARM_GIC_V2M if PCI
91 select ARM_GIC_V3_ITS if PCI
93 select BUILDTIME_TABLE_SORT
94 select CLONE_BACKWARDS
96 select CPU_PM if (SUSPEND || CPU_IDLE)
98 select DCACHE_WORD_ACCESS
99 select DMA_DIRECT_REMAP
102 select GENERIC_ALLOCATOR
103 select GENERIC_ARCH_TOPOLOGY
104 select GENERIC_CLOCKEVENTS
105 select GENERIC_CLOCKEVENTS_BROADCAST
106 select GENERIC_CPU_AUTOPROBE
107 select GENERIC_CPU_VULNERABILITIES
108 select GENERIC_EARLY_IOREMAP
109 select GENERIC_IDLE_POLL_SETUP
110 select GENERIC_IRQ_IPI
111 select GENERIC_IRQ_MULTI_HANDLER
112 select GENERIC_IRQ_PROBE
113 select GENERIC_IRQ_SHOW
114 select GENERIC_IRQ_SHOW_LEVEL
115 select GENERIC_PCI_IOMAP
116 select GENERIC_PTDUMP
117 select GENERIC_SCHED_CLOCK
118 select GENERIC_SMP_IDLE_THREAD
119 select GENERIC_STRNCPY_FROM_USER
120 select GENERIC_STRNLEN_USER
121 select GENERIC_TIME_VSYSCALL
122 select GENERIC_GETTIMEOFDAY
123 select GENERIC_VDSO_TIME_NS
124 select HANDLE_DOMAIN_IRQ
125 select HARDIRQS_SW_RESEND
127 select HAVE_ACPI_APEI if (ACPI && EFI)
128 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
129 select HAVE_ARCH_AUDITSYSCALL
130 select HAVE_ARCH_BITREVERSE
131 select HAVE_ARCH_COMPILER_H
132 select HAVE_ARCH_HUGE_VMAP
133 select HAVE_ARCH_JUMP_LABEL
134 select HAVE_ARCH_JUMP_LABEL_RELATIVE
135 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
136 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
137 select HAVE_ARCH_KGDB
138 select HAVE_ARCH_MMAP_RND_BITS
139 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
140 select HAVE_ARCH_PREL32_RELOCATIONS
141 select HAVE_ARCH_SECCOMP_FILTER
142 select HAVE_ARCH_STACKLEAK
143 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
144 select HAVE_ARCH_TRACEHOOK
145 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
146 select HAVE_ARCH_VMAP_STACK
147 select HAVE_ARM_SMCCC
148 select HAVE_ASM_MODVERSIONS
150 select HAVE_C_RECORDMCOUNT
151 select HAVE_CMPXCHG_DOUBLE
152 select HAVE_CMPXCHG_LOCAL
153 select HAVE_CONTEXT_TRACKING
154 select HAVE_DEBUG_BUGVERBOSE
155 select HAVE_DEBUG_KMEMLEAK
156 select HAVE_DMA_CONTIGUOUS
157 select HAVE_DYNAMIC_FTRACE
158 select HAVE_DYNAMIC_FTRACE_WITH_REGS \
159 if $(cc-option,-fpatchable-function-entry=2)
160 select HAVE_EFFICIENT_UNALIGNED_ACCESS
162 select HAVE_FTRACE_MCOUNT_RECORD
163 select HAVE_FUNCTION_TRACER
164 select HAVE_FUNCTION_ERROR_INJECTION
165 select HAVE_FUNCTION_GRAPH_TRACER
166 select HAVE_GCC_PLUGINS
167 select HAVE_HW_BREAKPOINT if PERF_EVENTS
168 select HAVE_IRQ_TIME_ACCOUNTING
170 select HAVE_PATA_PLATFORM
171 select HAVE_PERF_EVENTS
172 select HAVE_PERF_REGS
173 select HAVE_PERF_USER_STACK_DUMP
174 select HAVE_REGS_AND_STACK_ACCESS_API
175 select HAVE_FUNCTION_ARG_ACCESS_API
176 select HAVE_FUTEX_CMPXCHG if FUTEX
177 select MMU_GATHER_RCU_TABLE_FREE
179 select HAVE_STACKPROTECTOR
180 select HAVE_SYSCALL_TRACEPOINTS
182 select HAVE_KRETPROBES
183 select HAVE_GENERIC_VDSO
184 select IOMMU_DMA if IOMMU_SUPPORT
186 select IRQ_FORCED_THREADING
187 select MODULES_USE_ELF_RELA
188 select NEED_DMA_MAP_STATE
189 select NEED_SG_DMA_LENGTH
191 select OF_EARLY_FLATTREE
192 select PCI_DOMAINS_GENERIC if PCI
193 select PCI_ECAM if (ACPI && PCI)
194 select PCI_SYSCALL if PCI
199 select SYSCTL_EXCEPTION_TRACE
200 select THREAD_INFO_IN_TASK
202 ARM 64-bit (AArch64) Linux support.
210 config ARM64_PAGE_SHIFT
212 default 16 if ARM64_64K_PAGES
213 default 14 if ARM64_16K_PAGES
216 config ARM64_CONT_PTE_SHIFT
218 default 5 if ARM64_64K_PAGES
219 default 7 if ARM64_16K_PAGES
222 config ARM64_CONT_PMD_SHIFT
224 default 5 if ARM64_64K_PAGES
225 default 5 if ARM64_16K_PAGES
228 config ARCH_MMAP_RND_BITS_MIN
229 default 14 if ARM64_64K_PAGES
230 default 16 if ARM64_16K_PAGES
233 # max bits determined by the following formula:
234 # VA_BITS - PAGE_SHIFT - 3
235 config ARCH_MMAP_RND_BITS_MAX
236 default 19 if ARM64_VA_BITS=36
237 default 24 if ARM64_VA_BITS=39
238 default 27 if ARM64_VA_BITS=42
239 default 30 if ARM64_VA_BITS=47
240 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
241 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
242 default 33 if ARM64_VA_BITS=48
243 default 14 if ARM64_64K_PAGES
244 default 16 if ARM64_16K_PAGES
247 config ARCH_MMAP_RND_COMPAT_BITS_MIN
248 default 7 if ARM64_64K_PAGES
249 default 9 if ARM64_16K_PAGES
252 config ARCH_MMAP_RND_COMPAT_BITS_MAX
258 config STACKTRACE_SUPPORT
261 config ILLEGAL_POINTER_VALUE
263 default 0xdead000000000000
265 config LOCKDEP_SUPPORT
268 config TRACE_IRQFLAGS_SUPPORT
275 config GENERIC_BUG_RELATIVE_POINTERS
277 depends on GENERIC_BUG
279 config GENERIC_HWEIGHT
285 config GENERIC_CALIBRATE_DELAY
289 bool "Support DMA zone" if EXPERT
293 bool "Support DMA32 zone" if EXPERT
296 config ARCH_ENABLE_MEMORY_HOTPLUG
299 config ARCH_ENABLE_MEMORY_HOTREMOVE
305 config KERNEL_MODE_NEON
308 config FIX_EARLYCON_MEM
311 config PGTABLE_LEVELS
313 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
314 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
315 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
316 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
317 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
318 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
320 config ARCH_SUPPORTS_UPROBES
323 config ARCH_PROC_KCORE_TEXT
326 config BROKEN_GAS_INST
327 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
329 config KASAN_SHADOW_OFFSET
332 default 0xdfffa00000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS
333 default 0xdfffd00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
334 default 0xdffffe8000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
335 default 0xdfffffd000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
336 default 0xdffffffa00000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
337 default 0xefff900000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS
338 default 0xefffc80000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
339 default 0xeffffe4000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
340 default 0xefffffc800000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
341 default 0xeffffff900000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
342 default 0xffffffffffffffff
344 source "arch/arm64/Kconfig.platforms"
346 menu "Kernel Features"
348 menu "ARM errata workarounds via the alternatives framework"
350 config ARM64_WORKAROUND_CLEAN_CACHE
353 config ARM64_ERRATUM_826319
354 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
356 select ARM64_WORKAROUND_CLEAN_CACHE
358 This option adds an alternative code sequence to work around ARM
359 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
360 AXI master interface and an L2 cache.
362 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
363 and is unable to accept a certain write via this interface, it will
364 not progress on read data presented on the read data channel and the
367 The workaround promotes data cache clean instructions to
368 data cache clean-and-invalidate.
369 Please note that this does not necessarily enable the workaround,
370 as it depends on the alternative framework, which will only patch
371 the kernel if an affected CPU is detected.
375 config ARM64_ERRATUM_827319
376 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
378 select ARM64_WORKAROUND_CLEAN_CACHE
380 This option adds an alternative code sequence to work around ARM
381 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
382 master interface and an L2 cache.
384 Under certain conditions this erratum can cause a clean line eviction
385 to occur at the same time as another transaction to the same address
386 on the AMBA 5 CHI interface, which can cause data corruption if the
387 interconnect reorders the two transactions.
389 The workaround promotes data cache clean instructions to
390 data cache clean-and-invalidate.
391 Please note that this does not necessarily enable the workaround,
392 as it depends on the alternative framework, which will only patch
393 the kernel if an affected CPU is detected.
397 config ARM64_ERRATUM_824069
398 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
400 select ARM64_WORKAROUND_CLEAN_CACHE
402 This option adds an alternative code sequence to work around ARM
403 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
404 to a coherent interconnect.
406 If a Cortex-A53 processor is executing a store or prefetch for
407 write instruction at the same time as a processor in another
408 cluster is executing a cache maintenance operation to the same
409 address, then this erratum might cause a clean cache line to be
410 incorrectly marked as dirty.
412 The workaround promotes data cache clean instructions to
413 data cache clean-and-invalidate.
414 Please note that this option does not necessarily enable the
415 workaround, as it depends on the alternative framework, which will
416 only patch the kernel if an affected CPU is detected.
420 config ARM64_ERRATUM_819472
421 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
423 select ARM64_WORKAROUND_CLEAN_CACHE
425 This option adds an alternative code sequence to work around ARM
426 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
427 present when it is connected to a coherent interconnect.
429 If the processor is executing a load and store exclusive sequence at
430 the same time as a processor in another cluster is executing a cache
431 maintenance operation to the same address, then this erratum might
432 cause data corruption.
434 The workaround promotes data cache clean instructions to
435 data cache clean-and-invalidate.
436 Please note that this does not necessarily enable the workaround,
437 as it depends on the alternative framework, which will only patch
438 the kernel if an affected CPU is detected.
442 config ARM64_ERRATUM_832075
443 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
446 This option adds an alternative code sequence to work around ARM
447 erratum 832075 on Cortex-A57 parts up to r1p2.
449 Affected Cortex-A57 parts might deadlock when exclusive load/store
450 instructions to Write-Back memory are mixed with Device loads.
452 The workaround is to promote device loads to use Load-Acquire
454 Please note that this does not necessarily enable the workaround,
455 as it depends on the alternative framework, which will only patch
456 the kernel if an affected CPU is detected.
460 config ARM64_ERRATUM_834220
461 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
465 This option adds an alternative code sequence to work around ARM
466 erratum 834220 on Cortex-A57 parts up to r1p2.
468 Affected Cortex-A57 parts might report a Stage 2 translation
469 fault as the result of a Stage 1 fault for load crossing a
470 page boundary when there is a permission or device memory
471 alignment fault at Stage 1 and a translation fault at Stage 2.
473 The workaround is to verify that the Stage 1 translation
474 doesn't generate a fault before handling the Stage 2 fault.
475 Please note that this does not necessarily enable the workaround,
476 as it depends on the alternative framework, which will only patch
477 the kernel if an affected CPU is detected.
481 config ARM64_ERRATUM_845719
482 bool "Cortex-A53: 845719: a load might read incorrect data"
486 This option adds an alternative code sequence to work around ARM
487 erratum 845719 on Cortex-A53 parts up to r0p4.
489 When running a compat (AArch32) userspace on an affected Cortex-A53
490 part, a load at EL0 from a virtual address that matches the bottom 32
491 bits of the virtual address used by a recent load at (AArch64) EL1
492 might return incorrect data.
494 The workaround is to write the contextidr_el1 register on exception
495 return to a 32-bit task.
496 Please note that this does not necessarily enable the workaround,
497 as it depends on the alternative framework, which will only patch
498 the kernel if an affected CPU is detected.
502 config ARM64_ERRATUM_843419
503 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
505 select ARM64_MODULE_PLTS if MODULES
507 This option links the kernel with '--fix-cortex-a53-843419' and
508 enables PLT support to replace certain ADRP instructions, which can
509 cause subsequent memory accesses to use an incorrect address on
510 Cortex-A53 parts up to r0p4.
514 config ARM64_ERRATUM_1024718
515 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
518 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
520 Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
521 update of the hardware dirty bit when the DBM/AP bits are updated
522 without a break-before-make. The workaround is to disable the usage
523 of hardware DBM locally on the affected cores. CPUs not affected by
524 this erratum will continue to use the feature.
528 config ARM64_ERRATUM_1418040
529 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
533 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
534 errata 1188873 and 1418040.
536 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
537 cause register corruption when accessing the timer registers
538 from AArch32 userspace.
542 config ARM64_WORKAROUND_SPECULATIVE_AT
545 config ARM64_ERRATUM_1165522
546 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
548 select ARM64_WORKAROUND_SPECULATIVE_AT
550 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
552 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
553 corrupted TLBs by speculating an AT instruction during a guest
558 config ARM64_ERRATUM_1319367
559 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
561 select ARM64_WORKAROUND_SPECULATIVE_AT
563 This option adds work arounds for ARM Cortex-A57 erratum 1319537
564 and A72 erratum 1319367
566 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
567 speculating an AT instruction during a guest context switch.
571 config ARM64_ERRATUM_1530923
572 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
574 select ARM64_WORKAROUND_SPECULATIVE_AT
576 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
578 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
579 corrupted TLBs by speculating an AT instruction during a guest
584 config ARM64_WORKAROUND_REPEAT_TLBI
587 config ARM64_ERRATUM_1286807
588 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
590 select ARM64_WORKAROUND_REPEAT_TLBI
592 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
594 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
595 address for a cacheable mapping of a location is being
596 accessed by a core while another core is remapping the virtual
597 address to a new physical page using the recommended
598 break-before-make sequence, then under very rare circumstances
599 TLBI+DSB completes before a read using the translation being
600 invalidated has been observed by other observers. The
601 workaround repeats the TLBI+DSB operation.
603 config ARM64_ERRATUM_1463225
604 bool "Cortex-A76: Software Step might prevent interrupt recognition"
607 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
609 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
610 of a system call instruction (SVC) can prevent recognition of
611 subsequent interrupts when software stepping is disabled in the
612 exception handler of the system call and either kernel debugging
613 is enabled or VHE is in use.
615 Work around the erratum by triggering a dummy step exception
616 when handling a system call from a task that is being stepped
617 in a VHE configuration of the kernel.
621 config ARM64_ERRATUM_1542419
622 bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
625 This option adds a workaround for ARM Neoverse-N1 erratum
628 Affected Neoverse-N1 cores could execute a stale instruction when
629 modified by another CPU. The workaround depends on a firmware
632 Workaround the issue by hiding the DIC feature from EL0. This
633 forces user-space to perform cache maintenance.
637 config CAVIUM_ERRATUM_22375
638 bool "Cavium erratum 22375, 24313"
641 Enable workaround for errata 22375 and 24313.
643 This implements two gicv3-its errata workarounds for ThunderX. Both
644 with a small impact affecting only ITS table allocation.
646 erratum 22375: only alloc 8MB table size
647 erratum 24313: ignore memory access type
649 The fixes are in ITS initialization and basically ignore memory access
650 type and table size provided by the TYPER and BASER registers.
654 config CAVIUM_ERRATUM_23144
655 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
659 ITS SYNC command hang for cross node io and collections/cpu mapping.
663 config CAVIUM_ERRATUM_23154
664 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
667 The gicv3 of ThunderX requires a modified version for
668 reading the IAR status to ensure data synchronization
669 (access to icc_iar1_el1 is not sync'ed before and after).
673 config CAVIUM_ERRATUM_27456
674 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
677 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
678 instructions may cause the icache to become corrupted if it
679 contains data for a non-current ASID. The fix is to
680 invalidate the icache when changing the mm context.
684 config CAVIUM_ERRATUM_30115
685 bool "Cavium erratum 30115: Guest may disable interrupts in host"
688 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
689 1.2, and T83 Pass 1.0, KVM guest execution may disable
690 interrupts in host. Trapping both GICv3 group-0 and group-1
691 accesses sidesteps the issue.
695 config CAVIUM_TX2_ERRATUM_219
696 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
699 On Cavium ThunderX2, a load, store or prefetch instruction between a
700 TTBR update and the corresponding context synchronizing operation can
701 cause a spurious Data Abort to be delivered to any hardware thread in
704 Work around the issue by avoiding the problematic code sequence and
705 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
706 trap handler performs the corresponding register access, skips the
707 instruction and ensures context synchronization by virtue of the
712 config FUJITSU_ERRATUM_010001
713 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
716 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
717 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
718 accesses may cause undefined fault (Data abort, DFSC=0b111111).
719 This fault occurs under a specific hardware condition when a
720 load/store instruction performs an address translation using:
721 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
722 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
723 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
724 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
726 The workaround is to ensure these bits are clear in TCR_ELx.
727 The workaround only affects the Fujitsu-A64FX.
731 config HISILICON_ERRATUM_161600802
732 bool "Hip07 161600802: Erroneous redistributor VLPI base"
735 The HiSilicon Hip07 SoC uses the wrong redistributor base
736 when issued ITS commands such as VMOVP and VMAPP, and requires
737 a 128kB offset to be applied to the target address in this commands.
741 config QCOM_FALKOR_ERRATUM_1003
742 bool "Falkor E1003: Incorrect translation due to ASID change"
745 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
746 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
747 in TTBR1_EL1, this situation only occurs in the entry trampoline and
748 then only for entries in the walk cache, since the leaf translation
749 is unchanged. Work around the erratum by invalidating the walk cache
750 entries for the trampoline before entering the kernel proper.
752 config QCOM_FALKOR_ERRATUM_1009
753 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
755 select ARM64_WORKAROUND_REPEAT_TLBI
757 On Falkor v1, the CPU may prematurely complete a DSB following a
758 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
759 one more time to fix the issue.
763 config QCOM_QDF2400_ERRATUM_0065
764 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
767 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
768 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
769 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
773 config QCOM_FALKOR_ERRATUM_E1041
774 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
777 Falkor CPU may speculatively fetch instructions from an improper
778 memory location when MMU translation is changed from SCTLR_ELn[M]=1
779 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
783 config SOCIONEXT_SYNQUACER_PREITS
784 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
787 Socionext Synquacer SoCs implement a separate h/w block to generate
788 MSI doorbell writes with non-zero values for the device ID.
797 default ARM64_4K_PAGES
799 Page size (translation granule) configuration.
801 config ARM64_4K_PAGES
804 This feature enables 4KB pages support.
806 config ARM64_16K_PAGES
809 The system will use 16KB pages support. AArch32 emulation
810 requires applications compiled with 16K (or a multiple of 16K)
813 config ARM64_64K_PAGES
816 This feature enables 64KB pages support (4KB by default)
817 allowing only two levels of page tables and faster TLB
818 look-up. AArch32 emulation requires applications compiled
819 with 64K aligned segments.
824 prompt "Virtual address space size"
825 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
826 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
827 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
829 Allows choosing one of multiple possible virtual address
830 space sizes. The level of translation table is determined by
831 a combination of page size and virtual address space size.
833 config ARM64_VA_BITS_36
834 bool "36-bit" if EXPERT
835 depends on ARM64_16K_PAGES
837 config ARM64_VA_BITS_39
839 depends on ARM64_4K_PAGES
841 config ARM64_VA_BITS_42
843 depends on ARM64_64K_PAGES
845 config ARM64_VA_BITS_47
847 depends on ARM64_16K_PAGES
849 config ARM64_VA_BITS_48
852 config ARM64_VA_BITS_52
854 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
856 Enable 52-bit virtual addressing for userspace when explicitly
857 requested via a hint to mmap(). The kernel will also use 52-bit
858 virtual addresses for its own mappings (provided HW support for
859 this feature is available, otherwise it reverts to 48-bit).
861 NOTE: Enabling 52-bit virtual addressing in conjunction with
862 ARMv8.3 Pointer Authentication will result in the PAC being
863 reduced from 7 bits to 3 bits, which may have a significant
864 impact on its susceptibility to brute-force attacks.
866 If unsure, select 48-bit virtual addressing instead.
870 config ARM64_FORCE_52BIT
871 bool "Force 52-bit virtual addresses for userspace"
872 depends on ARM64_VA_BITS_52 && EXPERT
874 For systems with 52-bit userspace VAs enabled, the kernel will attempt
875 to maintain compatibility with older software by providing 48-bit VAs
876 unless a hint is supplied to mmap.
878 This configuration option disables the 48-bit compatibility logic, and
879 forces all userspace addresses to be 52-bit on HW that supports it. One
880 should only enable this configuration option for stress testing userspace
881 memory management code. If unsure say N here.
885 default 36 if ARM64_VA_BITS_36
886 default 39 if ARM64_VA_BITS_39
887 default 42 if ARM64_VA_BITS_42
888 default 47 if ARM64_VA_BITS_47
889 default 48 if ARM64_VA_BITS_48
890 default 52 if ARM64_VA_BITS_52
893 prompt "Physical address space size"
894 default ARM64_PA_BITS_48
896 Choose the maximum physical address range that the kernel will
899 config ARM64_PA_BITS_48
902 config ARM64_PA_BITS_52
903 bool "52-bit (ARMv8.2)"
904 depends on ARM64_64K_PAGES
905 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
907 Enable support for a 52-bit physical address space, introduced as
908 part of the ARMv8.2-LPA extension.
910 With this enabled, the kernel will also continue to work on CPUs that
911 do not support ARMv8.2-LPA, but with some added memory overhead (and
912 minor performance overhead).
918 default 48 if ARM64_PA_BITS_48
919 default 52 if ARM64_PA_BITS_52
923 default CPU_LITTLE_ENDIAN
925 Select the endianness of data accesses performed by the CPU. Userspace
926 applications will need to be compiled and linked for the endianness
927 that is selected here.
929 config CPU_BIG_ENDIAN
930 bool "Build big-endian kernel"
932 Say Y if you plan on running a kernel with a big-endian userspace.
934 config CPU_LITTLE_ENDIAN
935 bool "Build little-endian kernel"
937 Say Y if you plan on running a kernel with a little-endian userspace.
938 This is usually the case for distributions targeting arm64.
943 bool "Multi-core scheduler support"
945 Multi-core scheduler support improves the CPU scheduler's decision
946 making when dealing with multi-core CPU chips at a cost of slightly
947 increased overhead in some places. If unsure say N here.
950 bool "SMT scheduler support"
952 Improves the CPU scheduler's decision making when dealing with
953 MultiThreading at a cost of slightly increased overhead in some
954 places. If unsure say N here.
957 int "Maximum number of CPUs (2-4096)"
962 bool "Support for hot-pluggable CPUs"
963 select GENERIC_IRQ_MIGRATION
965 Say Y here to experiment with turning CPUs off and on. CPUs
966 can be controlled through /sys/devices/system/cpu.
968 # Common NUMA Features
970 bool "NUMA Memory Allocation and Scheduler Support"
971 select ACPI_NUMA if ACPI
974 Enable NUMA (Non-Uniform Memory Access) support.
976 The kernel will try to allocate memory used by a CPU on the
977 local memory of the CPU and add some more
978 NUMA awareness to the kernel.
981 int "Maximum NUMA Nodes (as a power of 2)"
984 depends on NEED_MULTIPLE_NODES
986 Specify the maximum number of NUMA Nodes available on the target
987 system. Increases memory reserved to accommodate various tables.
989 config USE_PERCPU_NUMA_NODE_ID
993 config HAVE_SETUP_PER_CPU_AREA
997 config NEED_PER_CPU_EMBED_FIRST_CHUNK
1001 config HOLES_IN_ZONE
1004 source "kernel/Kconfig.hz"
1006 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
1009 config ARCH_SPARSEMEM_ENABLE
1011 select SPARSEMEM_VMEMMAP_ENABLE
1013 config ARCH_SPARSEMEM_DEFAULT
1014 def_bool ARCH_SPARSEMEM_ENABLE
1016 config ARCH_SELECT_MEMORY_MODEL
1017 def_bool ARCH_SPARSEMEM_ENABLE
1019 config ARCH_FLATMEM_ENABLE
1022 config HAVE_ARCH_PFN_VALID
1025 config HW_PERF_EVENTS
1029 config SYS_SUPPORTS_HUGETLBFS
1032 config ARCH_WANT_HUGE_PMD_SHARE
1034 config ARCH_HAS_CACHE_LINE_SIZE
1037 config ARCH_ENABLE_SPLIT_PMD_PTLOCK
1038 def_bool y if PGTABLE_LEVELS > 2
1040 # Supported by clang >= 7.0
1041 config CC_HAVE_SHADOW_CALL_STACK
1042 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1045 bool "Enable paravirtualization code"
1047 This changes the kernel so it can modify itself when it is run
1048 under a hypervisor, potentially improving performance significantly
1049 over full virtualization.
1051 config PARAVIRT_TIME_ACCOUNTING
1052 bool "Paravirtual steal time accounting"
1055 Select this option to enable fine granularity task steal time
1056 accounting. Time spent executing other tasks in parallel with
1057 the current vCPU is discounted from the vCPU power. To account for
1058 that, there can be a small performance impact.
1060 If in doubt, say N here.
1063 depends on PM_SLEEP_SMP
1065 bool "kexec system call"
1067 kexec is a system call that implements the ability to shutdown your
1068 current kernel, and to start another kernel. It is like a reboot
1069 but it is independent of the system firmware. And like a reboot
1070 you can start any kernel with it, not just Linux.
1073 bool "kexec file based system call"
1076 This is new version of kexec system call. This system call is
1077 file based and takes file descriptors as system call argument
1078 for kernel and initramfs as opposed to list of segments as
1079 accepted by previous system call.
1082 bool "Verify kernel signature during kexec_file_load() syscall"
1083 depends on KEXEC_FILE
1085 Select this option to verify a signature with loaded kernel
1086 image. If configured, any attempt of loading a image without
1087 valid signature will fail.
1089 In addition to that option, you need to enable signature
1090 verification for the corresponding kernel image type being
1091 loaded in order for this to work.
1093 config KEXEC_IMAGE_VERIFY_SIG
1094 bool "Enable Image signature verification support"
1096 depends on KEXEC_SIG
1097 depends on EFI && SIGNED_PE_FILE_VERIFICATION
1099 Enable Image signature verification support.
1101 comment "Support for PE file signature verification disabled"
1102 depends on KEXEC_SIG
1103 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
1106 bool "Build kdump crash kernel"
1108 Generate crash dump after being started by kexec. This should
1109 be normally only set in special crash dump kernels which are
1110 loaded in the main kernel with kexec-tools into a specially
1111 reserved region and then later executed after a crash by
1114 For more details see Documentation/admin-guide/kdump/kdump.rst
1121 bool "Xen guest support on ARM64"
1122 depends on ARM64 && OF
1126 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1128 config FORCE_MAX_ZONEORDER
1130 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
1131 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
1134 The kernel memory allocator divides physically contiguous memory
1135 blocks into "zones", where each zone is a power of two number of
1136 pages. This option selects the largest power of two that the kernel
1137 keeps in the memory allocator. If you need to allocate very large
1138 blocks of physically contiguous memory, then you may need to
1139 increase this value.
1141 This config option is actually maximum order plus one. For example,
1142 a value of 11 means that the largest free memory block is 2^10 pages.
1144 We make sure that we can allocate upto a HugePage size for each configuration.
1146 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1148 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1149 4M allocations matching the default size used by generic code.
1151 config UNMAP_KERNEL_AT_EL0
1152 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1155 Speculation attacks against some high-performance processors can
1156 be used to bypass MMU permission checks and leak kernel data to
1157 userspace. This can be defended against by unmapping the kernel
1158 when running in userspace, mapping it back in on exception entry
1159 via a trampoline page in the vector table.
1163 config RODATA_FULL_DEFAULT_ENABLED
1164 bool "Apply r/o permissions of VM areas also to their linear aliases"
1167 Apply read-only attributes of VM areas to the linear alias of
1168 the backing pages as well. This prevents code or read-only data
1169 from being modified (inadvertently or intentionally) via another
1170 mapping of the same memory page. This additional enhancement can
1171 be turned off at runtime by passing rodata=[off|on] (and turned on
1172 with rodata=full if this option is set to 'n')
1174 This requires the linear region to be mapped down to pages,
1175 which may adversely affect performance in some cases.
1177 config ARM64_SW_TTBR0_PAN
1178 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1180 Enabling this option prevents the kernel from accessing
1181 user-space memory directly by pointing TTBR0_EL1 to a reserved
1182 zeroed area and reserved ASID. The user access routines
1183 restore the valid TTBR0_EL1 temporarily.
1185 config ARM64_TAGGED_ADDR_ABI
1186 bool "Enable the tagged user addresses syscall ABI"
1189 When this option is enabled, user applications can opt in to a
1190 relaxed ABI via prctl() allowing tagged addresses to be passed
1191 to system calls as pointer arguments. For details, see
1192 Documentation/arm64/tagged-address-abi.rst.
1195 bool "Kernel support for 32-bit EL0"
1196 depends on ARM64_4K_PAGES || EXPERT
1197 select COMPAT_BINFMT_ELF if BINFMT_ELF
1199 select OLD_SIGSUSPEND3
1200 select COMPAT_OLD_SIGACTION
1202 This option enables support for a 32-bit EL0 running under a 64-bit
1203 kernel at EL1. AArch32-specific components such as system calls,
1204 the user helper functions, VFP support and the ptrace interface are
1205 handled appropriately by the kernel.
1207 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1208 that you will only be able to execute AArch32 binaries that were compiled
1209 with page size aligned segments.
1211 If you want to execute 32-bit userspace applications, say Y.
1215 config KUSER_HELPERS
1216 bool "Enable kuser helpers page for 32-bit applications"
1219 Warning: disabling this option may break 32-bit user programs.
1221 Provide kuser helpers to compat tasks. The kernel provides
1222 helper code to userspace in read only form at a fixed location
1223 to allow userspace to be independent of the CPU type fitted to
1224 the system. This permits binaries to be run on ARMv4 through
1225 to ARMv8 without modification.
1227 See Documentation/arm/kernel_user_helpers.rst for details.
1229 However, the fixed address nature of these helpers can be used
1230 by ROP (return orientated programming) authors when creating
1233 If all of the binaries and libraries which run on your platform
1234 are built specifically for your platform, and make no use of
1235 these helpers, then you can turn this option off to hinder
1236 such exploits. However, in that case, if a binary or library
1237 relying on those helpers is run, it will not function correctly.
1239 Say N here only if you are absolutely certain that you do not
1240 need these helpers; otherwise, the safe option is to say Y.
1243 bool "Enable vDSO for 32-bit applications"
1244 depends on !CPU_BIG_ENDIAN && "$(CROSS_COMPILE_COMPAT)" != ""
1245 select GENERIC_COMPAT_VDSO
1248 Place in the process address space of 32-bit applications an
1249 ELF shared object providing fast implementations of gettimeofday
1252 You must have a 32-bit build of glibc 2.22 or later for programs
1253 to seamlessly take advantage of this.
1255 config THUMB2_COMPAT_VDSO
1256 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1257 depends on COMPAT_VDSO
1260 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1261 otherwise with '-marm'.
1263 menuconfig ARMV8_DEPRECATED
1264 bool "Emulate deprecated/obsolete ARMv8 instructions"
1267 Legacy software support may require certain instructions
1268 that have been deprecated or obsoleted in the architecture.
1270 Enable this config to enable selective emulation of these
1277 config SWP_EMULATION
1278 bool "Emulate SWP/SWPB instructions"
1280 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1281 they are always undefined. Say Y here to enable software
1282 emulation of these instructions for userspace using LDXR/STXR.
1283 This feature can be controlled at runtime with the abi.swp
1284 sysctl which is disabled by default.
1286 In some older versions of glibc [<=2.8] SWP is used during futex
1287 trylock() operations with the assumption that the code will not
1288 be preempted. This invalid assumption may be more likely to fail
1289 with SWP emulation enabled, leading to deadlock of the user
1292 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1293 on an external transaction monitoring block called a global
1294 monitor to maintain update atomicity. If your system does not
1295 implement a global monitor, this option can cause programs that
1296 perform SWP operations to uncached memory to deadlock.
1300 config CP15_BARRIER_EMULATION
1301 bool "Emulate CP15 Barrier instructions"
1303 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1304 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1305 strongly recommended to use the ISB, DSB, and DMB
1306 instructions instead.
1308 Say Y here to enable software emulation of these
1309 instructions for AArch32 userspace code. When this option is
1310 enabled, CP15 barrier usage is traced which can help
1311 identify software that needs updating. This feature can be
1312 controlled at runtime with the abi.cp15_barrier sysctl.
1316 config SETEND_EMULATION
1317 bool "Emulate SETEND instruction"
1319 The SETEND instruction alters the data-endianness of the
1320 AArch32 EL0, and is deprecated in ARMv8.
1322 Say Y here to enable software emulation of the instruction
1323 for AArch32 userspace code. This feature can be controlled
1324 at runtime with the abi.setend sysctl.
1326 Note: All the cpus on the system must have mixed endian support at EL0
1327 for this feature to be enabled. If a new CPU - which doesn't support mixed
1328 endian - is hotplugged in after this feature has been enabled, there could
1329 be unexpected results in the applications.
1336 menu "ARMv8.1 architectural features"
1338 config ARM64_HW_AFDBM
1339 bool "Support for hardware updates of the Access and Dirty page flags"
1342 The ARMv8.1 architecture extensions introduce support for
1343 hardware updates of the access and dirty information in page
1344 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1345 capable processors, accesses to pages with PTE_AF cleared will
1346 set this bit instead of raising an access flag fault.
1347 Similarly, writes to read-only pages with the DBM bit set will
1348 clear the read-only bit (AP[2]) instead of raising a
1351 Kernels built with this configuration option enabled continue
1352 to work on pre-ARMv8.1 hardware and the performance impact is
1353 minimal. If unsure, say Y.
1356 bool "Enable support for Privileged Access Never (PAN)"
1359 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1360 prevents the kernel or hypervisor from accessing user-space (EL0)
1363 Choosing this option will cause any unprotected (not using
1364 copy_to_user et al) memory access to fail with a permission fault.
1366 The feature is detected at runtime, and will remain as a 'nop'
1367 instruction if the cpu does not implement the feature.
1369 config ARM64_LSE_ATOMICS
1371 default ARM64_USE_LSE_ATOMICS
1372 depends on $(as-instr,.arch_extension lse)
1374 config ARM64_USE_LSE_ATOMICS
1375 bool "Atomic instructions"
1376 depends on JUMP_LABEL
1379 As part of the Large System Extensions, ARMv8.1 introduces new
1380 atomic instructions that are designed specifically to scale in
1383 Say Y here to make use of these instructions for the in-kernel
1384 atomic routines. This incurs a small overhead on CPUs that do
1385 not support these instructions and requires the kernel to be
1386 built with binutils >= 2.25 in order for the new instructions
1390 bool "Enable support for Virtualization Host Extensions (VHE)"
1393 Virtualization Host Extensions (VHE) allow the kernel to run
1394 directly at EL2 (instead of EL1) on processors that support
1395 it. This leads to better performance for KVM, as they reduce
1396 the cost of the world switch.
1398 Selecting this option allows the VHE feature to be detected
1399 at runtime, and does not affect processors that do not
1400 implement this feature.
1404 menu "ARMv8.2 architectural features"
1407 bool "Enable support for User Access Override (UAO)"
1410 User Access Override (UAO; part of the ARMv8.2 Extensions)
1411 causes the 'unprivileged' variant of the load/store instructions to
1412 be overridden to be privileged.
1414 This option changes get_user() and friends to use the 'unprivileged'
1415 variant of the load/store instructions. This ensures that user-space
1416 really did have access to the supplied memory. When addr_limit is
1417 set to kernel memory the UAO bit will be set, allowing privileged
1418 access to kernel memory.
1420 Choosing this option will cause copy_to_user() et al to use user-space
1423 The feature is detected at runtime, the kernel will use the
1424 regular load/store instructions if the cpu does not implement the
1428 bool "Enable support for persistent memory"
1429 select ARCH_HAS_PMEM_API
1430 select ARCH_HAS_UACCESS_FLUSHCACHE
1432 Say Y to enable support for the persistent memory API based on the
1433 ARMv8.2 DCPoP feature.
1435 The feature is detected at runtime, and the kernel will use DC CVAC
1436 operations if DC CVAP is not supported (following the behaviour of
1437 DC CVAP itself if the system does not define a point of persistence).
1439 config ARM64_RAS_EXTN
1440 bool "Enable support for RAS CPU Extensions"
1443 CPUs that support the Reliability, Availability and Serviceability
1444 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1445 errors, classify them and report them to software.
1447 On CPUs with these extensions system software can use additional
1448 barriers to determine if faults are pending and read the
1449 classification from a new set of registers.
1451 Selecting this feature will allow the kernel to use these barriers
1452 and access the new registers if the system supports the extension.
1453 Platform RAS features may additionally depend on firmware support.
1456 bool "Enable support for Common Not Private (CNP) translations"
1458 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1460 Common Not Private (CNP) allows translation table entries to
1461 be shared between different PEs in the same inner shareable
1462 domain, so the hardware can use this fact to optimise the
1463 caching of such entries in the TLB.
1465 Selecting this option allows the CNP feature to be detected
1466 at runtime, and does not affect PEs that do not implement
1471 menu "ARMv8.3 architectural features"
1473 config ARM64_PTR_AUTH
1474 bool "Enable support for pointer authentication"
1476 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_PAC
1477 # Modern compilers insert a .note.gnu.property section note for PAC
1478 # which is only understood by binutils starting with version 2.33.1.
1479 depends on LD_IS_LLD || LD_VERSION >= 233010000 || (CC_IS_GCC && GCC_VERSION < 90100)
1480 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE
1481 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1483 Pointer authentication (part of the ARMv8.3 Extensions) provides
1484 instructions for signing and authenticating pointers against secret
1485 keys, which can be used to mitigate Return Oriented Programming (ROP)
1488 This option enables these instructions at EL0 (i.e. for userspace).
1489 Choosing this option will cause the kernel to initialise secret keys
1490 for each process at exec() time, with these keys being
1491 context-switched along with the process.
1493 If the compiler supports the -mbranch-protection or
1494 -msign-return-address flag (e.g. GCC 7 or later), then this option
1495 will also cause the kernel itself to be compiled with return address
1496 protection. In this case, and if the target hardware is known to
1497 support pointer authentication, then CONFIG_STACKPROTECTOR can be
1498 disabled with minimal loss of protection.
1500 The feature is detected at runtime. If the feature is not present in
1501 hardware it will not be advertised to userspace/KVM guest nor will it
1504 If the feature is present on the boot CPU but not on a late CPU, then
1505 the late CPU will be parked. Also, if the boot CPU does not have
1506 address auth and the late CPU has then the late CPU will still boot
1507 but with the feature disabled. On such a system, this option should
1510 This feature works with FUNCTION_GRAPH_TRACER option only if
1511 DYNAMIC_FTRACE_WITH_REGS is enabled.
1513 config CC_HAS_BRANCH_PROT_PAC_RET
1514 # GCC 9 or later, clang 8 or later
1515 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1517 config CC_HAS_SIGN_RETURN_ADDRESS
1519 def_bool $(cc-option,-msign-return-address=all)
1522 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
1524 config AS_HAS_CFI_NEGATE_RA_STATE
1525 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
1529 menu "ARMv8.4 architectural features"
1531 config ARM64_AMU_EXTN
1532 bool "Enable support for the Activity Monitors Unit CPU extension"
1535 The activity monitors extension is an optional extension introduced
1536 by the ARMv8.4 CPU architecture. This enables support for version 1
1537 of the activity monitors architecture, AMUv1.
1539 To enable the use of this extension on CPUs that implement it, say Y.
1541 Note that for architectural reasons, firmware _must_ implement AMU
1542 support when running on CPUs that present the activity monitors
1543 extension. The required support is present in:
1544 * Version 1.5 and later of the ARM Trusted Firmware
1546 For kernels that have this configuration enabled but boot with broken
1547 firmware, you may need to say N here until the firmware is fixed.
1548 Otherwise you may experience firmware panics or lockups when
1549 accessing the counter registers. Even if you are not observing these
1550 symptoms, the values returned by the register reads might not
1551 correctly reflect reality. Most commonly, the value read will be 0,
1552 indicating that the counter is not enabled.
1554 config AS_HAS_ARMV8_4
1555 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
1557 config ARM64_TLB_RANGE
1558 bool "Enable support for tlbi range feature"
1560 depends on AS_HAS_ARMV8_4
1562 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
1563 range of input addresses.
1565 The feature introduces new assembly instructions, and they were
1566 support when binutils >= 2.30.
1570 menu "ARMv8.5 architectural features"
1573 bool "Branch Target Identification support"
1576 Branch Target Identification (part of the ARMv8.5 Extensions)
1577 provides a mechanism to limit the set of locations to which computed
1578 branch instructions such as BR or BLR can jump.
1580 To make use of BTI on CPUs that support it, say Y.
1582 BTI is intended to provide complementary protection to other control
1583 flow integrity protection mechanisms, such as the Pointer
1584 authentication mechanism provided as part of the ARMv8.3 Extensions.
1585 For this reason, it does not make sense to enable this option without
1586 also enabling support for pointer authentication. Thus, when
1587 enabling this option you should also select ARM64_PTR_AUTH=y.
1589 Userspace binaries must also be specifically compiled to make use of
1590 this mechanism. If you say N here or the hardware does not support
1591 BTI, such binaries can still run, but you get no additional
1592 enforcement of branch destinations.
1594 config ARM64_BTI_KERNEL
1595 bool "Use Branch Target Identification for kernel"
1597 depends on ARM64_BTI
1598 depends on ARM64_PTR_AUTH
1599 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI
1600 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697
1601 depends on !CC_IS_GCC || GCC_VERSION >= 100100
1602 depends on !(CC_IS_CLANG && GCOV_KERNEL)
1603 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1605 Build the kernel with Branch Target Identification annotations
1606 and enable enforcement of this for kernel code. When this option
1607 is enabled and the system supports BTI all kernel code including
1608 modular code must have BTI enabled.
1610 config CC_HAS_BRANCH_PROT_PAC_RET_BTI
1611 # GCC 9 or later, clang 8 or later
1612 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
1615 bool "Enable support for E0PD"
1618 E0PD (part of the ARMv8.5 extensions) allows us to ensure
1619 that EL0 accesses made via TTBR1 always fault in constant time,
1620 providing similar benefits to KASLR as those provided by KPTI, but
1621 with lower overhead and without disrupting legitimate access to
1622 kernel memory such as SPE.
1624 This option enables E0PD for TTBR1 where available.
1627 bool "Enable support for random number generation"
1630 Random number generation (part of the ARMv8.5 Extensions)
1631 provides a high bandwidth, cryptographically secure
1632 hardware random number generator.
1634 config ARM64_AS_HAS_MTE
1635 # Initial support for MTE went in binutils 2.32.0, checked with
1636 # ".arch armv8.5-a+memtag" below. However, this was incomplete
1637 # as a late addition to the final architecture spec (LDGM/STGM)
1638 # is only supported in the newer 2.32.x and 2.33 binutils
1639 # versions, hence the extra "stgm" instruction check below.
1640 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
1643 bool "Memory Tagging Extension support"
1645 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI
1646 select ARCH_USES_HIGH_VMA_FLAGS
1648 Memory Tagging (part of the ARMv8.5 Extensions) provides
1649 architectural support for run-time, always-on detection of
1650 various classes of memory error to aid with software debugging
1651 to eliminate vulnerabilities arising from memory-unsafe
1654 This option enables the support for the Memory Tagging
1655 Extension at EL0 (i.e. for userspace).
1657 Selecting this option allows the feature to be detected at
1658 runtime. Any secondary CPU not implementing this feature will
1659 not be allowed a late bring-up.
1661 Userspace binaries that want to use this feature must
1662 explicitly opt in. The mechanism for the userspace is
1665 Documentation/arm64/memory-tagging-extension.rst.
1670 bool "ARM Scalable Vector Extension support"
1672 depends on !KVM || ARM64_VHE
1674 The Scalable Vector Extension (SVE) is an extension to the AArch64
1675 execution state which complements and extends the SIMD functionality
1676 of the base architecture to support much larger vectors and to enable
1677 additional vectorisation opportunities.
1679 To enable use of this extension on CPUs that implement it, say Y.
1681 On CPUs that support the SVE2 extensions, this option will enable
1684 Note that for architectural reasons, firmware _must_ implement SVE
1685 support when running on SVE capable hardware. The required support
1688 * version 1.5 and later of the ARM Trusted Firmware
1689 * the AArch64 boot wrapper since commit 5e1261e08abf
1690 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1692 For other firmware implementations, consult the firmware documentation
1695 If you need the kernel to boot on SVE-capable hardware with broken
1696 firmware, you may need to say N here until you get your firmware
1697 fixed. Otherwise, you may experience firmware panics or lockups when
1698 booting the kernel. If unsure and you are not observing these
1699 symptoms, you should assume that it is safe to say Y.
1701 CPUs that support SVE are architecturally required to support the
1702 Virtualization Host Extensions (VHE), so the kernel makes no
1703 provision for supporting SVE alongside KVM without VHE enabled.
1704 Thus, you will need to enable CONFIG_ARM64_VHE if you want to support
1705 KVM in the same kernel image.
1707 config ARM64_MODULE_PLTS
1708 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1710 select HAVE_MOD_ARCH_SPECIFIC
1712 Allocate PLTs when loading modules so that jumps and calls whose
1713 targets are too far away for their relative offsets to be encoded
1714 in the instructions themselves can be bounced via veneers in the
1715 module's PLT. This allows modules to be allocated in the generic
1716 vmalloc area after the dedicated module memory area has been
1719 When running with address space randomization (KASLR), the module
1720 region itself may be too far away for ordinary relative jumps and
1721 calls, and so in that case, module PLTs are required and cannot be
1724 Specific errata workaround(s) might also force module PLTs to be
1725 enabled (ARM64_ERRATUM_843419).
1727 config ARM64_PSEUDO_NMI
1728 bool "Support for NMI-like interrupts"
1731 Adds support for mimicking Non-Maskable Interrupts through the use of
1732 GIC interrupt priority. This support requires version 3 or later of
1735 This high priority configuration for interrupts needs to be
1736 explicitly enabled by setting the kernel parameter
1737 "irqchip.gicv3_pseudo_nmi" to 1.
1742 config ARM64_DEBUG_PRIORITY_MASKING
1743 bool "Debug interrupt priority masking"
1745 This adds runtime checks to functions enabling/disabling
1746 interrupts when using priority masking. The additional checks verify
1747 the validity of ICC_PMR_EL1 when calling concerned functions.
1753 bool "Build a relocatable kernel image" if EXPERT
1754 select ARCH_HAS_RELR
1757 This builds the kernel as a Position Independent Executable (PIE),
1758 which retains all relocation metadata required to relocate the
1759 kernel binary at runtime to a different virtual address than the
1760 address it was linked at.
1761 Since AArch64 uses the RELA relocation format, this requires a
1762 relocation pass at runtime even if the kernel is loaded at the
1763 same address it was linked at.
1765 config RANDOMIZE_BASE
1766 bool "Randomize the address of the kernel image"
1767 select ARM64_MODULE_PLTS if MODULES
1770 Randomizes the virtual address at which the kernel image is
1771 loaded, as a security feature that deters exploit attempts
1772 relying on knowledge of the location of kernel internals.
1774 It is the bootloader's job to provide entropy, by passing a
1775 random u64 value in /chosen/kaslr-seed at kernel entry.
1777 When booting via the UEFI stub, it will invoke the firmware's
1778 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1779 to the kernel proper. In addition, it will randomise the physical
1780 location of the kernel Image as well.
1784 config RANDOMIZE_MODULE_REGION_FULL
1785 bool "Randomize the module region over a 4 GB range"
1786 depends on RANDOMIZE_BASE
1789 Randomizes the location of the module region inside a 4 GB window
1790 covering the core kernel. This way, it is less likely for modules
1791 to leak information about the location of core kernel data structures
1792 but it does imply that function calls between modules and the core
1793 kernel will need to be resolved via veneers in the module PLT.
1795 When this option is not set, the module region will be randomized over
1796 a limited range that contains the [_stext, _etext] interval of the
1797 core kernel, so branch relocations are always in range.
1799 config CC_HAVE_STACKPROTECTOR_SYSREG
1800 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
1802 config STACKPROTECTOR_PER_TASK
1804 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
1810 config ARM64_ACPI_PARKING_PROTOCOL
1811 bool "Enable support for the ARM64 ACPI parking protocol"
1814 Enable support for the ARM64 ACPI parking protocol. If disabled
1815 the kernel will not allow booting through the ARM64 ACPI parking
1816 protocol even if the corresponding data is present in the ACPI
1820 string "Default kernel command string"
1823 Provide a set of default command-line options at build time by
1824 entering them here. As a minimum, you should specify the the
1825 root device (e.g. root=/dev/nfs).
1827 config CMDLINE_FORCE
1828 bool "Always use the default kernel command string"
1829 depends on CMDLINE != ""
1831 Always use the default kernel command string, even if the boot
1832 loader passes other arguments to the kernel.
1833 This is useful if you cannot or don't want to change the
1834 command-line options your boot loader passes to the kernel.
1840 bool "UEFI runtime support"
1841 depends on OF && !CPU_BIG_ENDIAN
1842 depends on KERNEL_MODE_NEON
1843 select ARCH_SUPPORTS_ACPI
1846 select EFI_PARAMS_FROM_FDT
1847 select EFI_RUNTIME_WRAPPERS
1849 select EFI_GENERIC_STUB
1852 This option provides support for runtime services provided
1853 by UEFI firmware (such as non-volatile variables, realtime
1854 clock, and platform reset). A UEFI stub is also provided to
1855 allow the kernel to be booted as an EFI application. This
1856 is only useful on systems that have UEFI firmware.
1859 bool "Enable support for SMBIOS (DMI) tables"
1863 This enables SMBIOS/DMI feature for systems.
1865 This option is only useful on systems that have UEFI firmware.
1866 However, even with this option, the resultant kernel should
1867 continue to boot on existing non-UEFI platforms.
1871 config SYSVIPC_COMPAT
1873 depends on COMPAT && SYSVIPC
1875 config ARCH_ENABLE_HUGEPAGE_MIGRATION
1877 depends on HUGETLB_PAGE && MIGRATION
1879 config ARCH_ENABLE_THP_MIGRATION
1881 depends on TRANSPARENT_HUGEPAGE
1883 menu "Power management options"
1885 source "kernel/power/Kconfig"
1887 config ARCH_HIBERNATION_POSSIBLE
1891 config ARCH_HIBERNATION_HEADER
1893 depends on HIBERNATION
1895 config ARCH_SUSPEND_POSSIBLE
1900 menu "CPU Power Management"
1902 source "drivers/cpuidle/Kconfig"
1904 source "drivers/cpufreq/Kconfig"
1908 source "drivers/firmware/Kconfig"
1910 source "drivers/acpi/Kconfig"
1912 source "arch/arm64/kvm/Kconfig"
1915 source "arch/arm64/crypto/Kconfig"