1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2011-2013 Xilinx Inc.
9 #include <linux/reboot.h>
10 #include <linux/mfd/syscon.h>
11 #include <linux/of_address.h>
12 #include <linux/regmap.h>
15 /* register offsets */
16 #define SLCR_UNLOCK_OFFSET 0x8 /* SCLR unlock register */
17 #define SLCR_PS_RST_CTRL_OFFSET 0x200 /* PS Software Reset Control */
18 #define SLCR_A9_CPU_RST_CTRL_OFFSET 0x244 /* CPU Software Reset Control */
19 #define SLCR_REBOOT_STATUS_OFFSET 0x258 /* PS Reboot Status */
20 #define SLCR_PSS_IDCODE 0x530 /* PS IDCODE */
21 #define SLCR_L2C_RAM 0xA1C /* L2C_RAM in AR#54190 */
23 #define SLCR_UNLOCK_MAGIC 0xDF0D
24 #define SLCR_A9_CPU_CLKSTOP 0x10
25 #define SLCR_A9_CPU_RST 0x1
26 #define SLCR_PSS_IDCODE_DEVICE_SHIFT 12
27 #define SLCR_PSS_IDCODE_DEVICE_MASK 0x1F
29 static void __iomem *zynq_slcr_base;
30 static struct regmap *zynq_slcr_regmap;
33 * zynq_slcr_write - Write to a register in SLCR block
35 * @val: Value to write to the register
36 * @offset: Register offset in SLCR block
38 * Return: a negative value on error, 0 on success
40 static int zynq_slcr_write(u32 val, u32 offset)
42 return regmap_write(zynq_slcr_regmap, offset, val);
46 * zynq_slcr_read - Read a register in SLCR block
48 * @val: Pointer to value to be read from SLCR
49 * @offset: Register offset in SLCR block
51 * Return: a negative value on error, 0 on success
53 static int zynq_slcr_read(u32 *val, u32 offset)
55 return regmap_read(zynq_slcr_regmap, offset, val);
59 * zynq_slcr_unlock - Unlock SLCR registers
61 * Return: a negative value on error, 0 on success
63 static inline int zynq_slcr_unlock(void)
65 zynq_slcr_write(SLCR_UNLOCK_MAGIC, SLCR_UNLOCK_OFFSET);
71 * zynq_slcr_get_device_id - Read device code id
73 * Return: Device code id
75 u32 zynq_slcr_get_device_id(void)
79 zynq_slcr_read(&val, SLCR_PSS_IDCODE);
80 val >>= SLCR_PSS_IDCODE_DEVICE_SHIFT;
81 val &= SLCR_PSS_IDCODE_DEVICE_MASK;
87 * zynq_slcr_system_restart - Restart the entire system.
89 * @nb: Pointer to restart notifier block (unused)
90 * @action: Reboot mode (unused)
91 * @data: Restart handler private data (unused)
96 int zynq_slcr_system_restart(struct notifier_block *nb,
97 unsigned long action, void *data)
102 * Clear 0x0F000000 bits of reboot status register to workaround
103 * the FSBL not loading the bitstream after soft-reboot
104 * This is a temporary solution until we know more.
106 zynq_slcr_read(&reboot, SLCR_REBOOT_STATUS_OFFSET);
107 zynq_slcr_write(reboot & 0xF0FFFFFF, SLCR_REBOOT_STATUS_OFFSET);
108 zynq_slcr_write(1, SLCR_PS_RST_CTRL_OFFSET);
112 static struct notifier_block zynq_slcr_restart_nb = {
113 .notifier_call = zynq_slcr_system_restart,
118 * zynq_slcr_cpu_start - Start cpu
121 void zynq_slcr_cpu_start(int cpu)
125 zynq_slcr_read(®, SLCR_A9_CPU_RST_CTRL_OFFSET);
126 reg &= ~(SLCR_A9_CPU_RST << cpu);
127 zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET);
128 reg &= ~(SLCR_A9_CPU_CLKSTOP << cpu);
129 zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET);
131 zynq_slcr_cpu_state_write(cpu, false);
135 * zynq_slcr_cpu_stop - Stop cpu
138 void zynq_slcr_cpu_stop(int cpu)
142 zynq_slcr_read(®, SLCR_A9_CPU_RST_CTRL_OFFSET);
143 reg |= (SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu;
144 zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET);
148 * zynq_slcr_cpu_state_read - Read cpu state
151 * SLCR_REBOOT_STATUS save upper 2 bits (31/30 cpu states for cpu0 and cpu1)
152 * 0 means cpu is running, 1 cpu is going to die.
154 * Return: true if cpu is running, false if cpu is going to die
156 bool zynq_slcr_cpu_state_read(int cpu)
160 state = readl(zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET);
161 state &= 1 << (31 - cpu);
167 * zynq_slcr_cpu_state_write - Write cpu state
169 * @die: cpu state - true if cpu is going to die
171 * SLCR_REBOOT_STATUS save upper 2 bits (31/30 cpu states for cpu0 and cpu1)
172 * 0 means cpu is running, 1 cpu is going to die.
174 void zynq_slcr_cpu_state_write(int cpu, bool die)
178 state = readl(zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET);
179 mask = 1 << (31 - cpu);
184 writel(state, zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET);
188 * zynq_early_slcr_init - Early slcr init function
190 * Return: 0 on success, negative errno otherwise.
192 * Called very early during boot from platform code to unlock SLCR.
194 int __init zynq_early_slcr_init(void)
196 struct device_node *np;
198 np = of_find_compatible_node(NULL, NULL, "xlnx,zynq-slcr");
200 pr_err("%s: no slcr node found\n", __func__);
204 zynq_slcr_base = of_iomap(np, 0);
205 if (!zynq_slcr_base) {
206 pr_err("%s: Unable to map I/O memory\n", __func__);
210 np->data = (__force void *)zynq_slcr_base;
212 zynq_slcr_regmap = syscon_regmap_lookup_by_compatible("xlnx,zynq-slcr");
213 if (IS_ERR(zynq_slcr_regmap)) {
214 pr_err("%s: failed to find zynq-slcr\n", __func__);
219 /* unlock the SLCR so that registers can be changed */
222 /* See AR#54190 design advisory */
223 regmap_update_bits(zynq_slcr_regmap, SLCR_L2C_RAM, 0x70707, 0x20202);
225 register_restart_handler(&zynq_slcr_restart_nb);
227 pr_info("%pOFn mapped to %p\n", np, zynq_slcr_base);