arch/arm/mach-omap2/omap_hwmod_81xx_data.c

   1 /*
   2  * DM81xx hwmod data.
   3  *
   4  * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
   5  * Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation version 2.
  10  *
  11  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  12  * kind, whether express or implied; without even the implied warranty
  13  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  */
  17
  18 #include <linux/types.h>
  19
  20 #include <linux/platform_data/gpio-omap.h>
  21 #include <linux/platform_data/hsmmc-omap.h>
  22 #include <linux/platform_data/spi-omap2-mcspi.h>
  23 #include <plat/dmtimer.h>
  24
  25 #include "omap_hwmod_common_data.h"
  26 #include "cm81xx.h"
  27 #include "ti81xx.h"
  28 #include "wd_timer.h"
  29
  30 /*
  31  * DM816X hardware modules integration data
  32  *
  33  * Note: This is incomplete and at present, not generated from h/w database.
  34  */
  35
  36 /*
  37  * Common alwon .clkctrl_offs from dm814x TRM "Table 2-278. CM_ALWON REGISTERS"
  38  * also dm816x TRM 18.7.17 CM_ALWON device register values minus 0x1400.
  39  */
  40 #define DM81XX_CM_ALWON_MCASP0_CLKCTRL          0x140
  41 #define DM81XX_CM_ALWON_MCASP1_CLKCTRL          0x144
  42 #define DM81XX_CM_ALWON_MCASP2_CLKCTRL          0x148
  43 #define DM81XX_CM_ALWON_MCBSP_CLKCTRL           0x14c
  44 #define DM81XX_CM_ALWON_UART_0_CLKCTRL          0x150
  45 #define DM81XX_CM_ALWON_UART_1_CLKCTRL          0x154
  46 #define DM81XX_CM_ALWON_UART_2_CLKCTRL          0x158
  47 #define DM81XX_CM_ALWON_GPIO_0_CLKCTRL          0x15c
  48 #define DM81XX_CM_ALWON_GPIO_1_CLKCTRL          0x160
  49 #define DM81XX_CM_ALWON_I2C_0_CLKCTRL           0x164
  50 #define DM81XX_CM_ALWON_I2C_1_CLKCTRL           0x168
  51 #define DM81XX_CM_ALWON_WDTIMER_CLKCTRL         0x18c
  52 #define DM81XX_CM_ALWON_SPI_CLKCTRL             0x190
  53 #define DM81XX_CM_ALWON_MAILBOX_CLKCTRL         0x194
  54 #define DM81XX_CM_ALWON_SPINBOX_CLKCTRL         0x198
  55 #define DM81XX_CM_ALWON_MMUDATA_CLKCTRL         0x19c
  56 #define DM81XX_CM_ALWON_MMUCFG_CLKCTRL          0x1a8
  57 #define DM81XX_CM_ALWON_CONTROL_CLKCTRL         0x1c4
  58 #define DM81XX_CM_ALWON_GPMC_CLKCTRL            0x1d0
  59 #define DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL      0x1d4
  60 #define DM81XX_CM_ALWON_L3_CLKCTRL              0x1e4
  61 #define DM81XX_CM_ALWON_L4HS_CLKCTRL            0x1e8
  62 #define DM81XX_CM_ALWON_L4LS_CLKCTRL            0x1ec
  63 #define DM81XX_CM_ALWON_RTC_CLKCTRL             0x1f0
  64 #define DM81XX_CM_ALWON_TPCC_CLKCTRL            0x1f4
  65 #define DM81XX_CM_ALWON_TPTC0_CLKCTRL           0x1f8
  66 #define DM81XX_CM_ALWON_TPTC1_CLKCTRL           0x1fc
  67 #define DM81XX_CM_ALWON_TPTC2_CLKCTRL           0x200
  68 #define DM81XX_CM_ALWON_TPTC3_CLKCTRL           0x204
  69
  70 /* Registers specific to dm814x */
  71 #define DM814X_CM_ALWON_MCASP_3_4_5_CLKCTRL     0x16c
  72 #define DM814X_CM_ALWON_ATL_CLKCTRL             0x170
  73 #define DM814X_CM_ALWON_MLB_CLKCTRL             0x174
  74 #define DM814X_CM_ALWON_PATA_CLKCTRL            0x178
  75 #define DM814X_CM_ALWON_UART_3_CLKCTRL          0x180
  76 #define DM814X_CM_ALWON_UART_4_CLKCTRL          0x184
  77 #define DM814X_CM_ALWON_UART_5_CLKCTRL          0x188
  78 #define DM814X_CM_ALWON_OCM_0_CLKCTRL           0x1b4
  79 #define DM814X_CM_ALWON_VCP_CLKCTRL             0x1b8
  80 #define DM814X_CM_ALWON_MPU_CLKCTRL             0x1dc
  81 #define DM814X_CM_ALWON_DEBUGSS_CLKCTRL         0x1e0
  82 #define DM814X_CM_ALWON_DCAN_0_1_CLKCTRL        0x218
  83 #define DM814X_CM_ALWON_MMCHS_0_CLKCTRL         0x21c
  84 #define DM814X_CM_ALWON_MMCHS_1_CLKCTRL         0x220
  85 #define DM814X_CM_ALWON_MMCHS_2_CLKCTRL         0x224
  86 #define DM814X_CM_ALWON_CUST_EFUSE_CLKCTRL      0x228
  87
  88 /* Registers specific to dm816x */
  89 #define DM816X_DM_ALWON_BASE            0x1400
  90 #define DM816X_CM_ALWON_TIMER_1_CLKCTRL (0x1570 - DM816X_DM_ALWON_BASE)
  91 #define DM816X_CM_ALWON_TIMER_2_CLKCTRL (0x1574 - DM816X_DM_ALWON_BASE)
  92 #define DM816X_CM_ALWON_TIMER_3_CLKCTRL (0x1578 - DM816X_DM_ALWON_BASE)
  93 #define DM816X_CM_ALWON_TIMER_4_CLKCTRL (0x157c - DM816X_DM_ALWON_BASE)
  94 #define DM816X_CM_ALWON_TIMER_5_CLKCTRL (0x1580 - DM816X_DM_ALWON_BASE)
  95 #define DM816X_CM_ALWON_TIMER_6_CLKCTRL (0x1584 - DM816X_DM_ALWON_BASE)
  96 #define DM816X_CM_ALWON_TIMER_7_CLKCTRL (0x1588 - DM816X_DM_ALWON_BASE)
  97 #define DM816X_CM_ALWON_SDIO_CLKCTRL    (0x15b0 - DM816X_DM_ALWON_BASE)
  98 #define DM816X_CM_ALWON_OCMC_0_CLKCTRL  (0x15b4 - DM816X_DM_ALWON_BASE)
  99 #define DM816X_CM_ALWON_OCMC_1_CLKCTRL  (0x15b8 - DM816X_DM_ALWON_BASE)
 100 #define DM816X_CM_ALWON_ETHERNET_1_CLKCTRL (0x15d8 - DM816X_DM_ALWON_BASE)
 101 #define DM816X_CM_ALWON_MPU_CLKCTRL     (0x15dc - DM816X_DM_ALWON_BASE)
 102 #define DM816X_CM_ALWON_SR_0_CLKCTRL    (0x1608 - DM816X_DM_ALWON_BASE)
 103 #define DM816X_CM_ALWON_SR_1_CLKCTRL    (0x160c - DM816X_DM_ALWON_BASE)
 104
 105 /*
 106  * The default .clkctrl_offs field is offset from CM_DEFAULT, that's
 107  * TRM 18.7.6 CM_DEFAULT device register values minus 0x500
 108  */
 109 #define DM81XX_CM_DEFAULT_OFFSET        0x500
 110 #define DM81XX_CM_DEFAULT_USB_CLKCTRL   (0x558 - DM81XX_CM_DEFAULT_OFFSET)
 111 #define DM81XX_CM_DEFAULT_SATA_CLKCTRL  (0x560 - DM81XX_CM_DEFAULT_OFFSET)
 112
 113 /* L3 Interconnect entries clocked at 125, 250 and 500MHz */
 114 static struct omap_hwmod dm81xx_alwon_l3_slow_hwmod = {
 115         .name           = "alwon_l3_slow",
 116         .clkdm_name     = "alwon_l3s_clkdm",
 117         .class          = &l3_hwmod_class,
 118         .flags          = HWMOD_NO_IDLEST,
 119 };
 120
 121 static struct omap_hwmod dm81xx_default_l3_slow_hwmod = {
 122         .name           = "default_l3_slow",
 123         .clkdm_name     = "default_l3_slow_clkdm",
 124         .class          = &l3_hwmod_class,
 125         .flags          = HWMOD_NO_IDLEST,
 126 };
 127
 128 static struct omap_hwmod dm81xx_alwon_l3_med_hwmod = {
 129         .name           = "l3_med",
 130         .clkdm_name     = "alwon_l3_med_clkdm",
 131         .class          = &l3_hwmod_class,
 132         .flags          = HWMOD_NO_IDLEST,
 133 };
 134
 135 static struct omap_hwmod dm81xx_alwon_l3_fast_hwmod = {
 136         .name           = "l3_fast",
 137         .clkdm_name     = "alwon_l3_fast_clkdm",
 138         .class          = &l3_hwmod_class,
 139         .flags          = HWMOD_NO_IDLEST,
 140 };
 141
 142 /*
 143  * L4 standard peripherals, see TRM table 1-12 for devices using this.
 144  * See TRM table 1-73 for devices using the 125MHz SYSCLK6 clock.
 145  */
 146 static struct omap_hwmod dm81xx_l4_ls_hwmod = {
 147         .name           = "l4_ls",
 148         .clkdm_name     = "alwon_l3s_clkdm",
 149         .class          = &l4_hwmod_class,
 150         .flags          = HWMOD_NO_IDLEST,
 151 };
 152
 153 /*
 154  * L4 high-speed peripherals. For devices using this, please see the TRM
 155  * table 1-13. On dm816x, only EMAC, MDIO and SATA use this. See also TRM
 156  * table 1-73 for devices using 250MHz SYSCLK5 clock.
 157  */
 158 static struct omap_hwmod dm81xx_l4_hs_hwmod = {
 159         .name           = "l4_hs",
 160         .clkdm_name     = "alwon_l3_med_clkdm",
 161         .class          = &l4_hwmod_class,
 162         .flags          = HWMOD_NO_IDLEST,
 163 };
 164
 165 /* L3 slow -> L4 ls peripheral interface running at 125MHz */
 166 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__l4_ls = {
 167         .master = &dm81xx_alwon_l3_slow_hwmod,
 168         .slave  = &dm81xx_l4_ls_hwmod,
 169         .user   = OCP_USER_MPU,
 170 };
 171
 172 /* L3 med -> L4 fast peripheral interface running at 250MHz */
 173 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__l4_hs = {
 174         .master = &dm81xx_alwon_l3_med_hwmod,
 175         .slave  = &dm81xx_l4_hs_hwmod,
 176         .user   = OCP_USER_MPU,
 177 };
 178
 179 /* MPU */
 180 static struct omap_hwmod dm814x_mpu_hwmod = {
 181         .name           = "mpu",
 182         .clkdm_name     = "alwon_l3s_clkdm",
 183         .class          = &mpu_hwmod_class,
 184         .flags          = HWMOD_INIT_NO_IDLE,
 185         .main_clk       = "mpu_ck",
 186         .prcm           = {
 187                 .omap4 = {
 188                         .clkctrl_offs = DM814X_CM_ALWON_MPU_CLKCTRL,
 189                         .modulemode = MODULEMODE_SWCTRL,
 190                 },
 191         },
 192 };
 193
 194 static struct omap_hwmod_ocp_if dm814x_mpu__alwon_l3_slow = {
 195         .master         = &dm814x_mpu_hwmod,
 196         .slave          = &dm81xx_alwon_l3_slow_hwmod,
 197         .user           = OCP_USER_MPU,
 198 };
 199
 200 /* L3 med peripheral interface running at 200MHz */
 201 static struct omap_hwmod_ocp_if dm814x_mpu__alwon_l3_med = {
 202         .master = &dm814x_mpu_hwmod,
 203         .slave  = &dm81xx_alwon_l3_med_hwmod,
 204         .user   = OCP_USER_MPU,
 205 };
 206
 207 static struct omap_hwmod dm816x_mpu_hwmod = {
 208         .name           = "mpu",
 209         .clkdm_name     = "alwon_mpu_clkdm",
 210         .class          = &mpu_hwmod_class,
 211         .flags          = HWMOD_INIT_NO_IDLE,
 212         .main_clk       = "mpu_ck",
 213         .prcm           = {
 214                 .omap4 = {
 215                         .clkctrl_offs = DM816X_CM_ALWON_MPU_CLKCTRL,
 216                         .modulemode = MODULEMODE_SWCTRL,
 217                 },
 218         },
 219 };
 220
 221 static struct omap_hwmod_ocp_if dm816x_mpu__alwon_l3_slow = {
 222         .master         = &dm816x_mpu_hwmod,
 223         .slave          = &dm81xx_alwon_l3_slow_hwmod,
 224         .user           = OCP_USER_MPU,
 225 };
 226
 227 /* L3 med peripheral interface running at 250MHz */
 228 static struct omap_hwmod_ocp_if dm816x_mpu__alwon_l3_med = {
 229         .master = &dm816x_mpu_hwmod,
 230         .slave  = &dm81xx_alwon_l3_med_hwmod,
 231         .user   = OCP_USER_MPU,
 232 };
 233
 234 /* RTC */
 235 static struct omap_hwmod_class_sysconfig ti81xx_rtc_sysc = {
 236         .rev_offs       = 0x74,
 237         .sysc_offs      = 0x78,
 238         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 239         .idlemodes      = SIDLE_FORCE | SIDLE_NO |
 240                           SIDLE_SMART | SIDLE_SMART_WKUP,
 241         .sysc_fields    = &omap_hwmod_sysc_type3,
 242 };
 243
 244 static struct omap_hwmod_class ti81xx_rtc_hwmod_class = {
 245         .name           = "rtc",
 246         .sysc           = &ti81xx_rtc_sysc,
 247 };
 248
 249 static struct omap_hwmod ti81xx_rtc_hwmod = {
 250         .name           = "rtc",
 251         .class          = &ti81xx_rtc_hwmod_class,
 252         .clkdm_name     = "alwon_l3s_clkdm",
 253         .flags          = HWMOD_NO_IDLEST,
 254         .main_clk       = "sysclk18_ck",
 255         .prcm           = {
 256                 .omap4  = {
 257                         .clkctrl_offs = DM81XX_CM_ALWON_RTC_CLKCTRL,
 258                         .modulemode = MODULEMODE_SWCTRL,
 259                 },
 260         },
 261 };
 262
 263 static struct omap_hwmod_ocp_if ti81xx_l4_ls__rtc = {
 264         .master         = &dm81xx_l4_ls_hwmod,
 265         .slave          = &ti81xx_rtc_hwmod,
 266         .clk            = "sysclk6_ck",
 267         .user           = OCP_USER_MPU,
 268 };
 269
 270 /* UART common */
 271 static struct omap_hwmod_class_sysconfig uart_sysc = {
 272         .rev_offs       = 0x50,
 273         .sysc_offs      = 0x54,
 274         .syss_offs      = 0x58,
 275         .sysc_flags     = SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 276                                 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 277                                 SYSS_HAS_RESET_STATUS,
 278         .idlemodes      = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 279                                 MSTANDBY_SMART_WKUP,
 280         .sysc_fields    = &omap_hwmod_sysc_type1,
 281 };
 282
 283 static struct omap_hwmod_class uart_class = {
 284         .name = "uart",
 285         .sysc = &uart_sysc,
 286 };
 287
 288 static struct omap_hwmod dm81xx_uart1_hwmod = {
 289         .name           = "uart1",
 290         .clkdm_name     = "alwon_l3s_clkdm",
 291         .main_clk       = "sysclk10_ck",
 292         .prcm           = {
 293                 .omap4 = {
 294                         .clkctrl_offs = DM81XX_CM_ALWON_UART_0_CLKCTRL,
 295                         .modulemode = MODULEMODE_SWCTRL,
 296                 },
 297         },
 298         .class          = &uart_class,
 299         .flags          = DEBUG_TI81XXUART1_FLAGS,
 300 };
 301
 302 static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart1 = {
 303         .master         = &dm81xx_l4_ls_hwmod,
 304         .slave          = &dm81xx_uart1_hwmod,
 305         .clk            = "sysclk6_ck",
 306         .user           = OCP_USER_MPU,
 307 };
 308
 309 static struct omap_hwmod dm81xx_uart2_hwmod = {
 310         .name           = "uart2",
 311         .clkdm_name     = "alwon_l3s_clkdm",
 312         .main_clk       = "sysclk10_ck",
 313         .prcm           = {
 314                 .omap4 = {
 315                         .clkctrl_offs = DM81XX_CM_ALWON_UART_1_CLKCTRL,
 316                         .modulemode = MODULEMODE_SWCTRL,
 317                 },
 318         },
 319         .class          = &uart_class,
 320         .flags          = DEBUG_TI81XXUART2_FLAGS,
 321 };
 322
 323 static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart2 = {
 324         .master         = &dm81xx_l4_ls_hwmod,
 325         .slave          = &dm81xx_uart2_hwmod,
 326         .clk            = "sysclk6_ck",
 327         .user           = OCP_USER_MPU,
 328 };
 329
 330 static struct omap_hwmod dm81xx_uart3_hwmod = {
 331         .name           = "uart3",
 332         .clkdm_name     = "alwon_l3s_clkdm",
 333         .main_clk       = "sysclk10_ck",
 334         .prcm           = {
 335                 .omap4 = {
 336                         .clkctrl_offs = DM81XX_CM_ALWON_UART_2_CLKCTRL,
 337                         .modulemode = MODULEMODE_SWCTRL,
 338                 },
 339         },
 340         .class          = &uart_class,
 341         .flags          = DEBUG_TI81XXUART3_FLAGS,
 342 };
 343
 344 static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart3 = {
 345         .master         = &dm81xx_l4_ls_hwmod,
 346         .slave          = &dm81xx_uart3_hwmod,
 347         .clk            = "sysclk6_ck",
 348         .user           = OCP_USER_MPU,
 349 };
 350
 351 static struct omap_hwmod_class_sysconfig wd_timer_sysc = {
 352         .rev_offs       = 0x0,
 353         .sysc_offs      = 0x10,
 354         .syss_offs      = 0x14,
 355         .sysc_flags     = SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
 356                                 SYSS_HAS_RESET_STATUS,
 357         .sysc_fields    = &omap_hwmod_sysc_type1,
 358 };
 359
 360 static struct omap_hwmod_class wd_timer_class = {
 361         .name           = "wd_timer",
 362         .sysc           = &wd_timer_sysc,
 363         .pre_shutdown   = &omap2_wd_timer_disable,
 364         .reset          = &omap2_wd_timer_reset,
 365 };
 366
 367 static struct omap_hwmod dm81xx_wd_timer_hwmod = {
 368         .name           = "wd_timer",
 369         .clkdm_name     = "alwon_l3s_clkdm",
 370         .main_clk       = "sysclk18_ck",
 371         .flags          = HWMOD_NO_IDLEST,
 372         .prcm           = {
 373                 .omap4 = {
 374                         .clkctrl_offs = DM81XX_CM_ALWON_WDTIMER_CLKCTRL,
 375                         .modulemode = MODULEMODE_SWCTRL,
 376                 },
 377         },
 378         .class          = &wd_timer_class,
 379 };
 380
 381 static struct omap_hwmod_ocp_if dm81xx_l4_ls__wd_timer1 = {
 382         .master         = &dm81xx_l4_ls_hwmod,
 383         .slave          = &dm81xx_wd_timer_hwmod,
 384         .clk            = "sysclk6_ck",
 385         .user           = OCP_USER_MPU,
 386 };
 387
 388 /* I2C common */
 389 static struct omap_hwmod_class_sysconfig i2c_sysc = {
 390         .rev_offs       = 0x0,
 391         .sysc_offs      = 0x10,
 392         .syss_offs      = 0x90,
 393         .sysc_flags     = SYSC_HAS_SIDLEMODE |
 394                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 395                                 SYSC_HAS_AUTOIDLE,
 396         .idlemodes      = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
 397         .sysc_fields    = &omap_hwmod_sysc_type1,
 398 };
 399
 400 static struct omap_hwmod_class i2c_class = {
 401         .name = "i2c",
 402         .sysc = &i2c_sysc,
 403 };
 404
 405 static struct omap_hwmod dm81xx_i2c1_hwmod = {
 406         .name           = "i2c1",
 407         .clkdm_name     = "alwon_l3s_clkdm",
 408         .main_clk       = "sysclk10_ck",
 409         .prcm           = {
 410                 .omap4 = {
 411                         .clkctrl_offs = DM81XX_CM_ALWON_I2C_0_CLKCTRL,
 412                         .modulemode = MODULEMODE_SWCTRL,
 413                 },
 414         },
 415         .class          = &i2c_class,
 416 };
 417
 418 static struct omap_hwmod_ocp_if dm81xx_l4_ls__i2c1 = {
 419         .master         = &dm81xx_l4_ls_hwmod,
 420         .slave          = &dm81xx_i2c1_hwmod,
 421         .clk            = "sysclk6_ck",
 422         .user           = OCP_USER_MPU,
 423 };
 424
 425 static struct omap_hwmod dm81xx_i2c2_hwmod = {
 426         .name           = "i2c2",
 427         .clkdm_name     = "alwon_l3s_clkdm",
 428         .main_clk       = "sysclk10_ck",
 429         .prcm           = {
 430                 .omap4 = {
 431                         .clkctrl_offs = DM81XX_CM_ALWON_I2C_1_CLKCTRL,
 432                         .modulemode = MODULEMODE_SWCTRL,
 433                 },
 434         },
 435         .class          = &i2c_class,
 436 };
 437
 438 static struct omap_hwmod_class_sysconfig dm81xx_elm_sysc = {
 439         .rev_offs       = 0x0000,
 440         .sysc_offs      = 0x0010,
 441         .syss_offs      = 0x0014,
 442         .sysc_flags     = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 443                                 SYSC_HAS_SOFTRESET |
 444                                 SYSS_HAS_RESET_STATUS,
 445         .idlemodes      = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
 446         .sysc_fields    = &omap_hwmod_sysc_type1,
 447 };
 448
 449 static struct omap_hwmod_ocp_if dm81xx_l4_ls__i2c2 = {
 450         .master         = &dm81xx_l4_ls_hwmod,
 451         .slave          = &dm81xx_i2c2_hwmod,
 452         .clk            = "sysclk6_ck",
 453         .user           = OCP_USER_MPU,
 454 };
 455
 456 static struct omap_hwmod_class dm81xx_elm_hwmod_class = {
 457         .name = "elm",
 458         .sysc = &dm81xx_elm_sysc,
 459 };
 460
 461 static struct omap_hwmod dm81xx_elm_hwmod = {
 462         .name           = "elm",
 463         .clkdm_name     = "alwon_l3s_clkdm",
 464         .class          = &dm81xx_elm_hwmod_class,
 465         .main_clk       = "sysclk6_ck",
 466 };
 467
 468 static struct omap_hwmod_ocp_if dm81xx_l4_ls__elm = {
 469         .master         = &dm81xx_l4_ls_hwmod,
 470         .slave          = &dm81xx_elm_hwmod,
 471         .clk            = "sysclk6_ck",
 472         .user           = OCP_USER_MPU,
 473 };
 474
 475 static struct omap_hwmod_class_sysconfig dm81xx_gpio_sysc = {
 476         .rev_offs       = 0x0000,
 477         .sysc_offs      = 0x0010,
 478         .syss_offs      = 0x0114,
 479         .sysc_flags     = SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
 480                                 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 481                                 SYSS_HAS_RESET_STATUS,
 482         .idlemodes      = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 483                                 SIDLE_SMART_WKUP,
 484         .sysc_fields    = &omap_hwmod_sysc_type1,
 485 };
 486
 487 static struct omap_hwmod_class dm81xx_gpio_hwmod_class = {
 488         .name   = "gpio",
 489         .sysc   = &dm81xx_gpio_sysc,
 490         .rev    = 2,
 491 };
 492
 493 static struct omap_gpio_dev_attr gpio_dev_attr = {
 494         .bank_width     = 32,
 495         .dbck_flag      = true,
 496 };
 497
 498 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 499         { .role = "dbclk", .clk = "sysclk18_ck" },
 500 };
 501
 502 static struct omap_hwmod dm81xx_gpio1_hwmod = {
 503         .name           = "gpio1",
 504         .clkdm_name     = "alwon_l3s_clkdm",
 505         .class          = &dm81xx_gpio_hwmod_class,
 506         .main_clk       = "sysclk6_ck",
 507         .prcm = {
 508                 .omap4 = {
 509                         .clkctrl_offs = DM81XX_CM_ALWON_GPIO_0_CLKCTRL,
 510                         .modulemode = MODULEMODE_SWCTRL,
 511                 },
 512         },
 513         .opt_clks       = gpio1_opt_clks,
 514         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
 515         .dev_attr       = &gpio_dev_attr,
 516 };
 517
 518 static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio1 = {
 519         .master         = &dm81xx_l4_ls_hwmod,
 520         .slave          = &dm81xx_gpio1_hwmod,
 521         .clk            = "sysclk6_ck",
 522         .user           = OCP_USER_MPU,
 523 };
 524
 525 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 526         { .role = "dbclk", .clk = "sysclk18_ck" },
 527 };
 528
 529 static struct omap_hwmod dm81xx_gpio2_hwmod = {
 530         .name           = "gpio2",
 531         .clkdm_name     = "alwon_l3s_clkdm",
 532         .class          = &dm81xx_gpio_hwmod_class,
 533         .main_clk       = "sysclk6_ck",
 534         .prcm = {
 535                 .omap4 = {
 536                         .clkctrl_offs = DM81XX_CM_ALWON_GPIO_1_CLKCTRL,
 537                         .modulemode = MODULEMODE_SWCTRL,
 538                 },
 539         },
 540         .opt_clks       = gpio2_opt_clks,
 541         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
 542         .dev_attr       = &gpio_dev_attr,
 543 };
 544
 545 static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio2 = {
 546         .master         = &dm81xx_l4_ls_hwmod,
 547         .slave          = &dm81xx_gpio2_hwmod,
 548         .clk            = "sysclk6_ck",
 549         .user           = OCP_USER_MPU,
 550 };
 551
 552 static struct omap_hwmod_class_sysconfig dm81xx_gpmc_sysc = {
 553         .rev_offs       = 0x0,
 554         .sysc_offs      = 0x10,
 555         .syss_offs      = 0x14,
 556         .sysc_flags     = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 557                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS,
 558         .idlemodes      = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
 559         .sysc_fields    = &omap_hwmod_sysc_type1,
 560 };
 561
 562 static struct omap_hwmod_class dm81xx_gpmc_hwmod_class = {
 563         .name   = "gpmc",
 564         .sysc   = &dm81xx_gpmc_sysc,
 565 };
 566
 567 static struct omap_hwmod dm81xx_gpmc_hwmod = {
 568         .name           = "gpmc",
 569         .clkdm_name     = "alwon_l3s_clkdm",
 570         .class          = &dm81xx_gpmc_hwmod_class,
 571         .main_clk       = "sysclk6_ck",
 572         /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
 573         .flags          = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
 574         .prcm = {
 575                 .omap4 = {
 576                         .clkctrl_offs = DM81XX_CM_ALWON_GPMC_CLKCTRL,
 577                         .modulemode = MODULEMODE_SWCTRL,
 578                 },
 579         },
 580 };
 581
 582 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__gpmc = {
 583         .master         = &dm81xx_alwon_l3_slow_hwmod,
 584         .slave          = &dm81xx_gpmc_hwmod,
 585         .user           = OCP_USER_MPU,
 586 };
 587
 588 /* USB needs udelay 1 after reset at least on hp t410, use 2 for margin */
 589 static struct omap_hwmod_class_sysconfig dm81xx_usbhsotg_sysc = {
 590         .rev_offs       = 0x0,
 591         .sysc_offs      = 0x10,
 592         .srst_udelay    = 2,
 593         .sysc_flags     = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
 594                                 SYSC_HAS_SOFTRESET,
 595         .idlemodes      = SIDLE_SMART | MSTANDBY_FORCE | MSTANDBY_SMART,
 596         .sysc_fields    = &omap_hwmod_sysc_type2,
 597 };
 598
 599 static struct omap_hwmod_class dm81xx_usbotg_class = {
 600         .name = "usbotg",
 601         .sysc = &dm81xx_usbhsotg_sysc,
 602 };
 603
 604 static struct omap_hwmod dm814x_usbss_hwmod = {
 605         .name           = "usb_otg_hs",
 606         .clkdm_name     = "default_l3_slow_clkdm",
 607         .main_clk       = "pll260dcoclkldo",    /* 481c5260.adpll.dcoclkldo */
 608         .prcm           = {
 609                 .omap4 = {
 610                         .clkctrl_offs = DM81XX_CM_DEFAULT_USB_CLKCTRL,
 611                         .modulemode = MODULEMODE_SWCTRL,
 612                 },
 613         },
 614         .class          = &dm81xx_usbotg_class,
 615 };
 616
 617 static struct omap_hwmod_ocp_if dm814x_default_l3_slow__usbss = {
 618         .master         = &dm81xx_default_l3_slow_hwmod,
 619         .slave          = &dm814x_usbss_hwmod,
 620         .clk            = "sysclk6_ck",
 621         .user           = OCP_USER_MPU,
 622 };
 623
 624 static struct omap_hwmod dm816x_usbss_hwmod = {
 625         .name           = "usb_otg_hs",
 626         .clkdm_name     = "default_l3_slow_clkdm",
 627         .main_clk       = "sysclk6_ck",
 628         .prcm           = {
 629                 .omap4 = {
 630                         .clkctrl_offs = DM81XX_CM_DEFAULT_USB_CLKCTRL,
 631                         .modulemode = MODULEMODE_SWCTRL,
 632                 },
 633         },
 634         .class          = &dm81xx_usbotg_class,
 635 };
 636
 637 static struct omap_hwmod_ocp_if dm816x_default_l3_slow__usbss = {
 638         .master         = &dm81xx_default_l3_slow_hwmod,
 639         .slave          = &dm816x_usbss_hwmod,
 640         .clk            = "sysclk6_ck",
 641         .user           = OCP_USER_MPU,
 642 };
 643
 644 static struct omap_hwmod_class_sysconfig dm816x_timer_sysc = {
 645         .rev_offs       = 0x0000,
 646         .sysc_offs      = 0x0010,
 647         .syss_offs      = 0x0014,
 648         .sysc_flags     = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET,
 649         .idlemodes      = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 650                                 SIDLE_SMART_WKUP,
 651         .sysc_fields    = &omap_hwmod_sysc_type2,
 652 };
 653
 654 static struct omap_hwmod_class dm816x_timer_hwmod_class = {
 655         .name = "timer",
 656         .sysc = &dm816x_timer_sysc,
 657 };
 658
 659 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
 660         .timer_capability       = OMAP_TIMER_ALWON,
 661 };
 662
 663 static struct omap_hwmod dm814x_timer1_hwmod = {
 664         .name           = "timer1",
 665         .clkdm_name     = "alwon_l3s_clkdm",
 666         .main_clk       = "timer1_fck",
 667         .dev_attr       = &capability_alwon_dev_attr,
 668         .class          = &dm816x_timer_hwmod_class,
 669         .flags          = HWMOD_NO_IDLEST,
 670 };
 671
 672 static struct omap_hwmod_ocp_if dm814x_l4_ls__timer1 = {
 673         .master         = &dm81xx_l4_ls_hwmod,
 674         .slave          = &dm814x_timer1_hwmod,
 675         .clk            = "sysclk6_ck",
 676         .user           = OCP_USER_MPU,
 677 };
 678
 679 static struct omap_hwmod dm816x_timer1_hwmod = {
 680         .name           = "timer1",
 681         .clkdm_name     = "alwon_l3s_clkdm",
 682         .main_clk       = "timer1_fck",
 683         .prcm           = {
 684                 .omap4 = {
 685                         .clkctrl_offs = DM816X_CM_ALWON_TIMER_1_CLKCTRL,
 686                         .modulemode = MODULEMODE_SWCTRL,
 687                 },
 688         },
 689         .dev_attr       = &capability_alwon_dev_attr,
 690         .class          = &dm816x_timer_hwmod_class,
 691 };
 692
 693 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer1 = {
 694         .master         = &dm81xx_l4_ls_hwmod,
 695         .slave          = &dm816x_timer1_hwmod,
 696         .clk            = "sysclk6_ck",
 697         .user           = OCP_USER_MPU,
 698 };
 699
 700 static struct omap_hwmod dm814x_timer2_hwmod = {
 701         .name           = "timer2",
 702         .clkdm_name     = "alwon_l3s_clkdm",
 703         .main_clk       = "timer2_fck",
 704         .dev_attr       = &capability_alwon_dev_attr,
 705         .class          = &dm816x_timer_hwmod_class,
 706         .flags          = HWMOD_NO_IDLEST,
 707 };
 708
 709 static struct omap_hwmod_ocp_if dm814x_l4_ls__timer2 = {
 710         .master         = &dm81xx_l4_ls_hwmod,
 711         .slave          = &dm814x_timer2_hwmod,
 712         .clk            = "sysclk6_ck",
 713         .user           = OCP_USER_MPU,
 714 };
 715
 716 static struct omap_hwmod dm816x_timer2_hwmod = {
 717         .name           = "timer2",
 718         .clkdm_name     = "alwon_l3s_clkdm",
 719         .main_clk       = "timer2_fck",
 720         .prcm           = {
 721                 .omap4 = {
 722                         .clkctrl_offs = DM816X_CM_ALWON_TIMER_2_CLKCTRL,
 723                         .modulemode = MODULEMODE_SWCTRL,
 724                 },
 725         },
 726         .dev_attr       = &capability_alwon_dev_attr,
 727         .class          = &dm816x_timer_hwmod_class,
 728 };
 729
 730 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer2 = {
 731         .master         = &dm81xx_l4_ls_hwmod,
 732         .slave          = &dm816x_timer2_hwmod,
 733         .clk            = "sysclk6_ck",
 734         .user           = OCP_USER_MPU,
 735 };
 736
 737 static struct omap_hwmod dm816x_timer3_hwmod = {
 738         .name           = "timer3",
 739         .clkdm_name     = "alwon_l3s_clkdm",
 740         .main_clk       = "timer3_fck",
 741         .prcm           = {
 742                 .omap4 = {
 743                         .clkctrl_offs = DM816X_CM_ALWON_TIMER_3_CLKCTRL,
 744                         .modulemode = MODULEMODE_SWCTRL,
 745                 },
 746         },
 747         .dev_attr       = &capability_alwon_dev_attr,
 748         .class          = &dm816x_timer_hwmod_class,
 749 };
 750
 751 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer3 = {
 752         .master         = &dm81xx_l4_ls_hwmod,
 753         .slave          = &dm816x_timer3_hwmod,
 754         .clk            = "sysclk6_ck",
 755         .user           = OCP_USER_MPU,
 756 };
 757
 758 static struct omap_hwmod dm816x_timer4_hwmod = {
 759         .name           = "timer4",
 760         .clkdm_name     = "alwon_l3s_clkdm",
 761         .main_clk       = "timer4_fck",
 762         .prcm           = {
 763                 .omap4 = {
 764                         .clkctrl_offs = DM816X_CM_ALWON_TIMER_4_CLKCTRL,
 765                         .modulemode = MODULEMODE_SWCTRL,
 766                 },
 767         },
 768         .dev_attr       = &capability_alwon_dev_attr,
 769         .class          = &dm816x_timer_hwmod_class,
 770 };
 771
 772 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer4 = {
 773         .master         = &dm81xx_l4_ls_hwmod,
 774         .slave          = &dm816x_timer4_hwmod,
 775         .clk            = "sysclk6_ck",
 776         .user           = OCP_USER_MPU,
 777 };
 778
 779 static struct omap_hwmod dm816x_timer5_hwmod = {
 780         .name           = "timer5",
 781         .clkdm_name     = "alwon_l3s_clkdm",
 782         .main_clk       = "timer5_fck",
 783         .prcm           = {
 784                 .omap4 = {
 785                         .clkctrl_offs = DM816X_CM_ALWON_TIMER_5_CLKCTRL,
 786                         .modulemode = MODULEMODE_SWCTRL,
 787                 },
 788         },
 789         .dev_attr       = &capability_alwon_dev_attr,
 790         .class          = &dm816x_timer_hwmod_class,
 791 };
 792
 793 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer5 = {
 794         .master         = &dm81xx_l4_ls_hwmod,
 795         .slave          = &dm816x_timer5_hwmod,
 796         .clk            = "sysclk6_ck",
 797         .user           = OCP_USER_MPU,
 798 };
 799
 800 static struct omap_hwmod dm816x_timer6_hwmod = {
 801         .name           = "timer6",
 802         .clkdm_name     = "alwon_l3s_clkdm",
 803         .main_clk       = "timer6_fck",
 804         .prcm           = {
 805                 .omap4 = {
 806                         .clkctrl_offs = DM816X_CM_ALWON_TIMER_6_CLKCTRL,
 807                         .modulemode = MODULEMODE_SWCTRL,
 808                 },
 809         },
 810         .dev_attr       = &capability_alwon_dev_attr,
 811         .class          = &dm816x_timer_hwmod_class,
 812 };
 813
 814 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer6 = {
 815         .master         = &dm81xx_l4_ls_hwmod,
 816         .slave          = &dm816x_timer6_hwmod,
 817         .clk            = "sysclk6_ck",
 818         .user           = OCP_USER_MPU,
 819 };
 820
 821 static struct omap_hwmod dm816x_timer7_hwmod = {
 822         .name           = "timer7",
 823         .clkdm_name     = "alwon_l3s_clkdm",
 824         .main_clk       = "timer7_fck",
 825         .prcm           = {
 826                 .omap4 = {
 827                         .clkctrl_offs = DM816X_CM_ALWON_TIMER_7_CLKCTRL,
 828                         .modulemode = MODULEMODE_SWCTRL,
 829                 },
 830         },
 831         .dev_attr       = &capability_alwon_dev_attr,
 832         .class          = &dm816x_timer_hwmod_class,
 833 };
 834
 835 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer7 = {
 836         .master         = &dm81xx_l4_ls_hwmod,
 837         .slave          = &dm816x_timer7_hwmod,
 838         .clk            = "sysclk6_ck",
 839         .user           = OCP_USER_MPU,
 840 };
 841
 842 /* CPSW on dm814x */
 843 static struct omap_hwmod_class_sysconfig dm814x_cpgmac_sysc = {
 844         .rev_offs       = 0x0,
 845         .sysc_offs      = 0x8,
 846         .syss_offs      = 0x4,
 847         .sysc_flags     = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
 848                           SYSS_HAS_RESET_STATUS,
 849         .idlemodes      = SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
 850                           MSTANDBY_NO,
 851         .sysc_fields    = &omap_hwmod_sysc_type3,
 852 };
 853
 854 static struct omap_hwmod_class dm814x_cpgmac0_hwmod_class = {
 855         .name           = "cpgmac0",
 856         .sysc           = &dm814x_cpgmac_sysc,
 857 };
 858
 859 static struct omap_hwmod dm814x_cpgmac0_hwmod = {
 860         .name           = "cpgmac0",
 861         .class          = &dm814x_cpgmac0_hwmod_class,
 862         .clkdm_name     = "alwon_ethernet_clkdm",
 863         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
 864         .main_clk       = "cpsw_125mhz_gclk",
 865         .prcm           = {
 866                 .omap4  = {
 867                         .clkctrl_offs = DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL,
 868                         .modulemode = MODULEMODE_SWCTRL,
 869                 },
 870         },
 871 };
 872
 873 static struct omap_hwmod_class dm814x_mdio_hwmod_class = {
 874         .name           = "davinci_mdio",
 875 };
 876
 877 static struct omap_hwmod dm814x_mdio_hwmod = {
 878         .name           = "davinci_mdio",
 879         .class          = &dm814x_mdio_hwmod_class,
 880         .clkdm_name     = "alwon_ethernet_clkdm",
 881         .main_clk       = "cpsw_125mhz_gclk",
 882 };
 883
 884 static struct omap_hwmod_ocp_if dm814x_l4_hs__cpgmac0 = {
 885         .master         = &dm81xx_l4_hs_hwmod,
 886         .slave          = &dm814x_cpgmac0_hwmod,
 887         .clk            = "cpsw_125mhz_gclk",
 888         .user           = OCP_USER_MPU,
 889 };
 890
 891 static struct omap_hwmod_ocp_if dm814x_cpgmac0__mdio = {
 892         .master         = &dm814x_cpgmac0_hwmod,
 893         .slave          = &dm814x_mdio_hwmod,
 894         .user           = OCP_USER_MPU,
 895         .flags          = HWMOD_NO_IDLEST,
 896 };
 897
 898 /* EMAC Ethernet */
 899 static struct omap_hwmod_class_sysconfig dm816x_emac_sysc = {
 900         .rev_offs       = 0x0,
 901         .sysc_offs      = 0x4,
 902         .sysc_flags     = SYSC_HAS_SOFTRESET,
 903         .sysc_fields    = &omap_hwmod_sysc_type2,
 904 };
 905
 906 static struct omap_hwmod_class dm816x_emac_hwmod_class = {
 907         .name           = "emac",
 908         .sysc           = &dm816x_emac_sysc,
 909 };
 910
 911 /*
 912  * On dm816x the MDIO is within EMAC0. As the MDIO driver is a separate
 913  * driver probed before EMAC0, we let MDIO do the clock idling.
 914  */
 915 static struct omap_hwmod dm816x_emac0_hwmod = {
 916         .name           = "emac0",
 917         .clkdm_name     = "alwon_ethernet_clkdm",
 918         .class          = &dm816x_emac_hwmod_class,
 919         .flags          = HWMOD_NO_IDLEST,
 920 };
 921
 922 static struct omap_hwmod_ocp_if dm81xx_l4_hs__emac0 = {
 923         .master         = &dm81xx_l4_hs_hwmod,
 924         .slave          = &dm816x_emac0_hwmod,
 925         .clk            = "sysclk5_ck",
 926         .user           = OCP_USER_MPU,
 927 };
 928
 929 static struct omap_hwmod_class dm81xx_mdio_hwmod_class = {
 930         .name           = "davinci_mdio",
 931         .sysc           = &dm816x_emac_sysc,
 932 };
 933
 934 static struct omap_hwmod dm81xx_emac0_mdio_hwmod = {
 935         .name           = "davinci_mdio",
 936         .class          = &dm81xx_mdio_hwmod_class,
 937         .clkdm_name     = "alwon_ethernet_clkdm",
 938         .main_clk       = "sysclk24_ck",
 939         .flags          = HWMOD_NO_IDLEST,
 940         /*
 941          * REVISIT: This should be moved to the emac0_hwmod
 942          * once we have a better way to handle device slaves.
 943          */
 944         .prcm           = {
 945                 .omap4 = {
 946                         .clkctrl_offs = DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL,
 947                         .modulemode = MODULEMODE_SWCTRL,
 948                 },
 949         },
 950 };
 951
 952 static struct omap_hwmod_ocp_if dm81xx_emac0__mdio = {
 953         .master         = &dm81xx_l4_hs_hwmod,
 954         .slave          = &dm81xx_emac0_mdio_hwmod,
 955         .user           = OCP_USER_MPU,
 956 };
 957
 958 static struct omap_hwmod dm816x_emac1_hwmod = {
 959         .name           = "emac1",
 960         .clkdm_name     = "alwon_ethernet_clkdm",
 961         .main_clk       = "sysclk24_ck",
 962         .flags          = HWMOD_NO_IDLEST,
 963         .prcm           = {
 964                 .omap4 = {
 965                         .clkctrl_offs = DM816X_CM_ALWON_ETHERNET_1_CLKCTRL,
 966                         .modulemode = MODULEMODE_SWCTRL,
 967                 },
 968         },
 969         .class          = &dm816x_emac_hwmod_class,
 970 };
 971
 972 static struct omap_hwmod_ocp_if dm816x_l4_hs__emac1 = {
 973         .master         = &dm81xx_l4_hs_hwmod,
 974         .slave          = &dm816x_emac1_hwmod,
 975         .clk            = "sysclk5_ck",
 976         .user           = OCP_USER_MPU,
 977 };
 978
 979 static struct omap_hwmod_class_sysconfig dm81xx_sata_sysc = {
 980         .sysc_offs      = 0x1100,
 981         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 982         .idlemodes      = SIDLE_FORCE,
 983         .sysc_fields    = &omap_hwmod_sysc_type3,
 984 };
 985
 986 static struct omap_hwmod_class dm81xx_sata_hwmod_class = {
 987         .name   = "sata",
 988         .sysc   = &dm81xx_sata_sysc,
 989 };
 990
 991 static struct omap_hwmod dm81xx_sata_hwmod = {
 992         .name           = "sata",
 993         .clkdm_name     = "default_clkdm",
 994         .flags          = HWMOD_NO_IDLEST,
 995         .prcm = {
 996                 .omap4 = {
 997                         .clkctrl_offs = DM81XX_CM_DEFAULT_SATA_CLKCTRL,
 998                         .modulemode   = MODULEMODE_SWCTRL,
 999                 },
1000         },
1001         .class          = &dm81xx_sata_hwmod_class,
1002 };
1003
1004 static struct omap_hwmod_ocp_if dm81xx_l4_hs__sata = {
1005         .master         = &dm81xx_l4_hs_hwmod,
1006         .slave          = &dm81xx_sata_hwmod,
1007         .clk            = "sysclk5_ck",
1008         .user           = OCP_USER_MPU,
1009 };
1010
1011 static struct omap_hwmod_class_sysconfig dm81xx_mmc_sysc = {
1012         .rev_offs       = 0x0,
1013         .sysc_offs      = 0x110,
1014         .syss_offs      = 0x114,
1015         .sysc_flags     = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1016                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1017                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS,
1018         .idlemodes      = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
1019         .sysc_fields    = &omap_hwmod_sysc_type1,
1020 };
1021
1022 static struct omap_hwmod_class dm81xx_mmc_class = {
1023         .name = "mmc",
1024         .sysc = &dm81xx_mmc_sysc,
1025 };
1026
1027 static struct omap_hwmod_opt_clk dm81xx_mmc_opt_clks[] = {
1028         { .role = "dbck", .clk = "sysclk18_ck", },
1029 };
1030
1031 static struct omap_hsmmc_dev_attr mmc_dev_attr = {
1032 };
1033
1034 static struct omap_hwmod dm814x_mmc1_hwmod = {
1035         .name           = "mmc1",
1036         .clkdm_name     = "alwon_l3s_clkdm",
1037         .opt_clks       = dm81xx_mmc_opt_clks,
1038         .opt_clks_cnt   = ARRAY_SIZE(dm81xx_mmc_opt_clks),
1039         .main_clk       = "sysclk8_ck",
1040         .prcm           = {
1041                 .omap4 = {
1042                         .clkctrl_offs = DM814X_CM_ALWON_MMCHS_0_CLKCTRL,
1043                         .modulemode = MODULEMODE_SWCTRL,
1044                 },
1045         },
1046         .dev_attr       = &mmc_dev_attr,
1047         .class          = &dm81xx_mmc_class,
1048 };
1049
1050 static struct omap_hwmod_ocp_if dm814x_l4_ls__mmc1 = {
1051         .master         = &dm81xx_l4_ls_hwmod,
1052         .slave          = &dm814x_mmc1_hwmod,
1053         .clk            = "sysclk6_ck",
1054         .user           = OCP_USER_MPU,
1055         .flags          = OMAP_FIREWALL_L4
1056 };
1057
1058 static struct omap_hwmod dm814x_mmc2_hwmod = {
1059         .name           = "mmc2",
1060         .clkdm_name     = "alwon_l3s_clkdm",
1061         .opt_clks       = dm81xx_mmc_opt_clks,
1062         .opt_clks_cnt   = ARRAY_SIZE(dm81xx_mmc_opt_clks),
1063         .main_clk       = "sysclk8_ck",
1064         .prcm           = {
1065                 .omap4 = {
1066                         .clkctrl_offs = DM814X_CM_ALWON_MMCHS_1_CLKCTRL,
1067                         .modulemode = MODULEMODE_SWCTRL,
1068                 },
1069         },
1070         .dev_attr       = &mmc_dev_attr,
1071         .class          = &dm81xx_mmc_class,
1072 };
1073
1074 static struct omap_hwmod_ocp_if dm814x_l4_ls__mmc2 = {
1075         .master         = &dm81xx_l4_ls_hwmod,
1076         .slave          = &dm814x_mmc2_hwmod,
1077         .clk            = "sysclk6_ck",
1078         .user           = OCP_USER_MPU,
1079         .flags          = OMAP_FIREWALL_L4
1080 };
1081
1082 static struct omap_hwmod dm814x_mmc3_hwmod = {
1083         .name           = "mmc3",
1084         .clkdm_name     = "alwon_l3_med_clkdm",
1085         .opt_clks       = dm81xx_mmc_opt_clks,
1086         .opt_clks_cnt   = ARRAY_SIZE(dm81xx_mmc_opt_clks),
1087         .main_clk       = "sysclk8_ck",
1088         .prcm           = {
1089                 .omap4 = {
1090                         .clkctrl_offs = DM814X_CM_ALWON_MMCHS_2_CLKCTRL,
1091                         .modulemode = MODULEMODE_SWCTRL,
1092                 },
1093         },
1094         .dev_attr       = &mmc_dev_attr,
1095         .class          = &dm81xx_mmc_class,
1096 };
1097
1098 static struct omap_hwmod_ocp_if dm814x_alwon_l3_med__mmc3 = {
1099         .master         = &dm81xx_alwon_l3_med_hwmod,
1100         .slave          = &dm814x_mmc3_hwmod,
1101         .clk            = "sysclk4_ck",
1102         .user           = OCP_USER_MPU,
1103 };
1104
1105 static struct omap_hwmod dm816x_mmc1_hwmod = {
1106         .name           = "mmc1",
1107         .clkdm_name     = "alwon_l3s_clkdm",
1108         .opt_clks       = dm81xx_mmc_opt_clks,
1109         .opt_clks_cnt   = ARRAY_SIZE(dm81xx_mmc_opt_clks),
1110         .main_clk       = "sysclk10_ck",
1111         .prcm           = {
1112                 .omap4 = {
1113                         .clkctrl_offs = DM816X_CM_ALWON_SDIO_CLKCTRL,
1114                         .modulemode = MODULEMODE_SWCTRL,
1115                 },
1116         },
1117         .dev_attr       = &mmc_dev_attr,
1118         .class          = &dm81xx_mmc_class,
1119 };
1120
1121 static struct omap_hwmod_ocp_if dm816x_l4_ls__mmc1 = {
1122         .master         = &dm81xx_l4_ls_hwmod,
1123         .slave          = &dm816x_mmc1_hwmod,
1124         .clk            = "sysclk6_ck",
1125         .user           = OCP_USER_MPU,
1126         .flags          = OMAP_FIREWALL_L4
1127 };
1128
1129 static struct omap_hwmod_class_sysconfig dm816x_mcspi_sysc = {
1130         .rev_offs       = 0x0,
1131         .sysc_offs      = 0x110,
1132         .syss_offs      = 0x114,
1133         .sysc_flags     = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1134                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1135                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS,
1136         .idlemodes      = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
1137         .sysc_fields    = &omap_hwmod_sysc_type1,
1138 };
1139
1140 static struct omap_hwmod_class dm816x_mcspi_class = {
1141         .name = "mcspi",
1142         .sysc = &dm816x_mcspi_sysc,
1143         .rev = OMAP3_MCSPI_REV,
1144 };
1145
1146 static struct omap2_mcspi_dev_attr dm816x_mcspi1_dev_attr = {
1147         .num_chipselect = 4,
1148 };
1149
1150 static struct omap_hwmod dm81xx_mcspi1_hwmod = {
1151         .name           = "mcspi1",
1152         .clkdm_name     = "alwon_l3s_clkdm",
1153         .main_clk       = "sysclk10_ck",
1154         .prcm           = {
1155                 .omap4 = {
1156                         .clkctrl_offs = DM81XX_CM_ALWON_SPI_CLKCTRL,
1157                         .modulemode = MODULEMODE_SWCTRL,
1158                 },
1159         },
1160         .class          = &dm816x_mcspi_class,
1161         .dev_attr       = &dm816x_mcspi1_dev_attr,
1162 };
1163
1164 static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi1 = {
1165         .master         = &dm81xx_l4_ls_hwmod,
1166         .slave          = &dm81xx_mcspi1_hwmod,
1167         .clk            = "sysclk6_ck",
1168         .user           = OCP_USER_MPU,
1169 };
1170
1171 static struct omap_hwmod_class_sysconfig dm81xx_mailbox_sysc = {
1172         .rev_offs       = 0x000,
1173         .sysc_offs      = 0x010,
1174         .syss_offs      = 0x014,
1175         .sysc_flags     = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1176                                 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE,
1177         .idlemodes      = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
1178         .sysc_fields    = &omap_hwmod_sysc_type1,
1179 };
1180
1181 static struct omap_hwmod_class dm81xx_mailbox_hwmod_class = {
1182         .name = "mailbox",
1183         .sysc = &dm81xx_mailbox_sysc,
1184 };
1185
1186 static struct omap_hwmod dm81xx_mailbox_hwmod = {
1187         .name           = "mailbox",
1188         .clkdm_name     = "alwon_l3s_clkdm",
1189         .class          = &dm81xx_mailbox_hwmod_class,
1190         .main_clk       = "sysclk6_ck",
1191         .prcm           = {
1192                 .omap4 = {
1193                         .clkctrl_offs = DM81XX_CM_ALWON_MAILBOX_CLKCTRL,
1194                         .modulemode = MODULEMODE_SWCTRL,
1195                 },
1196         },
1197 };
1198
1199 static struct omap_hwmod_ocp_if dm81xx_l4_ls__mailbox = {
1200         .master         = &dm81xx_l4_ls_hwmod,
1201         .slave          = &dm81xx_mailbox_hwmod,
1202         .clk            = "sysclk6_ck",
1203         .user           = OCP_USER_MPU,
1204 };
1205
1206 static struct omap_hwmod_class_sysconfig dm81xx_spinbox_sysc = {
1207         .rev_offs       = 0x000,
1208         .sysc_offs      = 0x010,
1209         .syss_offs      = 0x014,
1210         .sysc_flags     = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1211                                 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE,
1212         .idlemodes      = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
1213         .sysc_fields    = &omap_hwmod_sysc_type1,
1214 };
1215
1216 static struct omap_hwmod_class dm81xx_spinbox_hwmod_class = {
1217         .name = "spinbox",
1218         .sysc = &dm81xx_spinbox_sysc,
1219 };
1220
1221 static struct omap_hwmod dm81xx_spinbox_hwmod = {
1222         .name           = "spinbox",
1223         .clkdm_name     = "alwon_l3s_clkdm",
1224         .class          = &dm81xx_spinbox_hwmod_class,
1225         .main_clk       = "sysclk6_ck",
1226         .prcm           = {
1227                 .omap4 = {
1228                         .clkctrl_offs = DM81XX_CM_ALWON_SPINBOX_CLKCTRL,
1229                         .modulemode = MODULEMODE_SWCTRL,
1230                 },
1231         },
1232 };
1233
1234 static struct omap_hwmod_ocp_if dm81xx_l4_ls__spinbox = {
1235         .master         = &dm81xx_l4_ls_hwmod,
1236         .slave          = &dm81xx_spinbox_hwmod,
1237         .clk            = "sysclk6_ck",
1238         .user           = OCP_USER_MPU,
1239 };
1240
1241 static struct omap_hwmod_class dm81xx_tpcc_hwmod_class = {
1242         .name           = "tpcc",
1243 };
1244
1245 static struct omap_hwmod dm81xx_tpcc_hwmod = {
1246         .name           = "tpcc",
1247         .class          = &dm81xx_tpcc_hwmod_class,
1248         .clkdm_name     = "alwon_l3s_clkdm",
1249         .main_clk       = "sysclk4_ck",
1250         .prcm           = {
1251                 .omap4  = {
1252                         .clkctrl_offs   = DM81XX_CM_ALWON_TPCC_CLKCTRL,
1253                         .modulemode     = MODULEMODE_SWCTRL,
1254                 },
1255         },
1256 };
1257
1258 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tpcc = {
1259         .master         = &dm81xx_alwon_l3_fast_hwmod,
1260         .slave          = &dm81xx_tpcc_hwmod,
1261         .clk            = "sysclk4_ck",
1262         .user           = OCP_USER_MPU,
1263 };
1264
1265 static struct omap_hwmod_class dm81xx_tptc0_hwmod_class = {
1266         .name           = "tptc0",
1267 };
1268
1269 static struct omap_hwmod dm81xx_tptc0_hwmod = {
1270         .name           = "tptc0",
1271         .class          = &dm81xx_tptc0_hwmod_class,
1272         .clkdm_name     = "alwon_l3s_clkdm",
1273         .main_clk       = "sysclk4_ck",
1274         .prcm           = {
1275                 .omap4  = {
1276                         .clkctrl_offs   = DM81XX_CM_ALWON_TPTC0_CLKCTRL,
1277                         .modulemode     = MODULEMODE_SWCTRL,
1278                 },
1279         },
1280 };
1281
1282 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc0 = {
1283         .master         = &dm81xx_alwon_l3_fast_hwmod,
1284         .slave          = &dm81xx_tptc0_hwmod,
1285         .clk            = "sysclk4_ck",
1286         .user           = OCP_USER_MPU,
1287 };
1288
1289 static struct omap_hwmod_ocp_if dm81xx_tptc0__alwon_l3_fast = {
1290         .master         = &dm81xx_tptc0_hwmod,
1291         .slave          = &dm81xx_alwon_l3_fast_hwmod,
1292         .clk            = "sysclk4_ck",
1293         .user           = OCP_USER_MPU,
1294 };
1295
1296 static struct omap_hwmod_class dm81xx_tptc1_hwmod_class = {
1297         .name           = "tptc1",
1298 };
1299
1300 static struct omap_hwmod dm81xx_tptc1_hwmod = {
1301         .name           = "tptc1",
1302         .class          = &dm81xx_tptc1_hwmod_class,
1303         .clkdm_name     = "alwon_l3s_clkdm",
1304         .main_clk       = "sysclk4_ck",
1305         .prcm           = {
1306                 .omap4  = {
1307                         .clkctrl_offs   = DM81XX_CM_ALWON_TPTC1_CLKCTRL,
1308                         .modulemode     = MODULEMODE_SWCTRL,
1309                 },
1310         },
1311 };
1312
1313 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc1 = {
1314         .master         = &dm81xx_alwon_l3_fast_hwmod,
1315         .slave          = &dm81xx_tptc1_hwmod,
1316         .clk            = "sysclk4_ck",
1317         .user           = OCP_USER_MPU,
1318 };
1319
1320 static struct omap_hwmod_ocp_if dm81xx_tptc1__alwon_l3_fast = {
1321         .master         = &dm81xx_tptc1_hwmod,
1322         .slave          = &dm81xx_alwon_l3_fast_hwmod,
1323         .clk            = "sysclk4_ck",
1324         .user           = OCP_USER_MPU,
1325 };
1326
1327 static struct omap_hwmod_class dm81xx_tptc2_hwmod_class = {
1328         .name           = "tptc2",
1329 };
1330
1331 static struct omap_hwmod dm81xx_tptc2_hwmod = {
1332         .name           = "tptc2",
1333         .class          = &dm81xx_tptc2_hwmod_class,
1334         .clkdm_name     = "alwon_l3s_clkdm",
1335         .main_clk       = "sysclk4_ck",
1336         .prcm           = {
1337                 .omap4  = {
1338                         .clkctrl_offs   = DM81XX_CM_ALWON_TPTC2_CLKCTRL,
1339                         .modulemode     = MODULEMODE_SWCTRL,
1340                 },
1341         },
1342 };
1343
1344 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc2 = {
1345         .master         = &dm81xx_alwon_l3_fast_hwmod,
1346         .slave          = &dm81xx_tptc2_hwmod,
1347         .clk            = "sysclk4_ck",
1348         .user           = OCP_USER_MPU,
1349 };
1350
1351 static struct omap_hwmod_ocp_if dm81xx_tptc2__alwon_l3_fast = {
1352         .master         = &dm81xx_tptc2_hwmod,
1353         .slave          = &dm81xx_alwon_l3_fast_hwmod,
1354         .clk            = "sysclk4_ck",
1355         .user           = OCP_USER_MPU,
1356 };
1357
1358 static struct omap_hwmod_class dm81xx_tptc3_hwmod_class = {
1359         .name           = "tptc3",
1360 };
1361
1362 static struct omap_hwmod dm81xx_tptc3_hwmod = {
1363         .name           = "tptc3",
1364         .class          = &dm81xx_tptc3_hwmod_class,
1365         .clkdm_name     = "alwon_l3s_clkdm",
1366         .main_clk       = "sysclk4_ck",
1367         .prcm           = {
1368                 .omap4  = {
1369                         .clkctrl_offs   = DM81XX_CM_ALWON_TPTC3_CLKCTRL,
1370                         .modulemode     = MODULEMODE_SWCTRL,
1371                 },
1372         },
1373 };
1374
1375 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc3 = {
1376         .master         = &dm81xx_alwon_l3_fast_hwmod,
1377         .slave          = &dm81xx_tptc3_hwmod,
1378         .clk            = "sysclk4_ck",
1379         .user           = OCP_USER_MPU,
1380 };
1381
1382 static struct omap_hwmod_ocp_if dm81xx_tptc3__alwon_l3_fast = {
1383         .master         = &dm81xx_tptc3_hwmod,
1384         .slave          = &dm81xx_alwon_l3_fast_hwmod,
1385         .clk            = "sysclk4_ck",
1386         .user           = OCP_USER_MPU,
1387 };
1388
1389 /*
1390  * REVISIT: Test and enable the following once clocks work:
1391  * dm81xx_l4_ls__mailbox
1392  *
1393  * Also note that some devices share a single clkctrl_offs..
1394  * For example, i2c1 and 3 share one, and i2c2 and 4 share one.
1395  */
1396 static struct omap_hwmod_ocp_if *dm814x_hwmod_ocp_ifs[] __initdata = {
1397         &dm814x_mpu__alwon_l3_slow,
1398         &dm814x_mpu__alwon_l3_med,
1399         &dm81xx_alwon_l3_slow__l4_ls,
1400         &dm81xx_alwon_l3_slow__l4_hs,
1401         &dm81xx_l4_ls__uart1,
1402         &dm81xx_l4_ls__uart2,
1403         &dm81xx_l4_ls__uart3,
1404         &dm81xx_l4_ls__wd_timer1,
1405         &dm81xx_l4_ls__i2c1,
1406         &dm81xx_l4_ls__i2c2,
1407         &dm81xx_l4_ls__gpio1,
1408         &dm81xx_l4_ls__gpio2,
1409         &dm81xx_l4_ls__elm,
1410         &dm81xx_l4_ls__mcspi1,
1411         &dm814x_l4_ls__mmc1,
1412         &dm814x_l4_ls__mmc2,
1413         &ti81xx_l4_ls__rtc,
1414         &dm81xx_alwon_l3_fast__tpcc,
1415         &dm81xx_alwon_l3_fast__tptc0,
1416         &dm81xx_alwon_l3_fast__tptc1,
1417         &dm81xx_alwon_l3_fast__tptc2,
1418         &dm81xx_alwon_l3_fast__tptc3,
1419         &dm81xx_tptc0__alwon_l3_fast,
1420         &dm81xx_tptc1__alwon_l3_fast,
1421         &dm81xx_tptc2__alwon_l3_fast,
1422         &dm81xx_tptc3__alwon_l3_fast,
1423         &dm814x_l4_ls__timer1,
1424         &dm814x_l4_ls__timer2,
1425         &dm814x_l4_hs__cpgmac0,
1426         &dm814x_cpgmac0__mdio,
1427         &dm81xx_alwon_l3_slow__gpmc,
1428         &dm814x_default_l3_slow__usbss,
1429         &dm814x_alwon_l3_med__mmc3,
1430         NULL,
1431 };
1432
1433 int __init dm814x_hwmod_init(void)
1434 {
1435         omap_hwmod_init();
1436         return omap_hwmod_register_links(dm814x_hwmod_ocp_ifs);
1437 }
1438
1439 static struct omap_hwmod_ocp_if *dm816x_hwmod_ocp_ifs[] __initdata = {
1440         &dm816x_mpu__alwon_l3_slow,
1441         &dm816x_mpu__alwon_l3_med,
1442         &dm81xx_alwon_l3_slow__l4_ls,
1443         &dm81xx_alwon_l3_slow__l4_hs,
1444         &dm81xx_l4_ls__uart1,
1445         &dm81xx_l4_ls__uart2,
1446         &dm81xx_l4_ls__uart3,
1447         &dm81xx_l4_ls__wd_timer1,
1448         &dm81xx_l4_ls__i2c1,
1449         &dm81xx_l4_ls__i2c2,
1450         &dm81xx_l4_ls__gpio1,
1451         &dm81xx_l4_ls__gpio2,
1452         &dm81xx_l4_ls__elm,
1453         &ti81xx_l4_ls__rtc,
1454         &dm816x_l4_ls__mmc1,
1455         &dm816x_l4_ls__timer1,
1456         &dm816x_l4_ls__timer2,
1457         &dm816x_l4_ls__timer3,
1458         &dm816x_l4_ls__timer4,
1459         &dm816x_l4_ls__timer5,
1460         &dm816x_l4_ls__timer6,
1461         &dm816x_l4_ls__timer7,
1462         &dm81xx_l4_ls__mcspi1,
1463         &dm81xx_l4_ls__mailbox,
1464         &dm81xx_l4_ls__spinbox,
1465         &dm81xx_l4_hs__emac0,
1466         &dm81xx_emac0__mdio,
1467         &dm816x_l4_hs__emac1,
1468         &dm81xx_l4_hs__sata,
1469         &dm81xx_alwon_l3_fast__tpcc,
1470         &dm81xx_alwon_l3_fast__tptc0,
1471         &dm81xx_alwon_l3_fast__tptc1,
1472         &dm81xx_alwon_l3_fast__tptc2,
1473         &dm81xx_alwon_l3_fast__tptc3,
1474         &dm81xx_tptc0__alwon_l3_fast,
1475         &dm81xx_tptc1__alwon_l3_fast,
1476         &dm81xx_tptc2__alwon_l3_fast,
1477         &dm81xx_tptc3__alwon_l3_fast,
1478         &dm81xx_alwon_l3_slow__gpmc,
1479         &dm816x_default_l3_slow__usbss,
1480         NULL,
1481 };
1482
1483 int __init dm816x_hwmod_init(void)
1484 {
1485         omap_hwmod_init();
1486         return omap_hwmod_register_links(dm816x_hwmod_ocp_ifs);
1487 }