arch/arm/mach-omap2/omap_hwmod_54xx_data.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Hardware modules present on the OMAP54xx chips
   4  *
   5  * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
   6  *
   7  * Paul Walmsley
   8  * Benoit Cousson
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <linux/power/smartreflex.h>
  19
  20 #include "omap_hwmod.h"
  21 #include "omap_hwmod_common_data.h"
  22 #include "cm1_54xx.h"
  23 #include "cm2_54xx.h"
  24 #include "prm54xx.h"
  25
  26 /* Base offset for all OMAP5 interrupts external to MPUSS */
  27 #define OMAP54XX_IRQ_GIC_START  32
  28
  29 /*
  30  * IP blocks
  31  */
  32
  33 /*
  34  * 'l3' class
  35  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
  36  */
  37 static struct omap_hwmod_class omap54xx_l3_hwmod_class = {
  38         .name   = "l3",
  39 };
  40
  41 /* l3_instr */
  42 static struct omap_hwmod omap54xx_l3_instr_hwmod = {
  43         .name           = "l3_instr",
  44         .class          = &omap54xx_l3_hwmod_class,
  45         .clkdm_name     = "l3instr_clkdm",
  46         .prcm = {
  47                 .omap4 = {
  48                         .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
  49                         .context_offs = OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
  50                         .modulemode   = MODULEMODE_HWCTRL,
  51                 },
  52         },
  53 };
  54
  55 /* l3_main_1 */
  56 static struct omap_hwmod omap54xx_l3_main_1_hwmod = {
  57         .name           = "l3_main_1",
  58         .class          = &omap54xx_l3_hwmod_class,
  59         .clkdm_name     = "l3main1_clkdm",
  60         .prcm = {
  61                 .omap4 = {
  62                         .clkctrl_offs = OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
  63                         .context_offs = OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
  64                 },
  65         },
  66 };
  67
  68 /* l3_main_2 */
  69 static struct omap_hwmod omap54xx_l3_main_2_hwmod = {
  70         .name           = "l3_main_2",
  71         .class          = &omap54xx_l3_hwmod_class,
  72         .clkdm_name     = "l3main2_clkdm",
  73         .prcm = {
  74                 .omap4 = {
  75                         .clkctrl_offs = OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET,
  76                         .context_offs = OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET,
  77                 },
  78         },
  79 };
  80
  81 /* l3_main_3 */
  82 static struct omap_hwmod omap54xx_l3_main_3_hwmod = {
  83         .name           = "l3_main_3",
  84         .class          = &omap54xx_l3_hwmod_class,
  85         .clkdm_name     = "l3instr_clkdm",
  86         .prcm = {
  87                 .omap4 = {
  88                         .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET,
  89                         .context_offs = OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET,
  90                         .modulemode   = MODULEMODE_HWCTRL,
  91                 },
  92         },
  93 };
  94
  95 /*
  96  * 'l4' class
  97  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
  98  */
  99 static struct omap_hwmod_class omap54xx_l4_hwmod_class = {
 100         .name   = "l4",
 101 };
 102
 103 /* l4_cfg */
 104 static struct omap_hwmod omap54xx_l4_cfg_hwmod = {
 105         .name           = "l4_cfg",
 106         .class          = &omap54xx_l4_hwmod_class,
 107         .clkdm_name     = "l4cfg_clkdm",
 108         .prcm = {
 109                 .omap4 = {
 110                         .clkctrl_offs = OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 111                         .context_offs = OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 112                 },
 113         },
 114 };
 115
 116 /* l4_per */
 117 static struct omap_hwmod omap54xx_l4_per_hwmod = {
 118         .name           = "l4_per",
 119         .class          = &omap54xx_l4_hwmod_class,
 120         .clkdm_name     = "l4per_clkdm",
 121         .prcm = {
 122                 .omap4 = {
 123                         .clkctrl_offs = OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET,
 124                         .context_offs = OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 125                 },
 126         },
 127 };
 128
 129 /* l4_wkup */
 130 static struct omap_hwmod omap54xx_l4_wkup_hwmod = {
 131         .name           = "l4_wkup",
 132         .class          = &omap54xx_l4_hwmod_class,
 133         .clkdm_name     = "wkupaon_clkdm",
 134         .prcm = {
 135                 .omap4 = {
 136                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
 137                         .context_offs = OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
 138                 },
 139         },
 140 };
 141
 142 /*
 143  * 'sata' class
 144  * sata:  serial ata interface  gen2 compliant   ( 1 rx/ 1 tx)
 145  */
 146
 147 static struct omap_hwmod_class_sysconfig omap54xx_sata_sysc = {
 148         .rev_offs       = 0x00fc,
 149         .sysc_offs      = 0x0000,
 150         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
 151         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 152                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
 153                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
 154         .sysc_fields    = &omap_hwmod_sysc_type2,
 155 };
 156
 157 static struct omap_hwmod_class omap54xx_sata_hwmod_class = {
 158         .name   = "sata",
 159         .sysc   = &omap54xx_sata_sysc,
 160 };
 161
 162 /* sata */
 163 static struct omap_hwmod omap54xx_sata_hwmod = {
 164         .name           = "sata",
 165         .class          = &omap54xx_sata_hwmod_class,
 166         .clkdm_name     = "l3init_clkdm",
 167         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
 168         .main_clk       = "func_48m_fclk",
 169         .mpu_rt_idx     = 1,
 170         .prcm = {
 171                 .omap4 = {
 172                         .clkctrl_offs = OMAP54XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
 173                         .context_offs = OMAP54XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
 174                         .modulemode   = MODULEMODE_SWCTRL,
 175                 },
 176         },
 177 };
 178
 179 /* l4_cfg -> sata */
 180 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__sata = {
 181         .master         = &omap54xx_l4_cfg_hwmod,
 182         .slave          = &omap54xx_sata_hwmod,
 183         .clk            = "l3_iclk_div",
 184         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 185 };
 186
 187 /*
 188  * Interfaces
 189  */
 190
 191 /* l3_main_3 -> l3_instr */
 192 static struct omap_hwmod_ocp_if omap54xx_l3_main_3__l3_instr = {
 193         .master         = &omap54xx_l3_main_3_hwmod,
 194         .slave          = &omap54xx_l3_instr_hwmod,
 195         .clk            = "l3_iclk_div",
 196         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 197 };
 198
 199 /* l3_main_2 -> l3_main_1 */
 200 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_1 = {
 201         .master         = &omap54xx_l3_main_2_hwmod,
 202         .slave          = &omap54xx_l3_main_1_hwmod,
 203         .clk            = "l3_iclk_div",
 204         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 205 };
 206
 207 /* l4_cfg -> l3_main_1 */
 208 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_1 = {
 209         .master         = &omap54xx_l4_cfg_hwmod,
 210         .slave          = &omap54xx_l3_main_1_hwmod,
 211         .clk            = "l3_iclk_div",
 212         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 213 };
 214
 215 /* l3_main_1 -> l3_main_2 */
 216 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_2 = {
 217         .master         = &omap54xx_l3_main_1_hwmod,
 218         .slave          = &omap54xx_l3_main_2_hwmod,
 219         .clk            = "l3_iclk_div",
 220         .user           = OCP_USER_MPU,
 221 };
 222
 223 /* l4_cfg -> l3_main_2 */
 224 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_2 = {
 225         .master         = &omap54xx_l4_cfg_hwmod,
 226         .slave          = &omap54xx_l3_main_2_hwmod,
 227         .clk            = "l3_iclk_div",
 228         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 229 };
 230
 231 /* l3_main_1 -> l3_main_3 */
 232 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_3 = {
 233         .master         = &omap54xx_l3_main_1_hwmod,
 234         .slave          = &omap54xx_l3_main_3_hwmod,
 235         .clk            = "l3_iclk_div",
 236         .user           = OCP_USER_MPU,
 237 };
 238
 239 /* l3_main_2 -> l3_main_3 */
 240 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_3 = {
 241         .master         = &omap54xx_l3_main_2_hwmod,
 242         .slave          = &omap54xx_l3_main_3_hwmod,
 243         .clk            = "l3_iclk_div",
 244         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 245 };
 246
 247 /* l4_cfg -> l3_main_3 */
 248 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_3 = {
 249         .master         = &omap54xx_l4_cfg_hwmod,
 250         .slave          = &omap54xx_l3_main_3_hwmod,
 251         .clk            = "l3_iclk_div",
 252         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 253 };
 254
 255 /* l3_main_1 -> l4_cfg */
 256 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_cfg = {
 257         .master         = &omap54xx_l3_main_1_hwmod,
 258         .slave          = &omap54xx_l4_cfg_hwmod,
 259         .clk            = "l4_root_clk_div",
 260         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 261 };
 262
 263 /* l3_main_2 -> l4_per */
 264 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l4_per = {
 265         .master         = &omap54xx_l3_main_2_hwmod,
 266         .slave          = &omap54xx_l4_per_hwmod,
 267         .clk            = "l4_root_clk_div",
 268         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 269 };
 270
 271 /* l3_main_1 -> l4_wkup */
 272 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_wkup = {
 273         .master         = &omap54xx_l3_main_1_hwmod,
 274         .slave          = &omap54xx_l4_wkup_hwmod,
 275         .clk            = "wkupaon_iclk_mux",
 276         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 277 };
 278
 279 static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
 280         &omap54xx_l3_main_3__l3_instr,
 281         &omap54xx_l3_main_2__l3_main_1,
 282         &omap54xx_l4_cfg__l3_main_1,
 283         &omap54xx_l3_main_1__l3_main_2,
 284         &omap54xx_l4_cfg__l3_main_2,
 285         &omap54xx_l3_main_1__l3_main_3,
 286         &omap54xx_l3_main_2__l3_main_3,
 287         &omap54xx_l4_cfg__l3_main_3,
 288         &omap54xx_l3_main_1__l4_cfg,
 289         &omap54xx_l3_main_2__l4_per,
 290         &omap54xx_l3_main_1__l4_wkup,
 291         &omap54xx_l4_cfg__sata,
 292         NULL,
 293 };
 294
 295 int __init omap54xx_hwmod_init(void)
 296 {
 297         omap_hwmod_init();
 298         return omap_hwmod_register_links(omap54xx_hwmod_ocp_ifs);
 299 }