arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Hardware modules present on the OMAP44xx chips
   4  *
   5  * Copyright (C) 2009-2012 Texas Instruments, Inc.
   6  * Copyright (C) 2009-2010 Nokia Corporation
   7  *
   8  * Paul Walmsley
   9  * Benoit Cousson
  10  *
  11  * This file is automatically generated from the OMAP hardware databases.
  12  * We respectfully ask that any modifications to this file be coordinated
  13  * with the public linux-omap@vger.kernel.org mailing list and the
  14  * authors above to ensure that the autogeneration scripts are kept
  15  * up-to-date with the file contents.
  16  * Note that this file is currently not in sync with autogeneration scripts.
  17  * The above note to be removed, once it is synced up.
  18  */
  19
  20 #include <linux/io.h>
  21 #include <linux/power/smartreflex.h>
  22
  23 #include "omap_hwmod.h"
  24 #include "omap_hwmod_common_data.h"
  25 #include "cm1_44xx.h"
  26 #include "cm2_44xx.h"
  27 #include "prm44xx.h"
  28 #include "prm-regbits-44xx.h"
  29
  30 /* Base offset for all OMAP4 interrupts external to MPUSS */
  31 #define OMAP44XX_IRQ_GIC_START  32
  32
  33 /*
  34  * IP blocks
  35  */
  36
  37 /*
  38  * 'dmm' class
  39  * instance(s): dmm
  40  */
  41 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  42         .name   = "dmm",
  43 };
  44
  45 /* dmm */
  46 static struct omap_hwmod omap44xx_dmm_hwmod = {
  47         .name           = "dmm",
  48         .class          = &omap44xx_dmm_hwmod_class,
  49         .clkdm_name     = "l3_emif_clkdm",
  50         .prcm = {
  51                 .omap4 = {
  52                         .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
  53                         .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
  54                 },
  55         },
  56 };
  57
  58 /*
  59  * 'l3' class
  60  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
  61  */
  62 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
  63         .name   = "l3",
  64 };
  65
  66 /* l3_instr */
  67 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
  68         .name           = "l3_instr",
  69         .class          = &omap44xx_l3_hwmod_class,
  70         .clkdm_name     = "l3_instr_clkdm",
  71         .prcm = {
  72                 .omap4 = {
  73                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
  74                         .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
  75                         .modulemode   = MODULEMODE_HWCTRL,
  76                 },
  77         },
  78 };
  79
  80 /* l3_main_1 */
  81 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
  82         .name           = "l3_main_1",
  83         .class          = &omap44xx_l3_hwmod_class,
  84         .clkdm_name     = "l3_1_clkdm",
  85         .prcm = {
  86                 .omap4 = {
  87                         .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
  88                         .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
  89                 },
  90         },
  91 };
  92
  93 /* l3_main_2 */
  94 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
  95         .name           = "l3_main_2",
  96         .class          = &omap44xx_l3_hwmod_class,
  97         .clkdm_name     = "l3_2_clkdm",
  98         .prcm = {
  99                 .omap4 = {
 100                         .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
 101                         .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
 102                 },
 103         },
 104 };
 105
 106 /* l3_main_3 */
 107 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 108         .name           = "l3_main_3",
 109         .class          = &omap44xx_l3_hwmod_class,
 110         .clkdm_name     = "l3_instr_clkdm",
 111         .prcm = {
 112                 .omap4 = {
 113                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
 114                         .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
 115                         .modulemode   = MODULEMODE_HWCTRL,
 116                 },
 117         },
 118 };
 119
 120 /*
 121  * 'l4' class
 122  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 123  */
 124 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 125         .name   = "l4",
 126 };
 127
 128 /* l4_abe */
 129 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 130         .name           = "l4_abe",
 131         .class          = &omap44xx_l4_hwmod_class,
 132         .clkdm_name     = "abe_clkdm",
 133         .prcm = {
 134                 .omap4 = {
 135                         .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
 136                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 137                         .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK,
 138                         .flags        = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 139                 },
 140         },
 141 };
 142
 143 /* l4_cfg */
 144 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 145         .name           = "l4_cfg",
 146         .class          = &omap44xx_l4_hwmod_class,
 147         .clkdm_name     = "l4_cfg_clkdm",
 148         .prcm = {
 149                 .omap4 = {
 150                         .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 151                         .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 152                 },
 153         },
 154 };
 155
 156 /* l4_per */
 157 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 158         .name           = "l4_per",
 159         .class          = &omap44xx_l4_hwmod_class,
 160         .clkdm_name     = "l4_per_clkdm",
 161         .prcm = {
 162                 .omap4 = {
 163                         .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
 164                         .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 165                 },
 166         },
 167 };
 168
 169 /* l4_wkup */
 170 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 171         .name           = "l4_wkup",
 172         .class          = &omap44xx_l4_hwmod_class,
 173         .clkdm_name     = "l4_wkup_clkdm",
 174         .prcm = {
 175                 .omap4 = {
 176                         .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
 177                         .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
 178                 },
 179         },
 180 };
 181
 182 /*
 183  * 'mpu_bus' class
 184  * instance(s): mpu_private
 185  */
 186 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 187         .name   = "mpu_bus",
 188 };
 189
 190 /* mpu_private */
 191 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 192         .name           = "mpu_private",
 193         .class          = &omap44xx_mpu_bus_hwmod_class,
 194         .clkdm_name     = "mpuss_clkdm",
 195         .prcm = {
 196                 .omap4 = {
 197                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 198                 },
 199         },
 200 };
 201
 202 /*
 203  * 'ocp_wp_noc' class
 204  * instance(s): ocp_wp_noc
 205  */
 206 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
 207         .name   = "ocp_wp_noc",
 208 };
 209
 210 /* ocp_wp_noc */
 211 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
 212         .name           = "ocp_wp_noc",
 213         .class          = &omap44xx_ocp_wp_noc_hwmod_class,
 214         .clkdm_name     = "l3_instr_clkdm",
 215         .prcm = {
 216                 .omap4 = {
 217                         .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
 218                         .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
 219                         .modulemode   = MODULEMODE_HWCTRL,
 220                 },
 221         },
 222 };
 223
 224 /*
 225  * Modules omap_hwmod structures
 226  *
 227  * The following IPs are excluded for the moment because:
 228  * - They do not need an explicit SW control using omap_hwmod API.
 229  * - They still need to be validated with the driver
 230  *   properly adapted to omap_hwmod / omap_device
 231  *
 232  * usim
 233  */
 234
 235 /*
 236  * 'aess' class
 237  * audio engine sub system
 238  */
 239
 240 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
 241         .rev_offs       = 0x0000,
 242         .sysc_offs      = 0x0010,
 243         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
 244         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 245                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
 246                            MSTANDBY_SMART_WKUP),
 247         .sysc_fields    = &omap_hwmod_sysc_type2,
 248 };
 249
 250 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
 251         .name   = "aess",
 252         .sysc   = &omap44xx_aess_sysc,
 253         .enable_preprogram = omap_hwmod_aess_preprogram,
 254 };
 255
 256 /* aess */
 257 static struct omap_hwmod omap44xx_aess_hwmod = {
 258         .name           = "aess",
 259         .class          = &omap44xx_aess_hwmod_class,
 260         .clkdm_name     = "abe_clkdm",
 261         .main_clk       = "aess_fclk",
 262         .prcm = {
 263                 .omap4 = {
 264                         .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
 265                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 266                         .lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK,
 267                         .modulemode   = MODULEMODE_SWCTRL,
 268                 },
 269         },
 270 };
 271
 272 /*
 273  * 'counter' class
 274  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 275  */
 276
 277 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
 278         .rev_offs       = 0x0000,
 279         .sysc_offs      = 0x0004,
 280         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 281         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
 282         .sysc_fields    = &omap_hwmod_sysc_type1,
 283 };
 284
 285 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
 286         .name   = "counter",
 287         .sysc   = &omap44xx_counter_sysc,
 288 };
 289
 290 /* counter_32k */
 291 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
 292         .name           = "counter_32k",
 293         .class          = &omap44xx_counter_hwmod_class,
 294         .clkdm_name     = "l4_wkup_clkdm",
 295         .flags          = HWMOD_SWSUP_SIDLE,
 296         .main_clk       = "sys_32k_ck",
 297         .prcm = {
 298                 .omap4 = {
 299                         .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
 300                         .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
 301                 },
 302         },
 303 };
 304
 305 /*
 306  * 'ctrl_module' class
 307  * attila core control module + core pad control module + wkup pad control
 308  * module + attila wkup control module
 309  */
 310
 311 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
 312         .rev_offs       = 0x0000,
 313         .sysc_offs      = 0x0010,
 314         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 315         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 316                            SIDLE_SMART_WKUP),
 317         .sysc_fields    = &omap_hwmod_sysc_type2,
 318 };
 319
 320 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
 321         .name   = "ctrl_module",
 322         .sysc   = &omap44xx_ctrl_module_sysc,
 323 };
 324
 325 /* ctrl_module_core */
 326 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
 327         .name           = "ctrl_module_core",
 328         .class          = &omap44xx_ctrl_module_hwmod_class,
 329         .clkdm_name     = "l4_cfg_clkdm",
 330         .prcm = {
 331                 .omap4 = {
 332                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 333                 },
 334         },
 335 };
 336
 337 /* ctrl_module_pad_core */
 338 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
 339         .name           = "ctrl_module_pad_core",
 340         .class          = &omap44xx_ctrl_module_hwmod_class,
 341         .clkdm_name     = "l4_cfg_clkdm",
 342         .prcm = {
 343                 .omap4 = {
 344                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 345                 },
 346         },
 347 };
 348
 349 /* ctrl_module_wkup */
 350 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
 351         .name           = "ctrl_module_wkup",
 352         .class          = &omap44xx_ctrl_module_hwmod_class,
 353         .clkdm_name     = "l4_wkup_clkdm",
 354         .prcm = {
 355                 .omap4 = {
 356                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 357                 },
 358         },
 359 };
 360
 361 /* ctrl_module_pad_wkup */
 362 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
 363         .name           = "ctrl_module_pad_wkup",
 364         .class          = &omap44xx_ctrl_module_hwmod_class,
 365         .clkdm_name     = "l4_wkup_clkdm",
 366         .prcm = {
 367                 .omap4 = {
 368                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 369                 },
 370         },
 371 };
 372
 373 /*
 374  * 'debugss' class
 375  * debug and emulation sub system
 376  */
 377
 378 static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
 379         .name   = "debugss",
 380 };
 381
 382 /* debugss */
 383 static struct omap_hwmod omap44xx_debugss_hwmod = {
 384         .name           = "debugss",
 385         .class          = &omap44xx_debugss_hwmod_class,
 386         .clkdm_name     = "emu_sys_clkdm",
 387         .main_clk       = "trace_clk_div_ck",
 388         .prcm = {
 389                 .omap4 = {
 390                         .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
 391                         .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
 392                 },
 393         },
 394 };
 395
 396 /*
 397  * 'dmic' class
 398  * digital microphone controller
 399  */
 400
 401 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
 402         .rev_offs       = 0x0000,
 403         .sysc_offs      = 0x0010,
 404         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 405                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 406         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 407                            SIDLE_SMART_WKUP),
 408         .sysc_fields    = &omap_hwmod_sysc_type2,
 409 };
 410
 411 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
 412         .name   = "dmic",
 413         .sysc   = &omap44xx_dmic_sysc,
 414 };
 415
 416 /* dmic */
 417 static struct omap_hwmod omap44xx_dmic_hwmod = {
 418         .name           = "dmic",
 419         .class          = &omap44xx_dmic_hwmod_class,
 420         .clkdm_name     = "abe_clkdm",
 421         .main_clk       = "func_dmic_abe_gfclk",
 422         .prcm = {
 423                 .omap4 = {
 424                         .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
 425                         .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
 426                         .modulemode   = MODULEMODE_SWCTRL,
 427                 },
 428         },
 429 };
 430
 431 /*
 432  * 'dsp' class
 433  * dsp sub-system
 434  */
 435
 436 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
 437         .name   = "dsp",
 438 };
 439
 440 /* dsp */
 441 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
 442         { .name = "dsp", .rst_shift = 0 },
 443 };
 444
 445 static struct omap_hwmod omap44xx_dsp_hwmod = {
 446         .name           = "dsp",
 447         .class          = &omap44xx_dsp_hwmod_class,
 448         .clkdm_name     = "tesla_clkdm",
 449         .rst_lines      = omap44xx_dsp_resets,
 450         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
 451         .main_clk       = "dpll_iva_m4x2_ck",
 452         .prcm = {
 453                 .omap4 = {
 454                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
 455                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
 456                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
 457                         .modulemode   = MODULEMODE_HWCTRL,
 458                 },
 459         },
 460 };
 461
 462 /*
 463  * 'dss' class
 464  * display sub-system
 465  */
 466
 467 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
 468         .rev_offs       = 0x0000,
 469         .syss_offs      = 0x0014,
 470         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 471 };
 472
 473 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
 474         .name   = "dss",
 475         .sysc   = &omap44xx_dss_sysc,
 476         .reset  = omap_dss_reset,
 477 };
 478
 479 /* dss */
 480 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 481         { .role = "sys_clk", .clk = "dss_sys_clk" },
 482         { .role = "tv_clk", .clk = "dss_tv_clk" },
 483         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
 484 };
 485
 486 static struct omap_hwmod omap44xx_dss_hwmod = {
 487         .name           = "dss_core",
 488         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 489         .class          = &omap44xx_dss_hwmod_class,
 490         .clkdm_name     = "l3_dss_clkdm",
 491         .main_clk       = "dss_dss_clk",
 492         .prcm = {
 493                 .omap4 = {
 494                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 495                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 496                         .modulemode   = MODULEMODE_SWCTRL,
 497                 },
 498         },
 499         .opt_clks       = dss_opt_clks,
 500         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
 501 };
 502
 503 /*
 504  * 'dispc' class
 505  * display controller
 506  */
 507
 508 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
 509         .rev_offs       = 0x0000,
 510         .sysc_offs      = 0x0010,
 511         .syss_offs      = 0x0014,
 512         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 513                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
 514                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 515                            SYSS_HAS_RESET_STATUS),
 516         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 517                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 518         .sysc_fields    = &omap_hwmod_sysc_type1,
 519 };
 520
 521 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
 522         .name   = "dispc",
 523         .sysc   = &omap44xx_dispc_sysc,
 524 };
 525
 526 /* dss_dispc */
 527 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
 528         .manager_count          = 3,
 529         .has_framedonetv_irq    = 1
 530 };
 531
 532 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
 533         .name           = "dss_dispc",
 534         .class          = &omap44xx_dispc_hwmod_class,
 535         .clkdm_name     = "l3_dss_clkdm",
 536         .main_clk       = "dss_dss_clk",
 537         .prcm = {
 538                 .omap4 = {
 539                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 540                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 541                 },
 542         },
 543         .dev_attr       = &omap44xx_dss_dispc_dev_attr,
 544         .parent_hwmod   = &omap44xx_dss_hwmod,
 545 };
 546
 547 /*
 548  * 'dsi' class
 549  * display serial interface controller
 550  */
 551
 552 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
 553         .rev_offs       = 0x0000,
 554         .sysc_offs      = 0x0010,
 555         .syss_offs      = 0x0014,
 556         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 557                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 558                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 559         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 560         .sysc_fields    = &omap_hwmod_sysc_type1,
 561 };
 562
 563 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
 564         .name   = "dsi",
 565         .sysc   = &omap44xx_dsi_sysc,
 566 };
 567
 568 /* dss_dsi1 */
 569 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
 570         { .role = "sys_clk", .clk = "dss_sys_clk" },
 571 };
 572
 573 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
 574         .name           = "dss_dsi1",
 575         .class          = &omap44xx_dsi_hwmod_class,
 576         .clkdm_name     = "l3_dss_clkdm",
 577         .main_clk       = "dss_dss_clk",
 578         .prcm = {
 579                 .omap4 = {
 580                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 581                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 582                 },
 583         },
 584         .opt_clks       = dss_dsi1_opt_clks,
 585         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
 586         .parent_hwmod   = &omap44xx_dss_hwmod,
 587 };
 588
 589 /* dss_dsi2 */
 590 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
 591         { .role = "sys_clk", .clk = "dss_sys_clk" },
 592 };
 593
 594 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
 595         .name           = "dss_dsi2",
 596         .class          = &omap44xx_dsi_hwmod_class,
 597         .clkdm_name     = "l3_dss_clkdm",
 598         .main_clk       = "dss_dss_clk",
 599         .prcm = {
 600                 .omap4 = {
 601                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 602                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 603                 },
 604         },
 605         .opt_clks       = dss_dsi2_opt_clks,
 606         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi2_opt_clks),
 607         .parent_hwmod   = &omap44xx_dss_hwmod,
 608 };
 609
 610 /*
 611  * 'hdmi' class
 612  * hdmi controller
 613  */
 614
 615 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
 616         .rev_offs       = 0x0000,
 617         .sysc_offs      = 0x0010,
 618         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 619                            SYSC_HAS_SOFTRESET),
 620         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 621                            SIDLE_SMART_WKUP),
 622         .sysc_fields    = &omap_hwmod_sysc_type2,
 623 };
 624
 625 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
 626         .name   = "hdmi",
 627         .sysc   = &omap44xx_hdmi_sysc,
 628 };
 629
 630 /* dss_hdmi */
 631 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
 632         { .role = "sys_clk", .clk = "dss_sys_clk" },
 633         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
 634 };
 635
 636 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
 637         .name           = "dss_hdmi",
 638         .class          = &omap44xx_hdmi_hwmod_class,
 639         .clkdm_name     = "l3_dss_clkdm",
 640         /*
 641          * HDMI audio requires to use no-idle mode. Hence,
 642          * set idle mode by software.
 643          */
 644         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_OPT_CLKS_NEEDED,
 645         .main_clk       = "dss_48mhz_clk",
 646         .prcm = {
 647                 .omap4 = {
 648                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 649                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 650                 },
 651         },
 652         .opt_clks       = dss_hdmi_opt_clks,
 653         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
 654         .parent_hwmod   = &omap44xx_dss_hwmod,
 655 };
 656
 657 /*
 658  * 'rfbi' class
 659  * remote frame buffer interface
 660  */
 661
 662 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
 663         .rev_offs       = 0x0000,
 664         .sysc_offs      = 0x0010,
 665         .syss_offs      = 0x0014,
 666         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 667                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 668         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 669         .sysc_fields    = &omap_hwmod_sysc_type1,
 670 };
 671
 672 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
 673         .name   = "rfbi",
 674         .sysc   = &omap44xx_rfbi_sysc,
 675 };
 676
 677 /* dss_rfbi */
 678 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 679         { .role = "ick", .clk = "l3_div_ck" },
 680 };
 681
 682 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
 683         .name           = "dss_rfbi",
 684         .class          = &omap44xx_rfbi_hwmod_class,
 685         .clkdm_name     = "l3_dss_clkdm",
 686         .main_clk       = "dss_dss_clk",
 687         .prcm = {
 688                 .omap4 = {
 689                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 690                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 691                 },
 692         },
 693         .opt_clks       = dss_rfbi_opt_clks,
 694         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 695         .parent_hwmod   = &omap44xx_dss_hwmod,
 696 };
 697
 698 /*
 699  * 'venc' class
 700  * video encoder
 701  */
 702
 703 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
 704         .name   = "venc",
 705 };
 706
 707 /* dss_venc */
 708 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
 709         { .role = "tv_clk", .clk = "dss_tv_clk" },
 710 };
 711
 712 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
 713         .name           = "dss_venc",
 714         .class          = &omap44xx_venc_hwmod_class,
 715         .clkdm_name     = "l3_dss_clkdm",
 716         .main_clk       = "dss_tv_clk",
 717         .flags          = HWMOD_OPT_CLKS_NEEDED,
 718         .prcm = {
 719                 .omap4 = {
 720                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 721                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 722                 },
 723         },
 724         .parent_hwmod   = &omap44xx_dss_hwmod,
 725         .opt_clks       = dss_venc_opt_clks,
 726         .opt_clks_cnt   = ARRAY_SIZE(dss_venc_opt_clks),
 727 };
 728
 729 /* sha0 HIB2 (the 'P' (public) device) */
 730 static struct omap_hwmod_class_sysconfig omap44xx_sha0_sysc = {
 731         .rev_offs       = 0x100,
 732         .sysc_offs      = 0x110,
 733         .syss_offs      = 0x114,
 734         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 735 };
 736
 737 static struct omap_hwmod_class omap44xx_sha0_hwmod_class = {
 738         .name           = "sham",
 739         .sysc           = &omap44xx_sha0_sysc,
 740 };
 741
 742 static struct omap_hwmod omap44xx_sha0_hwmod = {
 743         .name           = "sham",
 744         .class          = &omap44xx_sha0_hwmod_class,
 745         .clkdm_name     = "l4_secure_clkdm",
 746         .main_clk       = "l3_div_ck",
 747         .prcm           = {
 748                 .omap4 = {
 749                         .clkctrl_offs = OMAP4_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET,
 750                         .context_offs = OMAP4_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET,
 751                         .modulemode   = MODULEMODE_SWCTRL,
 752                 },
 753         },
 754 };
 755
 756 /*
 757  * 'elm' class
 758  * bch error location module
 759  */
 760
 761 static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
 762         .rev_offs       = 0x0000,
 763         .sysc_offs      = 0x0010,
 764         .syss_offs      = 0x0014,
 765         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 766                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 767                            SYSS_HAS_RESET_STATUS),
 768         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 769         .sysc_fields    = &omap_hwmod_sysc_type1,
 770 };
 771
 772 static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
 773         .name   = "elm",
 774         .sysc   = &omap44xx_elm_sysc,
 775 };
 776
 777 /* elm */
 778 static struct omap_hwmod omap44xx_elm_hwmod = {
 779         .name           = "elm",
 780         .class          = &omap44xx_elm_hwmod_class,
 781         .clkdm_name     = "l4_per_clkdm",
 782         .prcm = {
 783                 .omap4 = {
 784                         .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
 785                         .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
 786                 },
 787         },
 788 };
 789
 790 /*
 791  * 'emif' class
 792  * external memory interface no1
 793  */
 794
 795 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
 796         .rev_offs       = 0x0000,
 797 };
 798
 799 static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
 800         .name   = "emif",
 801         .sysc   = &omap44xx_emif_sysc,
 802 };
 803
 804 /* emif1 */
 805 static struct omap_hwmod omap44xx_emif1_hwmod = {
 806         .name           = "emif1",
 807         .class          = &omap44xx_emif_hwmod_class,
 808         .clkdm_name     = "l3_emif_clkdm",
 809         .flags          = HWMOD_INIT_NO_IDLE,
 810         .main_clk       = "ddrphy_ck",
 811         .prcm = {
 812                 .omap4 = {
 813                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
 814                         .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
 815                         .modulemode   = MODULEMODE_HWCTRL,
 816                 },
 817         },
 818 };
 819
 820 /* emif2 */
 821 static struct omap_hwmod omap44xx_emif2_hwmod = {
 822         .name           = "emif2",
 823         .class          = &omap44xx_emif_hwmod_class,
 824         .clkdm_name     = "l3_emif_clkdm",
 825         .flags          = HWMOD_INIT_NO_IDLE,
 826         .main_clk       = "ddrphy_ck",
 827         .prcm = {
 828                 .omap4 = {
 829                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
 830                         .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
 831                         .modulemode   = MODULEMODE_HWCTRL,
 832                 },
 833         },
 834 };
 835
 836 /*
 837     Crypto modules AES0/1 belong to:
 838         PD_L4_PER power domain
 839         CD_L4_SEC clock domain
 840         On the L3, the AES modules are mapped to
 841         L3_CLK2: Peripherals and multimedia sub clock domain
 842 */
 843 static struct omap_hwmod_class_sysconfig omap44xx_aes_sysc = {
 844         .rev_offs       = 0x80,
 845         .sysc_offs      = 0x84,
 846         .syss_offs      = 0x88,
 847         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 848 };
 849
 850 static struct omap_hwmod_class omap44xx_aes_hwmod_class = {
 851         .name           = "aes",
 852         .sysc           = &omap44xx_aes_sysc,
 853 };
 854
 855 static struct omap_hwmod omap44xx_aes1_hwmod = {
 856         .name           = "aes1",
 857         .class          = &omap44xx_aes_hwmod_class,
 858         .clkdm_name     = "l4_secure_clkdm",
 859         .main_clk       = "l3_div_ck",
 860         .prcm           = {
 861                 .omap4  = {
 862                         .context_offs   = OMAP4_RM_L4SEC_AES1_CONTEXT_OFFSET,
 863                         .clkctrl_offs   = OMAP4_CM_L4SEC_AES1_CLKCTRL_OFFSET,
 864                         .modulemode     = MODULEMODE_SWCTRL,
 865                 },
 866         },
 867 };
 868
 869 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__aes1 = {
 870         .master         = &omap44xx_l4_per_hwmod,
 871         .slave          = &omap44xx_aes1_hwmod,
 872         .clk            = "l3_div_ck",
 873         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 874 };
 875
 876 static struct omap_hwmod omap44xx_aes2_hwmod = {
 877         .name           = "aes2",
 878         .class          = &omap44xx_aes_hwmod_class,
 879         .clkdm_name     = "l4_secure_clkdm",
 880         .main_clk       = "l3_div_ck",
 881         .prcm           = {
 882                 .omap4  = {
 883                         .context_offs   = OMAP4_RM_L4SEC_AES2_CONTEXT_OFFSET,
 884                         .clkctrl_offs   = OMAP4_CM_L4SEC_AES2_CLKCTRL_OFFSET,
 885                         .modulemode     = MODULEMODE_SWCTRL,
 886                 },
 887         },
 888 };
 889
 890 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__aes2 = {
 891         .master         = &omap44xx_l4_per_hwmod,
 892         .slave          = &omap44xx_aes2_hwmod,
 893         .clk            = "l3_div_ck",
 894         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 895 };
 896
 897 /*
 898  * 'des' class for DES3DES module
 899  */
 900 static struct omap_hwmod_class_sysconfig omap44xx_des_sysc = {
 901         .rev_offs       = 0x30,
 902         .sysc_offs      = 0x34,
 903         .syss_offs      = 0x38,
 904         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 905 };
 906
 907 static struct omap_hwmod_class omap44xx_des_hwmod_class = {
 908         .name           = "des",
 909         .sysc           = &omap44xx_des_sysc,
 910 };
 911
 912 static struct omap_hwmod omap44xx_des_hwmod = {
 913         .name           = "des",
 914         .class          = &omap44xx_des_hwmod_class,
 915         .clkdm_name     = "l4_secure_clkdm",
 916         .main_clk       = "l3_div_ck",
 917         .prcm           = {
 918                 .omap4  = {
 919                         .context_offs   = OMAP4_RM_L4SEC_DES3DES_CONTEXT_OFFSET,
 920                         .clkctrl_offs   = OMAP4_CM_L4SEC_DES3DES_CLKCTRL_OFFSET,
 921                         .modulemode     = MODULEMODE_SWCTRL,
 922                 },
 923         },
 924 };
 925
 926 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__des = {
 927         .master         = &omap44xx_l3_main_2_hwmod,
 928         .slave          = &omap44xx_des_hwmod,
 929         .clk            = "l3_div_ck",
 930         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 931 };
 932
 933 /*
 934  * 'fdif' class
 935  * face detection hw accelerator module
 936  */
 937
 938 static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
 939         .rev_offs       = 0x0000,
 940         .sysc_offs      = 0x0010,
 941         /*
 942          * FDIF needs 100 OCP clk cycles delay after a softreset before
 943          * accessing sysconfig again.
 944          * The lowest frequency at the moment for L3 bus is 100 MHz, so
 945          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
 946          *
 947          * TODO: Indicate errata when available.
 948          */
 949         .srst_udelay    = 2,
 950         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
 951                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 952         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 953                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 954         .sysc_fields    = &omap_hwmod_sysc_type2,
 955 };
 956
 957 static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
 958         .name   = "fdif",
 959         .sysc   = &omap44xx_fdif_sysc,
 960 };
 961
 962 /* fdif */
 963 static struct omap_hwmod omap44xx_fdif_hwmod = {
 964         .name           = "fdif",
 965         .class          = &omap44xx_fdif_hwmod_class,
 966         .clkdm_name     = "iss_clkdm",
 967         .main_clk       = "fdif_fck",
 968         .prcm = {
 969                 .omap4 = {
 970                         .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
 971                         .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
 972                         .modulemode   = MODULEMODE_SWCTRL,
 973                 },
 974         },
 975 };
 976
 977 /*
 978  * 'gpmc' class
 979  * general purpose memory controller
 980  */
 981
 982 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
 983         .rev_offs       = 0x0000,
 984         .sysc_offs      = 0x0010,
 985         .syss_offs      = 0x0014,
 986         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 987                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 988         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 989         .sysc_fields    = &omap_hwmod_sysc_type1,
 990 };
 991
 992 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
 993         .name   = "gpmc",
 994         .sysc   = &omap44xx_gpmc_sysc,
 995 };
 996
 997 /* gpmc */
 998 static struct omap_hwmod omap44xx_gpmc_hwmod = {
 999         .name           = "gpmc",
1000         .class          = &omap44xx_gpmc_hwmod_class,
1001         .clkdm_name     = "l3_2_clkdm",
1002         /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
1003         .flags          = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
1004         .prcm = {
1005                 .omap4 = {
1006                         .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
1007                         .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
1008                         .modulemode   = MODULEMODE_HWCTRL,
1009                 },
1010         },
1011 };
1012
1013
1014 /*
1015  * 'hsi' class
1016  * mipi high-speed synchronous serial interface (multichannel and full-duplex
1017  * serial if)
1018  */
1019
1020 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
1021         .rev_offs       = 0x0000,
1022         .sysc_offs      = 0x0010,
1023         .syss_offs      = 0x0014,
1024         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
1025                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1026                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1027         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1028                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1029                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1030         .sysc_fields    = &omap_hwmod_sysc_type1,
1031 };
1032
1033 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
1034         .name   = "hsi",
1035         .sysc   = &omap44xx_hsi_sysc,
1036 };
1037
1038 /* hsi */
1039 static struct omap_hwmod omap44xx_hsi_hwmod = {
1040         .name           = "hsi",
1041         .class          = &omap44xx_hsi_hwmod_class,
1042         .clkdm_name     = "l3_init_clkdm",
1043         .main_clk       = "hsi_fck",
1044         .prcm = {
1045                 .omap4 = {
1046                         .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
1047                         .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
1048                         .modulemode   = MODULEMODE_HWCTRL,
1049                 },
1050         },
1051 };
1052
1053 /*
1054  * 'ipu' class
1055  * imaging processor unit
1056  */
1057
1058 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
1059         .name   = "ipu",
1060 };
1061
1062 /* ipu */
1063 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
1064         { .name = "cpu0", .rst_shift = 0 },
1065         { .name = "cpu1", .rst_shift = 1 },
1066 };
1067
1068 static struct omap_hwmod omap44xx_ipu_hwmod = {
1069         .name           = "ipu",
1070         .class          = &omap44xx_ipu_hwmod_class,
1071         .clkdm_name     = "ducati_clkdm",
1072         .rst_lines      = omap44xx_ipu_resets,
1073         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
1074         .main_clk       = "ducati_clk_mux_ck",
1075         .prcm = {
1076                 .omap4 = {
1077                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
1078                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
1079                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
1080                         .modulemode   = MODULEMODE_HWCTRL,
1081                 },
1082         },
1083 };
1084
1085 /*
1086  * 'iss' class
1087  * external images sensor pixel data processor
1088  */
1089
1090 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
1091         .rev_offs       = 0x0000,
1092         .sysc_offs      = 0x0010,
1093         /*
1094          * ISS needs 100 OCP clk cycles delay after a softreset before
1095          * accessing sysconfig again.
1096          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1097          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1098          *
1099          * TODO: Indicate errata when available.
1100          */
1101         .srst_udelay    = 2,
1102         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1103                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1104         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1105                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1106                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1107         .sysc_fields    = &omap_hwmod_sysc_type2,
1108 };
1109
1110 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
1111         .name   = "iss",
1112         .sysc   = &omap44xx_iss_sysc,
1113 };
1114
1115 /* iss */
1116 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
1117         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
1118 };
1119
1120 static struct omap_hwmod omap44xx_iss_hwmod = {
1121         .name           = "iss",
1122         .class          = &omap44xx_iss_hwmod_class,
1123         .clkdm_name     = "iss_clkdm",
1124         .main_clk       = "ducati_clk_mux_ck",
1125         .prcm = {
1126                 .omap4 = {
1127                         .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
1128                         .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
1129                         .modulemode   = MODULEMODE_SWCTRL,
1130                 },
1131         },
1132         .opt_clks       = iss_opt_clks,
1133         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
1134 };
1135
1136 /*
1137  * 'iva' class
1138  * multi-standard video encoder/decoder hardware accelerator
1139  */
1140
1141 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
1142         .name   = "iva",
1143 };
1144
1145 /* iva */
1146 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1147         { .name = "seq0", .rst_shift = 0 },
1148         { .name = "seq1", .rst_shift = 1 },
1149         { .name = "logic", .rst_shift = 2 },
1150 };
1151
1152 static struct omap_hwmod omap44xx_iva_hwmod = {
1153         .name           = "iva",
1154         .class          = &omap44xx_iva_hwmod_class,
1155         .clkdm_name     = "ivahd_clkdm",
1156         .rst_lines      = omap44xx_iva_resets,
1157         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
1158         .main_clk       = "dpll_iva_m5x2_ck",
1159         .prcm = {
1160                 .omap4 = {
1161                         .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
1162                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
1163                         .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
1164                         .modulemode   = MODULEMODE_HWCTRL,
1165                 },
1166         },
1167 };
1168
1169 /*
1170  * 'kbd' class
1171  * keyboard controller
1172  */
1173
1174 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
1175         .rev_offs       = 0x0000,
1176         .sysc_offs      = 0x0010,
1177         .syss_offs      = 0x0014,
1178         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1179                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
1180                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1181                            SYSS_HAS_RESET_STATUS),
1182         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1183         .sysc_fields    = &omap_hwmod_sysc_type1,
1184 };
1185
1186 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
1187         .name   = "kbd",
1188         .sysc   = &omap44xx_kbd_sysc,
1189 };
1190
1191 /* kbd */
1192 static struct omap_hwmod omap44xx_kbd_hwmod = {
1193         .name           = "kbd",
1194         .class          = &omap44xx_kbd_hwmod_class,
1195         .clkdm_name     = "l4_wkup_clkdm",
1196         .main_clk       = "sys_32k_ck",
1197         .prcm = {
1198                 .omap4 = {
1199                         .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
1200                         .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
1201                         .modulemode   = MODULEMODE_SWCTRL,
1202                 },
1203         },
1204 };
1205
1206
1207 /*
1208  * 'mcpdm' class
1209  * multi channel pdm controller (proprietary interface with phoenix power
1210  * ic)
1211  */
1212
1213 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
1214         .rev_offs       = 0x0000,
1215         .sysc_offs      = 0x0010,
1216         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1217                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1218         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1219                            SIDLE_SMART_WKUP),
1220         .sysc_fields    = &omap_hwmod_sysc_type2,
1221 };
1222
1223 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
1224         .name   = "mcpdm",
1225         .sysc   = &omap44xx_mcpdm_sysc,
1226 };
1227
1228 /* mcpdm */
1229 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
1230         .name           = "mcpdm",
1231         .class          = &omap44xx_mcpdm_hwmod_class,
1232         .clkdm_name     = "abe_clkdm",
1233         /*
1234          * It's suspected that the McPDM requires an off-chip main
1235          * functional clock, controlled via I2C.  This IP block is
1236          * currently reset very early during boot, before I2C is
1237          * available, so it doesn't seem that we have any choice in
1238          * the kernel other than to avoid resetting it.
1239          *
1240          * Also, McPDM needs to be configured to NO_IDLE mode when it
1241          * is in used otherwise vital clocks will be gated which
1242          * results 'slow motion' audio playback.
1243          */
1244         .flags          = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE,
1245         .main_clk       = "pad_clks_ck",
1246         .prcm = {
1247                 .omap4 = {
1248                         .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
1249                         .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
1250                         .modulemode   = MODULEMODE_SWCTRL,
1251                 },
1252         },
1253 };
1254
1255 /*
1256  * 'mmu' class
1257  * The memory management unit performs virtual to physical address translation
1258  * for its requestors.
1259  */
1260
1261 static struct omap_hwmod_class_sysconfig mmu_sysc = {
1262         .rev_offs       = 0x000,
1263         .sysc_offs      = 0x010,
1264         .syss_offs      = 0x014,
1265         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1266                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1267         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1268         .sysc_fields    = &omap_hwmod_sysc_type1,
1269 };
1270
1271 static struct omap_hwmod_class omap44xx_mmu_hwmod_class = {
1272         .name = "mmu",
1273         .sysc = &mmu_sysc,
1274 };
1275
1276 /* mmu ipu */
1277
1278 static struct omap_hwmod omap44xx_mmu_ipu_hwmod;
1279 static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = {
1280         { .name = "mmu_cache", .rst_shift = 2 },
1281 };
1282
1283 /* l3_main_2 -> mmu_ipu */
1284 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = {
1285         .master         = &omap44xx_l3_main_2_hwmod,
1286         .slave          = &omap44xx_mmu_ipu_hwmod,
1287         .clk            = "l3_div_ck",
1288         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1289 };
1290
1291 static struct omap_hwmod omap44xx_mmu_ipu_hwmod = {
1292         .name           = "mmu_ipu",
1293         .class          = &omap44xx_mmu_hwmod_class,
1294         .clkdm_name     = "ducati_clkdm",
1295         .rst_lines      = omap44xx_mmu_ipu_resets,
1296         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_ipu_resets),
1297         .main_clk       = "ducati_clk_mux_ck",
1298         .prcm = {
1299                 .omap4 = {
1300                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
1301                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
1302                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
1303                         .modulemode   = MODULEMODE_HWCTRL,
1304                 },
1305         },
1306 };
1307
1308 /* mmu dsp */
1309
1310 static struct omap_hwmod omap44xx_mmu_dsp_hwmod;
1311 static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = {
1312         { .name = "mmu_cache", .rst_shift = 1 },
1313 };
1314
1315 /* l4_cfg -> dsp */
1316 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = {
1317         .master         = &omap44xx_l4_cfg_hwmod,
1318         .slave          = &omap44xx_mmu_dsp_hwmod,
1319         .clk            = "l4_div_ck",
1320         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1321 };
1322
1323 static struct omap_hwmod omap44xx_mmu_dsp_hwmod = {
1324         .name           = "mmu_dsp",
1325         .class          = &omap44xx_mmu_hwmod_class,
1326         .clkdm_name     = "tesla_clkdm",
1327         .rst_lines      = omap44xx_mmu_dsp_resets,
1328         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_dsp_resets),
1329         .main_clk       = "dpll_iva_m4x2_ck",
1330         .prcm = {
1331                 .omap4 = {
1332                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
1333                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
1334                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
1335                         .modulemode   = MODULEMODE_HWCTRL,
1336                 },
1337         },
1338 };
1339
1340 /*
1341  * 'mpu' class
1342  * mpu sub-system
1343  */
1344
1345 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
1346         .name   = "mpu",
1347 };
1348
1349 /* mpu */
1350 static struct omap_hwmod omap44xx_mpu_hwmod = {
1351         .name           = "mpu",
1352         .class          = &omap44xx_mpu_hwmod_class,
1353         .clkdm_name     = "mpuss_clkdm",
1354         .flags          = HWMOD_INIT_NO_IDLE,
1355         .main_clk       = "dpll_mpu_m2_ck",
1356         .prcm = {
1357                 .omap4 = {
1358                         .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
1359                         .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
1360                 },
1361         },
1362 };
1363
1364 /*
1365  * 'ocmc_ram' class
1366  * top-level core on-chip ram
1367  */
1368
1369 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
1370         .name   = "ocmc_ram",
1371 };
1372
1373 /* ocmc_ram */
1374 static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
1375         .name           = "ocmc_ram",
1376         .class          = &omap44xx_ocmc_ram_hwmod_class,
1377         .clkdm_name     = "l3_2_clkdm",
1378         .prcm = {
1379                 .omap4 = {
1380                         .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
1381                         .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
1382                 },
1383         },
1384 };
1385
1386 /*
1387  * 'ocp2scp' class
1388  * bridge to transform ocp interface protocol to scp (serial control port)
1389  * protocol
1390  */
1391
1392 static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc = {
1393         .rev_offs       = 0x0000,
1394         .sysc_offs      = 0x0010,
1395         .syss_offs      = 0x0014,
1396         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1397                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1398         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1399         .sysc_fields    = &omap_hwmod_sysc_type1,
1400 };
1401
1402 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
1403         .name   = "ocp2scp",
1404         .sysc   = &omap44xx_ocp2scp_sysc,
1405 };
1406
1407 /* ocp2scp_usb_phy */
1408 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
1409         .name           = "ocp2scp_usb_phy",
1410         .class          = &omap44xx_ocp2scp_hwmod_class,
1411         .clkdm_name     = "l3_init_clkdm",
1412         /*
1413          * ocp2scp_usb_phy_phy_48m is provided by the OMAP4 PRCM IP
1414          * block as an "optional clock," and normally should never be
1415          * specified as the main_clk for an OMAP IP block.  However it
1416          * turns out that this clock is actually the main clock for
1417          * the ocp2scp_usb_phy IP block:
1418          * http://lists.infradead.org/pipermail/linux-arm-kernel/2012-September/119943.html
1419          * So listing ocp2scp_usb_phy_phy_48m as a main_clk here seems
1420          * to be the best workaround.
1421          */
1422         .main_clk       = "ocp2scp_usb_phy_phy_48m",
1423         .prcm = {
1424                 .omap4 = {
1425                         .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
1426                         .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
1427                         .modulemode   = MODULEMODE_HWCTRL,
1428                 },
1429         },
1430 };
1431
1432 /*
1433  * 'prcm' class
1434  * power and reset manager (part of the prcm infrastructure) + clock manager 2
1435  * + clock manager 1 (in always on power domain) + local prm in mpu
1436  */
1437
1438 static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
1439         .name   = "prcm",
1440 };
1441
1442 /* prcm_mpu */
1443 static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
1444         .name           = "prcm_mpu",
1445         .class          = &omap44xx_prcm_hwmod_class,
1446         .clkdm_name     = "l4_wkup_clkdm",
1447         .flags          = HWMOD_NO_IDLEST,
1448         .prcm = {
1449                 .omap4 = {
1450                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
1451                 },
1452         },
1453 };
1454
1455 /* cm_core_aon */
1456 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
1457         .name           = "cm_core_aon",
1458         .class          = &omap44xx_prcm_hwmod_class,
1459         .flags          = HWMOD_NO_IDLEST,
1460         .prcm = {
1461                 .omap4 = {
1462                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
1463                 },
1464         },
1465 };
1466
1467 /* cm_core */
1468 static struct omap_hwmod omap44xx_cm_core_hwmod = {
1469         .name           = "cm_core",
1470         .class          = &omap44xx_prcm_hwmod_class,
1471         .flags          = HWMOD_NO_IDLEST,
1472         .prcm = {
1473                 .omap4 = {
1474                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
1475                 },
1476         },
1477 };
1478
1479 /* prm */
1480 static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
1481         { .name = "rst_global_warm_sw", .rst_shift = 0 },
1482         { .name = "rst_global_cold_sw", .rst_shift = 1 },
1483 };
1484
1485 static struct omap_hwmod omap44xx_prm_hwmod = {
1486         .name           = "prm",
1487         .class          = &omap44xx_prcm_hwmod_class,
1488         .rst_lines      = omap44xx_prm_resets,
1489         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_prm_resets),
1490 };
1491
1492 /*
1493  * 'scrm' class
1494  * system clock and reset manager
1495  */
1496
1497 static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
1498         .name   = "scrm",
1499 };
1500
1501 /* scrm */
1502 static struct omap_hwmod omap44xx_scrm_hwmod = {
1503         .name           = "scrm",
1504         .class          = &omap44xx_scrm_hwmod_class,
1505         .clkdm_name     = "l4_wkup_clkdm",
1506         .prcm = {
1507                 .omap4 = {
1508                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
1509                 },
1510         },
1511 };
1512
1513 /*
1514  * 'sl2if' class
1515  * shared level 2 memory interface
1516  */
1517
1518 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
1519         .name   = "sl2if",
1520 };
1521
1522 /* sl2if */
1523 static struct omap_hwmod omap44xx_sl2if_hwmod = {
1524         .name           = "sl2if",
1525         .class          = &omap44xx_sl2if_hwmod_class,
1526         .clkdm_name     = "ivahd_clkdm",
1527         .prcm = {
1528                 .omap4 = {
1529                         .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
1530                         .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
1531                         .modulemode   = MODULEMODE_HWCTRL,
1532                 },
1533         },
1534 };
1535
1536 /*
1537  * 'slimbus' class
1538  * bidirectional, multi-drop, multi-channel two-line serial interface between
1539  * the device and external components
1540  */
1541
1542 static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
1543         .rev_offs       = 0x0000,
1544         .sysc_offs      = 0x0010,
1545         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1546                            SYSC_HAS_SOFTRESET),
1547         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1548                            SIDLE_SMART_WKUP),
1549         .sysc_fields    = &omap_hwmod_sysc_type2,
1550 };
1551
1552 static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
1553         .name   = "slimbus",
1554         .sysc   = &omap44xx_slimbus_sysc,
1555 };
1556
1557 /* slimbus1 */
1558 static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
1559         { .role = "fclk_1", .clk = "slimbus1_fclk_1" },
1560         { .role = "fclk_0", .clk = "slimbus1_fclk_0" },
1561         { .role = "fclk_2", .clk = "slimbus1_fclk_2" },
1562         { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
1563 };
1564
1565 static struct omap_hwmod omap44xx_slimbus1_hwmod = {
1566         .name           = "slimbus1",
1567         .class          = &omap44xx_slimbus_hwmod_class,
1568         .clkdm_name     = "abe_clkdm",
1569         .prcm = {
1570                 .omap4 = {
1571                         .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
1572                         .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
1573                         .modulemode   = MODULEMODE_SWCTRL,
1574                 },
1575         },
1576         .opt_clks       = slimbus1_opt_clks,
1577         .opt_clks_cnt   = ARRAY_SIZE(slimbus1_opt_clks),
1578 };
1579
1580 /* slimbus2 */
1581 static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
1582         { .role = "fclk_1", .clk = "slimbus2_fclk_1" },
1583         { .role = "fclk_0", .clk = "slimbus2_fclk_0" },
1584         { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
1585 };
1586
1587 static struct omap_hwmod omap44xx_slimbus2_hwmod = {
1588         .name           = "slimbus2",
1589         .class          = &omap44xx_slimbus_hwmod_class,
1590         .clkdm_name     = "l4_per_clkdm",
1591         .prcm = {
1592                 .omap4 = {
1593                         .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
1594                         .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
1595                         .modulemode   = MODULEMODE_SWCTRL,
1596                 },
1597         },
1598         .opt_clks       = slimbus2_opt_clks,
1599         .opt_clks_cnt   = ARRAY_SIZE(slimbus2_opt_clks),
1600 };
1601
1602 /*
1603  * 'smartreflex' class
1604  * smartreflex module (monitor silicon performance and outputs a measure of
1605  * performance error)
1606  */
1607
1608 /* The IP is not compliant to type1 / type2 scheme */
1609 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
1610         .rev_offs       = -ENODEV,
1611         .sysc_offs      = 0x0038,
1612         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
1613         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1614                            SIDLE_SMART_WKUP),
1615         .sysc_fields    = &omap36xx_sr_sysc_fields,
1616 };
1617
1618 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
1619         .name   = "smartreflex",
1620         .sysc   = &omap44xx_smartreflex_sysc,
1621 };
1622
1623 /* smartreflex_core */
1624 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
1625         .sensor_voltdm_name   = "core",
1626 };
1627
1628 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
1629         .name           = "smartreflex_core",
1630         .class          = &omap44xx_smartreflex_hwmod_class,
1631         .clkdm_name     = "l4_ao_clkdm",
1632
1633         .main_clk       = "smartreflex_core_fck",
1634         .prcm = {
1635                 .omap4 = {
1636                         .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
1637                         .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
1638                         .modulemode   = MODULEMODE_SWCTRL,
1639                 },
1640         },
1641         .dev_attr       = &smartreflex_core_dev_attr,
1642 };
1643
1644 /* smartreflex_iva */
1645 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
1646         .sensor_voltdm_name     = "iva",
1647 };
1648
1649 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
1650         .name           = "smartreflex_iva",
1651         .class          = &omap44xx_smartreflex_hwmod_class,
1652         .clkdm_name     = "l4_ao_clkdm",
1653         .main_clk       = "smartreflex_iva_fck",
1654         .prcm = {
1655                 .omap4 = {
1656                         .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
1657                         .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
1658                         .modulemode   = MODULEMODE_SWCTRL,
1659                 },
1660         },
1661         .dev_attr       = &smartreflex_iva_dev_attr,
1662 };
1663
1664 /* smartreflex_mpu */
1665 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
1666         .sensor_voltdm_name     = "mpu",
1667 };
1668
1669 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
1670         .name           = "smartreflex_mpu",
1671         .class          = &omap44xx_smartreflex_hwmod_class,
1672         .clkdm_name     = "l4_ao_clkdm",
1673         .main_clk       = "smartreflex_mpu_fck",
1674         .prcm = {
1675                 .omap4 = {
1676                         .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
1677                         .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
1678                         .modulemode   = MODULEMODE_SWCTRL,
1679                 },
1680         },
1681         .dev_attr       = &smartreflex_mpu_dev_attr,
1682 };
1683
1684 /*
1685  * 'spinlock' class
1686  * spinlock provides hardware assistance for synchronizing the processes
1687  * running on multiple processors
1688  */
1689
1690 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
1691         .rev_offs       = 0x0000,
1692         .sysc_offs      = 0x0010,
1693         .syss_offs      = 0x0014,
1694         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1695                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1696                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1697         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1698         .sysc_fields    = &omap_hwmod_sysc_type1,
1699 };
1700
1701 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
1702         .name   = "spinlock",
1703         .sysc   = &omap44xx_spinlock_sysc,
1704 };
1705
1706 /* spinlock */
1707 static struct omap_hwmod omap44xx_spinlock_hwmod = {
1708         .name           = "spinlock",
1709         .class          = &omap44xx_spinlock_hwmod_class,
1710         .clkdm_name     = "l4_cfg_clkdm",
1711         .prcm = {
1712                 .omap4 = {
1713                         .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
1714                         .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
1715                 },
1716         },
1717 };
1718
1719 /*
1720  * 'timer' class
1721  * general purpose timer module with accurate 1ms tick
1722  * This class contains several variants: ['timer_1ms', 'timer']
1723  */
1724
1725 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
1726         .rev_offs       = 0x0000,
1727         .sysc_offs      = 0x0010,
1728         .syss_offs      = 0x0014,
1729         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1730                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
1731                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1732                            SYSS_HAS_RESET_STATUS),
1733         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1734         .sysc_fields    = &omap_hwmod_sysc_type1,
1735 };
1736
1737 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
1738         .name   = "timer",
1739         .sysc   = &omap44xx_timer_1ms_sysc,
1740 };
1741
1742 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
1743         .rev_offs       = 0x0000,
1744         .sysc_offs      = 0x0010,
1745         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1746                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1747         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1748                            SIDLE_SMART_WKUP),
1749         .sysc_fields    = &omap_hwmod_sysc_type2,
1750 };
1751
1752 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
1753         .name   = "timer",
1754         .sysc   = &omap44xx_timer_sysc,
1755 };
1756
1757 /* timer1 */
1758 static struct omap_hwmod omap44xx_timer1_hwmod = {
1759         .name           = "timer1",
1760         .class          = &omap44xx_timer_1ms_hwmod_class,
1761         .clkdm_name     = "l4_wkup_clkdm",
1762         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1763         .main_clk       = "dmt1_clk_mux",
1764         .prcm = {
1765                 .omap4 = {
1766                         .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
1767                         .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
1768                         .modulemode   = MODULEMODE_SWCTRL,
1769                 },
1770         },
1771 };
1772
1773 /* timer2 */
1774 static struct omap_hwmod omap44xx_timer2_hwmod = {
1775         .name           = "timer2",
1776         .class          = &omap44xx_timer_1ms_hwmod_class,
1777         .clkdm_name     = "l4_per_clkdm",
1778         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1779         .main_clk       = "cm2_dm2_mux",
1780         .prcm = {
1781                 .omap4 = {
1782                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
1783                         .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
1784                         .modulemode   = MODULEMODE_SWCTRL,
1785                 },
1786         },
1787 };
1788
1789 /* timer3 */
1790 static struct omap_hwmod omap44xx_timer3_hwmod = {
1791         .name           = "timer3",
1792         .class          = &omap44xx_timer_hwmod_class,
1793         .clkdm_name     = "l4_per_clkdm",
1794         .main_clk       = "cm2_dm3_mux",
1795         .prcm = {
1796                 .omap4 = {
1797                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
1798                         .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
1799                         .modulemode   = MODULEMODE_SWCTRL,
1800                 },
1801         },
1802 };
1803
1804 /* timer4 */
1805 static struct omap_hwmod omap44xx_timer4_hwmod = {
1806         .name           = "timer4",
1807         .class          = &omap44xx_timer_hwmod_class,
1808         .clkdm_name     = "l4_per_clkdm",
1809         .main_clk       = "cm2_dm4_mux",
1810         .prcm = {
1811                 .omap4 = {
1812                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
1813                         .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
1814                         .modulemode   = MODULEMODE_SWCTRL,
1815                 },
1816         },
1817 };
1818
1819 /* timer5 */
1820 static struct omap_hwmod omap44xx_timer5_hwmod = {
1821         .name           = "timer5",
1822         .class          = &omap44xx_timer_hwmod_class,
1823         .clkdm_name     = "abe_clkdm",
1824         .main_clk       = "timer5_sync_mux",
1825         .prcm = {
1826                 .omap4 = {
1827                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
1828                         .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
1829                         .modulemode   = MODULEMODE_SWCTRL,
1830                 },
1831         },
1832 };
1833
1834 /* timer6 */
1835 static struct omap_hwmod omap44xx_timer6_hwmod = {
1836         .name           = "timer6",
1837         .class          = &omap44xx_timer_hwmod_class,
1838         .clkdm_name     = "abe_clkdm",
1839         .main_clk       = "timer6_sync_mux",
1840         .prcm = {
1841                 .omap4 = {
1842                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
1843                         .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
1844                         .modulemode   = MODULEMODE_SWCTRL,
1845                 },
1846         },
1847 };
1848
1849 /* timer7 */
1850 static struct omap_hwmod omap44xx_timer7_hwmod = {
1851         .name           = "timer7",
1852         .class          = &omap44xx_timer_hwmod_class,
1853         .clkdm_name     = "abe_clkdm",
1854         .main_clk       = "timer7_sync_mux",
1855         .prcm = {
1856                 .omap4 = {
1857                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
1858                         .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
1859                         .modulemode   = MODULEMODE_SWCTRL,
1860                 },
1861         },
1862 };
1863
1864 /* timer8 */
1865 static struct omap_hwmod omap44xx_timer8_hwmod = {
1866         .name           = "timer8",
1867         .class          = &omap44xx_timer_hwmod_class,
1868         .clkdm_name     = "abe_clkdm",
1869         .main_clk       = "timer8_sync_mux",
1870         .prcm = {
1871                 .omap4 = {
1872                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
1873                         .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
1874                         .modulemode   = MODULEMODE_SWCTRL,
1875                 },
1876         },
1877 };
1878
1879 /* timer9 */
1880 static struct omap_hwmod omap44xx_timer9_hwmod = {
1881         .name           = "timer9",
1882         .class          = &omap44xx_timer_hwmod_class,
1883         .clkdm_name     = "l4_per_clkdm",
1884         .main_clk       = "cm2_dm9_mux",
1885         .prcm = {
1886                 .omap4 = {
1887                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
1888                         .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
1889                         .modulemode   = MODULEMODE_SWCTRL,
1890                 },
1891         },
1892 };
1893
1894 /* timer10 */
1895 static struct omap_hwmod omap44xx_timer10_hwmod = {
1896         .name           = "timer10",
1897         .class          = &omap44xx_timer_1ms_hwmod_class,
1898         .clkdm_name     = "l4_per_clkdm",
1899         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1900         .main_clk       = "cm2_dm10_mux",
1901         .prcm = {
1902                 .omap4 = {
1903                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
1904                         .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
1905                         .modulemode   = MODULEMODE_SWCTRL,
1906                 },
1907         },
1908 };
1909
1910 /* timer11 */
1911 static struct omap_hwmod omap44xx_timer11_hwmod = {
1912         .name           = "timer11",
1913         .class          = &omap44xx_timer_hwmod_class,
1914         .clkdm_name     = "l4_per_clkdm",
1915         .main_clk       = "cm2_dm11_mux",
1916         .prcm = {
1917                 .omap4 = {
1918                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
1919                         .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
1920                         .modulemode   = MODULEMODE_SWCTRL,
1921                 },
1922         },
1923 };
1924
1925 /*
1926  * 'usb_host_fs' class
1927  * full-speed usb host controller
1928  */
1929
1930 /* The IP is not compliant to type1 / type2 scheme */
1931 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
1932         .rev_offs       = 0x0000,
1933         .sysc_offs      = 0x0210,
1934         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1935                            SYSC_HAS_SOFTRESET),
1936         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1937                            SIDLE_SMART_WKUP),
1938         .sysc_fields    = &omap_hwmod_sysc_type_usb_host_fs,
1939 };
1940
1941 static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
1942         .name   = "usb_host_fs",
1943         .sysc   = &omap44xx_usb_host_fs_sysc,
1944 };
1945
1946 /* usb_host_fs */
1947 static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
1948         .name           = "usb_host_fs",
1949         .class          = &omap44xx_usb_host_fs_hwmod_class,
1950         .clkdm_name     = "l3_init_clkdm",
1951         .main_clk       = "usb_host_fs_fck",
1952         .prcm = {
1953                 .omap4 = {
1954                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
1955                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
1956                         .modulemode   = MODULEMODE_SWCTRL,
1957                 },
1958         },
1959 };
1960
1961 /*
1962  * 'usb_host_hs' class
1963  * high-speed multi-port usb host controller
1964  */
1965
1966 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
1967         .rev_offs       = 0x0000,
1968         .sysc_offs      = 0x0010,
1969         .syss_offs      = 0x0014,
1970         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1971                            SYSC_HAS_SOFTRESET | SYSC_HAS_RESET_STATUS),
1972         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1973                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1974                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1975         .sysc_fields    = &omap_hwmod_sysc_type2,
1976 };
1977
1978 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
1979         .name   = "usb_host_hs",
1980         .sysc   = &omap44xx_usb_host_hs_sysc,
1981 };
1982
1983 /* usb_host_hs */
1984 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
1985         .name           = "usb_host_hs",
1986         .class          = &omap44xx_usb_host_hs_hwmod_class,
1987         .clkdm_name     = "l3_init_clkdm",
1988         .main_clk       = "usb_host_hs_fck",
1989         .prcm = {
1990                 .omap4 = {
1991                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
1992                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
1993                         .modulemode   = MODULEMODE_SWCTRL,
1994                 },
1995         },
1996
1997         /*
1998          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
1999          * id: i660
2000          *
2001          * Description:
2002          * In the following configuration :
2003          * - USBHOST module is set to smart-idle mode
2004          * - PRCM asserts idle_req to the USBHOST module ( This typically
2005          *   happens when the system is going to a low power mode : all ports
2006          *   have been suspended, the master part of the USBHOST module has
2007          *   entered the standby state, and SW has cut the functional clocks)
2008          * - an USBHOST interrupt occurs before the module is able to answer
2009          *   idle_ack, typically a remote wakeup IRQ.
2010          * Then the USB HOST module will enter a deadlock situation where it
2011          * is no more accessible nor functional.
2012          *
2013          * Workaround:
2014          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
2015          */
2016
2017         /*
2018          * Errata: USB host EHCI may stall when entering smart-standby mode
2019          * Id: i571
2020          *
2021          * Description:
2022          * When the USBHOST module is set to smart-standby mode, and when it is
2023          * ready to enter the standby state (i.e. all ports are suspended and
2024          * all attached devices are in suspend mode), then it can wrongly assert
2025          * the Mstandby signal too early while there are still some residual OCP
2026          * transactions ongoing. If this condition occurs, the internal state
2027          * machine may go to an undefined state and the USB link may be stuck
2028          * upon the next resume.
2029          *
2030          * Workaround:
2031          * Don't use smart standby; use only force standby,
2032          * hence HWMOD_SWSUP_MSTANDBY
2033          */
2034
2035         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2036 };
2037
2038 /*
2039  * 'usb_tll_hs' class
2040  * usb_tll_hs module is the adapter on the usb_host_hs ports
2041  */
2042
2043 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
2044         .rev_offs       = 0x0000,
2045         .sysc_offs      = 0x0010,
2046         .syss_offs      = 0x0014,
2047         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2048                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2049                            SYSC_HAS_AUTOIDLE),
2050         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2051         .sysc_fields    = &omap_hwmod_sysc_type1,
2052 };
2053
2054 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
2055         .name   = "usb_tll_hs",
2056         .sysc   = &omap44xx_usb_tll_hs_sysc,
2057 };
2058
2059 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
2060         .name           = "usb_tll_hs",
2061         .class          = &omap44xx_usb_tll_hs_hwmod_class,
2062         .clkdm_name     = "l3_init_clkdm",
2063         .main_clk       = "usb_tll_hs_ick",
2064         .prcm = {
2065                 .omap4 = {
2066                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
2067                         .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
2068                         .modulemode   = MODULEMODE_HWCTRL,
2069                 },
2070         },
2071 };
2072
2073 /*
2074  * interfaces
2075  */
2076
2077 /* l3_main_1 -> dmm */
2078 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
2079         .master         = &omap44xx_l3_main_1_hwmod,
2080         .slave          = &omap44xx_dmm_hwmod,
2081         .clk            = "l3_div_ck",
2082         .user           = OCP_USER_SDMA,
2083 };
2084
2085 /* mpu -> dmm */
2086 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
2087         .master         = &omap44xx_mpu_hwmod,
2088         .slave          = &omap44xx_dmm_hwmod,
2089         .clk            = "l3_div_ck",
2090         .user           = OCP_USER_MPU,
2091 };
2092
2093 /* iva -> l3_instr */
2094 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
2095         .master         = &omap44xx_iva_hwmod,
2096         .slave          = &omap44xx_l3_instr_hwmod,
2097         .clk            = "l3_div_ck",
2098         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2099 };
2100
2101 /* l3_main_3 -> l3_instr */
2102 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
2103         .master         = &omap44xx_l3_main_3_hwmod,
2104         .slave          = &omap44xx_l3_instr_hwmod,
2105         .clk            = "l3_div_ck",
2106         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2107 };
2108
2109 /* ocp_wp_noc -> l3_instr */
2110 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
2111         .master         = &omap44xx_ocp_wp_noc_hwmod,
2112         .slave          = &omap44xx_l3_instr_hwmod,
2113         .clk            = "l3_div_ck",
2114         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2115 };
2116
2117 /* dsp -> l3_main_1 */
2118 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
2119         .master         = &omap44xx_dsp_hwmod,
2120         .slave          = &omap44xx_l3_main_1_hwmod,
2121         .clk            = "l3_div_ck",
2122         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2123 };
2124
2125 /* dss -> l3_main_1 */
2126 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
2127         .master         = &omap44xx_dss_hwmod,
2128         .slave          = &omap44xx_l3_main_1_hwmod,
2129         .clk            = "l3_div_ck",
2130         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2131 };
2132
2133 /* l3_main_2 -> l3_main_1 */
2134 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
2135         .master         = &omap44xx_l3_main_2_hwmod,
2136         .slave          = &omap44xx_l3_main_1_hwmod,
2137         .clk            = "l3_div_ck",
2138         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2139 };
2140
2141 /* l4_cfg -> l3_main_1 */
2142 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
2143         .master         = &omap44xx_l4_cfg_hwmod,
2144         .slave          = &omap44xx_l3_main_1_hwmod,
2145         .clk            = "l4_div_ck",
2146         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2147 };
2148
2149 /* mpu -> l3_main_1 */
2150 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
2151         .master         = &omap44xx_mpu_hwmod,
2152         .slave          = &omap44xx_l3_main_1_hwmod,
2153         .clk            = "l3_div_ck",
2154         .user           = OCP_USER_MPU,
2155 };
2156
2157 /* debugss -> l3_main_2 */
2158 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
2159         .master         = &omap44xx_debugss_hwmod,
2160         .slave          = &omap44xx_l3_main_2_hwmod,
2161         .clk            = "dbgclk_mux_ck",
2162         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2163 };
2164
2165 /* fdif -> l3_main_2 */
2166 static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
2167         .master         = &omap44xx_fdif_hwmod,
2168         .slave          = &omap44xx_l3_main_2_hwmod,
2169         .clk            = "l3_div_ck",
2170         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2171 };
2172
2173 /* hsi -> l3_main_2 */
2174 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
2175         .master         = &omap44xx_hsi_hwmod,
2176         .slave          = &omap44xx_l3_main_2_hwmod,
2177         .clk            = "l3_div_ck",
2178         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2179 };
2180
2181 /* ipu -> l3_main_2 */
2182 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
2183         .master         = &omap44xx_ipu_hwmod,
2184         .slave          = &omap44xx_l3_main_2_hwmod,
2185         .clk            = "l3_div_ck",
2186         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2187 };
2188
2189 /* iss -> l3_main_2 */
2190 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
2191         .master         = &omap44xx_iss_hwmod,
2192         .slave          = &omap44xx_l3_main_2_hwmod,
2193         .clk            = "l3_div_ck",
2194         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2195 };
2196
2197 /* iva -> l3_main_2 */
2198 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
2199         .master         = &omap44xx_iva_hwmod,
2200         .slave          = &omap44xx_l3_main_2_hwmod,
2201         .clk            = "l3_div_ck",
2202         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2203 };
2204
2205 /* l3_main_1 -> l3_main_2 */
2206 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
2207         .master         = &omap44xx_l3_main_1_hwmod,
2208         .slave          = &omap44xx_l3_main_2_hwmod,
2209         .clk            = "l3_div_ck",
2210         .user           = OCP_USER_MPU,
2211 };
2212
2213 /* l4_cfg -> l3_main_2 */
2214 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
2215         .master         = &omap44xx_l4_cfg_hwmod,
2216         .slave          = &omap44xx_l3_main_2_hwmod,
2217         .clk            = "l4_div_ck",
2218         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2219 };
2220
2221 /* usb_host_fs -> l3_main_2 */
2222 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = {
2223         .master         = &omap44xx_usb_host_fs_hwmod,
2224         .slave          = &omap44xx_l3_main_2_hwmod,
2225         .clk            = "l3_div_ck",
2226         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2227 };
2228
2229 /* usb_host_hs -> l3_main_2 */
2230 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
2231         .master         = &omap44xx_usb_host_hs_hwmod,
2232         .slave          = &omap44xx_l3_main_2_hwmod,
2233         .clk            = "l3_div_ck",
2234         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2235 };
2236
2237 /* l3_main_1 -> l3_main_3 */
2238 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
2239         .master         = &omap44xx_l3_main_1_hwmod,
2240         .slave          = &omap44xx_l3_main_3_hwmod,
2241         .clk            = "l3_div_ck",
2242         .user           = OCP_USER_MPU,
2243 };
2244
2245 /* l3_main_2 -> l3_main_3 */
2246 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
2247         .master         = &omap44xx_l3_main_2_hwmod,
2248         .slave          = &omap44xx_l3_main_3_hwmod,
2249         .clk            = "l3_div_ck",
2250         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2251 };
2252
2253 /* l4_cfg -> l3_main_3 */
2254 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
2255         .master         = &omap44xx_l4_cfg_hwmod,
2256         .slave          = &omap44xx_l3_main_3_hwmod,
2257         .clk            = "l4_div_ck",
2258         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2259 };
2260
2261 /* aess -> l4_abe */
2262 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe = {
2263         .master         = &omap44xx_aess_hwmod,
2264         .slave          = &omap44xx_l4_abe_hwmod,
2265         .clk            = "ocp_abe_iclk",
2266         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2267 };
2268
2269 /* dsp -> l4_abe */
2270 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
2271         .master         = &omap44xx_dsp_hwmod,
2272         .slave          = &omap44xx_l4_abe_hwmod,
2273         .clk            = "ocp_abe_iclk",
2274         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2275 };
2276
2277 /* l3_main_1 -> l4_abe */
2278 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
2279         .master         = &omap44xx_l3_main_1_hwmod,
2280         .slave          = &omap44xx_l4_abe_hwmod,
2281         .clk            = "l3_div_ck",
2282         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2283 };
2284
2285 /* mpu -> l4_abe */
2286 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
2287         .master         = &omap44xx_mpu_hwmod,
2288         .slave          = &omap44xx_l4_abe_hwmod,
2289         .clk            = "ocp_abe_iclk",
2290         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2291 };
2292
2293 /* l3_main_1 -> l4_cfg */
2294 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
2295         .master         = &omap44xx_l3_main_1_hwmod,
2296         .slave          = &omap44xx_l4_cfg_hwmod,
2297         .clk            = "l3_div_ck",
2298         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2299 };
2300
2301 /* l3_main_2 -> l4_per */
2302 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
2303         .master         = &omap44xx_l3_main_2_hwmod,
2304         .slave          = &omap44xx_l4_per_hwmod,
2305         .clk            = "l3_div_ck",
2306         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2307 };
2308
2309 /* l4_cfg -> l4_wkup */
2310 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
2311         .master         = &omap44xx_l4_cfg_hwmod,
2312         .slave          = &omap44xx_l4_wkup_hwmod,
2313         .clk            = "l4_div_ck",
2314         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2315 };
2316
2317 /* mpu -> mpu_private */
2318 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
2319         .master         = &omap44xx_mpu_hwmod,
2320         .slave          = &omap44xx_mpu_private_hwmod,
2321         .clk            = "l3_div_ck",
2322         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2323 };
2324
2325 /* l4_cfg -> ocp_wp_noc */
2326 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
2327         .master         = &omap44xx_l4_cfg_hwmod,
2328         .slave          = &omap44xx_ocp_wp_noc_hwmod,
2329         .clk            = "l4_div_ck",
2330         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2331 };
2332
2333 /* l4_abe -> aess */
2334 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = {
2335         .master         = &omap44xx_l4_abe_hwmod,
2336         .slave          = &omap44xx_aess_hwmod,
2337         .clk            = "ocp_abe_iclk",
2338         .user           = OCP_USER_MPU,
2339 };
2340
2341 /* l4_abe -> aess (dma) */
2342 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = {
2343         .master         = &omap44xx_l4_abe_hwmod,
2344         .slave          = &omap44xx_aess_hwmod,
2345         .clk            = "ocp_abe_iclk",
2346         .user           = OCP_USER_SDMA,
2347 };
2348
2349 /* l4_wkup -> counter_32k */
2350 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
2351         .master         = &omap44xx_l4_wkup_hwmod,
2352         .slave          = &omap44xx_counter_32k_hwmod,
2353         .clk            = "l4_wkup_clk_mux_ck",
2354         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2355 };
2356
2357 /* l4_cfg -> ctrl_module_core */
2358 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
2359         .master         = &omap44xx_l4_cfg_hwmod,
2360         .slave          = &omap44xx_ctrl_module_core_hwmod,
2361         .clk            = "l4_div_ck",
2362         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2363 };
2364
2365 /* l4_cfg -> ctrl_module_pad_core */
2366 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
2367         .master         = &omap44xx_l4_cfg_hwmod,
2368         .slave          = &omap44xx_ctrl_module_pad_core_hwmod,
2369         .clk            = "l4_div_ck",
2370         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2371 };
2372
2373 /* l4_wkup -> ctrl_module_wkup */
2374 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
2375         .master         = &omap44xx_l4_wkup_hwmod,
2376         .slave          = &omap44xx_ctrl_module_wkup_hwmod,
2377         .clk            = "l4_wkup_clk_mux_ck",
2378         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2379 };
2380
2381 /* l4_wkup -> ctrl_module_pad_wkup */
2382 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
2383         .master         = &omap44xx_l4_wkup_hwmod,
2384         .slave          = &omap44xx_ctrl_module_pad_wkup_hwmod,
2385         .clk            = "l4_wkup_clk_mux_ck",
2386         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2387 };
2388
2389 /* l3_instr -> debugss */
2390 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
2391         .master         = &omap44xx_l3_instr_hwmod,
2392         .slave          = &omap44xx_debugss_hwmod,
2393         .clk            = "l3_div_ck",
2394         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2395 };
2396
2397 /* l4_abe -> dmic */
2398 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
2399         .master         = &omap44xx_l4_abe_hwmod,
2400         .slave          = &omap44xx_dmic_hwmod,
2401         .clk            = "ocp_abe_iclk",
2402         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2403 };
2404
2405 /* dsp -> iva */
2406 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
2407         .master         = &omap44xx_dsp_hwmod,
2408         .slave          = &omap44xx_iva_hwmod,
2409         .clk            = "dpll_iva_m5x2_ck",
2410         .user           = OCP_USER_DSP,
2411 };
2412
2413 /* dsp -> sl2if */
2414 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = {
2415         .master         = &omap44xx_dsp_hwmod,
2416         .slave          = &omap44xx_sl2if_hwmod,
2417         .clk            = "dpll_iva_m5x2_ck",
2418         .user           = OCP_USER_DSP,
2419 };
2420
2421 /* l4_cfg -> dsp */
2422 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
2423         .master         = &omap44xx_l4_cfg_hwmod,
2424         .slave          = &omap44xx_dsp_hwmod,
2425         .clk            = "l4_div_ck",
2426         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2427 };
2428
2429 /* l3_main_2 -> dss */
2430 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
2431         .master         = &omap44xx_l3_main_2_hwmod,
2432         .slave          = &omap44xx_dss_hwmod,
2433         .clk            = "l3_div_ck",
2434         .user           = OCP_USER_SDMA,
2435 };
2436
2437 /* l4_per -> dss */
2438 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
2439         .master         = &omap44xx_l4_per_hwmod,
2440         .slave          = &omap44xx_dss_hwmod,
2441         .clk            = "l4_div_ck",
2442         .user           = OCP_USER_MPU,
2443 };
2444
2445 /* l3_main_2 -> dss_dispc */
2446 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
2447         .master         = &omap44xx_l3_main_2_hwmod,
2448         .slave          = &omap44xx_dss_dispc_hwmod,
2449         .clk            = "l3_div_ck",
2450         .user           = OCP_USER_SDMA,
2451 };
2452
2453 /* l4_per -> dss_dispc */
2454 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
2455         .master         = &omap44xx_l4_per_hwmod,
2456         .slave          = &omap44xx_dss_dispc_hwmod,
2457         .clk            = "l4_div_ck",
2458         .user           = OCP_USER_MPU,
2459 };
2460
2461 /* l3_main_2 -> dss_dsi1 */
2462 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
2463         .master         = &omap44xx_l3_main_2_hwmod,
2464         .slave          = &omap44xx_dss_dsi1_hwmod,
2465         .clk            = "l3_div_ck",
2466         .user           = OCP_USER_SDMA,
2467 };
2468
2469 /* l4_per -> dss_dsi1 */
2470 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
2471         .master         = &omap44xx_l4_per_hwmod,
2472         .slave          = &omap44xx_dss_dsi1_hwmod,
2473         .clk            = "l4_div_ck",
2474         .user           = OCP_USER_MPU,
2475 };
2476
2477 /* l3_main_2 -> dss_dsi2 */
2478 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
2479         .master         = &omap44xx_l3_main_2_hwmod,
2480         .slave          = &omap44xx_dss_dsi2_hwmod,
2481         .clk            = "l3_div_ck",
2482         .user           = OCP_USER_SDMA,
2483 };
2484
2485 /* l4_per -> dss_dsi2 */
2486 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
2487         .master         = &omap44xx_l4_per_hwmod,
2488         .slave          = &omap44xx_dss_dsi2_hwmod,
2489         .clk            = "l4_div_ck",
2490         .user           = OCP_USER_MPU,
2491 };
2492
2493 /* l3_main_2 -> dss_hdmi */
2494 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
2495         .master         = &omap44xx_l3_main_2_hwmod,
2496         .slave          = &omap44xx_dss_hdmi_hwmod,
2497         .clk            = "l3_div_ck",
2498         .user           = OCP_USER_SDMA,
2499 };
2500
2501 /* l4_per -> dss_hdmi */
2502 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
2503         .master         = &omap44xx_l4_per_hwmod,
2504         .slave          = &omap44xx_dss_hdmi_hwmod,
2505         .clk            = "l4_div_ck",
2506         .user           = OCP_USER_MPU,
2507 };
2508
2509 /* l3_main_2 -> dss_rfbi */
2510 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
2511         .master         = &omap44xx_l3_main_2_hwmod,
2512         .slave          = &omap44xx_dss_rfbi_hwmod,
2513         .clk            = "l3_div_ck",
2514         .user           = OCP_USER_SDMA,
2515 };
2516
2517 /* l4_per -> dss_rfbi */
2518 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
2519         .master         = &omap44xx_l4_per_hwmod,
2520         .slave          = &omap44xx_dss_rfbi_hwmod,
2521         .clk            = "l4_div_ck",
2522         .user           = OCP_USER_MPU,
2523 };
2524
2525 /* l3_main_2 -> dss_venc */
2526 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
2527         .master         = &omap44xx_l3_main_2_hwmod,
2528         .slave          = &omap44xx_dss_venc_hwmod,
2529         .clk            = "l3_div_ck",
2530         .user           = OCP_USER_SDMA,
2531 };
2532
2533 /* l4_per -> dss_venc */
2534 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
2535         .master         = &omap44xx_l4_per_hwmod,
2536         .slave          = &omap44xx_dss_venc_hwmod,
2537         .clk            = "l4_div_ck",
2538         .user           = OCP_USER_MPU,
2539 };
2540
2541 /* l3_main_2 -> sham */
2542 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__sha0 = {
2543         .master         = &omap44xx_l3_main_2_hwmod,
2544         .slave          = &omap44xx_sha0_hwmod,
2545         .clk            = "l3_div_ck",
2546         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2547 };
2548
2549 /* l4_per -> elm */
2550 static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
2551         .master         = &omap44xx_l4_per_hwmod,
2552         .slave          = &omap44xx_elm_hwmod,
2553         .clk            = "l4_div_ck",
2554         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2555 };
2556
2557 /* l4_cfg -> fdif */
2558 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
2559         .master         = &omap44xx_l4_cfg_hwmod,
2560         .slave          = &omap44xx_fdif_hwmod,
2561         .clk            = "l4_div_ck",
2562         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2563 };
2564
2565 /* l3_main_2 -> gpmc */
2566 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
2567         .master         = &omap44xx_l3_main_2_hwmod,
2568         .slave          = &omap44xx_gpmc_hwmod,
2569         .clk            = "l3_div_ck",
2570         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2571 };
2572
2573 /* l4_cfg -> hsi */
2574 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
2575         .master         = &omap44xx_l4_cfg_hwmod,
2576         .slave          = &omap44xx_hsi_hwmod,
2577         .clk            = "l4_div_ck",
2578         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2579 };
2580
2581 /* l3_main_2 -> ipu */
2582 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
2583         .master         = &omap44xx_l3_main_2_hwmod,
2584         .slave          = &omap44xx_ipu_hwmod,
2585         .clk            = "l3_div_ck",
2586         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2587 };
2588
2589 /* l3_main_2 -> iss */
2590 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
2591         .master         = &omap44xx_l3_main_2_hwmod,
2592         .slave          = &omap44xx_iss_hwmod,
2593         .clk            = "l3_div_ck",
2594         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2595 };
2596
2597 /* iva -> sl2if */
2598 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
2599         .master         = &omap44xx_iva_hwmod,
2600         .slave          = &omap44xx_sl2if_hwmod,
2601         .clk            = "dpll_iva_m5x2_ck",
2602         .user           = OCP_USER_IVA,
2603 };
2604
2605 /* l3_main_2 -> iva */
2606 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
2607         .master         = &omap44xx_l3_main_2_hwmod,
2608         .slave          = &omap44xx_iva_hwmod,
2609         .clk            = "l3_div_ck",
2610         .user           = OCP_USER_MPU,
2611 };
2612
2613 /* l4_wkup -> kbd */
2614 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
2615         .master         = &omap44xx_l4_wkup_hwmod,
2616         .slave          = &omap44xx_kbd_hwmod,
2617         .clk            = "l4_wkup_clk_mux_ck",
2618         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2619 };
2620
2621 /* l4_abe -> mcpdm */
2622 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
2623         .master         = &omap44xx_l4_abe_hwmod,
2624         .slave          = &omap44xx_mcpdm_hwmod,
2625         .clk            = "ocp_abe_iclk",
2626         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2627 };
2628
2629 /* l3_main_2 -> ocmc_ram */
2630 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
2631         .master         = &omap44xx_l3_main_2_hwmod,
2632         .slave          = &omap44xx_ocmc_ram_hwmod,
2633         .clk            = "l3_div_ck",
2634         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2635 };
2636
2637 /* l4_cfg -> ocp2scp_usb_phy */
2638 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
2639         .master         = &omap44xx_l4_cfg_hwmod,
2640         .slave          = &omap44xx_ocp2scp_usb_phy_hwmod,
2641         .clk            = "l4_div_ck",
2642         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2643 };
2644
2645 /* mpu_private -> prcm_mpu */
2646 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
2647         .master         = &omap44xx_mpu_private_hwmod,
2648         .slave          = &omap44xx_prcm_mpu_hwmod,
2649         .clk            = "l3_div_ck",
2650         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2651 };
2652
2653 /* l4_wkup -> cm_core_aon */
2654 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
2655         .master         = &omap44xx_l4_wkup_hwmod,
2656         .slave          = &omap44xx_cm_core_aon_hwmod,
2657         .clk            = "l4_wkup_clk_mux_ck",
2658         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2659 };
2660
2661 /* l4_cfg -> cm_core */
2662 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
2663         .master         = &omap44xx_l4_cfg_hwmod,
2664         .slave          = &omap44xx_cm_core_hwmod,
2665         .clk            = "l4_div_ck",
2666         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2667 };
2668
2669 /* l4_wkup -> prm */
2670 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
2671         .master         = &omap44xx_l4_wkup_hwmod,
2672         .slave          = &omap44xx_prm_hwmod,
2673         .clk            = "l4_wkup_clk_mux_ck",
2674         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2675 };
2676
2677 /* l4_wkup -> scrm */
2678 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
2679         .master         = &omap44xx_l4_wkup_hwmod,
2680         .slave          = &omap44xx_scrm_hwmod,
2681         .clk            = "l4_wkup_clk_mux_ck",
2682         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2683 };
2684
2685 /* l3_main_2 -> sl2if */
2686 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
2687         .master         = &omap44xx_l3_main_2_hwmod,
2688         .slave          = &omap44xx_sl2if_hwmod,
2689         .clk            = "l3_div_ck",
2690         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2691 };
2692
2693 /* l4_abe -> slimbus1 */
2694 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
2695         .master         = &omap44xx_l4_abe_hwmod,
2696         .slave          = &omap44xx_slimbus1_hwmod,
2697         .clk            = "ocp_abe_iclk",
2698         .user           = OCP_USER_MPU,
2699 };
2700
2701 /* l4_abe -> slimbus1 (dma) */
2702 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
2703         .master         = &omap44xx_l4_abe_hwmod,
2704         .slave          = &omap44xx_slimbus1_hwmod,
2705         .clk            = "ocp_abe_iclk",
2706         .user           = OCP_USER_SDMA,
2707 };
2708
2709 /* l4_per -> slimbus2 */
2710 static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
2711         .master         = &omap44xx_l4_per_hwmod,
2712         .slave          = &omap44xx_slimbus2_hwmod,
2713         .clk            = "l4_div_ck",
2714         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2715 };
2716
2717 /* l4_cfg -> smartreflex_core */
2718 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
2719         .master         = &omap44xx_l4_cfg_hwmod,
2720         .slave          = &omap44xx_smartreflex_core_hwmod,
2721         .clk            = "l4_div_ck",
2722         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2723 };
2724
2725 /* l4_cfg -> smartreflex_iva */
2726 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
2727         .master         = &omap44xx_l4_cfg_hwmod,
2728         .slave          = &omap44xx_smartreflex_iva_hwmod,
2729         .clk            = "l4_div_ck",
2730         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2731 };
2732
2733 /* l4_cfg -> smartreflex_mpu */
2734 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
2735         .master         = &omap44xx_l4_cfg_hwmod,
2736         .slave          = &omap44xx_smartreflex_mpu_hwmod,
2737         .clk            = "l4_div_ck",
2738         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2739 };
2740
2741 /* l4_cfg -> spinlock */
2742 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
2743         .master         = &omap44xx_l4_cfg_hwmod,
2744         .slave          = &omap44xx_spinlock_hwmod,
2745         .clk            = "l4_div_ck",
2746         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2747 };
2748
2749 /* l4_wkup -> timer1 */
2750 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
2751         .master         = &omap44xx_l4_wkup_hwmod,
2752         .slave          = &omap44xx_timer1_hwmod,
2753         .clk            = "l4_wkup_clk_mux_ck",
2754         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2755 };
2756
2757 /* l4_per -> timer2 */
2758 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
2759         .master         = &omap44xx_l4_per_hwmod,
2760         .slave          = &omap44xx_timer2_hwmod,
2761         .clk            = "l4_div_ck",
2762         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2763 };
2764
2765 /* l4_per -> timer3 */
2766 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
2767         .master         = &omap44xx_l4_per_hwmod,
2768         .slave          = &omap44xx_timer3_hwmod,
2769         .clk            = "l4_div_ck",
2770         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2771 };
2772
2773 /* l4_per -> timer4 */
2774 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
2775         .master         = &omap44xx_l4_per_hwmod,
2776         .slave          = &omap44xx_timer4_hwmod,
2777         .clk            = "l4_div_ck",
2778         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2779 };
2780
2781 /* l4_abe -> timer5 */
2782 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
2783         .master         = &omap44xx_l4_abe_hwmod,
2784         .slave          = &omap44xx_timer5_hwmod,
2785         .clk            = "ocp_abe_iclk",
2786         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2787 };
2788
2789 /* l4_abe -> timer6 */
2790 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
2791         .master         = &omap44xx_l4_abe_hwmod,
2792         .slave          = &omap44xx_timer6_hwmod,
2793         .clk            = "ocp_abe_iclk",
2794         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2795 };
2796
2797 /* l4_abe -> timer7 */
2798 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
2799         .master         = &omap44xx_l4_abe_hwmod,
2800         .slave          = &omap44xx_timer7_hwmod,
2801         .clk            = "ocp_abe_iclk",
2802         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2803 };
2804
2805 /* l4_abe -> timer8 */
2806 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
2807         .master         = &omap44xx_l4_abe_hwmod,
2808         .slave          = &omap44xx_timer8_hwmod,
2809         .clk            = "ocp_abe_iclk",
2810         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2811 };
2812
2813 /* l4_per -> timer9 */
2814 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
2815         .master         = &omap44xx_l4_per_hwmod,
2816         .slave          = &omap44xx_timer9_hwmod,
2817         .clk            = "l4_div_ck",
2818         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2819 };
2820
2821 /* l4_per -> timer10 */
2822 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
2823         .master         = &omap44xx_l4_per_hwmod,
2824         .slave          = &omap44xx_timer10_hwmod,
2825         .clk            = "l4_div_ck",
2826         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2827 };
2828
2829 /* l4_per -> timer11 */
2830 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
2831         .master         = &omap44xx_l4_per_hwmod,
2832         .slave          = &omap44xx_timer11_hwmod,
2833         .clk            = "l4_div_ck",
2834         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2835 };
2836
2837 /* l4_cfg -> usb_host_fs */
2838 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
2839         .master         = &omap44xx_l4_cfg_hwmod,
2840         .slave          = &omap44xx_usb_host_fs_hwmod,
2841         .clk            = "l4_div_ck",
2842         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2843 };
2844
2845 /* l4_cfg -> usb_host_hs */
2846 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
2847         .master         = &omap44xx_l4_cfg_hwmod,
2848         .slave          = &omap44xx_usb_host_hs_hwmod,
2849         .clk            = "l4_div_ck",
2850         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2851 };
2852
2853 /* l4_cfg -> usb_tll_hs */
2854 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
2855         .master         = &omap44xx_l4_cfg_hwmod,
2856         .slave          = &omap44xx_usb_tll_hs_hwmod,
2857         .clk            = "l4_div_ck",
2858         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2859 };
2860
2861 /* mpu -> emif1 */
2862 static struct omap_hwmod_ocp_if omap44xx_mpu__emif1 = {
2863         .master         = &omap44xx_mpu_hwmod,
2864         .slave          = &omap44xx_emif1_hwmod,
2865         .clk            = "l3_div_ck",
2866         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2867 };
2868
2869 /* mpu -> emif2 */
2870 static struct omap_hwmod_ocp_if omap44xx_mpu__emif2 = {
2871         .master         = &omap44xx_mpu_hwmod,
2872         .slave          = &omap44xx_emif2_hwmod,
2873         .clk            = "l3_div_ck",
2874         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2875 };
2876
2877 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
2878         &omap44xx_l3_main_1__dmm,
2879         &omap44xx_mpu__dmm,
2880         &omap44xx_iva__l3_instr,
2881         &omap44xx_l3_main_3__l3_instr,
2882         &omap44xx_ocp_wp_noc__l3_instr,
2883         &omap44xx_dsp__l3_main_1,
2884         &omap44xx_dss__l3_main_1,
2885         &omap44xx_l3_main_2__l3_main_1,
2886         &omap44xx_l4_cfg__l3_main_1,
2887         &omap44xx_mpu__l3_main_1,
2888         &omap44xx_debugss__l3_main_2,
2889         &omap44xx_fdif__l3_main_2,
2890         &omap44xx_hsi__l3_main_2,
2891         &omap44xx_ipu__l3_main_2,
2892         &omap44xx_iss__l3_main_2,
2893         &omap44xx_iva__l3_main_2,
2894         &omap44xx_l3_main_1__l3_main_2,
2895         &omap44xx_l4_cfg__l3_main_2,
2896         /* &omap44xx_usb_host_fs__l3_main_2, */
2897         &omap44xx_usb_host_hs__l3_main_2,
2898         &omap44xx_l3_main_1__l3_main_3,
2899         &omap44xx_l3_main_2__l3_main_3,
2900         &omap44xx_l4_cfg__l3_main_3,
2901         &omap44xx_aess__l4_abe,
2902         &omap44xx_dsp__l4_abe,
2903         &omap44xx_l3_main_1__l4_abe,
2904         &omap44xx_mpu__l4_abe,
2905         &omap44xx_l3_main_1__l4_cfg,
2906         &omap44xx_l3_main_2__l4_per,
2907         &omap44xx_l4_cfg__l4_wkup,
2908         &omap44xx_mpu__mpu_private,
2909         &omap44xx_l4_cfg__ocp_wp_noc,
2910         &omap44xx_l4_abe__aess,
2911         &omap44xx_l4_abe__aess_dma,
2912         &omap44xx_l4_wkup__counter_32k,
2913         &omap44xx_l4_cfg__ctrl_module_core,
2914         &omap44xx_l4_cfg__ctrl_module_pad_core,
2915         &omap44xx_l4_wkup__ctrl_module_wkup,
2916         &omap44xx_l4_wkup__ctrl_module_pad_wkup,
2917         &omap44xx_l3_instr__debugss,
2918         &omap44xx_l4_abe__dmic,
2919         &omap44xx_dsp__iva,
2920         /* &omap44xx_dsp__sl2if, */
2921         &omap44xx_l4_cfg__dsp,
2922         &omap44xx_l3_main_2__dss,
2923         &omap44xx_l4_per__dss,
2924         &omap44xx_l3_main_2__dss_dispc,
2925         &omap44xx_l4_per__dss_dispc,
2926         &omap44xx_l3_main_2__dss_dsi1,
2927         &omap44xx_l4_per__dss_dsi1,
2928         &omap44xx_l3_main_2__dss_dsi2,
2929         &omap44xx_l4_per__dss_dsi2,
2930         &omap44xx_l3_main_2__dss_hdmi,
2931         &omap44xx_l4_per__dss_hdmi,
2932         &omap44xx_l3_main_2__dss_rfbi,
2933         &omap44xx_l4_per__dss_rfbi,
2934         &omap44xx_l3_main_2__dss_venc,
2935         &omap44xx_l4_per__dss_venc,
2936         &omap44xx_l4_per__elm,
2937         &omap44xx_l4_cfg__fdif,
2938         &omap44xx_l3_main_2__gpmc,
2939         &omap44xx_l4_cfg__hsi,
2940         &omap44xx_l3_main_2__ipu,
2941         &omap44xx_l3_main_2__iss,
2942         /* &omap44xx_iva__sl2if, */
2943         &omap44xx_l3_main_2__iva,
2944         &omap44xx_l4_wkup__kbd,
2945         &omap44xx_l4_abe__mcpdm,
2946         &omap44xx_l3_main_2__mmu_ipu,
2947         &omap44xx_l4_cfg__mmu_dsp,
2948         &omap44xx_l3_main_2__ocmc_ram,
2949         &omap44xx_l4_cfg__ocp2scp_usb_phy,
2950         &omap44xx_mpu_private__prcm_mpu,
2951         &omap44xx_l4_wkup__cm_core_aon,
2952         &omap44xx_l4_cfg__cm_core,
2953         &omap44xx_l4_wkup__prm,
2954         &omap44xx_l4_wkup__scrm,
2955         /* &omap44xx_l3_main_2__sl2if, */
2956         &omap44xx_l4_abe__slimbus1,
2957         &omap44xx_l4_abe__slimbus1_dma,
2958         &omap44xx_l4_per__slimbus2,
2959         &omap44xx_l4_cfg__smartreflex_core,
2960         &omap44xx_l4_cfg__smartreflex_iva,
2961         &omap44xx_l4_cfg__smartreflex_mpu,
2962         &omap44xx_l4_cfg__spinlock,
2963         &omap44xx_l4_wkup__timer1,
2964         &omap44xx_l4_per__timer2,
2965         &omap44xx_l4_per__timer3,
2966         &omap44xx_l4_per__timer4,
2967         &omap44xx_l4_abe__timer5,
2968         &omap44xx_l4_abe__timer6,
2969         &omap44xx_l4_abe__timer7,
2970         &omap44xx_l4_abe__timer8,
2971         &omap44xx_l4_per__timer9,
2972         &omap44xx_l4_per__timer10,
2973         &omap44xx_l4_per__timer11,
2974         /* &omap44xx_l4_cfg__usb_host_fs, */
2975         &omap44xx_l4_cfg__usb_host_hs,
2976         &omap44xx_l4_cfg__usb_tll_hs,
2977         &omap44xx_mpu__emif1,
2978         &omap44xx_mpu__emif2,
2979         &omap44xx_l3_main_2__aes1,
2980         &omap44xx_l3_main_2__aes2,
2981         &omap44xx_l3_main_2__des,
2982         &omap44xx_l3_main_2__sha0,
2983         NULL,
2984 };
2985
2986 int __init omap44xx_hwmod_init(void)
2987 {
2988         omap_hwmod_init();
2989         return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
2990 }
2991